JP4867131B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device having a parallel pn structure in which a n-type semiconductor region and a p-type semiconductor region are alternately and repeatedly joined in a drift portion, and a method for manufacturing the same.

In general, semiconductor elements are classified into a horizontal element having electrodes formed on one side and a vertical element having electrodes on both sides. In the vertical semiconductor element, the direction in which the drift current flows in the on state is the same as the direction in which the depletion layer due to the reverse bias voltage extends in the off state. In a normal planar type n-channel vertical MOSFET (insulated gate field effect transistor), the high-resistance n ⁻ drift layer portion functions as a region in which a drift current flows in the vertical direction when in the ON state. Therefore, if the current path of the n ⁻ drift layer is shortened, the drift resistance is lowered, so that the substantial on-resistance of the MOSFET is reduced.

On the other hand, the portion of the high resistance n ⁻ drift layer is depleted in the off state to increase the breakdown voltage. Therefore, when the n ⁻ drift layer is thinned, the width of the drain-base depletion layer proceeding from the pn junction between the P base region and the n ⁻ drift layer is narrowed, and the critical electric field strength of silicon is reached quickly. The withstand voltage will decrease. On the other hand, in a semiconductor device with a high breakdown voltage, since the n ⁻ drift layer is thick, the on-resistance increases and the loss increases. Thus, there is a trade-off relationship between on-resistance and breakdown voltage.

  This trade-off relationship is also known to hold in semiconductor devices such as IGBTs, bipolar transistors, and diodes. This trade-off relationship is also common to lateral semiconductor elements in which the direction in which the drift current flows in the on state and the direction in which the depletion layer extends in the off state are different.

  As a solution to the above-described problem due to the trade-off relationship, the drift portion has a parallel pn structure in which a drift region made of an n-type semiconductor region with an increased impurity concentration and a partition region made of a p-type semiconductor region are alternately and repeatedly joined. Such a super junction semiconductor element is known (see, for example, Patent Document 1, Patent Document 2, Patent Document 3, and Patent Document 4). In the semiconductor element having such a structure, even when the impurity concentration of the parallel pn structure is high, the depletion layer extends laterally from each pn junction extending in the vertical direction of the parallel pn structure in the off state, and the entire drift portion Therefore, a high breakdown voltage can be achieved.

  Here, in order to obtain a low on-resistance while ensuring a breakdown voltage in the superjunction semiconductor element, the total impurity amount of the parallel pn structure n-type semiconductor region and the p-type semiconductor region is made substantially the same, and the depth in each region It is necessary to make the impurity concentration in the direction substantially uniform. For example, if the widths of the n-type semiconductor region and the p-type semiconductor region of the parallel pn structure are the same, the total impurity amount can be reduced by setting the impurity concentration of the n-type semiconductor region and the impurity concentration of the p-type semiconductor region to be approximately the same. Can be the same. However, in the conventional superjunction semiconductor element, since the operating resistance at the time of avalanche breakdown becomes a negative resistance, local concentration due to the avalanche current is likely to occur, and it is difficult to secure a sufficient avalanche resistance.

  Therefore, the present inventors have made the impurity concentration at the center of the p-type semiconductor region higher than the impurity concentration at the side close to the junction surface with the n-type semiconductor region in the parallel pn structure of the drift portion, A semiconductor device in which negative resistance at the time of avalanche breakdown is improved and avalanche resistance is improved has been filed (Japanese Patent Application No. 2002-235635). In addition, the inventors of the present invention configured the breakdown voltage portion surrounding the drift portion with a parallel pn structure in which n-type semiconductor regions and p-type semiconductor regions are alternately and repeatedly joined. A semiconductor device in which a sufficient breakdown voltage is secured in the breakdown voltage section by making the structure finer than the parallel pn structure of the sections has been filed earlier (see Patent Document 5). In Patent Document 5, a parallel pn structure is formed by repeatedly performing epitaxial growth of an n-type semiconductor layer and selective ion implantation of a p-type impurity.

European Patent Application No. 0053854 US Pat. No. 5,216,275 US Pat. No. 5,438,215 JP-A-9-266611 JP 2001-298190 A

  However, Japanese Patent Application No. 2002-235635 does not mention the configuration of the pressure-resistant portion for ensuring a sufficient breakdown voltage. On the other hand, Patent Document 5 does not describe the configuration of the active portion for ensuring the avalanche resistance. Further, as described in Patent Document 5, when a fine parallel pn structure of a withstand voltage portion is produced by repeating epitaxial growth and selective ion implantation, epitaxial growth is performed little by little, and selective ion implantation is performed each time. In this way, it is necessary to prevent the implanted ions from diffusing widely in the direction parallel to the ion implantation surface. For this reason, the number of repetitions of epitaxial growth and selective ion implantation increases, and there is a problem that the manufacturing cost becomes very high.

  The present invention has been made in view of the above-described circumstances, and is sufficient by combining the structure of the active part that can ensure avalanche resistance and the structure of the pressure part that can secure a sufficient breakdown voltage. An object of the present invention is to provide a semiconductor device that achieves both an avalanche resistance and a stable breakdown voltage. It is another object of the present invention to provide a method for manufacturing a semiconductor device, which can manufacture a semiconductor device having both a sufficient avalanche resistance and a stable breakdown voltage at a low cost with a small number of man-hours by a method of embedding a trench with an epitaxial growth layer. To do.

In order to solve the above-described problems and achieve the object, a semiconductor device according to a first aspect of the present invention is a parallel device in which a first conductivity type semiconductor region and a second conductivity type semiconductor region are alternately and repeatedly joined. A semiconductor device having a pn structure on a low resistance layer of a first conductivity type, wherein the parallel pn structure is a repetitive junction between the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type. On the first parallel pn structure part having a first period and a second parallel pn structure part having a second period shorter than the first period, and on the first parallel pn structure part A control electrode provided via an insulating film and the first conductivity type of the first parallel pn structure portion provided on the first parallel pn structure portion by applying a voltage to the control electrode An input electrode for injecting electrons into the semiconductor region, and the low-resistance layer, Has an output electrode disposed on the opposite side of the column pn structure, a, in the first parallel pn structure, the impurity concentration of the second conductivity type semiconductor region, the semiconductor of the first conductivity type It is higher in the first inner region from the surface of the first parallel pn structure part to a predetermined depth than in the first outer region near the junction with the region. In the second parallel pn structure portion, the impurity concentration of the second conductivity type semiconductor region is higher than that of the second outer region closer to the junction with the first conductivity type semiconductor region. Inside the second outer region and in the second inner region from the surface of the second parallel pn structure portion to a predetermined depth, the height is higher, and the first outer region has the first A width in a direction perpendicular to the boundary surface with the inner region, and the second outer region, The width in the direction perpendicular to the boundary surface between the side regions, characterized in that it is approximately the same.

  According to the first aspect of the present invention, when avalanche is generated in the parallel pn structure, the generated holes flow through the central portion of the p-type semiconductor region and escape to the source electrode due to the potential distribution of the parallel pn structure, The electrons flow through the central portion of the n-type semiconductor region and escape to the drain electrode. At this time, the impurity concentration in the central portion of the p-type semiconductor region is high, so that the charge balance when the avalanche occurs is secured. Therefore, the negative resistance is improved and the avalanche resistance is improved.

  According to the invention of claim 1, since the p-type semiconductor region in the breakdown voltage portion has the same effect as the guard ring, by shortening the period of the parallel pn structure in the breakdown voltage portion, The same effect as narrowing the interval is obtained. Therefore, the depletion layer in the pressure resistant part is easily extended, and the breakdown voltage is improved. In manufacturing a semiconductor device, a parallel pn structure is formed on a semiconductor substrate, and then a MOS (metal-oxide film-insulator) structure is formed on the surface of the substrate. Since a thermal history is added during the formation of the MOS structure, the impurity concentration of the parallel pn structure decreases due to the mutual diffusion of impurities. As the period of the parallel pn structure is shorter, the rate of decrease in the impurity concentration is larger. Therefore, the impurity concentration of the n-type semiconductor region of the parallel pn structure in the breakdown voltage portion is higher than the impurity concentration of the n-type semiconductor region of the parallel pn structure in the active portion. This contributes to an improvement in breakdown voltage.

  According to the first aspect of the present invention, in the parallel pn structure of the withstand voltage portion, the depletion layer of the withstand voltage portion is more likely to be expanded by increasing the impurity concentration on the surface side of the p-type semiconductor region. Further, the breakdown voltage can be secured more stably.

  A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the region of the second inner region having a higher impurity concentration than the second outer region is the second parallel pn structure portion. The second conductivity type semiconductor region is provided at the center of the semiconductor region.

The semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first or second aspect, wherein the area of the cross section of the first inner region parallel to the surface of the parallel pn structure is the second inner region. The area of the cross section parallel to the surface of the parallel pn structure is larger. The semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to any one of the first to third aspects, wherein the first inner region has a surface of the parallel pn structure than the second inner region. It is characterized by being deep against .

Such a semiconductor device in the invention of claim 5, in the invention described in any one of claims 1 to 4, the impurity concentration of said first inner region, than the impurity concentration of said second inner region, It is characterized by being expensive. Such a semiconductor device in the invention of claim 6, in the invention described in any one of claims 1 to 5, the impurity concentration of the first outer region, than the impurity concentration of said second outer region, It is characterized by being expensive. A semiconductor device according to a seventh aspect of the present invention is the semiconductor device according to any one of the first to sixth aspects, wherein the impurity concentration of the first conductivity type semiconductor region of the first parallel pn structure portion is the It is characterized by being higher than the impurity concentration of the first conductivity type semiconductor region of the second parallel pn structure part. The semiconductor device according to an eighth aspect of the present invention is the semiconductor device according to the first aspect, wherein the impurity concentration of the second conductivity type semiconductor region of the first parallel pn structure portion is the second parallel pn structure portion. The impurity concentration of the second conductivity type semiconductor region is higher than that of the second conductivity type.

A semiconductor device according to a ninth aspect of the present invention is the semiconductor device according to any one of the first to eighth aspects, wherein the second parallel pn structure portion is disposed at a peripheral portion of the first parallel pn structure portion. It is characterized by being. A semiconductor device according to a tenth aspect of the present invention is the semiconductor device according to any one of the first to eighth aspects, wherein the planar pattern of the parallel pn structure is a stripe shape.

According to an eleventh aspect of the present invention, there is provided the semiconductor device according to the tenth aspect , wherein the first parallel pn structure portion is disposed at a central portion of an element region having a rectangular planar shape, and the element region The first parallel pn structure portion is disposed at a peripheral portion along a side perpendicular to the longitudinal direction of the first conductivity type semiconductor region of the first parallel pn structure portion disposed in the central portion of the first parallel pn structure portion, and the element region The second parallel pn structure portion is disposed at a peripheral portion along a side parallel to the longitudinal direction of the first conductivity type semiconductor region of the first parallel pn structure portion disposed in the central portion of the first parallel pn structure portion. Features. A semiconductor device according to a twelfth aspect of the present invention is the semiconductor device according to any one of the ninth to eleventh aspects, wherein at least a part of the second parallel pn structure portion constitutes at least a part of a breakdown voltage structure. It is characterized by.

In order to solve the above-described problems and achieve the object, a semiconductor device manufacturing method according to the invention of claim 13 is provided on a low-resistance layer made of a semiconductor of the first conductivity type, higher than the low-resistance layer. A step of epitaxially growing a resistive first-conductivity-type semiconductor; a step of forming a trench in the first-conductivity-type semiconductor layer stacked on the low-resistance layer by the epitaxial growth; and the first-conductivity-type semiconductor layer A step of epitaxially growing a second conductivity type semiconductor in the trench formed in the trench, and filling the trench with the second conductivity type semiconductor region; and filling the trench and then the first conductivity type semiconductor. Forming a control electrode on the layer and an input electrode for injecting electrons into the semiconductor layer of the first conductivity type by applying a voltage to the control electrode; and Forming an output electrode on the opposite side to the conductive type semiconductor layer, and forming two or more different widths in the same element region when forming the trench in the first conductive type semiconductor layer. In the middle of forming a periodic trench and filling the trench with the second conductivity type semiconductor region, the impurity concentration of the second conductivity type semiconductor region is changed high before the narrow trench is completely filled . , By completely filling all trenches with the semiconductor having the changed impurity concentration, and filling the trenches with the second conductivity type semiconductor region, the first conductivity type semiconductor layer on the low resistance layer; The second conductivity type semiconductor regions are alternately and repeatedly joined, and the repetition cycle of the junction between the first conductivity type semiconductor layer and the second conductivity type semiconductor region is the first cycle. First parallel pn structure part A parallel pn structure having a second parallel pn structure portion having a second period shorter than the first period is formed, and the control is performed on the first parallel pn structure portion via an insulating film. An electrode is formed, and the input electrode for injecting electrons into the semiconductor layer of the first conductivity type of the first parallel pn structure portion is formed on the first parallel pn structure portion .

According to the thirteenth aspect of the present invention, even if the width and the period of each of the first conductivity type semiconductor region and the second conductivity type semiconductor region constituting the parallel pn structure are shortened, the trench etching is performed by one trench etching. After forming a trench with such a short width and cycle, the trench can be filled in by one epitaxial growth, so that the number of steps is significantly reduced compared to repeating epitaxial growth and selective ion implantation. A parallel pn structure of width and period can be made. Further, in the active portion and the breakdown voltage portion, the p-type semiconductor region has a higher impurity concentration in the inner region away from the junction than in the outer region near the junction between the n-type semiconductor region and the n-type semiconductor region. A parallel pn structure consisting of At this time, in order to change the impurity concentration during the epitaxial growth, it is only necessary to change the ratio of the gas flow rate during the epitaxial growth, so that the trench filling can be completed in one continuous epitaxial growth step.

  Further, the first conductivity type semiconductor region having a width and a period shorter than the width and the period of each of the first conductivity type semiconductor region and the second conductivity type semiconductor region constituting the parallel pn structure of the active portion in the breakdown voltage portion When the parallel pn structure composed of the semiconductor regions of the second conductivity type is disposed, the trench pattern for forming the parallel pn structure of the withstand voltage portion is made finer than the trench pattern for forming the parallel pn structure of the active portion. Just do it. Therefore, since it is not necessary to increase the number of processes, a fine parallel pn structure can be manufactured in the pressure-resistant portion without substantially increasing the manufacturing cost.

According to a fourteenth aspect of the present invention, there is provided a semiconductor device manufacturing method according to the thirteenth aspect of the present invention, wherein when the trench is formed in the first conductivity type semiconductor layer, the narrowest trench is formed in the low resistance layer. The process of forming a trench in the semiconductor layer is continued until the semiconductor layer reaches this level. According to a fifteenth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the thirteenth or fourteenth aspect of the present invention, wherein a trench having a first width and period is formed when a trench is formed in the first conductivity type semiconductor layer. A first trench and a second trench having a second width and period are formed in a peripheral portion of the first trench.

According to a sixteenth aspect of the present invention, there is provided a semiconductor device manufacturing method according to the fifteenth aspect of the present invention, wherein when the trench is formed in the semiconductor layer of the first conductivity type, the second width of the second trench and The period is shorter than the first width and period of the first trench. According to a seventeenth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the thirteenth or fourteenth aspect , wherein when the trench is formed in the first conductivity type semiconductor layer, the planar pattern of the trench is formed in a stripe shape. It is characterized by doing.

The method of manufacturing a semiconductor device according to claim 18 is the method according to claim 17 , wherein when the trench is formed in the semiconductor layer of the first conductivity type, the center of the element region having a rectangular shape in plan view is formed. A first trench having a first width and a period at a portion thereof, and a first trench having a first width and a period at a peripheral portion along a side perpendicular to the longitudinal direction of the first trench at the center of the element region The trench is characterized in that a second trench having a second width and period is formed in a peripheral portion along a side parallel to the longitudinal direction of the first trench in the central portion of the element region. According to a nineteenth aspect of the present invention, in the semiconductor device manufacturing method according to the eighteenth aspect of the present invention, when the trench is formed in the first conductivity type semiconductor layer, the second width of the second trench and The period is shorter than the first width and period of the first trench.

  According to the present invention, sufficient avalanche resistance and stable breakdown voltage can be obtained by manufacturing a semiconductor device with a small number of processes of one epitaxial growth process, one trench etching process, and one buried epitaxial growth process. There is an effect that a compatible semiconductor device can be obtained at low cost.

Exemplary embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be explained below in detail with reference to the accompanying drawings. In the following description and the accompanying drawings, a layer or region with n or p is a sign that electrons or holes are carriers. Further, ^{+, ++} , or ⁻ attached to n or p represents a relatively high impurity concentration or a relatively low impurity concentration, respectively. Note that the same reference numerals are given to the same components in all the attached drawings, and redundant description is omitted.

Embodiment 1 FIG.
FIG. 1 is a partial plan view showing the main part of the vertical MOSFET chip according to the first embodiment of the present invention. In FIG. 1, the surface layer of the parallel pn structure and the surface structure of the element formed thereon are omitted. In the following description, for convenience, a direction in which n drift regions and p partition regions of a parallel pn structure are alternately arranged is an x direction, and a direction in which each n drift region and each p partition region extends is a y direction.

  As shown in FIG. 1, the active part through which current flows in the on state of the MOSFET is arranged, for example, at the center of a rectangular chip, and is surrounded by a pressure-resistant part provided at the peripheral part of the chip. The parallel pn structure constituting the drift layer is such that n drift regions 12, n regions 19 and p partition regions 13, 20 extending in the y direction from one side of the rectangular chip in the x direction to the opposite side are alternately arranged in the x direction. It is configured to have a striped planar shape that is repeatedly joined.

  The parallel pn structure is divided into a first parallel pn structure portion 1 and a second parallel pn structure portion 2. The first parallel pn structure portion 1 and the second parallel pn structure portion 2 are in contact with each other at the n drift region 12 of the first parallel pn structure portion 1 and the p partition region 20 of the second parallel pn structure portion 2. ing. The width and repetition period of the n region 19 and the p partition region 20 of the second parallel pn structure part 2 are larger than the width and repetition period of the n drift region 12 and the p partition region 13 of the first parallel pn structure part 1. Also short. In the first embodiment, the n drift region 12, the n region 19 and the p partition regions 13 and 20 are continuous from one side of the rectangular chip in the x direction to the opposite side, and the width and period are halfway. does not change.

  The parallel pn structure of the active part is made of the first parallel pn structure part 1. A region between the side in the x direction of the rectangular chip and the active part of the breakdown voltage part is a first parallel pn structure part 1 continuing from the active part. In the breakdown voltage portion, the region along the side in the y direction of the rectangular chip has a second parallel pn structure portion 2, that is, a fine parallel pn structure. In other words, the parallel pn structure has a finer pitch between the side of the rectangular chip in the x direction and the opposite side in the region not including the active part than in the region including the active part. In addition, the edge that ends the side in the y direction of the rectangular chip is an n region 22. Further, channel stopper regions 23 are provided along the four sides of the rectangular chip.

FIG. 2 is a longitudinal cross-sectional view showing a cross-sectional configuration along a cutting line AA ′ crossing the active portion and the pressure-resistant portion in the x direction in FIG. As shown in FIG. 2, the first parallel pn structure portion 1 and the second parallel pn structure portion 2 are provided on the surface of the n ⁺⁺ drain layer 11 which is a low resistance layer in the active portion and the withstand voltage portion, respectively. It has been. The drain electrode 24 is provided on the back surface of the n ⁺⁺ drain layer 11.

The cross-sectional configuration in the active part is as follows. As shown in FIG. 2, the p partition region 13 of the first parallel pn structure portion 1 is connected to the n drift region 12 in an inner region (first inner region) away from the junction with the n drift region 12. A p ⁺ region 14 having a higher impurity concentration than the outer region (first outer region) close to the junction is provided. The p ⁺ region 14 is provided from the surface of the first parallel pn structure portion 1 to a predetermined depth. In the example shown in FIG. 2, the p ⁺ region 14 is provided partway through the p partition region 13 and does not contact the n ⁺⁺ drain layer 11.

The p-well region 15 is selectively provided on the surface layer of the first parallel pn structure portion 1 continuously to the p partition region 13. The n ⁺ source region 16 is selectively provided in the surface layer of the p well region 15 inside the p well region 15. The p ⁺ contact region 28 is selectively provided in the surface layer of the p well region 15 inside the p well region 15. The gate electrode 17 made of polycrystalline silicon is provided on the surface of the p well region 15 sandwiched between the n ⁺ source region 16 and the n drift region 12 via a gate insulating film 18. The source electrode 25 is provided on the first parallel pn structure portion 1 and is in common contact with the surfaces of the n ⁺ source region 16 and the p ⁺ contact region 28.

  The cross-sectional configuration in the pressure-resistant portion is as follows. As shown in FIG. 2, the field plate oxide film 21 is connected to the second parallel pn from the n drift region 12 in contact with the p partition region 20 of the second parallel pn structure portion 2 of the first parallel pn structure portion 1. The structure 2 covers the semiconductor surface up to the p partition region 20 in contact with the n region 22 at the end of the chip. The field plate oxide film 21 contributes to alleviating electric field concentration and protecting and stabilizing the element surface. The source electrode 25 extends from the active portion onto the field plate oxide film 21 and is provided partway through the field plate oxide film 21. That is, the end of the source electrode 25 where the electric field concentrates is located on the breakdown voltage portion.

The n region 22 at the end of the chip is a region where the n semiconductor layer epitaxially grown on the n ⁺⁺ drain layer 11 in the manufacturing method described later remains. Therefore, the impurity concentration of the n region 22 is approximately the same as that of the n drift region 12 of the first parallel pn structure portion 1 (1 × 10 ¹⁵ cm ⁻³ or more). Therefore, since the depletion layer hardly extends in the n region 22, the portion under the field plate oxide film 21 where the depletion layer may extend is, as illustrated, the n region 19 and the p partition region 20. It is desirable to continue.

  The low-resistance channel stopper region 23 is provided in the surface layer of the n region 22 at the end of the chip. The stopper electrode 26 is in contact with the channel stopper region 23 and extends to the middle of the field plate oxide film 21. The stopper electrode 26 is separated from the source electrode 25, and the same potential as that of the drain electrode 24 is applied to the stopper electrode 26.

Although not particularly limited, as an example, for a semiconductor element having a breakdown voltage of 600 V class, dimensions and impurity concentrations of each part are listed. The specific resistance of the n ⁺⁺ drain layer 11 is 0.01 Ωcm. The thickness of the n ⁺⁺ drain layer 11 is about 350 μm. The thickness of the parallel pn structure including the p well region 15 is about 50 μm. The depth of the p well region 15 is about 3 μm.

In the first parallel pn structure portion 1, the width in the x direction of the p partition region 13 is about 2 μm in the p ⁺ region 14 (first inner region), and a region other than the p ⁺ region 14 (first outer side). Area) is about 1.5 μm on each side, and the total is about 3 μm, and the total of both is 5 μm. The impurity concentration of the p partition region 13 is about 4.9 × 10 ¹⁵ cm ⁻³ in the p ⁺ region 14 (first inner region) and 4 in the region other than the p ⁺ region 14 (first outer region). .46 × 10 ¹⁵ cm ⁻³ or so. The width of the n drift region 12 in the x direction is 5 μm. The impurity concentration of the n drift region 12 is constant and is about 4.46 × 10 ¹⁵ cm ⁻³ .

In the second parallel pn structure portion 2, the widths in the x direction of the n region 19 and the p partition region 20 are both 3 μm. Further, the impurity concentrations of the n region 19 and the p partition region 20 are lower than the impurity concentrations of the n drift region 12 and the p partition region 13 of the first parallel pn structure portion 1, respectively, and both are about 8 × 10 ¹⁴ cm ^−3. It is.

Next, the operation of the semiconductor device configured as described above will be described. When a positive voltage is applied to the gate electrode 17, an inversion layer is induced in the surface layer of the region of the p well region 15 immediately below the gate electrode 17. Then, electrons are injected from the n ⁺ source region 16 into the channel region 12a of the surface layer of the n drift region 12 through this inversion layer. The electrons injected into the channel region 12 a reach the n ⁺⁺ drain layer 11 through the n drift region 12. As a result, the drain electrode 24 and the source electrode 25 become conductive.

  When the positive voltage applied to the gate electrode 17 is removed, the inversion layer induced in the surface layer of the p-well region 15 disappears. As a result, conduction between the drain electrode 24 and the source electrode 25 is eliminated, and the drain electrode 24 and the source electrode 25 are blocked. Since each p partition region 13 of the first parallel pn structure portion 1 is electrically connected to the source electrode 25 via the p well region 15, when the reverse bias voltage is further increased, the p well region 15 and the channel A depletion layer spreads from the pn junction Ja between the region 12a and the n drift region 12 and the p partition region 13 respectively. Thereby, the n drift region 12 and the p partition region 13 are depleted. At that time, the depletion layer spreads in the width direction of the n drift region 12 from the p partition regions 13 on both sides of each n drift region 12, so that the depletion layer is depleted very quickly. Therefore, the impurity concentration of n drift region 12 can be increased.

As described above, in the first parallel pn structure portion 1, the p ⁺ region 14 having a high impurity concentration is provided in the inner region of the p partition region 13. Thereby, the charge balance when the avalanche occurs is secured, the negative resistance is improved, and the operating resistance becomes positive. When the operating resistance becomes positive, an avalanche current flows and a breakdown voltage increases. Therefore, the avalanche is generated in the entire p ⁺ region 14. As a result, no avalanche current is concentrated, and the avalanche resistance is improved.

  Next, the behavior of the withstand voltage portion when the MOSFET is in the off state will be described. First, the behavior of the cross section shown in FIG. 2, that is, the cross section crossing the active portion and the pressure resistant portion in the x direction will be described. In a region where the source electrode 25 extends from the active portion in the breakdown voltage portion, the potential immediately below the field plate oxide film 21 is constant. Therefore, the depletion layer spreads from the pn junction between the n region 19 and the p partition region 20 of the second parallel pn structure portion 2, and the breakdown voltage is maintained.

On the other hand, in the region without the source electrode 25, the p partition region 20 is in a floating state. Therefore, in this region, the p partition region 20 functions as a guard ring penetrating from the surface of the second parallel pn structure portion 2 to the n ⁺⁺ drain layer 11. That is, in the second parallel pn structure portion 2, the region without the source electrode 25 has a structure in which a guard ring is periodically provided by the p partition region 20. For example, as described above, if the widths of the n region 19 and the p partition region 20 are both 3 μm, the period of the guard ring is 6 μm.

Even in a cross section crossing the active portion and the withstand voltage portion in the x direction, as in the first parallel pn structure portion 1 of the active portion, each of the parallel pn structures has a width of 5 μm and an impurity concentration of 4.46 ×. When an n region and a p partition region of 10 ¹⁵ cm ⁻³ are provided, the guard ring period is 10 μm. On the other hand, in this embodiment, the guard ring cycle is 6 μm, and the impurity concentrations of the n region 19 and the p partition region 20 are both 8 × 10 ¹⁴ cm ^−3. .

  On the other hand, as described above, the first parallel pn structure portion 1 of the active portion is extended as it is in the cross-sectional pressure line BB ′ crossing the active portion and the pressure resistant portion in the y direction in FIG. It has a structure. In the breakdown voltage section in this cross section, each p partition region 13 falls on the drain electrode 24, so that a depletion layer spreads from the pn junction between each p partition region 20 and each n region 19. That is, the super junction structure continues from the drain electrode 24 to the stopper electrode 26. Therefore, if the distance from the drain electrode 24 to the stopper electrode 26 is longer than the depth of the first parallel pn structure portion 1 in the active portion, a sufficient breakdown voltage can be ensured. It is not necessary to change the pitch of the parallel pn structure in the pressure-resistant portion in the cross section crossing in the direction.

Next, a method for manufacturing the semiconductor device of the first embodiment will be described. First, as shown in FIG. 3, for example, an impurity concentration of about 6 × 10 ¹⁵ cm ⁻³ is formed on a low resistance n ⁺⁺ semiconductor substrate 31 having a specific resistance of 0.01 Ωcm and a thickness of about 350 μm. The n semiconductor layer 32 is epitaxially grown to a thickness of 50 μm.

Next, as shown in FIG. 4, a mask oxide film 33 is formed on the surface of the epitaxially grown n semiconductor layer 32 to a thickness of, for example, 16000 angstroms by oxidation or CVD. Then, trench-shaped patterning is performed on the mask oxide film 33 by a photolithography process. Then, for example, by the RIE method, the first trench 34 having a width of 5 μm and the second trench 35 having a width of 3 μm every 5 μm are formed in the n semiconductor layer 32 at a depth reaching the n ⁺⁺ semiconductor substrate 31. Dig up.

  A first trench 34 is dug in a region to be an active part. A first trench 34 is dug in a region between the side in the x direction of the rectangular chip and the region serving as the active portion in the region serving as the pressure-resistant portion. Further, in the region serving as the pressure-resistant portion, the second trench 35 is dug in the region along the side in the y direction of the rectangular chip.

Note the following when digging a trench: That is, when the widths of the trenches 34 and 35 are different, the second trench 35 having a small width is shallower than the first trench 34 having a large width because the amount of plasma at the time of forming the trench is reduced. Therefore, if the trench is dug at a depth that allows the first trench 34 to reach the n ⁺⁺ semiconductor substrate 31, the second trench 35 does not reach the n ⁺⁺ semiconductor substrate 31. Therefore, when the trenches 34 and 35 are filled with a p semiconductor in a later step, the p partition region 20 does not reach the n ⁺⁺ drain layer 11 in the breakdown voltage portion as shown in FIG. This causes a problem that the withstand voltage decreases. In order to prevent this, it is necessary to dig a trench until the narrow second trench 35 reaches the n ⁺⁺ semiconductor substrate 31.

After the trenches 34 and 35 are formed, as shown in FIG. 5, epitaxial growth is performed to completely fill the second trench 35 with the p semiconductor 36. At this time, the first trench 34 having a width wider than the second trench 35 is not completely filled with the p-semiconductor 36, and the air gap 37 remains in the central portion thereof. The impurity concentration of the p semiconductor 36 is set to about 6 × 10 ¹⁵ cm ^−3, which is the same as that of the n semiconductor layer 32 epitaxially grown previously.

During the ongoing epitaxial growth, the gas concentration supplied into the chamber after the second trench 35 is completely filled with the p semiconductor 36 and before the first trench 34 is completely filled with the p semiconductor 36. By changing the ratio, as shown in FIG. 6, the gap 37 remaining in the first trench 34 is filled with a p ⁺ semiconductor 38 having an impurity concentration higher than that of the p semiconductor 36. The impurity concentration of the p ⁺ semiconductor 38 is, for example, about 6.6 × 10 ¹⁵ cm ⁻³ . In this series of epitaxial growth, the mask oxide film 33 used for the trench etching serves as a mask for preventing the epitaxial growth on the surface portion.

In this epitaxial growth, a step is generated for each trench due to a difference in depth and width of each trench in the wafer surface or a difference in epitaxial growth rate in the wafer surface. In order not to leave this step in the subsequent process, the p ⁺ semiconductor 38 is sufficiently grown above the surface of the mask oxide film 33 in all the trenches. Then, the step generated during the epitaxial growth is removed by polishing the surface, and then the mask oxide film 33 is removed and planarized, whereby the substrate of the semiconductor device shown in FIG. 7 is completed.

In the substrate shown in FIG. 7, the n ⁺⁺ semiconductor substrate 31 becomes the n ⁺⁺ drain layer 11 which is a low resistance layer. In the region of the n semiconductor layer 32 epitaxially grown on the n ⁺⁺ semiconductor substrate 31, the region serving as the active portion and the region serving as the withstand voltage portion between the side in the x direction of the rectangular chip and the region serving as the active portion. The portions 32a remaining in the regions (not appearing in FIG. 7) become the n drift regions 12 of the first parallel pn structure portion 1. Further, in the region to be the breakdown voltage portion of the n semiconductor layer 32, the portion 32b remaining in the region along the y-direction side of the rectangular chip becomes the n region 19 of the second parallel pn structure portion 2. . Further, the chip termination portion 32 c of the n semiconductor layer 32 remaining without forming a trench is the n region 22.

Of the p semiconductors 36 embedded in the trenches, the p semiconductors 36a embedded in the wide first trenches 34 and the p ⁺ semiconductors 38 embedded in the inner region thereof are respectively the first parallel pn. It becomes the p partition region 13 and the p ⁺ region 14 of the structure portion 1. Among the p semiconductors 36, the p semiconductor 36 b embedded in the narrow second trench 35 becomes the p partition region 20 of the second parallel pn structure portion 2.

Then, after the MOS structure and the field plate oxide film 21 are formed on this substrate, the drain electrode 24, the source electrode 25, and the stopper electrode 26 are vapor-deposited, and the passivation film is laminated, whereby the semiconductor device having the structure shown in FIG. It ’s done. In FIG. 2, the passivation film is omitted. Due to the thermal history in manufacturing the MOS structure, mutual diffusion of impurities occurs between the n semiconductor portions 32a and 32b, the p semiconductors 36a and 36b, and the p ⁺ semiconductor 38, and the respective impurity concentrations are lowered.

The impurity concentration of the n semiconductor portion 32a that becomes the n region 12 of the first parallel pn structure portion 1 and the p semiconductor 36a that becomes the p partition region 13 are both about 4.46 × 10 ¹⁵ cm ⁻³ . The impurity concentration of the p ⁺ semiconductor 38 to be the p ⁺ region 14 is about 4.9 × 10 ¹⁵ cm ⁻³ . Further, the impurity concentration of the n semiconductor portion 32b to be the n region 19 of the second parallel pn structure portion 2 and the p semiconductor 36b to be the p partition region 20 are both about 8 × 10 ¹⁴ cm ⁻³ .

Embodiment 2. FIG.
FIG. 8 is a vertical cross-sectional view showing a cross-sectional configuration crossing the active portion and the breakdown voltage portion of the vertical MOSFET chip according to the second embodiment of the present invention in the x direction. However, the x direction and the y direction are the same as those in the first embodiment. Therefore, FIG. 8 shows a cross-sectional configuration corresponding to the cutting line AA ′ in FIG.

As shown in FIG. 8, in the second embodiment, the p partition region 20 of the second parallel pn structure portion 2 is connected to the n region 19 in the same manner as the p partition region 13 of the first parallel pn structure portion 1. A p ⁺ region 27 having a higher impurity concentration than the outer region (second outer region) near the junction with the n region 19 is provided in the inner region (second inner region) away from the junction. Other configurations are the same as those of the first embodiment. Only differences from the first embodiment will be described below.

The p ⁺ region 27 is provided from the surface of the second parallel pn structure portion 2 to a predetermined depth, and is shallower than the p ⁺ region 14 (first inner region) of the first parallel pn structure portion 1. Further, the width of the p ⁺ region 27 in the x direction is narrower than the width of the p ⁺ region 14 in the x direction, for example, about 1 μm. Therefore, the area of the cross section of the p ⁺ region 27 parallel to the surface of the second parallel pn structure portion 2 is larger than the area of the cross section of the p ⁺ region 14 parallel to the surface of the first parallel pn structure portion 1. small. Further, the width in the x direction of the region other than the p ⁺ region 27 (second outer region) of the p partition region 20 is the same as the width of the region other than the p ⁺ region 14 (first outer region) of the p partition region 13. The width is almost the same as the width in the x direction. For example, the width is about 1 μm on each side, and the total is about 2 μm. Therefore, the width of the p ⁺ region 14 is about 3 μm.

The impurity concentration of p ⁺ region 27 is lower than the impurity concentration of p ⁺ region 14 and is, for example, about 8.8 × 10 ¹⁴ cm ⁻³ . The impurity concentration of the region other than the p ⁺ region 27 in the p partition region 20 is lower than the impurity concentration of the region other than the p ⁺ region 14 in the p partition region 13, for example, about 8 × 10 ¹⁴ cm ⁻³ . Unless otherwise specified, other dimensions and impurity concentrations are the same as those in the first embodiment. As in the second embodiment, when a region having a high impurity concentration is present in the central portion of the withstand voltage portion, the depletion layer becomes easier to extend. Therefore, the effect of ensuring the withstand voltage is easier than in the first embodiment. can get.

In manufacturing the semiconductor device of the second embodiment, first, as shown in FIGS. 3 and 4, after an n semiconductor layer 32 is epitaxially grown on an n ⁺⁺ semiconductor substrate 31, a mask oxide film 33 is used. First and second trenches 34 and 35 are formed. Next, as shown in FIG. 9, the p semiconductor 36 is epitaxially grown. At that time, the first trench 34 and the second trench 35 are not completely filled with the p semiconductor 36, and the gas concentration ratio supplied into the chamber is changed in a state where the air gap 37 and the air gap 39 remain in the central portion, respectively. .

Then, as shown in FIG. 10, the voids 37 and 39 are filled with a p ⁺ semiconductor 38 having an impurity concentration higher than that of the p semiconductor 36, and the step of the surface is eliminated, thereby completing the substrate of the semiconductor device. The impurity concentration of the p semiconductor 36 is set to about 6 × 10 ¹⁵ cm ^−3, which is the same as that of the n semiconductor layer 32 epitaxially grown previously. The impurity concentration of the p ⁺ semiconductor 38 is, for example, about 6.6 × 10 ¹⁵ cm ⁻³ .

In the substrate shown in FIG. 10, among the p semiconductors 36 buried in the trenches, the p semiconductor 36a buried in the wide first trench 34 and the p ⁺ semiconductor 38a buried in the inner region thereof are respectively It becomes the p partition region 13 and the p ⁺ region 14 of the first parallel pn structure portion 1. Among the p semiconductors 36, the p semiconductor 36 b embedded in the narrow second trench 35 and the p ⁺ semiconductor 38 b embedded in the inner region thereof are respectively divided into the p partitions of the second parallel pn structure portion 2. Region 20 and p ⁺ region 27 are formed.

Then, after the MOS structure and the field plate oxide film 21 are formed on this substrate, the drain electrode 24, the source electrode 25, and the stopper electrode 26 are vapor-deposited, and a passivation film (not shown) is laminated. A semiconductor device is completed. Due to the interdiffusion of impurities due to the thermal history during the fabrication of the MOS structure, the impurity concentration of the p semiconductor 36b that becomes the p partition region 20 of the second parallel pn structure portion 2 is about 8 × 10 ¹⁴ cm ⁻³ . Further, the impurity concentration of the p ⁺ semiconductor 38b to be the p ⁺ region 27 is about 8.8 × 10 ¹⁴ cm ⁻³ . The impurity concentration of the p ⁺ semiconductor 38a that becomes the p ⁺ region 14 of the first parallel pn structure portion 1 is about 4.9 × 10 ¹⁵ cm ⁻³ .

Embodiment 3 FIG.
FIG. 11 is a partial plan view showing the main part of the vertical MOSFET chip according to the third embodiment of the present invention. In FIG. 11, the surface layer of the parallel pn structure and the surface structure of the element formed thereon are omitted. In the third embodiment, the x direction and the y direction are the same as those in the first embodiment.

  As shown in FIG. 11, in the third embodiment, in the planar pattern shown in FIG. 1 of the first embodiment, the parallel pn of the region between the active part and the side in the x direction of the rectangular chip of the breakdown voltage part The structure is a second parallel pn structure portion 2 having a finer pitch than the first parallel pn structure portion 1 of the active portion. That is, the entire region of the pressure-resistant portion along the peripheral edges of the four sides of the rectangular chip is made of the second parallel pn structure portion 2.

As in the first embodiment, when the p ⁺ region 14 is provided only in the p partition region 13 of the first parallel pn structure portion 1, the active portion and the withstand voltage portion in FIG. The cross-sectional configuration at the cross section line CC ′ is the same as the configuration shown in FIG. The dimensions and concentration in that case are the same as in the first embodiment, and the manufacturing method is the same as in the first embodiment. However, the patterning of the mask oxide film 33 is changed in accordance with the pattern of the parallel pn structure shown in FIG. 11, and the pattern of the trench is changed. According to such a configuration, the depletion layer becomes easier to spread in the pressure-resistant portion, so that a more stable breakdown voltage can be ensured than in the first embodiment.

Similarly to the second embodiment, the p ⁺ region 14 is provided in the p partition region 13 of the first parallel pn structure portion 1 and the p partition region 20 of the second parallel pn structure portion 2 is p. ^{When the +} region 27 is provided, the cross-sectional configuration along the cutting line CC ′ in FIG. 11 is the same as the configuration shown in FIG. The dimensions and concentration in that case are the same as in the second embodiment, and the manufacturing method is the same as in the second embodiment. However, the patterning of the mask oxide film 33 is changed in accordance with the pattern of the parallel pn structure shown in FIG. 11, and the pattern of the trench is changed. According to such a configuration, the depletion layer becomes easier to spread in the pressure-resistant portion, so that a more stable breakdown voltage can be ensured than in the second embodiment.

Embodiment 4 FIG.
FIG. 12 is a partial plan view showing the main part of the vertical MOSFET chip according to the fourth embodiment of the present invention. In FIG. 12, the surface layer of the parallel pn structure and the surface structure of the element formed thereon are omitted. In the fourth embodiment, the x direction and the y direction are the same as those in the first embodiment.

  As shown in FIG. 12, in the fourth embodiment, in the planar pattern shown in FIG. 11 of the third embodiment, the second parallel pn structure portion 2 of the withstand voltage portion is replaced with the first parallel of which the stripe pattern is the active portion. They are arranged so as to be orthogonal to the stripe pattern of the pn structure portion 1. That is, in the breakdown voltage portion, the second parallel pn structure portion 2 has a configuration in which n regions 19 and p partition regions 20 extending in the x direction are alternately and repeatedly joined in the y direction. In this case, the n region 22 is provided along an edge that terminates in the x-direction side of the rectangular chip.

As in the first embodiment, when the p ⁺ region 14 is provided only in the p partition region 13 of the first parallel pn structure portion 1, the dimensions and concentration are the same as those in the first embodiment. The manufacturing method is also the same as in the first embodiment. Similarly to the second embodiment, the p ⁺ region 14 is provided in the p partition region 13 of the first parallel pn structure portion 1 and the p partition region 20 of the second parallel pn structure portion 2 is p. ^{When +} region 27 is provided, the dimensions and concentration are the same as in the second embodiment, and the manufacturing method is the same as in the second embodiment. However, in any case, the patterning of the mask oxide film 33 is changed in accordance with the pattern of the parallel pn structure shown in FIG. 12, and the pattern of the trench is changed.

Embodiment 5 FIG.
FIG. 13 is a partial plan view showing the main part of the vertical MOSFET chip according to the fifth embodiment of the present invention. In FIG. 13, the surface layer of the parallel pn structure and the surface structure of the element formed thereon are omitted. As shown in FIG. 13, the fifth embodiment is different from the planar pattern shown in FIG. 1 of the first embodiment in that the second parallel pn structure portion 2A of the withstand voltage portion is not a stripe pattern but the p partition region 20 is n. The configuration is such that it is discretely arranged so as to be surrounded by the region 19. In this case, the n region 22 is provided along the four sides of the rectangular chip. The configuration of the active part is the same as in the first embodiment.

The p partition region 20 is a columnar region in which the cross-sectional shape parallel to the surface of the second parallel pn structure portion 2A forms a substantially circular shape (including an ellipse and an oval shape). In the example illustrated in FIG. 13, the arrangement pattern of the p partition regions 20 is a hexagonal close-packed lattice shape, but may be a square lattice shape or the like. The area of the cross section of the columnar region constituting the p partition region 20 parallel to the surface of the second parallel pn structure portion 2A extends from the surface of the second parallel pn structure portion 2A to the n ⁺⁺ drain layer 11. It is constant.

  The diameter of the circle in the cross section of the p partition region 20 is smaller than the width of the p partition region 13 of the first parallel pn structure portion 1 of the active part. In the fifth embodiment, since the p partition regions 20 are discretely arranged, potential wraparound does not occur, and a guard ring can be used as the breakdown voltage structure.

Similar to the first embodiment, the p ⁺ region 14 may be provided only in the p partition region 13 of the first parallel pn structure portion 1. In this case, the manufacturing method is the same as in the first embodiment. Similarly to the second embodiment, the p ⁺ region 14 is provided in the p partition region 13 of the first parallel pn structure portion 1 and the p partition region 20 of the second parallel pn structure portion 2A is p. A configuration in which the ⁺ region 27 is provided may be employed. In this case, the manufacturing method is the same as that of the second embodiment. However, in any case, the patterning of the mask oxide film 33 is changed in accordance with the pattern of the parallel pn structure shown in FIG. 13, and the pattern of the trench is changed.

Embodiment 6 FIG.
FIG. 14 is a partial plan view showing the main part of the vertical MOSFET chip according to the sixth embodiment of the present invention. In FIG. 14, the surface layer of the parallel pn structure and the surface structure of the element formed thereon are omitted. As shown in FIG. 14, in the sixth embodiment, in the planar pattern shown in FIG. 13 of the fifth embodiment, the first parallel pn structure portion 1A of the active portion is not a stripe pattern but the p partition region 13 is n. The configuration is such that it is discretely arranged so as to be surrounded by the drift region 12. The configuration of the withstand voltage portion is the same as that of the fifth embodiment.

The p partition region 13 is a columnar region in which the cross-sectional shape parallel to the surface of the first parallel pn structure portion 1A forms a substantially circular shape (including an ellipse and an oval shape). In the example illustrated in FIG. 14, the arrangement pattern of the p partition regions 13 is a hexagonal close-packed lattice shape, but may be a square lattice shape or the like. The area of the cross section of the columnar region constituting the p partition region 13 parallel to the surface of the first parallel pn structure portion 1A extends from the surface of the first parallel pn structure portion 1A to the n ⁺⁺ drain layer 11. It is constant.

  Further, when the cross-sectional shapes of the p partition region 13 and the p partition region 20 are both circular, the diameter of the circle of the p partition region 20 in the pressure-resistant portion is smaller than the diameter of the circle of the p partition region 13 in the active portion. In the sixth embodiment, since the p partition regions 13 and 20 are discretely arranged, potential wraparound does not occur, and a guard ring can be used as a breakdown voltage structure.

Similar to the first embodiment, the p ⁺ region 14 may be provided only in the p partition region 13 of the first parallel pn structure portion 1A. In this case, the manufacturing method is the same as in the first embodiment. Similarly to the second embodiment, the p ⁺ region 14 is provided in the p partition region 13 of the first parallel pn structure portion 1A, and the p partition region 20 of the second parallel pn structure portion 2A is p. A configuration in which the ⁺ region 27 is provided may be employed. In this case, the manufacturing method is the same as that of the second embodiment. However, in any case, the patterning of the mask oxide film 33 is changed in accordance with the pattern of the parallel pn structure shown in FIG. 14, and the pattern of the trench is changed.

  As described above, the present invention is not limited to the above-described embodiments, and various modifications can be made. For example, dimensions and concentrations such as thickness and width are examples, and the present invention is not limited to these numerical values. Further, an element other than a MOSFET, such as an IGBT (insulated gate bipolar transistor) or a bipolar transistor, may be formed on the parallel pn structure. In each of the above-described embodiments, the first conductivity type is n-type and the second conductivity type is p-type. However, in the present invention, the first conductivity type is p-type and the second conductivity type is n-type. The same holds true.

  As described above, the present invention is useful for high-power semiconductor devices, and in particular, it is possible to achieve both high breakdown voltage and large current capacity of MOSFETs, IGBTs, bipolar transistors, etc. having a parallel pn structure in the drift portion. Suitable for semiconductor devices that can be used.

1 is a partial plan view showing a main part of a semiconductor device according to a first embodiment of the present invention; It is a longitudinal cross-sectional view which shows the cross-sectional structure in the cutting line A-A 'in FIG. It is a longitudinal cross-sectional view which shows the cross-sectional structure in the middle of manufacture of the semiconductor device concerning Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the cross-sectional structure in the middle of manufacture of the semiconductor device concerning Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the cross-sectional structure in the middle of manufacture of the semiconductor device concerning Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the cross-sectional structure in the middle of manufacture of the semiconductor device concerning Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the cross-sectional structure in the middle of manufacture of the semiconductor device concerning Embodiment 1 of this invention. It is a fragmentary top view which shows the principal part of the semiconductor device concerning Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the cross-sectional structure in the middle of manufacture of the semiconductor device concerning Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the cross-sectional structure in the middle of manufacture of the semiconductor device concerning Embodiment 2 of this invention. It is a fragmentary top view which shows the principal part of the semiconductor device concerning Embodiment 3 of this invention. It is a fragmentary top view which shows the principal part of the semiconductor device concerning Embodiment 4 of this invention. It is a fragmentary top view which shows the principal part of the semiconductor device concerning Embodiment 5 of this invention. It is a fragmentary top view which shows the principal part of the semiconductor device concerning Embodiment 6 of this invention. It is a longitudinal cross-sectional view which shows the cross-sectional structure in the middle of manufacture of the semiconductor device with insufficient digging of a trench.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1A 1st parallel pn structure part 2,2A 2nd parallel pn structure part 11 Low resistance layer (n ⁺⁺ drain layer) of 1st conductivity type
12 First conductivity type semiconductor region (n drift region)
13, 20 Second conductivity type semiconductor region (p partition region)
14 First inner region (p ⁺ region)
19 n region 27 second inner region (p ⁺ region)
31 Low conductivity layer of the first conductivity type (n ⁺⁺ semiconductor substrate)
32, 32a, 32b, 32c Epitaxially grown first conductivity type semiconductor (n semiconductor layer)
34 1st trench 35 2nd trench 36, 36a, 36b 2nd conductivity type semiconductor (p semiconductor) which fills a trench
38, 38a, 38b Second conductivity type semiconductor filling the trench (p ⁺ semiconductor)

Claims (19)

A semiconductor device having a parallel pn structure in which a first conductivity type semiconductor region and a second conductivity type semiconductor region are alternately and repeatedly joined on a low resistance layer of the first conductivity type,
The parallel pn structure includes a first parallel pn structure portion in which a repetition cycle of a junction between the first conductivity type semiconductor region and the second conductivity type semiconductor region is a first cycle; A second parallel pn structure portion having a second period shorter than the period;
A control electrode provided on the first parallel pn structure portion via an insulating film;
An input electrode that is provided on the first parallel pn structure portion and injects electrons into the first conductivity type semiconductor region of the first parallel pn structure portion by applying a voltage to the control electrode;
An output electrode provided on the opposite side of the parallel pn structure of the low resistance layer;
Have
In the first parallel pn structure portion, the impurity concentration of the second conductivity type semiconductor region is higher than that of the first outer region near the junction with the first conductivity type semiconductor region. Inside the region and in the first inner region from the surface of the first parallel pn structure portion to a predetermined depth,
In the second parallel pn structure portion, the impurity concentration of the second conductivity type semiconductor region is greater than the second outer region closer to the junction with the first conductivity type semiconductor region than the second outer region. Inside the region and in the second inner region from the surface of the second parallel pn structure part to a predetermined depth,
The width of the first outer region in the direction perpendicular to the boundary surface with the first inner region and the width of the second outer region perpendicular to the boundary surface with the second inner region A semiconductor device characterized by having substantially the same width in any direction. The region having a higher impurity concentration than the second outer region in the second inner region is provided in a central portion of the second conductivity type semiconductor region of the second parallel pn structure portion. The semiconductor device according to claim 1. An area of a cross section of the first inner region parallel to the surface of the parallel pn structure is larger than an area of a cross section of the second inner region parallel to the surface of the parallel pn structure. The semiconductor device according to claim 1 or 2. The semiconductor device according to claim 1, wherein the first inner region is deeper than the second inner region with respect to the surface of the parallel pn structure. The semiconductor device according to claim 1, wherein an impurity concentration of the first inner region is higher than an impurity concentration of the second inner region. The semiconductor device according to claim 1, wherein an impurity concentration of the first outer region is higher than an impurity concentration of the second outer region. An impurity concentration of the first conductivity type semiconductor region of the first parallel pn structure portion is higher than an impurity concentration of the first conductivity type semiconductor region of the second parallel pn structure portion. The semiconductor device according to claim 1. The impurity concentration of the second conductivity type semiconductor region of the first parallel pn structure portion is higher than the impurity concentration of the second conductivity type semiconductor region of the second parallel pn structure portion. The semiconductor device according to claim 1. The semiconductor device according to claim 1, wherein the second parallel pn structure portion is disposed at a peripheral edge portion of the first parallel pn structure portion. 2. The planar pattern of the parallel pn structure is a stripe shape.
The semiconductor device as described in any one of -8. The first parallel pn structure portion is disposed at the center of the element region having a rectangular planar shape, and the first conductivity type of the first parallel pn structure portion disposed at the center of the element region The first parallel pn structure portion is disposed at a peripheral portion along a side perpendicular to the longitudinal direction of the semiconductor region, and the first conductivity type of the first parallel pn structure portion disposed at the center of the element region 11. The semiconductor device according to claim 10, wherein the second parallel pn structure portion is disposed at a peripheral portion along a side parallel to a longitudinal direction of the semiconductor region. 12. The semiconductor device according to claim 9, wherein at least a part of the second parallel pn structure part constitutes at least a part of a breakdown voltage structure. Epitaxially growing a first conductivity type semiconductor having a higher resistance than the low resistance layer on a low resistance layer made of the first conductivity type semiconductor;
Forming a trench in the semiconductor layer of the first conductivity type stacked on the low resistance layer by the epitaxial growth;
A step of epitaxially growing a second conductivity type semiconductor in the trench formed in the first conductivity type semiconductor layer, and filling the trench with the second conductivity type semiconductor region;
After filling the trench, a control electrode and an input electrode for injecting electrons into the first conductivity type semiconductor layer by applying a voltage to the control electrode on the first conductivity type semiconductor layer. Forming an output electrode on the opposite side of the low-resistance layer to the first conductivity type semiconductor layer; and
Including
When forming a trench in the semiconductor layer of the first conductivity type, forming two or more different width and period trenches in the same element region,
In the middle of filling the trench with the second conductivity type semiconductor region, before the narrow trench is completely filled, the impurity concentration of the second conductivity type semiconductor region is changed high, and the changed impurity concentration is increased . Completely fill all trenches with semiconductor,
By filling the trench with the second conductive type semiconductor region, the first conductive type semiconductor layer and the second conductive type semiconductor region are alternately and repeatedly joined on the low resistance layer, In addition, the first parallel pn structure portion in which the repetition period of the junction between the first conductivity type semiconductor layer and the second conductivity type semiconductor region is the first period is shorter than the first period. Forming a parallel pn structure having a second parallel pn structure part having a second period;
Forming the control electrode on the first parallel pn structure portion via an insulating film;
A method of manufacturing a semiconductor device, comprising: forming the input electrode for injecting electrons into the semiconductor layer of the first conductivity type of the first parallel pn structure portion on the first parallel pn structure portion . 14. The process of forming a trench in the semiconductor layer is continued until the narrowest trench reaches the low resistance layer when forming the trench in the first conductivity type semiconductor layer. Semiconductor device manufacturing method. When forming a trench in the semiconductor layer of the first conductivity type, a first trench having a first width and period, and a second having a second width and period at a peripheral portion of the first trench. 15. The method of manufacturing a semiconductor device according to claim 13, wherein a trench is formed. When forming a trench in the semiconductor layer of the first conductivity type, the second width and period of the second trench are made shorter than the first width and period of the first trench. A method for manufacturing a semiconductor device according to claim 15. 15. The method for manufacturing a semiconductor device according to claim 13, wherein when the trench is formed in the semiconductor layer of the first conductivity type, a planar pattern of the trench is formed in a stripe shape. When forming a trench in the semiconductor layer of the first conductivity type, a first trench having a first width and period in a central portion of an element region having a rectangular planar shape, and the central portion of the element region A first trench having a first width and period at a peripheral portion along a side perpendicular to the longitudinal direction of the first trench, and a side parallel to the longitudinal direction of the first trench in the central portion of the element region 18. A second trench having a second width and period is formed at the periphery.
The manufacturing method of the semiconductor device as described in any one of Claims 1-3. When forming a trench in the semiconductor layer of the first conductivity type, the second width and period of the second trench are made shorter than the first width and period of the first trench. A method for manufacturing a semiconductor device according to claim 18.

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