JP4865653B2 - Image processing device - Google Patents

Description

  The present invention relates to an image processing apparatus that images an electronic component and performs image processing on the imaged electronic component in order to detect or recognize the position of the electronic component.

  Conventionally, an electronic component mounting apparatus for mounting an electronic component on a substrate is known. In this electronic component mounting apparatus, in order to accurately mount the electronic component at a predetermined position on the substrate, the electronic component sucked by the suction head of the electronic component mounting machine is imaged, and the electronic component image is processed to obtain the electronic component. Position detection (part center and part inclination detection), so-called component recognition is performed, and the mounting position is corrected based on the recognition result to mount the component.

  FIG. 21 is a block diagram illustrating a configuration of an image input unit of a conventional image processing apparatus. FIG. 21A illustrates a configuration using one CPU, and FIG. 21B illustrates a configuration using two CPUs. It is a figure which shows a structure.

  The image input unit includes an input circuit 7 that converts an image of an electronic component captured by the standard camera 4 or the high resolution camera 5 into a digital image, an image memory 8 that stores the image converted into a digital image, and an image memory 8. CPUs (arithmetic units) 10 and 11 for processing the image data.

  Conventionally, a configuration (FIG. 21A) in which image processing calculation is processed by a single CPU 10 is common. In this case, for example, even when there are two processes A and B that can be processed in parallel, this process is performed. A and process B were sequentially processed by one CPU 10.

  However, in order to increase the resolution of an image obtained by photographing an electronic component, increase the number of electrodes of the electronic component, and increase the accuracy of the positioning result, the image processing is becoming heavier. For example, in a ball component in which the electrodes are ball-shaped electronic components, the number of ball-shaped electrodes may eventually exceed 10,000, and the current CPU processing speed may not satisfy the required time of the device. .

  In the configuration of the conventional image input unit shown in FIG. 21A, a very high performance CPU is required, and there is a problem that no compatible CPU exists or the cost becomes high.

  Therefore, in order to increase the speed of image processing, parallel processing of image processing is being studied. As shown in FIG. 21B, in addition to the CPU 10, a CPU 17 is provided to make a plurality of CPUs to realize parallel processing. A configuration has been proposed (refer to Patent Document 1 and Patent Document 2 for distributed processing of image processing).

JP-A-8-44678 Japanese Patent No. 3646420

  However, in the case of a configuration in which a plurality of CPUs are provided, it is necessary to use a configuration using an expensive image memory with a wide bandwidth so that the image memory can withstand access from each CPU. That is, considering frequent access from both CPUs, it is necessary to provide an image memory with a fast access time and a high operation clock frequency so that accesses do not collide. In this case, there is a problem that there is no image memory that satisfies the requirement, or that the image memory becomes expensive.

  In particular, in the case of an image processing apparatus used in an electronic component mounting apparatus, not all of the electronic components handled have a heavy image processing load for component recognition, and such components are a very small number of limited components. If an expensive hardware resource is prepared in accordance with a rarely generated high-load process, there is a possibility that the device becomes uselessly expensive.

  The present invention has been made in view of the above points, and an object of the present invention is to provide an image processing apparatus capable of improving the image processing capability even when configured with an inexpensive CPU or image memory.

In order to achieve the above object, the present invention (Claim 1)
First storing the image of the image electronic components shooting and the second image memory,
A first CPU for processing an image stored in the first image memory;
A second CPU for processing an image stored in the second image memory;
The first CPU processes an image in a set image area among images in the first image memory, and the second CPU sets an image in the second image memory in the first image memory. An image in which an image in an image area different from the image area being processed is processed in parallel with the image processing by the first CPU, thereby processing the captured image of the electronic component and recognizing the electronic component A processing device comprising:
The first and second image memories and the first CPU are provided in the first and second image input systems, respectively.
The first CPU provided in the first image input system processes the image stored in the second image memory provided in the second image input system. Functions as a CPU,
The first CPU provided in the second image input system processes the image stored in the second image memory provided in the first image input system. To function as a CPU,
and,
The first CPU provided in each of the first and second image input systems sets priorities for processing performed as the main CPU and auxiliary processing functioning as the second CPU and performed as the sub CPU. The first CPUs mutually assist each other by distributed processing .

  The first and second CPUs process images containing different lead terminal arrays, images containing different sides or corners, or images of ball electrodes in different regions, respectively, and lead terminal positions, sides or Recognizes corner outlines or ball electrodes.

The present invention (Claim 5)
First storing the image of the image electronic components shooting and the second image memory,
A first CPU for processing an image stored in the first image memory;
A second CPU for processing an image stored in the second image memory;
The first CPU processes the image stored in the first image memory with a predetermined recognition parameter value, and the second CPU converts the image stored in the second image memory to the first CPU. An image processing apparatus for processing an image of the captured electronic component to recognize the electronic component by processing with a recognition parameter value different from the predetermined recognition parameter value in parallel with the image processing by
The first and second image memories and the first CPU are provided in the first and second image input systems, respectively.
The first CPU provided in the first image input system processes the image stored in the second image memory provided in the second image input system. Functions as a CPU,
The first CPU provided in the second image input system processes the image stored in the second image memory provided in the first image input system. To function as a CPU,
and,
The first CPU provided in each of the first and second image input systems sets priorities for processing performed as the main CPU and auxiliary processing functioning as the second CPU and performed as the sub CPU. The first CPUs mutually assist each other by distributed processing .

The present invention (Claim 6)
First storing the image of the image electronic components shooting and the second image memory,
A first CPU for processing an image stored in the first image memory;
A second CPU for processing an image stored in the second image memory;
The first CPU inspects the image stored in the first image memory by a predetermined algorithm, and the second CPU uses the image stored in the second image memory as an image by the first CPU. An image processing apparatus that inspects an electronic component by processing an image of the captured electronic component by inspecting with an algorithm different from the predetermined algorithm in parallel with processing ,
The first and second image memories and the first CPU are provided in the first and second image input systems, respectively.
The first CPU provided in the first image input system processes the image stored in the second image memory provided in the second image input system. Functions as a CPU,
The first CPU provided in the second image input system processes the image stored in the second image memory provided in the first image input system. To function as a CPU,
and,
The first CPU provided in each of the first and second image input systems sets priorities for processing performed as the main CPU and auxiliary processing functioning as the second CPU and performed as the sub CPU. The first CPUs mutually assist each other by distributed processing .

  At this time, if the inspection result is determined to be NG by one of the first CPU and the second CPU, if the other CPU is still performing an inspection using a different algorithm, A means for issuing an interrupt for interrupting the processing may be provided.

  According to the present invention, images of electronic components are stored in different image memories, and images in different areas of the images stored in the respective image memories are distributed by different CPUs for parallel processing. The processing speed can be increased to shorten the component recognition time, and high-speed component recognition can be performed with an inexpensive configuration without using expensive hardware resources (CPU, image memory).

  DETAILED DESCRIPTION Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram illustrating an example of a main part of an image processing apparatus and its peripheral configuration in an electronic component mounting apparatus.

  In this electronic component mounting apparatus, a suction nozzle 1 for sucking an electronic component (hereinafter simply referred to as a component) 2 and setting it to an imaging position, and a component substrate (not shown) such as movement of the suction nozzle 1 and driving of the illumination device 3 are shown. ) Machine control device 15 that controls the mounting operation on top, standard camera 4 and high-resolution camera 5 that function as an imaging device for imaging component 2, and image processing that processes the captured image and recognizes the component And the device 14.

  The image processing apparatus 14 includes an input circuit 7 that converts an image of a part captured by the cameras 4 and 5 into a digital image, an image memory 8 that stores the image converted into a digital image, a work memory 9, and an image memory 8. An arithmetic circuit (CPU) 10 that performs arithmetic processing of data, a component data storage memory 12, an interface 13, and a control CPU 11 that controls the flow of data between each device or memory and calculates data necessary for component mounting. The In addition, a monitor 6 for displaying the captured image or the processed image is provided.

  The machine control device 15 transmits the component data to the image processing device 14 via the interface 13. The image processing device 14 stores the received component data in the component data storage memory 12. The machine control device 15 usually selects the standard camera 4 or the high-resolution camera 5 according to the type of component, particularly the electrode size of the component, sucks the component 2 with the suction nozzle 1, and sets it at the imaging position of the selected camera. . At this time, the illumination device 3 is moved and lit so that it can be imaged by the selected camera, and the image processing device 14 is instructed to execute processing together with the selected camera channel information via the interface 13.

  The image processing device 14 controls the designated camera 4 or 5, digitizes the captured image of the component 2 by the input circuit 7, and stores it in the image memory 8 as multivalued image data. Then, the arithmetic circuit 10 processes the data in the image memory 8, detects the position of the lead tip, corner, etc., calculates the deviation between the component center and the adsorption center, and the component adsorption inclination, and positions the component (component Recognition).

  The machine control device 15 receives the component recognition result, moves the suction nozzle 1 to the mounting position, corrects the component suction displacement (deviation between the component center and the suction center and the suction angle displacement) according to the component recognition result, and performs the component 2 Is mounted at a predetermined position on the substrate.

In the present invention, in order to realize high-speed image processing, as shown in FIG. 2 (b), a plurality of image memories and a plurality of arithmetic circuits (CPU) is provided in the image processing apparatus 14. The configuration shown in FIG. 2A is a reference example used for explaining the present invention.

In FIG. 2A, the image data from the cameras 4 and 5 is read via the input circuit 7, distributed to the two image memories 8 and 19 via the distributor 18, and the image distributed to the image memory 8. The data is processed by the CPU 10, and the image data distributed to the image memory 19 is processed by the CPU 17. In this reference example, only the CPU 10 can access the image memory 8 and only the CPU 17 can access the image memory 19, and a plurality of CPUs do not access one memory. Parallel processing is possible without using a wide and expensive image memory.

By the way, it is conceivable that the CPU 17 is mounted only for parallel processing of dispersible processing because there is a time when the CPU 17 is not executing any processing, and the CPU 17 is not effectively used. Therefore, in the embodiment shown in FIG. 2 (b), in the electronic component mounting apparatus of the second head operation, and provide an input system of the image for each head, in performing the processing of each head in parallel to provide a CPU with each If there are surplus CPU resources, they are effectively utilized by each other to increase processing capacity. That is, the image data from the cameras 4 and 5 included in the first image input system is written into the first image memory 8 through the input circuit 7, but is distributed between the input circuit 7 and the image memory 8. A device 18 is provided to write the same data as the image memory 8 to the second image memory 19 at the same time.

Further, the image data from the standard camera 64 and the high resolution camera 65 included in the second image input system of the other head is written into the first image memory 22 through the input circuit 20 similar to the input circuit 7. However, a distributor 21 is provided between the input circuit 20 and the image memory 22, and the same data as the image memory 22 is written to the second image memory 23 at the same time.

The first CPU 17 provided in the second image input system accesses the second image memory 19 as a sub CPU (second CPU) of the first CPU 10 provided in the first image input system. Then, the CPU 10 executes the process by accessing the second image memory 23 as a sub CPU (second CPU) of the CPU 17. Only the CPU 10 can access the image memory 8, and only the CPU 17 can access the image memory 19. Further, only the CPU 17 can access the image memory 22, and only the CPU 10 can access the image memory 23.

  Also in the embodiment of FIG. 2B, since a plurality of CPUs do not access a single memory, parallel processing can be performed in a similar manner without using an expensive image memory with a wide bandwidth. Processing is possible.

As shown in FIG. 2, when a plurality of CPUs are provided, as shown in FIG. 3, one CPU 10 (or 17) is the main CPU (first CPU) , and the other CPU 17 (or 10) is the sub CPU ( The second CPU) , the auxiliary CPU can execute auxiliary processing, and distributed processing can be performed. FIG. 3A is a diagram showing a case where the sub CPU performs auxiliary processing within a range that does not hinder the processing imposed on the main CPU, and FIG. 3B varies the level of assistance depending on the priority of the auxiliary processing. FIG.

  In the example of FIG. 3A, the sub CPU executes the task 51 having the lowest priority among the application tasks 50 processed by the main CPU as an idle task. When there is a request for distributed processing (step S1), the secondary CPU distributes the task with the lowest priority (step S2) and transmits the result (result) (step S3). The work memory 9 stores a request processing state, a request, and a result. In this way, by performing auxiliary processing with an idle task with the lowest priority, each of the two CPUs can give priority to the original processing and mutually assist each other with distributed processing at a level that is not impossible. .

  Further, in the case where the level of assistance is changed depending on the priority of assistance processing, it can be realized by dynamically controlling the priority of idle tasks as shown in FIG. In this case, the degree of assistance can be increased as necessary, and flexible scheduling can be realized.

  As an auxiliary process request, for example, the urgency and load parameters 50a are added to the application task. Here, the urgency is a parameter indicating the degree of urgency that must be processed, and the load is a parameter indicating how much CPU power the process requires. The degree of urgency and the load may be set relatively for each distributed process. For example, if you are performing a process with a high degree of urgency, you will not accept any auxiliary process as a sub CPU, but if you are performing a process that is not too urgent or that has a light load This is a parameter that enables control such as accepting as a secondary CPU if the processing is light.

  The reception of the auxiliary process itself is performed by the task 52 having the highest priority, and the interruption process is performed even during the process of the main CPU. When accepting the auxiliary process, first, the urgency and load parameters 50a are read out and a request is awaited (step S4). At this time, the urgency and load are set in advance for the processing of the main CPU as well as the auxiliary processing.

  If the main CPU is in the process of accepting the auxiliary process, the priority of the execution task (for example, idle task) is determined by comparing the urgency and load of the process with the urgency and load of the request process. Then, the request is temporarily changed (step S5), and the request is transferred from the reception task to the execution task (step S6). The sub CPU executes the task in steps S7 to S9, sends a process end notification to the reception task, and the reception task restores the priority of the execution task. The relationship between the urgency and load parameters and the task priority may be created according to the system. The shared memory 9 stores a request processing state, a request, and a result, as in FIG.

  FIG. 4 is a table showing an example of objects to be processed in parallel in the image processing apparatus. FIG. 4A is a diagram showing a specific application example in which the same processing is distributed and processed in parallel. FIG. It is a figure which shows the specific example of application in the case of carrying out parallel processing of continuous processing.

  No. 4 in FIG. 1-No. 3 sets predetermined image areas in the image data stored in the image memories 8 and 19 according to the component terminals and component characteristics, and assigns the image processing of each area to the CPUs 10 and 17 for parallel processing. It is to increase the speed.

  No. 4 in FIG. 1, for example, as shown in FIG. 5 a, when recognizing the lead terminals provided on each side of the rectangular component 30, the lead terminals provided on one side of the component 30 stored in the image memory 8. An area 8 a including the column 30 a is set, and an area 19 a including the lead terminal array 30 b provided on the other side of the component 30 stored in the image memory 19 is set. The CPU 10 processes the image data of the image area 8a set in the image memory 8 and detects the position of each lead terminal in the lead terminal row 30a. In parallel with this process, the other CPU 17 processes the image data of the image area 19a set in the image memory 19 to detect the position of each lead terminal of the different lead terminal row 30b.

  No. 4 in FIG. 2, in the image processing for recognizing the outer shape of the rectangular component, the distributed processing is performed by performing the recognition processing for each side or each corner of the component by another CPU. For example, as shown in FIG. 5b, when recognizing the outer shape of a side or corner of a rectangular component 31, image regions 8b and 8c including one side 31a or corner 31b of the component 31 stored in the image memory 8 are displayed. Regions 19b and 19c including the other side 31c or corner 31d of the component 31 set and stored in the image memory 19 are set. The CPU 10 processes the image data in the regions 8b and 8c of the image memory 8 to recognize the outer shape of the side 31a or the corner 31b. In parallel with this processing, the other CPU 17 performs the processing of the region 19b, The image data of 19c is processed to recognize the outer shape of a different side 31c or corner 31d.

  No. 4 in FIG. 3, in image processing for recognizing a ball of a component having a ball-shaped electrode on the bottom surface, different image areas are set, and recognition processing is performed by a separate CPU for each area to perform distributed processing. For example, as shown in FIG. 5c, in the case of the component 32 having a large number of ball electrodes 32a, one image area 8d including the ball electrode is set in the image of the component 32 stored in the image memory 8, and the image memory In the image of the component 32 stored in 19, an area 19 d different from the area 8 d including other ball electrodes is set. The CPU 10 processes the image data in the area 8d of the image memory 8 to detect the position of each ball electrode in this area, and in parallel with this processing, the other CPU 17 performs the image of the area 19d in the image memory 19. The data is processed to detect the position of each ball electrode in this area 19d.

  In addition, No. 4 in FIG. 4, in image processing for matching imaging data of components with pre-registered component data, the imaging data is divided into a plurality of blocks, and recognition processing is performed by different CPUs for each block. It can be performed. In other words, the matching region is divided, and the correlation operation for obtaining the matching is performed in parallel by distributed processing to increase the speed.

  No. 4 in FIG. 5 is an application to processing that changes the conditions and adopts a good processing result. If the processing is not successful, if it does not work, it can be retried by changing the conditions and reprocessing. When performing, both processes are performed at the same time, the results are compared, and a good process result is adopted, and this parallel processing can greatly reduce the processing time.

  Such distributed / parallel processing of retry processing may be applied to retry processing of an edge determination threshold value at the time of component lead detection, for example.

  Conventionally, filter calculation values for model leads are acquired in advance for each filter type and size, and a reference edge detection threshold value is determined based on the result, corresponding to variations in reflection of leads due to differences in lots, etc. Therefore, the edge determination threshold value is adjusted by retry processing according to the captured image. If the terminal of the component is dark in the captured image and the edge cannot be detected with the default threshold value, the threshold value will be lowered, and if there is a noise component, the extra edge will be detected. And retry to detect only correct leads. In this example, the edge determination threshold corresponds to the recognition parameter value.

  FIG. 6 is a diagram for explaining the relationship between the result of the filtering process (DOG filtering process (Marr & Posio's Difference-Of-Gaussian filtering process)) and the edge determination threshold value, and FIG. 6 (b) is a graph showing the density value at the position of the scan line L in FIG. 6 (a), and FIG. 6 (c) is a graph showing the result of the filter processing. FIG. 6D is a graph showing the amount of change at the zero-cross point in FIG. 6C when the threshold value is changed.

  In FIG.6 (c), the zero crossing point of a filter calculation result is an edge. Depending on the DOG filter, it is easy to react to a slight change in density, and not all the zero-cross points are lead edges. In the case of the lead edge, the filter reaction value becomes large, so that the amount of change before and after the zero cross point of the filter result is a certain constant value (= edge determination threshold = filter threshold) as shown in FIG. The above is determined as the lead edge.

  As shown in FIG. 7, when there is a lead terminal 41 with poor reflection, the number of leads that can be detected decreases if the filter threshold 42 is too high with respect to the amount of change in the lead edge portion, as shown in FIG. In addition, when the noise 43 exists at the same interval as the lead terminal, if the edge determination threshold 44 is too low with respect to the change amount of the lead edge portion, noise other than the lead is erroneously detected, and the number of detections is large. turn into.

  In other words, if the number of detected leads is less than the specified number of leads, the edge determination threshold may have been too high, and conversely if the number of detected leads is large, the edge determination threshold is low. Maybe too. If there is an error in the number of leads, the number of leads will not change even if the threshold value is changed. Conversely, the threshold value should be changed only at a level where the number of normal leads does not change.

  When the present invention is used, lead detection is performed with the default filter threshold value 42 or 44 by one CPU, and a slightly lower filter threshold value 42 ′ or a higher filter threshold value 44 with another CPU. By performing the lead detection processing in parallel with ', it is possible to complete the retry processing by changing the recognition parameter value in the original processing time (the first one retry processing must be performed in parallel) Is possible). Then, for the two results obtained by the parallel processing, it is possible to determine whether or not the obtained result is correct by comparing the number of detected leads and the designated number of leads. Choose the correct result of the two results. If both are correct, the default setting result is selected.

  Even when retry processing is performed several times in succession, the recognition parameter value is changed by the same image processing, and the same image data is processed by using a different CPU for each recognition parameter value, thereby reducing the retry processing time by half. can do.

  Next, No. 4 in FIG. 1-No. The processing flow shown in FIG. 4 will be described with reference to FIG. In this example, the configuration shown in FIG. 2A is used as the configuration of the image input unit.

  The main CPU (for example, CPU 10) receives a command from the machine control device 15 shown in FIG. 1 via the interface 13 (step S11).

  Subsequently, the main CPU 10 operates the input circuit 7 shown in FIG. The image data is written in the image memories 8 and 19 at the same time by the distributor 18 shown in FIG. 2A (step S12).

  Next, the main CPU 10 calculates a region on the image to be distributed (step S13). Further, the main CPU sets parameters necessary for processing such as the processing area obtained in step S13, and transmits a request to the sub CPU (for example, the CPU 17 shown in FIG. 2A) (step S14).

  In step S15, the main CPU executes the distributed processing (1) assigned to itself.

  On the other hand, the sub CPU receives a request from the main CPU (step S17), and the processes of steps S17 to S19 by the sub CPU are executed in parallel with step S15.

  In step S18, the sub CPU determines the distributed processing type (step S18a). Depending on the situation and type, the priority of the task that executes the requested distributed processing (2) can be controlled, and a flexible mechanism can be incorporated.

  In step S18, each execution processing routine is called to execute the distributed processing (2) (steps S18b to S18e). When the processing ends, the result of the distributed processing (2) is transmitted to the main CPU 10 ( Step S19). In step S16, the main CPU receives the result of the distributed processing (2) requested to the sub CPU in step S14.

  The contents of the distributed process (1) performed in step S15 are the same as those in steps S18a to S18e of the distributed process (2) performed in step S18.

  The lead string detection process performed in each of steps S15 and S18 is No. in FIG. This is the process described in relation to FIG. Further, the ball group detection processing performed in steps S15 and S18 is No. 1 in FIG. 3, which is the processing described in relation to FIG. 5 c, and the outer shape detection processing is No. 3 in FIG. This is the process described in relation to FIG. Further, the divided region matching processing performed in steps S15 and S18 is No. in FIG. 4 processing.

  In addition, when the above-described dispersion processing (1) and (2) is required for the lead terminal rows, sides, corners, or ball electrode groups in other different regions, the same dispersion processing is necessary. The number of times is performed, and based on the lead terminal row, side, corner, or ball electrode group recognized by each image processing, the center of the part and the inclination of the part are calculated, and the part recognition ends.

  FIG. 10 shows No. 1 in FIG. 9 is a flowchart showing the operation of each CPU when the retry processing described in FIGS. 6 to 8 is distributed.

  First, the main CPU 10 operates the input circuit 1 to take an image (step S21). The same image data is written into the image memories 8 and 19 through the distributor 18 at the same time.

  The main CPU 10 creates a distributed processing request so as to change the recognition parameter value, that is, the edge determination threshold value, for detection of the lead string in the same area as that of itself (step S22).

  In step S23, the main CPU 10 transmits the request created in step S22 to the sub CPU 17.

  Thereafter, the main CPU 10 executes a lead detection process assigned to itself with a predetermined recognition parameter value (parameter (1)) (step S24).

  On the other hand, the sub CPU 17 operates in parallel with the main CPU 10 and receives a request from the main CPU 10 (step S27), determines the distributed processing type, calls the designated processing module (step S28), and sets parameters ( The lead detection process is performed with a recognition parameter value (parameter (2)) different from 1), that is, with a different edge determination threshold value (step S29), and the result of the process is transmitted to the main CPU 10 (step S30).

  On the other hand, the main CPU 10 receives the result of the lead detection process performed by the sub CPU 17 in step S29 (step S25).

  The main CPU 10 compares the number of detected leads obtained as a result of the process executed by itself in step S24 with the designated number of leads set in advance, and obtained as a result of receiving from the sub CPU 17 in step S25. The number of detected leads is compared with a preset number of specified leads, and the correct result is selected (step S26). If both are correct, the processing result of the main CPU is prioritized.

  The distributed processing described above can also be performed with the configuration shown in FIG. The configuration shown in FIG. 2B is the basic operation of the present invention in order to increase the processing capability by effectively using each other if there is a surplus CPU resource while each CPU performs the processing of each head in parallel. Is expanded.

  FIG. 11 is a flowchart showing the processing of the main CPU at the time of mutual assistance of distributed processing with the configuration shown in FIG.

  In the configuration shown in FIG. 2B, the CPU 10 is the main CPU and the CPU 17 is the sub CPU when viewed from the head having the cameras 4 and 5, and the CPU 17 is viewed from the head having the cameras 64 and 65. Is the main CPU, and CPU 10 is the sub CPU. In the following description, the configuration of the head having the cameras 4 and 5 will be described.

  The main CPU (CPU 10) receives a command from the machine control device 15 shown in FIG. 1 via the interface 13 (step S41).

  Subsequently, the main CPU operates the input circuit 7 shown in FIG. The image data is written into the image memories 8 and 19 at the same time by the distributor 18 shown in FIG. 2B (step S42).

  Next, the main CPU calculates an area on the image to be distributed (step S43). Further, the main CPU sets parameters necessary for processing such as the processing area obtained in step S43, and transmits a request to the sub CPU (CPU 17) (step S44).

  In step S45, the main CPU executes distributed processing (1) assigned to itself. On the other hand, the secondary CPU receives a request from the main CPU, and executes a distributed process (2) requested from the main CPU if there is a margin in its own resources. The distributed processes (1) and (2) are the same processes as the distributed processes (1) and (2) in steps S15 and S18 of FIG.

  The main CPU receives the result of the distributed processing (2) requested to the sub CPU in step S44 (step S46). However, if the request processing is completed at this point, the result can be received, but it may not be the case.

  In step S47, it is confirmed whether the requested distributed process (2) is completed. If completed, the process proceeds to the next process (process (3)) in step S51. If not, the process proceeds to step S48. .

  In step S48, the processing status is confirmed, and it is determined whether the distributed processing (2) is left to the sub CPU as it is, or whether the request is canceled and processed by itself. Whether the distributed processing (2) is left to the sub CPU as it is or whether the request is canceled is determined based on, for example, whether the elapsed time from the processing request has exceeded a predetermined time or from the sub CPU. Judgment can be made based on the report.

  If it is determined to wait for the process of the sub CPU, the process branches to step S46 and waits for the completion of the distributed process (2). If it is determined in step S48 that the request to the sub CPU is canceled, a request cancel is transmitted to the sub CPU (step S49), and the main CPU itself performs the distributed processing (2) (step S50).

[Reference example]
Next, a reference example shown in FIG. 12 will be described. The image input unit in FIG. 12 is configured to implement a mechanism for operating sequential sequential processing in parallel to improve the overall processing capability.

  This configuration is effective when there are two types of operations to be sequentially processed in the processing executed by the CPU and the processing occurs continuously. For example, the process is as shown in FIG.

  In the configuration shown in FIG. 12, the image data captured by the cameras 4 and 5 can be stored in the image memories 8 and 19 by the distributor 18, respectively. However, in this embodiment, switches 24 and 25 are provided for each of the two routes. That is, the storage state of the image data in the image memories 8 and 19 can be controlled as shown in FIG. 13 by ON / OFF control of the switches 24 and 25.

  As shown in FIG. 12, the CPU (arithmetic circuit) 10 is provided so that both the image memory 8 and the image memory 19 can be accessed by switching the switch 26. By switching 26, both the image memory 8 and the image memory 19 can be accessed.

  FIG. 14 is a flowchart illustrating the flow of processing in the configuration of FIG. In the figure, processing A and processing B correspond to processing A and processing B shown in FIG.

  FIG. 15 is a timing chart showing transition of processing executed by each CPU of FIG. In this figure, the image memory 8 is referred to as A side, and the image memory 19 is referred to as B side.

  In step S61 in FIG. 14, the switches 24 and 25 are turned ON, and the image data is taken into both sides, that is, both the image memory 8 and the image memory 19.

  First, the CPU 10 executes the process A on the data in the image memory 8 (A surface), and when the process A is completed, issues a request to start the process B to the CPU 17 (step S62).

  In step S63, since the image has already been captured at the first time passing through this step, it is skipped, and after the second time, in order to synchronize with the processing of the CPU 17, the end of the processing B by the CPU 17 is awaited.

  If it is confirmed that the processing B on the A side by the CPU 17 is completed, the switch 24 is turned on and the switch 25 is turned off so that only the image memory 8 (A side) can be stored.

  In step S64, an image is already captured for the first time, so the process is skipped, and images are captured for the second and subsequent times. At this time, only one of the two memories is updated by the control of the switch 24 and the switch 25 in step S63.

  Subsequently, in step S65, the switch 26 is switched so that the CPU 10 can perform the process A on the image newly captured in step S64. For example, at the first time, the CPU 10 can access the image memory 8.

  The CPU 17 performs steps S66 to S68 in parallel with steps S62 to S65 by the CPU 10. First, in step S66, execution of the process B is started by the request issued in step S62.

  If the process B is completed, in step S67, the switch 26 is switched to switch the memory accessed by the CPU 17 to the next image memory to be processed. For example, at the first time, since the CPU 17 can access the image memory 8, switching is performed so that the CPU 17 can access the image memory 19 in step S 67.

  CPU17 will notify that to CPU10, if the process B is complete | finished (step S68).

Next, a description will be given of a third embodiment according to claim 6 for detecting (determining) a chip standing which is an abnormality in the component suction state. For the sake of convenience, here, an example in which the image input unit of the reference example shown in FIG.

  This is because No. of FIG. No. 6 was added as a chip standing inspection. 1-No. Similarly to each processing of 5, the image input unit having the configuration shown in FIG. 2B can be applied.

  By the way, when trying to perform chip standing inspection (determination of component adsorption state) by image processing, FIG. 16 shows (a) normal adsorption (small rectangles at both ends are lead (electrode) terminals), As shown in the image of the difference in the error state in relation to the nozzles indicated by circles in (b) to (e), various situations are conceivable for the oblique standing of the chip. Therefore, it is impossible to determine the suction state in all situations using one determination algorithm. Therefore, it is necessary to classify the component adsorption states such as oblique standing, prepare a plurality of determination algorithms corresponding to each situation, and repeatedly perform the determination processing while sequentially switching the determination algorithms. This will be specifically described below.

  FIG. 17 shows a flowchart when processing is performed in accordance with a chip standing (adsorption state) determination algorithm.

  In step S71, a value for binarization is obtained from the captured image by, for example, a discriminant analysis method, the image is binarized, and a labeling process for obtaining a block from the obtained binary image is performed (step S72).

  Next, it is determined whether the number of lumps is 1 or 2 from the labeling image, and if it is 1, the area is checked as the whole part, and if it is 2 as shown in FIG. The area ratio is checked (steps S73 to S75).

  It is determined whether the processing results in steps S73 to S75 are OK (the area is correct or the area ratio is 1) or NG. If the area ratio is not 1 as shown in the image of FIG. For example, the subsequent processing is canceled and NG processing is performed. If OK, the process proceeds to the next process (step S76).

  In step S77, the inertia spindle (nozzle center), which is the next process, is calculated to obtain a linear expression of the spindle.

  Usually, the cause of the slanting is the slant suction that occurs when the corner of the component enters the suction hole at the tip of the nozzle, so that the position of the component center shifts from the center of the nozzle. By utilizing this fact, as shown in FIG. 18B, whether or not the outer peripheral position of the lump acquired by labeling is present at a certain distance or more from the nozzle center (= image center) (large suction deviation). Is checked (step S78).

  It is determined whether the position check result is OK or NG. If it is NG, the subsequent processing is canceled and NG processing is performed. If OK, the process proceeds to the next process (step S79).

  In the case of normal suction as shown in FIG. 16A, the straight line circumscribing the four sides around the chip part is rectangular. In order to use this principle, four circumscribing lines are obtained, and it is determined whether or not the intersection angle of each side is within an allowable range of 90 ° ± α (step S80).

  It is determined whether the circumscribed line shape result is OK or NG. If it is NG, the subsequent processing is canceled and NG processing is performed. If OK, the process proceeds to the next process (step S81). Incidentally, as shown in FIG. 18 (c), when the angle of intersection of the circumscribing lines is greatly deviated from 90 °, it is determined that the NG is obliquely standing as in (c ′).

  Next, if the chip component is normally adsorbed, the area within the window equal to or greater than the binarization threshold is almost 100%. In order to use this, the outermost edge point on the inertial main axis obtained in step S77 is calculated, and a rectangular window (two small rectangles in FIG. 18D) perpendicular to the main axis is applied (step S82). ). The size of the window (determination rectangle to be acquired) is obtained by obtaining a general terminal size from the component size and setting it to the same size or teaching in advance.

  Thereafter, an area equal to or greater than the binarization threshold in the window applied above is obtained, and it is determined whether the area occupies a ratio equal to or greater than a certain value with respect to the window. That is, it is determined whether the area check result based on the number of pixels of the terminal portion for the window (rectangle) is OK or NG (step S83). Here, if NG, NG processing is performed, and if OK, OK processing is performed and the process is terminated. Incidentally, FIG. 18 (d) is NG because of the oblique standing shown in (d ').

  As described in detail above, when performing chip standing inspection by image processing, classify oblique standing states, prepare multiple judgment algorithms for each situation, and repeat judgment processing while sequentially switching judgment algorithms. Must be done.

  Therefore, when the number of CPUs is one as in the conventional image processing apparatus, it takes a long time because sequential processing must be performed even for a processing target capable of parallel processing. In particular, in order to obtain a determination result that is normal, it is necessary to apply all of the prepared determination algorithms and obtain an OK determination in all the processes, so the longest processing time is required. Since the normal state is overwhelmingly more frequent, the degree of influence on the production tact is extremely large.

Therefore, in FIG. Example 3 according to the present invention, which was made as a result of intensive studies so as to efficiently realize the chip standing inspection listed as 6, will be described below.

  FIG. 19 is a flowchart showing the inspection (judgment) processing procedure according to this embodiment.

  In the flowchart of the main CPU shown on the left side, first, in step S91, the main CPU operates the input circuit 1 in FIG.

  The captured image data is written into the image memories 8 and 19 at the same time by the distributor 18 in FIG.

  In step S92, the chip standing inspection algorithm considers a combination so that the processing time is almost equivalent, and is divided into two patterns as shown in FIG.

  The main CPU creates a distributed processing request to perform chip standing inspection with the algorithm pattern 2 for the chip parts on the same image as itself, and transmits the request to the sub CPU at step S93, and at step S94 to itself. The assigned chip standing inspection (algorithm pattern 1) is executed.

  Thereafter, in step S95, it is determined whether or not the processing of itself is interrupted by an interrupt (described later) from the other CPU. If it is interrupted, it is determined that the NG determination has already been confirmed by the inspection of the other CPU. I reckon.

  In step S96, if the inspection is normally completed without being interrupted, the inspection result is determined by its own processing. If it is NG, the processing of the other CPU is interrupted. Interrupt the other CPU.

  In step S98, the result of the chip standing inspection requested to the sub CPU in step S93 is received. In step S99, if it is determined as NG in either inspection, it is determined to be NG, and both are OK only. And select the result.

  On the other hand, the flowchart of the sub CPU shown on the right side is as follows. This operates in parallel with the process of step S94 by the main CPU.

  In step S101, when the request in step S93 is received from the main CPU, in step S102, the requested distributed processing type is determined, and the designated processing module is called.

  In step S103, chip standing inspection (algorithm pattern 2) is executed.

  Thereafter, in step S104, it is determined whether or not the processing of itself is interrupted by the other CPU. If it is interrupted, it is considered that the NG determination has already been confirmed by the inspection of the other CPU.

  In step S105, if the inspection is normally completed without being interrupted, the inspection result is determined by its own processing. If it is NG, the processing of the other CPU is interrupted. While interrupting the other CPU, in step S107, the result of distributed processing is transmitted to the main CPU.

  As described with reference to FIG. 17 and FIG. The chip standing inspection described in 6 requires an OK / NG determination process by sequentially testing a plurality of determination algorithms. Therefore, normally, a determination is made by a certain algorithm, and if it is OK, the re-determination is repeated by changing to the next algorithm. In this embodiment, a plurality of determination processes are efficiently performed in parallel, and the longest processing is performed. Time can be greatly reduced.

  In the case of such an OK / NG determination process, since the longest processing time is required for the determination of OK with high frequency, the effect is extremely great.

As described above, according to the third embodiment, the following effects can be obtained.

  (1) By decentralizing processing and performing parallel processing, the normal inspection time can be greatly shortened.

  (2) By providing a notification means for interrupting the processing by interruption, the inspection time at the time of error can be minimized.

Above-described one of the first and second embodiments, even in 3 performs parallel processing by distributed processing, it can be shortened component recognition time, use of the hardware resources of conventional performance (CPU, an image memory) The efficiency can be improved and the processing capacity can be improved, which is advantageous in terms of cost.

  In conventional distributed processing, the processing target data is shared by the same memory, so that the memory needs to be expensive, and even if each memory is stored and processed, the extra data copy is required. Processing has occurred. On the other hand, in the present invention, by using a distributor, the same data can be stored in two separate memories at the time of imaging. This makes it possible to construct an efficient distributed process while using hardware resources with conventional performance.

  Furthermore, in the present invention, each of the two CPUs prioritizes the original processing and adopts a scheduling method in which mutual processing is supported by distributed processing at a reasonable level, and the degree of assistance can be increased as necessary. It also incorporates a mechanism that can perform flexible scheduling.

  In the present invention, in the image processing apparatus of the electronic component mounting apparatus, application processing, which is image processing related to component recognition, is distributed and performed in parallel, so that the existing resources are not relied solely on hardware acceleration. Can maximize the efficiency of use, eliminate waste, and increase processing capacity.

The block diagram which shows an example of the principal part of the image processing apparatus in an electronic component mounting apparatus, and its periphery structure (A) is a block diagram showing an image input unit of a reference example used for explaining the present invention, (b) is a block diagram showing an example of an image input unit of the image processing apparatus according to the present invention . (A) is explanatory drawing which shows the case where an auxiliary | assistant process is performed in the range which does not interfere with the process imposed on own CPU, (b) shows the case where the level of assistance is fluctuate | varied with the priority of an auxiliary | assistant process. Illustration (A) is a table | surface figure which shows the example of the specific application process which distributes an independent process and performs parallel processing, (b) shows the example of the specific application process in the case of operating a sequential continuous process in parallel. Table Explanatory drawing showing an example of distributed processing of lead string detection Explanatory drawing showing an example of distributed processing for contour detection Explanatory drawing showing an example of distributed processing of ball electrode detection It is explanatory drawing explaining the relationship between the result of a filter, and an edge determination threshold value, (a) shows the lead part of a captured image, (b) is the density value of the position of the scan line L of (a). (C) is a graph showing the result of the filter, and (d) is a graph showing the amount of change at the zero cross point of (c). It is a figure explaining the relationship between the result of a filter and an edge determination threshold value, Comprising: It is explanatory drawing in case there exists a lead terminal with poor reflection, (a) shows the lead part of a picked-up image, (B) is a graph showing the result of the filter at the position of the scan line L in (a), and (c) is a graph showing the amount of change at the zero cross point in (b). It is explanatory drawing explaining the relationship between the result of a filter, and an edge determination threshold value, Comprising: It is a figure in case noise exists with the same space | interval as a lead terminal, (a) shows the lead part of a captured image. (B) is a graph showing the result of the filter of the position of the scan line L of (a), (c) is a graph showing the variation | change_quantity in the zero crossing point of (b). The flowchart which shows operation | movement of each CPU when the process shown to Fig.4 (a) is performed by main CPU and sub CPU. A flowchart showing the operation of each CPU when the retry process shown in FIG. 4A is performed by the main CPU and the sub CPU. A flowchart showing the operation of each CPU when the distributed processing shown in FIG. 4A is performed by the main CPU and the sub CPU. The block diagram which shows the further another structural example of the image input part of the image processing apparatus by this invention. Table for explaining the switching operation of the switch of FIG. Flowchart showing the flow of processing in the configuration shown in FIG. Timing chart showing processing transition in the configuration shown in FIG. Explanatory drawing showing the difference in the adsorption state of the chip Flowchart showing an example of chip standing judgment algorithm Explanatory drawing showing an image of an application example of the above algorithm The flowchart which shows the determination processing of the chip | tip standing inspection by this invention Chart showing examples of algorithm pattern classification for chip standing inspection It is a block diagram which shows the structure of the conventional image input part, (a) is a block diagram which shows the structure using one CPU, (b) is the block diagram which shows the structure using two CPUs

DESCRIPTION OF SYMBOLS 1 ... Adsorption nozzle 2 ... Electronic component 3 ... Illuminating device 4, 64 ... Standard camera 5, 65 ... High resolution camera 6 ... Monitor 7, 20 ... Input circuit 8, 19, 22, 23 ... Image memory 9 ... Working memory 10 , 17 ... CPU
11 ... Control CPU
DESCRIPTION OF SYMBOLS 12 ... Component data storage memory 13 ... Interface 14 ... Image processing device 15 ... Machine control device 16 ... Image input part 18, 21 ... Distribution circuit 24, 25, 26 ... Switch 30, 31, 32 ... Electronic component

Claims (7)

First storing the image of the image electronic components shooting and the second image memory,
A first CPU for processing an image stored in the first image memory;
A second CPU for processing an image stored in the second image memory;
The first CPU processes an image in a set image area among images in the first image memory, and the second CPU sets an image in the second image memory in the first image memory. An image in which an image in an image area different from the image area being processed is processed in parallel with the image processing by the first CPU, thereby processing the captured image of the electronic component and recognizing the electronic component A processing device comprising:
The first and second image memories and the first CPU are provided in the first and second image input systems, respectively.
The first CPU provided in the first image input system processes the image stored in the second image memory provided in the second image input system. Functions as a CPU,
The first CPU provided in the second image input system processes the image stored in the second image memory provided in the first image input system. To function as a CPU,
and,
The first CPU provided in each of the first and second image input systems sets priorities for processing performed as the main CPU and auxiliary processing functioning as the second CPU and performed as the sub CPU. An image processing apparatus characterized in that the first CPUs mutually assist each other by distributed processing .   The electronic component is an electronic component having a lead terminal. The first CPU processes an image area including a predetermined lead terminal of the electronic component stored in the first image memory, and the second CPU is the predetermined CPU. The image processing apparatus according to claim 1, wherein an image area of a second image memory including a lead terminal different from the lead terminal is processed to detect a position of the lead terminal in each image area.   The electronic component is an electronic component having at least two sides or corners, and the first CPU processes an image including a predetermined side or corner of the electronic component stored in the first image memory, and the second CPU 2. The method according to claim 1, further comprising: processing an image area of a second image memory including a side or corner different from the predetermined side or corner to recognize an outline of the side or corner in each image area. The image processing apparatus described.   The electronic component is an electronic component having a plurality of ball electrodes, the first CPU processes an image area including a predetermined ball electrode of the electronic component stored in the first image memory, and the second CPU The image processing apparatus according to claim 1, wherein an image area of a second image memory including a ball electrode different from a predetermined ball electrode is processed to detect a position of the ball electrode in each image area. . First storing the image of the image electronic components shooting and the second image memory,
A first CPU for processing an image stored in the first image memory;
A second CPU for processing an image stored in the second image memory;
The first CPU processes the image stored in the first image memory with a predetermined recognition parameter value, and the second CPU converts the image stored in the second image memory to the first CPU. An image processing apparatus for processing an image of the captured electronic component to recognize the electronic component by processing with a recognition parameter value different from the predetermined recognition parameter value in parallel with the image processing by
The first and second image memories and the first CPU are provided in the first and second image input systems, respectively.
The first CPU provided in the first image input system processes the image stored in the second image memory provided in the second image input system. Functions as a CPU,
The first CPU provided in the second image input system processes the image stored in the second image memory provided in the first image input system. To function as a CPU,
and,
The first CPU provided in each of the first and second image input systems sets priorities for processing performed as the main CPU and auxiliary processing functioning as the second CPU and performed as the sub CPU. An image processing apparatus characterized in that the first CPUs mutually assist each other by distributed processing . First storing the image of the image electronic components shooting and the second image memory,
A first CPU for processing an image stored in the first image memory;
A second CPU for processing an image stored in the second image memory;
The first CPU inspects the image stored in the first image memory by a predetermined algorithm, and the second CPU uses the image stored in the second image memory as an image by the first CPU. An image processing apparatus that inspects an electronic component by processing an image of the captured electronic component by inspecting with an algorithm different from the predetermined algorithm in parallel with processing ,
The first and second image memories and the first CPU are provided in the first and second image input systems, respectively.
The first CPU provided in the first image input system processes the image stored in the second image memory provided in the second image input system. Functions as a CPU,
The first CPU provided in the second image input system processes the image stored in the second image memory provided in the first image input system. To function as a CPU,
and,
The first CPU provided in each of the first and second image input systems sets priorities for processing performed as the main CPU and auxiliary processing functioning as the second CPU and performed as the sub CPU. An image processing apparatus characterized in that the first CPUs mutually assist each other by distributed processing .   If the inspection result is determined to be NG by one of the first CPU and the second CPU, if the other CPU is still executing an inspection using a different algorithm, the other CPU is processed. The image processing apparatus according to claim 6, further comprising means for issuing an interrupt to be interrupted.

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