JP4862402B2 - Solid-state image sensor - Google Patents

Description

  The present invention relates to a solid-state image sensor formed by divided exposure.

In recent years, video cameras and electronic cameras using solid-state imaging devices such as a CCD (Charge Coupled Device) type and a CMOS (Complementary Metal Oxide Semiconductor) type (or called an amplification type) have been widely used. A solid-state image sensor has a plurality of unit pixels arranged in a two-dimensional array.
FIG. 10 is a plan view of a unit pixel in a conventional CMOS solid-state imaging device, where (a) is an overall view and (b) is a partially enlarged view. 801 is a unit pixel, 802 is a field portion (element isolation region) formed by a LOCOS oxide film, 803a is a floating diffusion region, 805a is a source of a selection transistor, 806 is a metal wiring, 304c is a source of a reset transistor, Reference numeral 804a denotes a diffusion region for making contact with the substrate. Further, symbols 303b, 304b, 357b, 359b, 803b, 804b, 805b, 807 and 808 indicate contact portions for connecting to signal lines, GND (ground), Vdd (power supply) and the like not shown. Here, the floating diffusion region 803a is formed in a self-aligned manner using the gate 303 of the transfer transistor made of polysilicon, the gate 305 of the reset transistor, and the LOCOS oxide film of the field portion 802 as a mask for ion implantation. The

  By the way, a solid-state imaging device mounted on an electronic camera or the like is preferable because the amount of received light increases as the area of the effective pixel region increases. For this reason, large-scale solid-state image sensors are used in high-end machines such as digital single-lens cameras. On the other hand, as is well known, a semiconductor device such as a solid-state imaging device uses an exposure apparatus in its manufacturing process. However, the exposure apparatus has a limited area (exposure area) to be exposed at one time, and the element area is limited. Therefore, a technique has been proposed in which a single element is connected and exposed several times (Patent Document 1).

A large CMOS solid-state image sensor is manufactured by such a divided exposure technique. By the way, for example, when the gate 303 and the gate 305 are displaced in the d direction due to the variation in alignment, the gate 303 and the gate 305 are formed at the positions indicated by the dotted lines. Therefore, the area of the floating diffusion region 803a is larger than that in the original position.
That is, when misalignment between the gate 303 and the gate 305 with respect to the field portion 802 occurs in the X-axis direction or the Y-axis direction, the area of the floating diffusion region 803a changes. In multiple divided exposures, since the alignment accuracy generally varies for each divided exposure region, the area of the floating diffusion region 803a between the divided exposure regions is different. As a result, the voltage conversion gain also changes for each divided exposure area, and even if a subject with a uniform exposure amount is captured, the image output signal changes for each divided exposure area. Voltage conversion gain difference occurs as an image signal step, which causes a problem that image quality is significantly deteriorated. Therefore, in Patent Document 2, a polysilicon pattern that affects the operation of the solid-state imaging device is formed by batch exposure with a single mask.
Japanese Patent Application Laid-Open No. 09-190962 JP 2004-111866 A

  If the gate 303 of the transfer transistor and the gate 305 of the reset transistor are formed by batch exposure using a single mask as in the prior art described above, the influence of misalignment during exposure is eliminated. However, in the case of a lens having a wide exposure area, the pattern resolution is not as good as that of a lens having a narrow exposure area. For this reason, a gate length error occurs in the gate 303 of the transfer transistor and the gate 305 of the reset transistor. In particular, if there is a gate length error in the gate 303 of the transfer transistor, the transfer characteristics of the transfer transistor vary, which has a problem of affecting the image quality of the captured image.

  In view of the above problems, the object of the present invention is to suppress the discontinuity of the image signal generated at the boundary portion of the divided exposure and obtain a uniform image quality on the entire screen even if the unit pixels are arranged in an array by divided exposure. It is in providing a solid-state image sensor.

In order to achieve the above object, a solid-state imaging device according to the present invention is formed by divided exposure in which exposure is performed by dividing into a plurality of areas, and a photoelectric conversion unit that converts an optical signal into a signal charge, and the signal charge is transferred. A transfer transistor, a rectangular floating diffusion region for holding the transferred signal charge, an amplifying transistor for outputting the signal potential of the floating diffusion region, and a reset transistor for resetting the held signal charge; In the solid-state imaging device in which the unit pixels are arranged in a matrix, the gate of the transfer transistor and the gate of the reset transistor are exposed with the same mask so as to form a side on the side of the rectangular floating diffusion region. The rectangular floating diffusion region is disposed between the gate of the transfer transistor and the reset transistor. Each of the pixels is arranged in two locations, a region formed by the gate of the transfer transistor and a region formed by the gate of the reset transistor. sum of the areas of the floating diffusion region of each of the rectangular shape disposed in the two places in the pixels, characterized in that the division is constant regardless of the formed areas by exposure.

  In addition, an electrode is further provided at a position opposite to the gate of the transfer transistor and the gate of the reset transistor, and one of the floating diffusion regions arranged in the two locations is the transfer transistor. The other floating diffusion region is formed between the gate of the resetting transistor and the gate of the resetting transistor, and the electrode is connected to the transfer gate. The exposure transistor is positioned by exposure using the same mask as the gate of the transistor for resetting and the gate of the resetting transistor.

  Alternatively, the electrode is exposed with the same mask as the gate of the transfer transistor and the gate of the reset transistor, and the first electrode arranged in parallel to the gate of the transfer transistor and the gate of the transfer transistor And a second electrode exposed in the same mask as the gate of the reset transistor and arranged in parallel to the gate of the reset transistor.

  In particular, the electrode or the first electrode and the second electrode are set to a potential for accumulating charges in the floating diffusion region.

  According to the present invention, fluctuations in the pattern size of the gate of a transistor used in a solid-state imaging device, in particular, a transfer transistor that transfers signal charges from a photoelectric conversion unit that affects the image quality of a captured image are suppressed. The area is formed to be substantially constant regardless of the position shift due to the divided exposure. For this reason, the transfer characteristics and voltage conversion gain are uniform over the entire pixel area without depending on the area of the divided exposure, and it is possible to suppress the inconsistency of the image signal at the boundary of the divided exposure. .

  Hereinafter, embodiments of the solid-state imaging device according to the present invention will be described. First, the configuration of the entire solid-state imaging device common to each embodiment will be described. FIG. 8 is a plan view showing the entire solid-state image sensor, and the solid-state image sensor 700 is composed of a plurality of unit pixels 701. In the case of the figure, the configuration is 4 × 4 pixels. Each unit pixel 701 is provided with a selection drive signal line 707, a reset drive signal line 708, and a transfer drive signal line 709 from the vertical scanning circuit 702, and the signal charges accumulated in the photodiode (not shown) are The voltage is converted into a voltage and read by the constant current source circuit 704 to the vertical signal line 705 constituting the source follower circuit. The signal of each column read to each vertical signal line 705 is read in the horizontal direction by the reading circuit 703 and output from the output amplifier 706.

  A general circuit of each unit pixel 701 is as shown in FIG. Light from the subject is accumulated as signal charges in the photodiode 301, and the accumulated signal charges are transferred and held in the floating diffusion region (FD region) by the transfer transistor 302. The signal charge in the floating diffusion region is reset by the reset transistor 304 before the signal charge is transferred. The signal charge held in the floating diffusion region enters the gate 359 of the amplification transistor 358, is converted into a voltage, and is amplified. The selection transistor 356, the signal line 311 and the constant current source 310 constitute a source follower. When a signal for selecting an arbitrary row in the array is supplied to the gate 357 of the selection transistor, the amplified image signal is Read out to the signal line 311. Reference numeral 303 denotes a transfer transistor gate, and reference numeral 305 denotes a reset transistor gate.

Each embodiment will be described below.
(First embodiment)
FIG. 1A is a plan view of a unit pixel of the solid-state imaging device according to the first embodiment of the present invention. A region surrounded by a broken line is a unit pixel 101 corresponding to one pixel, and a horizontal direction on the paper is an X coordinate and a vertical direction is a Y coordinate. Reference numeral 102 denotes a photodiode that generates and accumulates charges corresponding to incident light, and 103a denotes a gate of a MOS type transfer transistor that transfers signal charges accumulated in the photodiode 102 to a floating diffusion region. For example, the gate 103a of the transfer transistor is formed of polysilicon having a thickness of 400 nm. Reference numeral 103 b denotes a contact portion for connecting the gate 103 a of the transfer transistor to the transfer drive signal line 709.

  108a and 109a are floating diffusion regions that temporarily hold signal charges transferred from the photodiode 102 by the transfer transistor. 104a is a gate of a MOS type reset transistor that resets the signal charges transferred to the floating diffusion regions 108a and 109a, and 104b is a contact portion for connecting the gate 104a of the reset transistor to the reset drive signal line 708. . Reference numeral 105a denotes a gate of an amplifying transistor that outputs the potential of the floating diffusion regions 108a and 109a as a voltage. Reference numeral 111 denotes a metal wiring that connects the floating diffusion regions 108a and 109a and the gate of the amplifying transistor by contact portions 108b, 109b, and 105b.

  106a is a gate of a MOS type selection transistor for selecting a pixel to be read, and 106b is a contact portion for connecting the gate 106a of the selection transistor to a selection drive signal line 707. Reference numeral 107 a denotes a source of the selection transistor, and 107 b denotes a contact portion for connecting the source of the selection transistor to the vertical signal line 705. 110a is a diffusion region for making contact with the substrate, 110b is a contact portion for grounding (not shown) the diffusion region 110a, 112 is a contact portion for connecting to a power source (Vdd), and 113 is a field portion. Show. Note that the circuit configuration of the unit pixel of the solid-state imaging device of the present embodiment is the same as that of FIG. 9 described in the prior art.

  In FIG. 1A, W is the width of the floating diffusion regions 108a and 109a in the X-axis direction, Lt is the length of the floating diffusion region 108a in the Y-axis direction, and Lr is the length of the floating diffusion region 109a in the Y-axis direction. Respectively. Assuming that the floating diffusion regions 108a and 109a are square, the area of the floating diffusion region 108a is W × Lt, and the area of the floating diffusion region 109a is W × Lr.

  In this embodiment, it is assumed that at least the gate 103a of the transfer transistor and the gate 104a of the reset transistor are formed by exposure with the same mask, and at least the field portion 113 is formed by exposure with a different mask. The floating diffusion regions 108a and 109a are formed in a self-aligned manner using the gate 103a of the transfer transistor, the gate 104a of the reset transistor, and the field portion 113 as an ion implantation mask.

Here, when divided exposure is performed, as described above, the positions of the gate 103a of the transfer transistor and the gate 104a of the reset transistor and the positions of the floating diffusion regions 108a and 109a are relatively shifted for each exposure area. . However, in this embodiment, even if a positional shift occurs due to the divided exposure, the sum of the area (W × Lt) of the floating diffusion region 108a and the area (W × Lr) of the floating diffusion region 109a is constant (formula 1 ).
(W × Lt) + (W × Lr) = constant (Expression 1)
This will be described in detail below. FIG. 1B shows a state in which the masks of the transfer transistor gate 103a and the reset transistor gate 104a are slightly displaced in the rotation direction, the X-axis direction, and the Y-axis direction during the divided exposure.

  Now, assuming that the area of the floating diffusion region 108a when the gate 103a of the transfer transistor is not displaced is S1, S1 is a portion surrounded by a rectangle (A1, B1, C1, D1). Similarly, when the area of the floating diffusion region 109a when the gate 104a of the reset transistor is not displaced is S2, S2 is a portion surrounded by a rectangle (A2, B2, C2, D2).

  On the other hand, if the area of the floating diffusion region 108a when the gate 103a of the transfer transistor is displaced is S1 ', S1' is a portion surrounded by a rectangle (A1, B1, C1 ', D1'). Similarly, assuming that the area of the floating diffusion region 109a when the gate 104a of the reset transistor is displaced is S2 ', S2' is a portion surrounded by a rectangle (A2, B2, C2 ', D2').

Here, the floating diffusion regions 108a and 109a are exposed with the same mask. Since the transfer transistor gate 103a and the reset transistor gate 104a, which serve as the mask, are exposed and formed with the same mask, misalignment occurs parallel to each other. Therefore, the relationship of (Formula 2) and (Formula 3) is established.
Side (A1, D1) + Side (A2, D2) = Side (A1, D1 ') + Side (A2, D2') ... (Formula 2)
Side (B1, C1) + Side (B2, C2) = Side (B1, C1 ') + Side (B2, C2') ... (Formula 3)
Assuming that the widths W of the floating diffusion regions 108a and 108b are equal, the sum of the sides is equal from the relationship of (Equation 2) and (Equation 3), so the area S1 when the floating diffusion region 108a is not displaced and the displacement The relationship between the area S1 ′ in this case, the area S2 in the case where the floating diffusion region 109a is not displaced, and the area S2 ′ in the case where the position is displaced is expressed by (Expression 4).
S1 + S2 = S1 ′ + S2 ′ (Expression 4)
As described above, in the structure of the unit pixel of the present embodiment, the floating diffusion region 108a is independent of the alignment accuracy between the gate 103a of the transfer transistor made of polysilicon and the gate 104a of the reset transistor with respect to the field portion 113. 109a is always constant. That is, the capacitance components of the floating diffusion regions 108a and 109a are also constant regardless of the alignment accuracy, and the gain for converting the signal charge into the voltage is also constant.

  Therefore, according to this embodiment, even when a CMOS (or amplification) solid-state imaging device is manufactured by divided exposure, the gate length error of the transfer transistor can be suppressed and the voltage conversion gain can be made constant over the entire pixel region. The image signal discontinuity does not occur at the divided exposure boundary, and a uniform image can be obtained. In this embodiment, even if there is a positional shift between the gate 103a of the transfer transistor made of polysilicon and the gate 104a of the reset transistor with respect to the field portion 113, the respective area variations of the floating diffusion regions 108a and 109a cancel each other. To change. Even if the width of the gate 103a of the transfer transistor and the width of the gate 104a of the reset transistor are different within a practical range, the sum of the areas of the floating diffusion regions 108a and 109a can be regarded as substantially constant.

(Second Embodiment)
FIG. 2 is a plan view of a solid-state imaging device according to the second embodiment of the present invention. In FIG. 2, unit pixels 201, 202, 203, and 204 indicated by broken lines are continuously formed vertically, and the reset transistor in the floating diffusion region uses the reset transistor of the adjacent unit pixel. It is configured. Here, the description will focus on the unit pixel 202, but the other unit pixels have the same configuration. 1 are the same as those in FIG.

  Reference numeral 205a denotes an amplifying transistor gate that outputs the potentials of the floating diffusion regions 208a and 209a as a voltage, and is connected to the metal wiring 211 via the contact portion 205b. Reference numeral 206a denotes a gate of a MOS type selection transistor for selecting a pixel to be read out, and 206b denotes a contact portion for connecting the gate 206a of the selection transistor to the selection drive signal line 707. Reference numerals 208a and 209a denote floating diffusion regions, and 208b and 209b denote contact portions for connecting the floating diffusion regions 208a and 209a to the metal wiring 211, respectively.

  Note that the circuit configuration of the unit pixel of the solid-state imaging device of the present embodiment is as shown in FIG. 9 denote the same components. Further, the selection transistor 356 and the amplification transistor 358 in FIG. 9 are interchanged, and the source of the amplification transistor 308 is directly connected to the read signal line 311 and the constant current source 310. As described above, even if the connection relationship between the selection transistor 356 and the amplification transistor 358 is changed, the drive and function thereof are the same as those in the first embodiment.

  Similarly to the first embodiment, misalignment of the transfer transistor gate 103a made of polysilicon and the reset transistor gate 104a with respect to the field portion 113 in the X-axis direction, the Y-axis direction, and the rotation direction is shifted. Even if this occurs, the area variation of the floating diffusion regions 208a and 209a changes in a direction that cancels each other. Accordingly, the capacitance components of the floating diffusion regions 208a and 209a are constant regardless of the alignment accuracy, and the gain for converting the signal charge into the voltage is also constant.

As described above, according to the present embodiment, even when a CMOS (or amplification) solid-state imaging device is manufactured by divided exposure, the gate length error of the transfer transistor is suppressed over the entire pixel region, and the voltage conversion gain is constant. The image signal discontinuity does not occur at the divided exposure boundary, and a homogeneous image can be obtained.
Furthermore, since the length of the metal wiring 211 can be shortened as compared with the first embodiment, the parasitic oxide film capacitance component of the metal wiring 211 is reduced, and a higher voltage conversion gain can be obtained. That is, the sensitivity and SN ratio of the solid-state imaging device are improved, and a higher quality image can be obtained.

(Third embodiment)
FIG. 4 is a plan view of a solid-state imaging device according to the third embodiment of the present invention. In FIG. 4, 301 is a unit pixel, 408a and 409a are floating diffusion regions, and 408b and 409b are contact portions for connecting the floating diffusion regions 408a and 409a to the metal wiring 411, respectively. 404a is a gate of a MOS type reset transistor that resets signal charges transferred to the floating diffusion regions 408a and 409a, and 404b is a contact portion for connecting the gate 404a of the reset transistor to the reset drive signal line 708. .

  Reference numeral 405a denotes a gate of an amplifying transistor that outputs the potential of the floating diffusion regions 408a and 409a connected via the contact portion 405b and the metal wiring 411 as a voltage. Reference numeral 406 a denotes a gate of a MOS type selection transistor for selecting a pixel to be read, and 406 b denotes a contact portion for connecting the selection transistor gate 406 a to the selection drive signal line 707.

  451a is an electrode made of polysilicon at a position facing the gate 103a of the transfer transistor and the gate 404a of the reset transistor in parallel, and 451b is a potential for turning off both the gate 103a of the transfer transistor and the gate 404a of the reset transistor. This is a contact portion for connecting a wiring (not shown) for supplying the electrode 451a. In addition, the same code | symbol as FIG. 1 shows the same thing.

  Here, the electrode 451a will be described. FIG. 5 is a cross-sectional view taken along the cross-sectional position (A1-A2) of FIG. 4, and the end where the electrode 451a and the floating diffusion regions 409a and 408a are positioned vertically is formed on the substrate 150. It is separated from the field part 113 by a distance Lf. The distance Lf is set to a value larger than the alignment accuracy of the electrode 451a made of polysilicon with respect to the field portion 113. On the other hand, the floating diffusion regions 409a and 408a are formed in a self-aligned manner using the gate 103a of the transfer transistor, the gate 404a of the reset transistor, the electrode 451a, and the field portion 113 as an ion implantation mask. . Therefore, also in the structure of the unit pixel of this embodiment, it depends on the alignment accuracy in the Y-axis direction between the position of the gate 103a of the transfer transistor, the gate 404a of the reset transistor, and the electrode 451a and the position of the field portion 113. In other words, the sum of the areas of the floating diffusion regions 408a and 409a is constant. As in the first embodiment, the positions of the gate 103a of the transfer transistor, the gate 404a of the reset transistor, and the electrode 451a and the position of the field portion 113 are displaced in the X-axis direction or the rotational direction. Even in this case, the areas are the same.

In this embodiment, the electrode 451a is given a potential for turning off both the gate 103a of the transfer transistor and the gate 404a of the reset transistor, and the surface of the substrate 150 under the electrode 451a is in the accumulation mode. In the electrode 451a, no parasitic capacitance is added to the capacitance components of the floating diffusion regions 408a and 409a.
Therefore, according to this embodiment, even when a CMOS (or amplification) solid-state imaging device is manufactured by divided exposure, the gate length error of the transfer transistor can be suppressed and the voltage conversion gain can be made constant over the entire pixel region. The image signal discontinuity does not occur at the divided exposure boundary, and a uniform image can be obtained.

(Fourth embodiment)
FIG. 6 is a plan view of a solid-state imaging device according to the fourth embodiment of the present invention. In FIG. 6, reference numeral 501 denotes a unit pixel, 508a and 509a denote floating diffusion regions, and 508b and 509b denote contact portions that connect the floating diffusion regions 508a and 509a to the metal wiring 511, respectively. Reference numeral 504a denotes a gate of a MOS-type reset transistor that resets signal charges transferred to the floating diffusion regions 508a and 509a, and reference numeral 504b denotes a contact portion for connecting the reset transistor gate 504a to the reset drive signal line 708. .

  Reference numeral 505a denotes a gate of an amplifying transistor that outputs the potential of the floating diffusion regions 508a and 509a connected via the contact portion 505b and the metal wiring 511 as a voltage. Reference numeral 506a denotes a gate of a MOS-type selection transistor for selecting a pixel to be read, and 506b denotes a contact portion for connecting the selection transistor gate 506a to the selection drive signal line 707.

  Reference numeral 551a denotes an electrode formed of polysilicon at a position facing the transfer transistor gate 103a in parallel. Reference numeral 551b connects a wiring (not shown) for applying a potential for turning off the transfer transistor gate 103a to the electrode 551a. It is a contact part. Reference numeral 552a denotes an electrode formed of polysilicon at a position facing the reset transistor gate 504a in parallel. Reference numeral 552b connects a wiring (not shown) for turning off the reset transistor gate 504a to the electrode 552a. It is a contact part. In addition, the same code | symbol as FIG. 1 shows the same thing.

  The electrode 551a and the electrode 552a are configured in the same manner as the electrode 451a of FIG. 5 described in the third embodiment. That is, when the electrode 451a in FIG. 5 is replaced with the electrode 551a and the floating diffusion region 409a is replaced with the floating diffusion region 509a, the distance Lf is determined by the alignment accuracy of the electrode 551a made of polysilicon with respect to the field portion 113. Therefore, the area of the floating diffusion region 509a is constant regardless of the alignment accuracy in the Y-axis direction between the position of the gate 103a and the electrode 551a of the transfer transistor and the position of the field portion 113. Become. Similarly, when the electrode 451a is replaced with the electrode 552a and the floating diffusion region 409a is replaced with the floating diffusion region 508a, the positions of the gate 504a and the electrode 552a of the reset transistor and the position of the field portion 113 are Regardless of the alignment accuracy in the X-axis direction, the area of the floating diffusion region 508a is also constant. Similar to the first embodiment, even when the position of the gate 504a and the electrode 552a of the reset transistor and the position of the field portion 113 are displaced in the Y-axis direction or the rotation direction, the area is the same. Become.

In this embodiment, the electrode 551a is given a potential to turn off both the gate 103a of the transfer transistor and the gate 404a of the reset transistor, and the surface of the substrate 150 under the electrode 551a is in the accumulation mode. Parasitic capacitance added to the capacitance components of the floating diffusion regions 508a and 509a does not occur in the electrode 551a.
Therefore, according to this embodiment, even when a CMOS (or amplification) solid-state imaging device is manufactured by divided exposure, the gate length error of the transfer transistor can be suppressed and the voltage conversion gain can be made constant over the entire pixel region. The image signal discontinuity does not occur at the divided exposure boundary, and a uniform image can be obtained.

(Fifth embodiment)
FIG. 7 is a plan view of a solid-state imaging device according to the fifth embodiment of the present invention. In FIG. 7, reference numeral 601 denotes a unit pixel, 608a denotes a floating diffusion region, and 608b denotes a contact portion that connects the floating diffusion region 608a to the metal wiring 611. Reference numeral 604a denotes a gate of a MOS type reset transistor that resets the signal charge transferred to the floating diffusion region 608a, and reference numeral 604b denotes a contact portion for connecting the reset transistor gate 604a to the reset drive signal line 708.

  Reference numeral 605a denotes a gate of an amplifying transistor that outputs the potential of the floating diffusion region 608a connected via the contact portion 605b and the metal wiring 611 as a voltage. Reference numeral 606a denotes a gate of a MOS type selection transistor for selecting a pixel to be read, and reference numeral 606b denotes a contact portion for connecting the selection transistor gate 606a to the selection drive signal line 707. In addition, the same code | symbol as FIG. 1 shows the same thing.

  In any of the first to fourth embodiments described above, there are two floating diffusion regions, but this embodiment has only one floating diffusion region 608a. In addition, the floating diffusion region 608a is located between the transfer transistor gate 103a and the reset transistor gate 604a. Since the gate 103a of the transfer transistor and the gate 604a of the reset transistor are exposed and formed simultaneously with the same mask, they are sandwiched between the X-axis direction, the Y-axis direction, and the rotation direction even if they are misaligned. The area of the part is always kept constant without changing. That is, the capacitance component of the floating diffusion region 608a is also constant regardless of the alignment accuracy, and the gain for converting the signal charge into voltage is also constant. Therefore, according to this embodiment, even when a CMOS (or amplification) solid-state imaging device is manufactured by divided exposure, the gate length error of the transfer transistor can be suppressed and the voltage conversion gain can be made constant over the entire pixel region. The image signal discontinuity does not occur at the divided exposure boundary, and a uniform image can be obtained.

  As described above in each embodiment, according to the present invention, the floating diffusion region of the amplifying unit that suppresses the gate length error of the transfer transistor, holds the signal charge transferred from the photodiode, and converts it into a voltage is provided. Since it is formed in a self-aligned manner and the area of the floating diffusion region is substantially constant regardless of the positional deviation in the exposure process, transfer characteristics and voltage conversion over the entire pixel region without depending on the divided exposure region And the inconsistency of the image signal at the boundary portion of the divided exposure can be suppressed. As a result, it is possible to provide a solid-state imaging device capable of obtaining uniform image quality over the entire screen.

It is a top view of a unit pixel of a solid-state image sensing device concerning a 1st embodiment of the present invention. It is a top view of a unit pixel of a solid-state image sensing device concerning a 2nd embodiment of the present invention. It is a circuit diagram of a unit pixel of a second embodiment. It is a top view of a unit pixel of a solid-state image sensing device concerning a 3rd embodiment of the present invention. It is sectional drawing of the electrode part of 3rd Embodiment. It is a top view of a unit pixel of a solid-state image sensing device concerning a 4th embodiment of the present invention. It is a top view of a unit pixel of a solid-state image sensing device concerning a 5th embodiment of the present invention. It is a whole block diagram of a general solid-state image sensor. It is a circuit diagram of a unit pixel of a general solid-state image sensor. It is a top view of the unit pixel of the solid-state image sensor of a prior art.

Explanation of symbols

101, 202, 301, 501, 601 ... unit pixel 102 ... photodiode 103a ... transfer transistor gate 104a ... reset transistor gate 108a, 109a, 208a, 209a, 408a, 409a .. Floating diffusion region 113... Field portion 302... Transfer transistor 304... Reset transistor 306, 356... Select transistor 308, 358 .. amplify transistor 451 a, 551 a, 552 a. . Electrodes 508a, 509a, 608a ... floating diffusion region

Claims (4)

Formed by divided exposure to divide and expose in multiple areas,
A photoelectric conversion unit that converts an optical signal into a signal charge;
A transfer transistor for transferring the signal charge;
A rectangular floating diffusion region for holding the transferred signal charge;
An amplifying transistor that outputs a signal potential of the floating diffusion region;
In a solid-state imaging device in which unit pixels each including a resetting transistor that resets the held signal charge are arranged in a matrix,
The gate of the transfer transistor and the gate of the reset transistor are arranged to be exposed with the same mask so as to form a side on the side of the rectangular floating diffusion region,
The rectangular floating diffusion region is formed in a self-aligned manner with the gate of the transfer transistor and the gate of the reset transistor, and a region formed with the gate of the transfer transistor in each pixel; The sum of the areas of the respective rectangular floating diffusion regions arranged at the two locations in each pixel is formed by the divided exposure. A solid-state image pickup device characterized by being constant regardless of the area where it is placed. An electrode is further provided at a position facing the gate of the transfer transistor and the gate of the reset transistor,
Of the floating diffusion regions disposed at the two locations, one of the floating diffusion regions is formed between an electrode disposed in parallel with the gate of the transfer transistor, and the other floating diffusion region is the electrode. And the gate of the resetting transistor arranged in parallel with each other,
The solid-state imaging device according to claim 1, wherein the electrode is exposed and positioned with the same mask as the gate of the transfer transistor and the gate of the reset transistor. The electrode is
A first electrode that is exposed with the same mask as the gate of the transfer transistor and the gate of the reset transistor, and is arranged in parallel to the gate of the transfer transistor;
3. The method according to claim 2, further comprising: a second electrode that is exposed with the same mask as the gate of the transfer transistor and the gate of the reset transistor and is arranged in parallel to the gate of the reset transistor. The solid-state imaging device described. The electrode or the first electrode and the second electrode is a solid-state imaging device according to claim 2 or 3, characterized in that it is set to a potential for storing charge to the floating diffusion region.

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