JP4859227B2 - Pattern formation method - Google Patents

Description

  The present invention relates to a pattern forming method for performing lithography processing and etching processing on a substrate such as a semiconductor wafer or an LCD glass substrate.

  In general, in the manufacture of semiconductor devices, a photolithography technique is used to form an ITO (Indium Tin Oxide) thin film or an electrode pattern on a substrate such as a semiconductor wafer or an LCD glass substrate. In this photolithography technique, a photoresist (hereinafter referred to as a resist) is applied to a substrate, a resist film formed thereby is exposed in accordance with a predetermined circuit pattern, and the exposure pattern is developed to form a resist film. In this process, a desired circuit pattern is formed by a series of lithography processes.

  Such processing is generally performed on a resist coating processing unit that applies a resist solution to a substrate for processing, a heating processing unit that heats a substrate after completion of the resist coating processing or a substrate after exposure processing, and development on a substrate after exposure processing. This is performed by a coating / development processing system provided with a plurality of development processing units or the like for supplying a liquid for development processing.

  Incidentally, in recent years, there has been an increasing demand for miniaturization of device patterns. As one of the miniaturization methods, there is a technique for forming a photoresist pattern by exposing a photoresist on a substrate a plurality of times using a predetermined mask pattern, and then miniaturizing the photoresist pattern using plasma ashing or the like. It is known (see, for example, Patent Document 1).

  As another miniaturization method, a so-called multi-patterning technique using a lithography process a plurality of times has been studied. In this multi-patterning technique, in addition to a plurality of lithography processes, an etching process for performing fine formation of a resist is required.

2. Description of the Related Art Conventionally, there has been known an apparatus that transports a substrate to a plurality of processing apparatuses and etching apparatuses that perform lithography processing and performs lithography processing and etching processing. In this apparatus, the lithography process can be repeatedly performed. (For example, refer to Patent Document 2).
JP-A-7-147219 (Claims) Japanese Patent Laid-Open No. 7-66265 (Claims, FIG. 1)

  However, in this type of multi-patterning technology, as shown in FIG. 9, when the second resist 1 is applied to the surface of the substrate after the first etching process, for example, the surface of the wafer W, a part of the resist 1 becomes an etching pattern. Since the thickness of the resist 1 is smaller than the predetermined thickness (α), the in-plane uniformity of the surface cannot be obtained. Therefore, there is a problem that the patterning accuracy of the second and subsequent exposure, development and etching processes is lowered.

  As shown in FIG. 10, a multilayer film structure in which a lower layer film 3 is interposed between the resist 1 and the wafer W is known. In this multilayer film structure, for example, an etching pattern 2 such as a hole is used. When the depth of is increased, a part of the lower layer film 3 enters the space of the etching pattern 2. As a result, the surface of the lower layer film 3 has a wave shape, and the surface of the resist 1 also has a wave shape, and the in-plane uniformity of the resist surface cannot be sufficiently obtained. Further, if the lower layer film is made thick in order to maintain the in-plane uniformity of the surface of the resist film, it becomes difficult to apply the resist, and there is a concern that patterning dimensional accuracy is lowered.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a pattern forming method capable of improving patterning dimensional accuracy in device miniaturization.

In order to solve the above problems, a pattern forming method according to claim 1 is a lithography process in which a predetermined pattern is formed by performing lithography processing such as resist coating processing, exposure processing, and development processing on a substrate to be processed; And an etching process using the processed pattern as a mask, and a hydrophobic treatment is performed on the surface of the substrate to be processed after the first etching process. and coating the sacrificial layer to leave a space etched pattern formed on a substrate to be processed, then subjected to second and subsequent lithographic steps and etching to form a pattern, characterized in that.

  With this configuration, the sacrificial film is coated on the surface of the substrate to be processed after the first etching process, leaving a space for the etching pattern formed on the substrate to be processed, and a resist is formed on the surface of the sacrificial film. By applying, the in-plane uniformity of the surface of the resist film after the second time can be maintained, and the pattern can be formed by performing the lithography process and the etching process after the second time.

In addition, since the surface of the substrate to be processed after the first etching process can be hydrophobized, the adhesion between the surface of the substrate to be processed and the sacrificial film after the first etching process is improved.

Further, the material of the sacrificial film needs to have a viscosity that does not enter the space of the etching pattern when applied and coated on the surface of the substrate to be processed, and the film thickness does not increase more than necessary. Any material can be used as long as it has a thickness that does not hinder the application of the resist. Preferably, the material of the sacrificial film is, for example, polystyrene, polymethyl methacrylate, polyvinyl alcohol, or poly It is better to use a polymer polymer material of vinyl acetate (claim 2).

According to a third aspect of the present invention, there is provided a pattern forming method comprising: a lithography process for forming a predetermined pattern by performing a lithography process such as a resist coating process, an exposure process, and a development process on a substrate to be processed; and masking the pattern after the development process A pattern forming method for repeatedly performing the etching step, wherein a space of the etching pattern formed on the substrate to be processed is left on the surface of the substrate to be processed after the first etching process, and polystyrene, polymethyl A sacrificial film made of a polymer polymer material such as methacrylate, polyvinyl alcohol, or polyvinyl acetate is coated, and then a pattern is formed by performing the second and subsequent lithography steps and etching steps.

By configuring as described in claims 2 and 3, the bonding of the composition forming the sacrificial film can be strengthened, and the sacrificial film can be prevented from entering the space of the etching pattern.

  As described above, since the pattern forming method of the present invention is configured as described above, the following remarkable effects can be obtained.

  (1) According to the first aspect of the present invention, the sacrificial film is coated on the surface of the substrate to be processed after the first etching process, leaving a space for the etching pattern formed on the substrate to be processed. By applying a resist on the surface of the film, the in-plane uniformity of the surface of the resist film after the second time can be maintained, and the pattern can be formed by performing the lithography process and the etching process after the second time. The accuracy of patterning dimensions in miniaturization can be improved.

(2) According to the invention described in claim 1 , since the adhesion between the surface of the substrate to be processed and the sacrificial film after the first etching process is improved, in addition to the above (1), patterning in further miniaturization The dimensional accuracy can be improved.

(3) According to the second and third aspects of the invention, the molecular bond of the composition forming the sacrificial film can be strengthened and the sacrificial film can be prevented from entering the space of the etching pattern. Therefore, the thickness of the sacrificial film can be set to a thickness that does not hinder the application of the resist, and the accuracy of patterning dimensions in miniaturization can be improved.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the best embodiment of the present invention will be described in detail with reference to the accompanying drawings. Here, a case where the pattern forming method according to the present invention is applied to a semiconductor wafer resist coating / development processing system will be described.

  FIG. 1 is a schematic plan view showing an example of the resist coating / developing system, and FIG. 2 is a schematic perspective view of the resist coating / developing apparatus.

  The resist coating / development processing system includes a carrier block S1 which is a loading / unloading unit for loading / unloading, for example, 25 carriers 20 in which a semiconductor wafer W (hereinafter referred to as a wafer W) as a substrate to be processed is hermetically contained. A coating / development processing block S2 (hereinafter referred to as processing block S2), which is a coating / development processing unit configured by vertically arranging a plurality of unit blocks B1 to B4, for example, and an interface block as an interface unit And a resist coating / development processing apparatus 10 including S3 and an exposure apparatus S4, a carrier block S1 which is a loading / unloading section for loading and unloading the carrier 20, and an etching block S5 including an etching unit 80. It is mainly composed of the etching apparatus 12. Further, the resist coating / developing system includes an arm A1, which will be described later, as a transfer means for transferring the wafer W between the blocks S1 to S4, between the processing units in the block, and between the processing units of the etching block S5. , A2, C, D, and E are provided.

  The carrier block S1 of the resist coating / development processing apparatus 10 and the etching apparatus 12 has a mounting table 21 on which a plurality of (for example, four) carriers 20 can be mounted, and a front wall surface viewed from the mounting table 21. And a transfer arm C for taking out the wafer W from the carrier 20 via the opening / closing part 22.

  The transfer arm C in the resist coating / development processing apparatus 10 is movable in the horizontal X, Y and vertical Z directions so as to transfer the wafer W to and from the transfer stage TRS1 provided in the processing block S2. In addition, it is configured to be freely rotatable about the vertical axis.

  Further, the transfer arm C in the etching apparatus 12 is movable in the horizontal X, Y and vertical Z directions so as to transfer the wafer W to and from the transfer stage TRS3 provided in the etching block *. It is configured to be freely rotatable about a vertical axis.

  Further, in the vicinity of the opening / closing part 22 of the carrier block S1, for example, an identification display such as an ID display (not shown) attached to the carrier 20 is read, and the processing state of the wafer W stored in the carrier 20 is detected. That is, a detection unit 23 is provided for recognizing whether the process is an unprocessed (first) process or a second or subsequent n-th process.

  The detection unit 23 is electrically connected to a control unit 60 that is a control unit, and a signal detected by the detection unit 23 is transmitted to the control unit 60. As a result, it is determined whether the wafer W to be processed is an unprocessed (first) process or a second or subsequent n-th process.

  The control unit 60 has a storage unit composed of a computer, and the program storage unit stores a transfer schedule of the first lithography process (process) and etching process (process) of the wafer W and processes according to the transfer schedule. Stored is a program made up of, for example, software in which instructions are incorporated so as to control the conveying means A1, A2, C, D, E and the processing unit described later based on the history. Then, when this program is read out by the control unit 60, the control unit 60 controls the operations of the conveying means A1, A2, C, D, E and the processing unit. The program is stored in the program storage unit in a state of being stored in a recording medium such as a hard disk, a compact disk, a magnetic optical disk, or a memory card.

  A processing block S2 surrounded by a housing 70 is connected to the back side of the carrier block S1. In this example, the processing block S2 includes, from the lower side, a first unit block (CHM) B1 for storing chemical liquid containers such as a resist solution and a developing solution, and a second unit block (DEV layer for performing a developing process). ) B2, the coating film forming unit block for performing the two-stage resist solution coating process and the third and fourth unit blocks (COT layers) B3 and B4 which are the cleaning unit blocks for performing the cleaning process. (See FIG. 3). In this case, one of the unit blocks for forming the coating film, for example, the third unit block (COT layer) B3 is used as a unit block (BCT) for performing an antireflection film forming process formed on the lower layer side of the resist film. Layer). Further, an antireflection film forming unit block for performing an antireflection film forming process formed on the upper layer side of the resist film may be provided above the fourth unit block (COT layer) B4. .

  The first to fourth unit blocks B1 to B4 are disposed on the front surface side, are disposed on the rear surface side with a liquid processing unit for applying a chemical solution to the wafer W, and are performed by the liquid processing unit. Treatment units such as various heat treatment units for performing pre-treatment and post-treatment of the treatment to be performed; the liquid treatment unit disposed on the front side; and a treatment unit such as the heat treatment unit disposed on the back side; Specifically, a substrate dedicated for transferring the wafer W between a processing unit such as a heat processing unit and a liquid processing unit in which a development processing unit is arranged in the lower stage and a resist processing unit is arranged in the upper stage Main arms A1 and A2 which are conveying means are provided.

  In this example, the unit blocks B1 to B4 are formed in the same arrangement layout of the liquid processing unit, the processing unit such as the heat processing unit, and the conveying means between the unit blocks B1 to B4. . Here, the same arrangement layout means that the center on which the wafer W is placed in each processing unit, that is, the center of the spin chuck that is the means for holding the wafer W in the liquid processing unit, and the heating plate and cooling plate in the heating processing unit. It means that the center of is the same.

  As shown in FIG. 1, the DEV layer B2 is connected to the carrier block S1 and the interface block S3 in the longitudinal direction (Y direction in the figure) of the DEV layer B2 at the approximate center of the DEV layer B2. A transfer area R1 (horizontal movement area of the main arm A1) of the wafer W is formed. Further, although not shown, the COT layers B3 and B4 are similar to the DEV layer B2 in the center of the COT layers B3 and B4 in the length direction (Y direction in the figure) of the COT layers B3 and B4. A wafer W transfer area R2 (horizontal movement area of the main arm A2) for connecting S1 and the interface block S3 is formed.

  On both sides of the transport region R1 (R2) viewed from the carrier block S1 side, a plurality of units for performing development processing as the liquid processing unit on the right side from the near side (carrier block S1 side) to the back side. For example, three development processing units 31, a two-stage coating processing unit 32, and a cleaning unit (SCR) are provided.

  As shown in FIG. 5, the coating processing unit 32 includes a spin chuck 33 which is a substrate holding unit for sucking and attracting the central portion on the back surface side of the wafer W and holding it horizontally, and the spin chuck 33 and the wafer W. A rotating cup 34 to be accommodated and a fixed cup 35 that surrounds the outer peripheral side of the rotating cup 34 are provided.

  In this case, the spin chuck 33 is connected to the elevating mechanism 36 through the shaft portion 33a so as to be able to elevate. A first driven sprocket 38 a is attached to the shaft portion 33 a of the spin chuck 33, and a first timing is applied to the first driven sprocket 38 a and the drive sprocket 37 b attached to the drive shaft 37 a of the drive motor 37. A belt 39 a is stretched over and a spin chuck 33 is formed to be rotatable by a drive motor 37.

  The rotating cup 34 has a rotating cylinder part 34c disposed via a bearing 34b between the rotating cup part 34a and the shaft part 33a of the spin chuck 33, and a second follower mounted on the rotating cylinder part 34c. A second timing belt 39 b is stretched between the sprocket 38 b and the drive sprocket 37 b mounted on the drive shaft 37 a of the drive motor 37, so that the drive motor 37 can rotate synchronously with the spin chuck 33. Note that the opening 34a of the rotating cup 34 is closed by a lid 34d during processing. The lid 34d is moved up and down by the robot arm F so as to be openable and closable with respect to the opening 34a of the rotary cup 34. The fixed cup 35 disposed outside the rotating cup 34 has a drain port 35a at the bottom and an exhaust port 35b at the side.

  Further, the coating unit 32 is supplied with a first supply nozzle 41 for supplying a resist and a sacrificial film chemical solution made of a polymer polymer material which is a material of the sacrificial film, to the three liquid processing units. The second supply nozzle 42 for supplying the liquid, the third supply nozzle 43 for supplying pure water as the rinse liquid, and the first to third supply nozzles 41, 42, 43 in the rotary cup 34. There is provided a nozzle moving mechanism (not shown) that is movable in the horizontal X, Y direction and vertical Z direction that moves to the upper part of the center of the wafer W and outward of the rotary cup 34. In this case, the first supply nozzle 41 is connected to the resist supply source 44b via a resist supply pipe 44a provided with an on-off valve V1 capable of adjusting the flow rate. Further, the second supply nozzle 42 is connected to a sacrificial film chemical supply source 45b via a sacrificial film chemical supply pipe 45a provided with an on-off valve V2 capable of adjusting the flow rate. The third supply nozzle 43 is connected to a pure water supply source 46b via a pure water supply pipe 46a provided with an on-off valve V3. The on-off valves V1 and V2 are electrically connected to the control unit 60, and the opening degree is adjusted based on a control signal from the control unit 60 to supply a predetermined amount of resist and sacrificial film chemical to the wafer surface. It is formed to be (discharged).

  For the sacrificial film chemical, a low-humidity (for example, 30%) polymer polymer material such as polystyrene, polymethyl methacrylate, polyvinyl alcohol, or polyvinyl acetate can be used.

  On the other hand, each unit block is provided with, for example, four shelf units U1, U2, U3, U4 in which heating units are multi-staged in order from the front side to the left side in the DEV layer B2. Is configured such that various processing units for performing pre-processing and post-processing of the processing performed in the development processing unit 31 are stacked in a plurality of stages, for example, three stages. In this way, the developing unit 31 and the shelf units U1 to U4 are partitioned by the transport region R1, and the cleaning air is ejected and exhausted to the transport region R1, thereby suppressing the floating of particles in the region. It is like that.

  Among the various units for performing the above-described pre-processing and post-processing, for example, as shown in FIG. 4, a heat processing unit (PEB) called a post-exposure baking unit that heat-processes the wafer W after exposure. ), And a heat treatment unit (POST) called a post-baking unit that heat-treats the wafer W after the development treatment to remove moisture. Each processing unit such as these heat processing units (PEB, POST) is accommodated in the processing container 40, and the shelf units U1 to U4 are configured by stacking the processing containers 47 in three stages. A wafer loading / unloading port 48 is formed on the surface of the container 47 facing the transfer region R1. Note that the heat treatment unit (PEB, POST) is electrically connected to the control unit 60 and is formed so that the heating temperature and the heating time can be adjusted based on a control signal from the control unit 60.

  The main arm A1 is provided in the transfer region R1. The main arm A1 transfers wafers to and from all modules (places where the wafer W is placed) in the DEV layer B2, for example, the processing units of the shelf units U1 to U4 and the units of the development processing unit 31. For this reason, it is configured to be movable in the horizontal X and Y directions and the vertical Z direction and to be rotatable about the vertical axis.

  The main arm A1 (A2) is configured in the same manner, and the main arm A1 will be described as a representative example. For example, as shown in FIG. The arm main body 50 which has the curved arm piece 51 is provided, and these curved arm pieces 51 are comprised so that advancement / retraction is mutually independent along the base which is not shown in figure. The base is configured to be rotatable about a vertical axis, movable in the Y direction, and movable up and down. Thus, the bending arm piece 51 is configured to be movable back and forth in the X direction, movable in the Y direction, freely movable up and down, and rotatable about the vertical axis, and is arranged on each unit of the shelf units U1 to U4 and on the carrier block S1 side. The wafer W can be transferred between the transfer stage TRS1 of the shelf unit U5 and the liquid processing unit. The driving of the main arm A1 is controlled by a controller (not shown) based on a command from the control unit 60 serving as a control unit. Further, in order to prevent heat storage in the heat treatment unit of the main arm A1 (A2), the order of receiving the wafers W can be arbitrarily controlled by a program.

  Further, the unit blocks B3 and B4 for forming the coating film are configured in the same manner, and are configured in the same manner as the unit block B2 for development processing described above. Specifically, a coating processing unit 32 for applying a resist solution to the wafer W is provided as a liquid processing unit, and the shelf units U1 to U4 of the COT layers B3 and B4 are provided with a resist solution after coating. A heat treatment unit (CLHP) for heating and cooling the wafer W and a hydrophobic treatment unit (ADH) for improving the adhesion between the resist solution and the wafer W are provided, and are configured in the same manner as the DEV layer B2. . That is, the coating unit, the heat treatment unit (CLHP), and the hydrophobic treatment unit (ADH) are configured to be partitioned by the transfer region R2 of the main arm A2 (horizontal movement region of the main arm A2). In the COT layers B3 and B4, the main arm A2 transfers the wafer W to the transfer stage TRS1 of the shelf unit U5, the coating processing unit 32, and the processing units of the shelf units U1 to U4. To be done. The hydrophobic treatment unit (ADH) performs gas treatment in an HMDS atmosphere, but may be provided in any one of the unit blocks B3 and B4 for forming a coating film.

  Further, as shown in FIG. 1, a shelf unit U6 is provided at a position where the main arm A1 can access the adjacent area of the processing block S2 and the interface block S3. The shelf unit U6 includes a delivery stage TRS2 and a delivery stage (not shown) having a cooling function for delivering the wafer W so as to deliver the wafer W to and from the main arm A1 of the DEV layer B2. ing. In addition, in a region adjacent to the processing block S2 and the interface block S3, as shown in FIGS. 1 and 4, two stages of peripheral edge exposure devices (WEE) are arranged.

  On the other hand, an exposure apparatus S4 is connected to the back side of the shelf unit U6 in the processing block S2 via an interface block S3. The interface block S3 includes an interface arm D for delivering the wafer W to each part of the shelf unit U6 of the DEV layer B2 of the processing block S2 and the exposure apparatus S4. The interface arm D serves as a transfer means for the wafer W interposed between the processing block S2 and the exposure apparatus S4. In this example, the wafer W is transferred to the transfer stage TRS2 and the like of the DEV layer B2. It is configured to be movable in the horizontal X and Y directions and the vertical Z direction and to be rotatable about the vertical axis.

  On the other hand, the etching block S5 in the etching apparatus 12 includes an etching processing unit 80 (hereinafter referred to as an etching unit 80) which is a dry etching apparatus stacked in multiple stages, for example, four stages, in the housing 70a. A transfer arm E for loading / unloading the wafer W to / from the unit 80 and a delivery stage TRS3 are provided. In this case, the transfer arm E is formed so as to be able to move in the horizontal X, Y and vertical directions, and to rotate, which transfers the wafer W to and from the transfer stage TRS3 in the etching block S5. . The etching unit 80 is formed so that the etching rate can be controlled by adjusting etching process conditions such as applied high frequency, high frequency voltage and gas pressure in a vacuum atmosphere, for example.

  In the etching block S5 configured as described above, a shield for shielding electromagnetic waves is applied to the housing 70a so that electromagnetic waves generated from the etching unit 80 do not affect the outside during the dry etching process. Any shield may be used as long as it is a shield plate made of conductive metal or synthetic resin. In this embodiment, for example, a shield plate made of aluminum alloy is used to form the casing 70a. Yes.

  By configuring the casing 70a of the etching block S5 with an electromagnetic wave shielding plate in this manner, electromagnetic waves generated from the etching unit 80 can be blocked from leaking to the outside during the dry etching process.

  The resist coating / developing apparatus 10 and the etching apparatus 12 configured as described above are formed so that the wafer W can be transferred, as indicated by arrows in FIG. In this case, the transfer control of the wafer W may be carried by, for example, a carrier 20 unit that accommodates 25 wafers W, or may be carried by a single wafer (one wafer unit).

  Next, processing of the wafer W in the resist coating / development processing system configured as described above will be described with reference to the flowchart shown in FIG.

  First, the carrier 20 containing the wafer W to be processed is placed on the opening / closing part 22 on the mounting table 21 of the carrier block S1. In this state, the identification display attached to the carrier 20 is detected by the detection means 23, and the detection signal is transmitted to the control unit 60, and whether the wafer W to be processed is the first or n-th (second or later). Is determined. When it is determined that the wafer W to be processed is the first time, a first transfer schedule is created, or a first lithography process is performed based on a previously created transfer schedule.

  That is, the wafer W temporarily subjected to the hydrophobic treatment and temporarily stored in the shelf unit U5 is taken out of the shelf unit U5 by the main arm A2, and is transferred to the coating processing unit 32 to form a resist film (S-1). ). The wafer W on which the resist film is formed is transferred to the heat treatment unit (CLHP) by the main arm A2, and pre-baked (PAB) for evaporating the solvent from the resist film is performed (S-2). Thereafter, the wafer W is subjected to a cooling process in a heat treatment unit (CLHP) (S-3). Although not shown, after pre-baking (PAB) is performed, the wafer W is transferred to a peripheral exposure apparatus (WEE), and after the peripheral exposure process, the heating process and the cooling process are performed. Next, the wafer W is transferred to the exposure apparatus S4 by the interface arm D, where a predetermined exposure process is performed (S-4).

  The wafer W after the exposure processing is transferred by the interface arm D to the delivery stage TRS2 of the shelf unit U6 in order to deliver the wafer W to the DEV layer B2, and the wafer W on the stage TRS2 is the main of the DEV layer B2. After being received by the arm A1 and first subjected to post-exposure baking (S-5) in the heat treatment unit (PEB) in the DEV layer B2, a cooling plate (not shown) in the heat treatment unit (PEB) Is adjusted to a predetermined temperature. Next, the wafer W is taken out of the heat treatment unit (PEB) by the main arm A1, and is transferred to the development processing unit 31, where a developer is applied (S-6). Thereafter, the main arm A1 conveys the heat treatment unit (POST) to perform a predetermined development process.

  The wafer W after the development processing is stored and carried out in an empty carrier 20 placed on the placement table 21 of the carrier block S1.

  The wafer W subjected to the first lithography process by the resist coating / development processing system is transferred to the carrier block S of the etching apparatus 12 and subjected to the etching process using the pattern after the development process as a mask (S-). 7). Thereafter, the wafer W is accommodated in the carrier 20 and loaded again into the carrier block S1 of the resist coating / developing apparatus 10.

  When the carrier 20 containing the wafer W that has been subjected to the first lithography process (process) and etching process (process) is inserted into the mounting table 21 of the carrier block S1, the identification display attached to the carrier 20 is detected. When it is detected by the means 23 and it is determined that the second time or later, for example, the second time, the control unit 60 confirms the previous (first) conveyance history based on the detection signal. When the previous transfer history is confirmed, the control unit 60 creates a tuned transfer schedule using the processing unit used for the predetermined process of the lithography process based on the previous (first) transfer schedule, and the nth ( A second lithography process is performed.

  When the carrier 20 containing the wafer W that has been subjected to the first lithography process (process) and etching process (process) is loaded, the wafer W in the carrier 20 is taken out by the transfer arm C, and the shelf unit U5 The wafer W is transferred to the delivery stage TRS1. Then, the wafer W is transferred to the hydrophobic treatment unit (ADH) by the main arm A2 and subjected to the hydrophobic treatment (S-8). The wafer W temporarily stored in the shelf unit U5 after being subjected to the hydrophobic treatment is taken out from the shelf unit U5 by the main arm A2 and transferred to the coating processing unit 32, where the sacrificial film 4 made of a polymer material is formed. A film is formed (S-9: see FIG. 7). At this time, the sacrificial film chemical is supplied (discharged) from the second supply nozzle 42 while the wafer W is held by the spin chuck 33 of the coating processing unit 32, and then the opening 34 a of the rotary cup 34 is covered. In a state where the body 34d is closed, the wafer W is rotated at a high speed (for example, 4000 rpm) together with the rotating cup 34 by driving the drive motor 37, and the sacrificial film 4 is coated with the sacrificial film chemical solution (FIG. 7). (See (a)). In the film treatment of the sacrificial film 4, the sacrificial film 4 is formed of a low-humidity (for example, 30%) polymer polymer material such as polystyrene, polymethyl methacrylate, polyvinyl alcohol, or polyvinyl acetate as described above. In addition, since the wafer surface is hydrophobized, the sacrificial film 4 does not enter the etching pattern 2 (hole), and the sacrificial film 4 has a thickness that does not hinder the resist application. In the state, the surface becomes flat. The wafer W coated with the sacrificial film 4 is taken out from the coating processing unit 32 by the main arm A2, transferred to the heat treatment unit (CLHP), and baked, for example, in a temperature atmosphere of 300 to 350 ° C. for 90 seconds (S -10), the cooling process is performed (S-11).

  Next, the wafer W is transferred to the coating processing unit 32 by the main arm A2 and subjected to a resist coating process, and a resist film 1 is formed on the surface of the sacrificial film 4 as shown in FIG. (S-12). In this case, since the surface of the sacrificial film 4 is maintained flat, the surface of the resist film 1 is also flat, and the in-plane uniformity of the resist film 1 can be improved.

  The wafer W on which the resist film is formed is subjected to pre-baking (PAB) (S-13) → cooling processing (S-14) → exposure processing (EXP) (S-15) as in the first processing (FIG. 15). 7 (c)). In this exposure process, since the in-plane uniformity of the surface of the resist film 1 is maintained, the exposure accuracy is improved. After the exposure process, a post-exposure bake process is performed using the processing unit PEB (S-16). By performing this post-exposure bake treatment, for example, in a chemically amplified resist, the treatment time and the in-plane temperature affecting the acid catalyst reaction can be made constant.

  The wafer W that has been subjected to the post-exposure bake process is transferred to the processing unit DEV and subjected to a development process (S-17).

  The wafer W on which the second lithography process (process) has been performed as described above is accommodated in the empty carrier 20 placed on the carrier block S1 by the transfer arm C, and the second lithography process is performed. Applied.

  The carrier 20 containing the wafer W that has been subjected to the second lithography process is transferred to the etching apparatus 12 and subjected to an etching process using the developed pattern as a mask. The sacrificial film 4 remaining on the surface of the wafer W is removed by ashing.

  By performing the processing as described above, for example, a pattern having a pitch P / 2 can be formed by additionally forming a pattern between the pitches P of the pattern formed by one lithography process. Miniaturization can be achieved. The wafer W that has been subjected to the second etching process is accommodated in the carrier 20 and the process ends.

  In the above embodiment, the case where the antireflection film is not formed has been described. However, the pattern forming method (system) according to the present invention is similarly applied to the case where the antireflection film is formed below or above the resist film. Can be applied. That is, as shown in FIG. 8, the surface of the wafer W after the first lithography process and the etching process is subjected to a hydrophobic treatment, and then the sacrificial film 4 is formed on the surface of the wafer W as described above. After coating and baking and cooling, an antireflection film 5 is formed (coated) on the surface of the sacrificial film 4. Then, after the resist film 1 is formed on the surface of the antireflection film 5, exposure processing and development processing can be performed. In this case, as shown in FIG. 6C, between the cooling process (S-11) and the resist coating process (S-12), the antireflection film coating process (S-20) → the baking process (S-21). ) → Cooling process (S-22) is added.

  In the above embodiment, the description is omitted, but it is preferable that the resist coating / development processing system includes a line width measuring device. By providing this line width measuring apparatus, the line width of the pattern formed on the wafer W that has been subjected to the first lithography process and etching process is measured by the line width measuring apparatus, and the measured measurement information is controlled. The pattern is transmitted to the unit 60 and stored in the control unit 60, and the control signal is transmitted from the control unit 60 to the exposure apparatus S4, the heat treatment unit (PEB) and the etching unit 80 based on the stored information. Based on the measurement information of the line width, exposure correction in the exposure process of the second and subsequent lithography processes, exposure correction such as exposure amount and exposure focus, and the heating temperature and heating in the heating process of the heating processing unit (PEB) after exposure By adjusting the etching process conditions such as temperature correction such as time, applied high frequency, high frequency voltage and gas pressure in the etching process It can be etched correction of etching rate or the like.

  In the above description, the case where the lithography process and the etching process are performed twice has been described. However, the pattern forming method according to the present invention can also be applied to the case where the lithography process and the etching process are repeated three times or more.

1 is a schematic plan view showing an example of a resist coating / development processing system to which a pattern forming method according to the present invention is applied. 1 is a schematic perspective view of a resist coating / developing apparatus according to the present invention. It is a schematic front view which shows the liquid processing part of the said resist application | coating / development processing apparatus. It is a schematic back view which shows the heat processing part of the said resist application | coating / development processing apparatus. It is a schematic sectional drawing which shows the coating processing unit in this invention. It is a flowchart which shows the process process of the pattern formation method which concerns on this invention. It is an expanded sectional view (a) which shows the coat state of a sacrificial film in this invention, an enlarged sectional view (b) which shows the state where a resist film was formed on the surface of a sacrificial film, and an enlarged sectional view (c) which shows an exposure state. It is the expanded sectional view (a) which shows the state which laminated | stacked the sacrificial film and resist film at the time of forming an antireflection film, and the expanded sectional view (b) which shows the exposure state after that. It is an expanded sectional view which shows the state which applied the multi-pattern technique to the conventional resist application. It is an expanded sectional view which shows the state which applied the multi-pattern technique to another conventional resist application.

W Semiconductor wafer (substrate to be processed)
S1 Carrier block S2 Processing block S3 Interface block S4 Exposure device S5 Etching block 1 Resist film 2 Etching pattern 4 Sacrificial film 5 Antireflection film 10 Resist coating / development processing device 12 Etching device 31 Development processing unit 32 Coating processing unit 33 Spin chuck 34 Rotating cup 41 first supply nozzle (resist supply nozzle)
42 Second supply nozzle (sacrificial film chemical supply nozzle)
44b Resist supply source 45b Sacrificial film chemical supply source 60 Control unit (control means)
80 Etching unit

Claims (3)

A pattern forming method for repeatedly performing a lithography process in which a predetermined pattern is formed by subjecting a substrate to be processed to a lithography process such as a resist coating process, an exposure process, and a development process, and an etching process using the pattern after the development process as a mask Because
After hydrophobizing the surface of the substrate to be processed after the first etching process, a sacrificial film is coated on the surface of the substrate to be processed, leaving a space for the etching pattern formed on the substrate to be processed. A pattern forming method, wherein a pattern is formed by performing a lithography process and an etching process after the second time. In the pattern formation method of Claim 1,
A pattern forming method, wherein the sacrificial film is made of a polymer polymer material of polystyrene, polymethyl methacrylate, polyvinyl alcohol, or polyvinyl acetate . A pattern forming method for repeatedly performing a lithography process in which a predetermined pattern is formed by subjecting a substrate to be processed to a lithography process such as a resist coating process, an exposure process, and a development process, and an etching process using the pattern after the development process as a mask Because
A sacrifice made of a polymer material of polystyrene, polymethyl methacrylate, polyvinyl alcohol, or polyvinyl acetate , leaving a space for an etching pattern formed on the substrate to be processed on the surface of the substrate to be processed after the first etching process. A pattern forming method, wherein a film is coated, and then a pattern is formed by performing a second and subsequent lithography steps and etching steps.

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