JP4849143B2 - Reading method, responder and interrogator - Google Patents

Description

  The present invention relates to an identification method and apparatus for identifying a responder by exchanging signals between an interrogator and a plurality of responders. In particular, the present invention relates to an interrogator, a method and apparatus for controlling and identifying congestion of response signals from a plurality of responders.

  References referred to in this specification are as follows. References shall be referenced by their reference numbers.

  When a plurality of responders exist in the effective radio wave area of the interrogator, it is necessary to identify response signals from the plurality of responders. There is Literature 1 as a technique for preventing interference from a plurality of responders.

  This reference 1 receives an interrogation signal from an interrogator, and the responder transmits a predetermined number of bits. The interrogator receives a predetermined number of bits transmitted from the responder and returns it to the responder. The transponder transmits the predetermined number of bits following the already transmitted bit, and the same process is repeated. The unequal responders do not participate in the identification process until the next interrogation signal is received. By repeating this process, only one responder finally recognizes its own identification number. By repeating this recognition process until there are no unprocessed responders, the identification process of a plurality of responders is completed.

  In this document 1, since transmission and reception with an interrogator are repeated in a predetermined number of bits, various commands (question signal, received bit return signal, identification failure notification signal, identification completion notification signal) A logic circuit for switching the transmission / reception and for controlling the memory address counter is required, which requires the number of operation stages, a flip-flop representing the state transition, and a data comparison circuit.

  Document 2 discloses that a responder having a memory for storing an identification number in response to a clock pulse from an interrogator transmits the identification number. In Document 2, a responder, which is an RFID, sends an identification number in response to a clock pulse from an interrogator, thereby eliminating a command in communication and simplifying a transmission / reception reception method.

International Publication No. 98/21691 Pamphlet International Publication No. 00/36555 Pamphlet

In the present invention, the RFID function is narrowed down by simplifying the transmission / reception method and the congestion control function in the responder, the interrogator, the mass productivity is improved by increasing the number of chips (RFID tags) that can be cut out per wafer, and the RFID is congested. Provide the control function and solve the problem of reducing the manufacturing unit price.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  When there is an interrogator that reads the identification number in the responder wirelessly and the corresponding responder, and a clock pulse is modulated from the antenna of the interrogator to a corresponding high frequency carrier and transmitted to the responder The interrogator has a first case where the interval between the clock pulses is short and a second case where the interval between the clock pulses is long, and the clock pulse in the first case and the clock pulse in the second case are combined. A responder characterized in that reading of the identification number is controlled.

It is drawing which shows a clock pulse interval classification circuit. It is drawing which shows the Example of a counter memory circuit structure. It is drawing which shows the Example inside a responder. It is drawing which shows the Example of the memory structure of a responder. It is drawing which shows the Example of a counter and a memory structure. It is drawing which shows the Example of reading from a responder. It is drawing which shows the Example of the retry of reading. It is drawing which shows the case where congestion control is required. It is drawing which shows the Example of the operation | movement flow of the responder of this invention. It is drawing which shows the Example of a protocol. It is drawing which shows the Example of a flip-flop. It is drawing which shows the Example of EB writing. It is drawing which shows the Example of the state of a memory. It is drawing which shows the Example of a clock pulse space | interval detection circuit. It is drawing which shows the internal structure of an interrogator. It is drawing which shows the operation | movement flow of an interrogator.

  Since RFID tags are distributed in large quantities and the collection cost is enormous, RFID tags that are disposable are subject to reduction in manufacturing unit price.

  To place multiple RFIDs in the effective radio wave area from the interrogator, and to expand the effective radio wave area to the size of the RFID mounted object and the range beyond the arrangement interval, it is necessary to give the RFID a congestion control function It is essential.

  In the present invention, the RFID function is narrowed down by simplifying the transmission / reception method and the congestion control function in the responder, the interrogator, the mass productivity is improved by increasing the number of chips (RFID tags) that can be cut out per wafer, and the RFID is congested. Provide the control function and solve the problem of reducing the manufacturing unit price.

  For example, RFID attached to products such as clothing has a huge collection cost, and it is convenient for business and management to be disposable. Furthermore, in order to manage a plurality of products in a shipping box etc. without opening them, congestion control is essential. Accordingly, it is necessary to make the RFID tag disposable by reducing the cost of the RFID tag and further to enable congestion control.

  FIG. 8 shows an example in which a plurality of responders 902-906 according to the present invention are present in the effective radio wave area 901 of the interrogator 907. FIG. 8 shows an example in which there are five responders 902-906. Although details will be described later, even when there are a plurality of responders in the effective radio wave area 901, each response is made by operating each responder with two types of clock pulses (modulation signals) from the interrogator. The memory of the device can be read.

  FIG. 10 shows a specific responder, communication method in the interrogator, and congestion control method. FIG. 10 shows a case where two chips A and B exist in the effective radio wave area. Further, in this embodiment, for simplicity, the counter in each chip shows a case of 2 bits. When a clock pulse from the interrogator starts, chip A and chip B simultaneously set an initial value of a predetermined page number in the counter. In this example, the page number was 01 for chip A and 11 for chip B. The interrogator attempts to read the responder's memory by issuing short intervals of clock pulses, but each chip does not send out the memory contents because the counter in each chip is not yet 00. Then, since the interrogator receives no data, the interrogator determines that there is no responder in operation, stops sending clock pulses at short intervals, and sends clock pulses at long intervals. Then, each chip increments the page number by +1 and becomes 10 for chip A and 00 for chip B. At this time, the chip B sets the operation switching flip-flop and sends the memory data to the interrogator with the next short interval clock pulse. When it ends normally, the interrogator also issues a long-interval clock pulse and eventually the chip A counter becomes 00 and chip A sends out the data. As shown in this example, chip A and chip B transmit memory data without overlapping, and the interrogator performs an operation of turning pages at a high speed by a clock pulse with a long interval. Is shortened.

  FIG. 9 shows a flowchart of the communication method and the congestion control method with the interrogator in the responder of the present invention. The responders 902 to 906 demodulate the modulation signal from the interrogator 907 and take out two types of clock pulses that are either short or long intervals.

  As a basic operation of the transponder, the page number is counted up with a clock pulse with a long clock interval, and the memory address is counted up with a clock pulse with a short clock interval. Pulse, short clock pulse is called short clock pulse). By adopting two types of clock pulses having different clock intervals, it is possible to simplify the configuration of the communication method, the congestion control method, the responder, and the interrogator.

Further, in the embodiment of the present application, the clock interval represents a time interval between a certain L level and the next L level, that is, a time interval from the falling to the falling from the H level to the L level. It shall represent.

  The clock width is defined by the length of time in the L level state, that is, it is defined by the time interval from the falling from the H level to the L level to the rising from the L level to the H level. In the flowchart of FIG. 9, these clock intervals and clock widths are controlled separately.

  The page number is counted up when the operation switching flip-flop is in the reset state, and the memory address is counted up when the operation switching flip-flop is in the set state.

At 1001, the transponder receives the first clock pulse from the interrogator. This first clock pulse can be either long or short. At 1002, a page number (random number) held uniquely for each responder is set as an initial value in a counter. The page number is a number that defines the order in which identification numbers are sent when there are a plurality of responders in the effective radio wave area of the interrogator. At 1003, the L level width of the next clock pulse is monitored, and the responder receives the next clock pulse and checks whether the interval is long or short. When the clock pulse interval is long (in the case of a long clock pulse), the procedure proceeds to 1010, and when the clock pulse interval is short (in the case of a short clock pulse), the procedure proceeds to 1008. At 1010, the operation switching flip-flop in the responder is reset, that is, the page number can be counted up, and the process proceeds to 1004 to increment the page number set in the counter by +1. When a carry is issued from the counter at 1005, it indicates that the counter content has become zero. In other words, the binary counter counts up bit by bit, and after all 1s becomes all zeros. Carry comes out when it becomes all-zero. It is checked whether a carry has come out of the counter. If a carry comes out at 1006 at this time, the operation switching flip-flop is set by using the carry at 1005 in the responder. That is, the memory address can be counted up. When the carry does not come out, the process returns to 1003 to wait for the next clock pulse. At 1007, after waiting for the next clock pulse, the L level width of this clock pulse is monitored. When the clock pulse width is narrow, the process returns to 1003. When the clock pulse width is wide, the process proceeds to 1011. Set another page number in the counter and return to 1003.
On the other hand, if the operation is performed from 1003 to 1008, it is checked in 1008 whether or not the operation switching flip-flop in the responder is set. If it is set, the memory address is incremented by 1 at 1012 in FIG. 9, and the process proceeds to 1009 to send one bit of the responder number. Then go to 1007.

  It should be noted that this flow is one of the embodiments, and the branch condition 1003 in FIG. 9 may be reversed, and the branch condition 1007 in FIG. 9 may be reversed.

  When the responder receives a short interval clock pulse, it checks whether the operation switching flip-flop in its own chip is set. If the operation switching flip-flop is set, the memory data is transmitted. If the operation switching flip-flop is not set, the short-period clock pulse is ignored.

  Since there is an operation switching flip-flop in the responder, when this flip-flop is set, the corresponding responder sends a number according to the clock pulse of the interrogator, and when the operation switching flip-flop is not set, the number By not performing the sending operation, it is possible to prevent the responders from operating simultaneously and the number sending from being congested.

  If a large number of wireless IC tag chips stochastically exist in the effective radio wave area, there is a high possibility that page numbers will collide. If multiple responders have the same page number, the operation switching flip-flops are set at the same time and send the numbers to the interrogator at the same time. Is received as a logical OR, the error detection code incorporated in the number does not become a normal code, and the interrogator accepts it as an error number.

  Therefore, if a plurality of page numbers are held in the responder and the first page number set by the counter is the same as the page number of the other responder, the first page number and the page number of 1011 in FIG. By resetting to a different second page number, the possibility that the page number will hit twice in a row is reduced. It is possible to set according to the number of bits of the page number, the number of page numbers in the responder, or the number of responders existing in the effective radio wave area of the interrogator.

  When the modulation method is ASK, it is the same state from the interrogator side that the responder does not exist within the effective radio wave area of the interrogator and that the responder transmits a bit indicating L level. The interrogator can transmit the identification number if there is a bit that electrically goes to the first bit of the memory of the responder that stores the identification number (or the first bit when transmitting the identification number to the interrogator). Therefore, it is convenient from the viewpoint of shortening the reading time of the identification number. More generally, in the transmission order of each bit of the identification number, it is possible to prepare a bit that electrically indicates the H level before half of the total number of bits. Convenient for quickly confirming the presence of the vessel.

  At this time, the noise does not prevent the responder from appearing to be present or that a plurality of responders exist and operate. When this noise is present, it becomes indeterminate which flow of the responder goes to FIG. 9, and the interrogator stops sending the modulation signal to the responder and retry reading again.

  If no bit that is electrically at the H level is transmitted, the interrogator assumes that there is no received data. That is, in the transmission order of each bit of the identification number, if there is no bit that electrically indicates H level before half of the total number of bits, the interrogator considers that there is no responder.

  FIG. 16 shows a flowchart of a communication method and a congestion control method with an interrogator in the responder of the present invention. At 1601, the interrogator sends an initial clock pulse toward the responder. In 1602, the interrogator checks whether the number reception mode is selected. If the number reception mode is selected, the process proceeds to 1604. If not, the process proceeds to 1603. At 1604, a short clock pulse is transmitted from the interrogator to the responder, and one bit of the identification number is received from the responder. In 1605, it is checked whether 1 bit is received. If received, the process proceeds to 1606. If not received, the process returns to 1602. In 1606, it is checked whether all the identification numbers have been received. If all the identification numbers have not been received, the process returns to 1602 in FIG. When all are received, the process proceeds to 1607 and checks whether the error check code is normal. If it is not normal at 1607, the process returns to 1602 to repeat reading, and if it is normal, the process proceeds to 1608. In 1608, it is checked whether or not the page is switched. When the page is switched, the process proceeds to 1609, and a long clock pulse is transmitted to set another page number in the responder counter. If the page is not switched, the process returns to 1602.

  FIG. 6 shows clock pulses transmitted by the interrogator when reading the identification number from the responder. There is a page number count-up period 701 by a long clock pulse, and a memory read period 702 by a short-interval clock pulse.

  FIG. 7 shows clock pulses sent by the interrogator when reading the identification number from the responder. 6 is the same as that of FIG. 6 except that there is a portion where the memory reading period 702 is repeated by a short-interval clock pulse. The portion where the memory read period 702 repeats corresponds to the repetition of (1003) → (1008) → (1012) → (1007) → (1003) in the flow of FIG.

  In the portion where the memory read period 702 repeats, in the first memory read period 702, the interrogator reads out the memory of the responder, and after reading all the memory, is it normal by the error check code that read the data? Check if it is abnormal.

  If abnormal, the interrogator continues to send short intervals of clock pulses continuously before sending the next long interval of clock pulses and retry the reading. Since the binary counter indicating the memory address in the responder keeps counting up repeatedly by a short interval clock pulse, the data in the memory is repeatedly transmitted.

  On the other hand, when a short-period clock pulse is repeatedly output from the noise source, the interrogator repeatedly outputs a short-period clock pulse and tries to read the data normally as if there is a responder. In the case of only the source, it only reads data as a noise source. When a plurality of responders are operated, the responders are operated repeatedly, and data is detected in the interrogator and is not regarded as normal data.

  FIG. 3 shows the configuration of the responders 902-905 in FIG. The responders 902 to 905 of the present invention can be made by various techniques. In the following embodiments, a case where the responders 902 to 905 are realized as a semiconductor chip will be described as an example.

  The antenna 301 receives a modulated signal from the interrogator and is connected to the rectifier circuit 302. The rectifier circuit 302 doubles the modulated signal and rectifies it to supply the power supply voltage VDD. The clock pulse extraction circuit 303 demodulates the high frequency modulation signal, and the low frequency clock pulse is extracted and input to the counter memory circuit 305. Each bit of the identification number in the memory is selected by the counter of the counter / memory circuit, the impedance between the antennas 301 is changed by the load switch 304, and the identification number is transmitted to the interrogator.

  FIG. 15 shows the internal configuration of the interrogator in FIG. The interrogator antenna 1501 receives radio waves from the responder and is connected to the transmission / reception high-frequency circuit 1502. Modulation circuit 1503 performs modulation for the clock pulse waveform, and demodulation circuit 1504 detects and demodulates the signal from the responder. The baseband processing circuit 1505 performs transmission / reception digital signal processing. A congestion control circuit 1506 is built in the baseband processing 1505, and the flow shown in FIG. 16 is controlled by a logic circuit.

  FIG. 2 shows a circuit diagram of the counter memory circuit 305 in FIG. The counter / memory circuit 305 counts up the page number, counts up the memory address for selecting each bit of the identification number, and selects each bit of the identification number. The counter / memory circuit 305 incorporates a congestion control circuit 306 configured by a logic circuit, and controls the flow shown in FIG.

  Sharing the page number count-up counter and the memory address count-up counter is effective in order not to increase the chip size.

  In the present application, an example in which the counter is shared is shown, but it is not necessary to share the counter when the chip area is not considered.

  When the counter is shared, the number of bits of the page number becomes the number of bits of the memory address of the identification number. In general, the memory address is often around 10 bits, so the page number is also around 10 bits, and there is a high possibility of collision with the page numbers of other responders. In this case, as described above, the collision probability can be lowered by holding a plurality of page numbers in the responder and resetting the counters as indicated by 1011 in FIG. In this application, the Example at the time of preparing two types of page numbers is shown.

  The counter 116 counts up one of the clock pulses CK1 and CK2 selected by the output of the operation switching flip-flop.

  The operation switching flip-flop has a function of switching between a page number count-up operation and a memory address count-up operation. In the operation switching flip-flop, the output of the operation switching flip-flop changes from the L level to the H level when the output of the highest flip-flop 124 in the counter 116 changes from the H level to the L level. Here, the set state is when the output of the operation switching flip-flop is H, and the reset state is when the output of the operation switching flip-flop is L.

  When the output of the operation switching flip-flop 117 is at the H level, CK1 generated at a short clock pulse interval by the AND gate 120 and the OR gate 122 is input to the flip-flop 115 of the counter 116, and the counter 116 receives the memory address at CK1. Count up. In the page number count-up operation, an initial value of the page number is set in advance, and the page number is counted up with a signal CK2 by a long interval clock pulse.

  When the output of the operation switching flip-flop 117 is at L level, the signal is set to H level by the inverter gate 123, and CK2 generated at a long clock pulse interval is input to the flip-flop 115 by the AND gate 120 and OR gate 122. The counter 116 counts up the page number at CK2. In the memory address count-up operation, the contents of the counter are all zero, that is, when the output of each flip-flop of the counter is at L level, the counter is counted up with a signal CK1 by a short interval clock pulse.

  The clock pulse interval discriminating circuit 125 is a circuit that discriminates CK1 that is a short clock pulse interval and CK2 that is a long clock pulse interval from the clock pulse (CLK) from the interrogator, and the details are shown in FIG. The description of FIG. 1 will be described later.

  When a plurality of connection terminals 102 are connected to either the electrical H terminal 101 or the electrical L terminal 104, the page number first setting unit 103 holds each bit of the first page number. . The page number first setting unit 103 is electrically set with HLLH and connection terminals from the left. The number 1001 is logically shown on the premise of positive logic.

  Similarly, the plurality of connection terminals 109 serve as the electrical H terminal 105, the page number second setting unit 106, and the electrical L terminal 107, so that the first page number of the page number second setting unit 106 is set. Holds each bit. The page number second setting unit 106 has LHHL and connection terminals set from the left. The number 0110 is logically shown on the premise of positive logic.

  Specifically, the connection terminals 102 and 109 are set by a pattern by electron beam drawing. In the embodiment of FIG. 2, the counter has 4 bits. However, the present invention does not prevent the number of bits from being 4 bits or more.

  The selector unit 108 selects either the first page number or the second page number based on the selection signals S1 and S2 input to the first selection terminal 110 and the second selection terminal 111, respectively. input. More specifically, each bit of the first page number is input from the connection terminal 102 to the AND gate 112, and the selection signal S 1 is input from the first selection terminal 110. Similarly, each bit of the second page number is input to the AND gate 113 from the connection terminal 109 and the selection signal S2 is input from the second selection terminal 111. The outputs of the AND gates 111 and 112 are input to the OR gate 114. The output of the OR gate is set to a plurality of flip-flops 115 constituting the counter 116 as an initial value of the counter 116.

  The output of each flip-flop of the counter is input to the memory 118. The output of the memory is controlled by an AND gate 119 and an operation switching flip-flop.

  FIG. 5 shows the configuration of the counter 116 and the memory 118 of the responder of FIG. The memory 118 includes a decoder 505 and memory cells 508. A memory address output 504 is input to the decoder 505 from each flip-flop constituting the counter 116 of FIG.

  From the decoder 505, a decoder output 506 (a bit string representing X0... X15, Y0... Y7 in FIG. 13) is input to the memory cell 508. Each bit of the identification number selected by the decoder output 506 is output from the memory cell to the AND gate 119 as the memory output 507.

  That is, each bit of the identification number corresponding to the count value of the counter 116 during the memory address count-up operation is read. As for the relationship between the memory address and the decoder output, it is sufficient that the memory address and the decoder output have a one-to-one correspondence so that all bits of the identification number are read out.

  Since the counter 502 of FIG. 2 is used for counting up the memory address and the page number, the address output 504 is electrically at the H level or at the L level when the page number is counted up. And the output of the switching flip-flop are input to the AND gate 119, and the output from the memory 118 is ignored by causing the AND gate 119 to be electrically at the L level. The content is not read and the responder appears to be idle.

  In the embodiment of FIG. 2, the counter 502 is used for counting up the memory address and the page number, so the number of bits of the memory address is equal to the number of bits of the page number.

FIG. 13 shows the data structure of the memory cell 508 of the present invention. In this example, the map format is 16 columns horizontally and 8 rows vertically. In this example, it is assumed that the first transmission data is transmitted to the interrogator in the order of the X1 column and the X2 column in order from the X0 column of the Y0 row.

  At this time, as described above, if the Y0 and X0 data of the memory that is the first bit of the identification number is always set to 1, the interrogator immediately reads the head of the memory and at the same time immediately confirms that the responder exists. It becomes possible to do. More generally, it is convenient for the interrogator to quickly confirm the presence of the responder by providing a bit that logically indicates the presence of data in the first half of at least half of the transmitted data.

  FIG. 11 shows an example of a counter flip-flop used in the present invention. The NOR gate 1101 has a ground terminal 1103 and a selector terminal 1104 that receive a signal from the AND gate 1102 and a set (S) signal, and is connected to one of the switching terminals 1105. In this example, the ground terminal is connected to the switching terminal. The switching terminal is inverted by the PMOS transistor 1106 and the NMOS transistor and input to the AND gate. First, when the S signal is electrically changed from L → H → L level, the output (OUT) of the flip-flop becomes an electrical L level. Next, when the ground terminal is connected to the switching terminal as in the example of this figure, this state is maintained until the clock pulse (CLK) is received. If the switching terminal is connected to the selector terminal, the output (OUT) of the flip-flop changes from L → H when the select terminal changes from L → H → L level. That is, 1 is logically set.

  FIG. 12 shows a pattern 1203 showing a part of the layout pattern of FIG. 11 and a pattern dropped to the ground potential 1103 in FIG. Reference numeral 1204 denotes a pattern connected to the selector terminal 1104 in FIG. 1205 in FIG. 12 has a pattern corresponding to 1105 in FIG.

  The first through hole 1201 is used to connect the upper metal pattern 1204 indicating the selector terminal and the lower metal pattern 1205 indicating the connection terminal, and the second through hole 1202 is connected to the upper metal pattern 1203 indicating the ground terminal. It is used for connection with a lower metal pattern 1205 indicating a connection terminal. Either the first through-hole 1201 or the second through-hole 1202 is formed with a pattern by a glass mask pattern or electron beam direct drawing. The number is directly written to each RFID tag chip on the wafer by electron beam direct drawing. This number may be a random number. The numbers are written so that the same page number does not exist on the wafer, or the numbers are distributed within the wafer and between the wafers. That is, the circuit shown in FIG. 11 can be realized in a compact manner by using only the wiring and the through hole. Normally, when setting a random number in a flip-flop, a random number generating circuit or a complicated circuit for setting is required, but it can be realized with a small area by forming it with a pattern.

  FIG. 14 shows a circuit for detecting the interval between clock pulses. The output of the first inverter gate 1401 is a signal (CK1) indicating the detection result. In FIG. 14, the resistor R1, resistor R2, transistor Q1, and transistor Q2 allow a constant current to flow through the transistor Q3. Since the responder can supply energy from the interrogator to the responder when there is a carrier wave, the clock pulse signal (CLK) in the figure is set shorter when electrically L than when it is electrically H. Is done. In other words, when CLK has an H level, the clock pulse is at a negative logic when the clock pulse is at an L level. Accordingly, when CLK is at the H level in FIG. 14, the transistor Q4 is a PMOS transistor and is turned off. At this time, when the first clock pulse is input, CLK becomes L level and the transistor Q4 is turned on. Then, the capacitor C1 is charged up. CK1 changes from H to L level. Next, although the charge of C1 is extracted by the transistor Q3, the transistor Q4 is turned on and charged up to C1 each time a clock pulse with a short interval. Conversely, if the interval between clock pulses is long, the voltage of C1 will eventually drop due to the charge extraction of C1, and CK1 will eventually go from L to H level. Eventually, when a clock pulse comes, CK1 returns to the H → L level. That is, when the clock pulse interval is long enough to extract the charge of C1, the signal of CK1 outputs a signal of L → H → L.

  FIG. 1 shows the clock pulse interval sorting circuit 116 of FIG. FIG. 1 is a circuit based on the circuit of FIG. 14, to which transistors Q5 and Q6, a capacitor C2, and an inverter 1402 are added. The first inverter gate 1402 is an inverter output (CK2) having the capacitor C2 as an input.

  It is possible to detect clock pulses (CK1, CK2) at different intervals by adding a few elements to FIG. 14 and changing the capacitance between C1 and C2. In this embodiment, C2 is made larger than the capacity C1. An example of realizing this is the transistor Q6, the transistor Q5, and the capacitor C2 in FIG. Compared to the case where the capacitance value of C2 is increased or the gate length of Q5 is increased so that the CK1 signal becomes L → H → L level, and there is a clock pulse with a long interval, the CK2 signal becomes L → H → L level. Become.

  FIG. 4 shows a memory format in the wireless IC tag chip of the present invention. The header portion 401 is at the top of the memory, the identification number 402 is at the center of the memory, and the page number portion 403 is at the end of the memory. The header portion 401 is a display bit indicating the presence of a transponder, and has a function to notify the interrogator of the presence of the transponder as soon as possible. That is, it is convenient for the interrogator to quickly confirm the presence of a responder capable of transmitting the identification number before preparing the bit that electrically indicates the H level before transmitting the identification number. It is also possible to make the header portion 401 a part of the identification number 402. The page number part 403 may also be used as the entire error check code. In this way, when the wireless IC tag data is transmitted in the order controlled by the page number in the congestion control, if the reader is normal, it is confirmed that there is no error, and at the same time, the page number order. It is possible to immediately confirm that data is being transmitted.

  As described above, the present invention simplifies the congestion control method for the responder and the interrogator, and improves the mass productivity by increasing the number of chips (RFID tags) with the congestion control function that can be cut out from the wafer. Reduction is possible.

  A disposable RFID can be obtained by improving the mass productivity and reducing the manufacturing unit price.

  Furthermore, it is possible to arrange a plurality of RFIDs in the effective radio wave area of the interrogator, and further, it is possible to expand the effective radio wave area of the interrogator to a range equal to or larger than the size of the RFID mounted object and the arrangement interval. .

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, there may be two types of clock pulses, and the functions of long and short clock pulses may be reversed. The responder may store various data instead of the identification number.

  It can be used for RFID, which is the technical field behind this application. Further, the present invention is not limited to this, and can be applied to congestion control in a general wireless LAN or a mobile phone, for example.

Claims (11)

A first counter;
A second counter;
A memory for storing an identification number;
The first counter counts a first clock pulse from an initial value;
After the count value of the first counter reaches a predetermined value, the second counter counts the second clock pulse,
The responder, wherein the memory reads each bit of the identification number in accordance with a count value of the second counter. The responder of claim 1, wherein
Having a decoder;
The decoder decodes the count value of the second counter;
The responder, wherein the memory reads each bit of the identification number selected by the output of the decoder. The responder of claim 1, wherein
The responder according to claim 1, wherein an interval between the first clock pulses is different from an interval between the second clock pulses. The responder of claim 1, wherein
The responder according to claim 1, wherein an interval between the first clock pulses is longer than an interval between the second clock pulses. The responder of claim 1, wherein
The transponder receives the ASK-modulated first clock pulse and second clock pulse. A counter,
An operation switching flip-flop;
A memory for storing an identification number;
When the operation switching flip-flop is in a reset state, a first clock pulse is input to the counter,
When the operation switching flip-flop is in a set state, a second clock pulse is input to the counter,
The counter counts the first clock pulse from the initial value,
When the count value of the counter reaches 0, the counter outputs a carry,
After the operation switching flip-flop transitions to the set state by the carry, the counter counts the second clock pulse, and the memory reads each bit of the identification number according to the count value of the counter To respond. The responder according to claim 6, wherein
When the operation switching flip-flop is in the reset state, the operation switching flip-flop outputs a first signal of a first level;
The responder, wherein when the operation switching flip-flop is in the set state, the operation switching flip-flop outputs a second signal of a second level. The responder according to claim 7, wherein
Having a decoder;
The decoder decodes the count value of the counter;
The responder, wherein the memory reads each bit of the identification number selected by the output of the decoder. The responder according to claim 7, wherein
The responder according to claim 1, wherein an interval between the first clock pulses is different from an interval between the second clock pulses. The responder according to claim 7, wherein
The responder according to claim 1, wherein an interval between the first clock pulses is longer than an interval between the second clock pulses. The responder according to claim 7, wherein
The transponder receives the first clock pulse and the second clock pulse that are ASK-modulated.

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