JP4836724B2 - Phase adjustment circuit and test apparatus - Google Patents

Description

  The present invention relates to testing of semiconductor devices such as LSI and SRAM.

  The dual port memory has two ports for reading and writing data. This allows reading and writing separately from the two ports. In the test of the dual port memory, a test is performed by inputting a clock signal and a control signal to each of the two ports.

  According to the conventional dual port memory test method described in JP-A-7-73699, JP-A-2004-13980, and the like, as a test content, a write clock signal to the memory input from the outside, By adjusting the read clock signal itself, a memory test in each phase relationship is performed. Japanese Patent Laid-Open Nos. 7-73699 and 2004-13980 describe methods for avoiding abnormal access.

  Note that the strobe signal delay device described in Japanese Patent Application Laid-Open No. 2006-12363 has a delay to a flip-flop of a strobe signal corrected by a delay element in an interface portion of a data receiving device using a delay element (DLL). The goal is to eliminate values and their variations. For this reason, the strobe signal is output with a phase delay using a delay element. The delayed phase is detected to control the delay amount of the delay element. The memory test is not described.

JP-A-7-73699 Japanese Patent Laid-Open No. 2004-13980 JP 2006-12363 A

  Due to the recent miniaturization process, there is a concern about memory operation failure due to the influence of leak, noise, etc. in the memory operation. In particular, regarding dual port memory, simultaneous operation of a write clock and a read clock occurs, so there is a concern that the dual port memory may not operate normally due to the influence of crosstalk due to the simultaneous operation and the occurrence of noise.

  According to the conventional dual port memory test methods described in Japanese Patent Application Laid-Open Nos. 7-73699, 2004-13980, etc., in the memory test, the write clock signal and the read clock to the memory input from the outside Each signal is adjusted. For this reason, when the dual port memory test in each clock phase relationship is performed, a great work period is required for test pattern creation, and the test time also increases.

  An object of the present invention is to make it possible to easily test a variation in a phase difference between a write clock signal and a read clock signal with respect to a dual port memory.

The phase adjustment circuit according to the first invention is:
A calculation circuit that includes a plurality of delay buffers connected in series, and that calculates the number of delay buffers according to the period of the clock signal when an input clock signal propagates through the plurality of delay buffers;
A plurality of delay buffers connected in series and a selection circuit; the clock signal input to the calculation circuit is input; and the plurality of delay buffers are propagated to phase the clock signal by a phase delay amount. A delay clock generating circuit that generates a plurality of delayed clock signals by delaying, and selects and outputs one of the plurality of delayed clock signals by the selection circuit ;
A phase difference control circuit that sets the phase delay amount not exceeding the number of delay buffers based on the number of delay buffers calculated by the calculation circuit and outputs the phase delay amount to a selection circuit of the delay clock generation circuit;
The phase difference control circuit can input a phase difference control signal for controlling the phase difference from the outside, and is generated by the delay clock generation circuit corresponding to the number of delay buffers and the phase difference control signal. Set a phase difference between the plurality of delay clock signals, sequentially generate the phase delay amount corresponding to the plurality of delay clock signals, and output to the selection circuit of the delay clock generation circuit,
The selection circuit selects one delayed clock signal from the plurality of delayed clock signals at a predetermined phase interval, and outputs the selected delayed clock signal to a dual port memory having two ports. A port memory test is performed.

In the phase adjustment circuit, preferably, the phase difference control circuit further divides one phase of the input clock signal to shift the phase difference based on a predetermined phase division control signal indicating the number of divisions. And the phase interval is set in the selection circuit .

  In the phase adjustment circuit, preferably, the phase difference control circuit is further capable of inputting a phase adjustment signal from the outside, and changing the phase of the delay clock signal in response to the phase adjustment signal to generate the delay clock signal. Output.

The test apparatus according to the second invention is
For the dual port memory having the two ports, the phase adjustment circuit comprising a phase adjustment circuit that inputs a write clock signal or a read clock signal as the clock signal and outputs the clock signal after being delayed by the phase delay amount. Test equipment,
The test apparatus further inputs a clock signal delayed by the phase delay amount from the phase adjustment circuit, and inputs a second write clock signal or a read clock signal, and the two ports of the dual port memory And a built-in self-test circuit for generating two clock signals for accessing each .

A tester device according to a third invention is
A first phase adjusting circuit that is configured to input a first write clock signal or a read clock signal as the clock signal and output the delayed clock signal as a first delayed clock signal;
A second phase adjustment circuit for inputting a second write clock signal or a read clock signal as the clock signal and outputting the delayed clock signal as a second delayed clock signal; A test apparatus for a dual port memory having the two ports,
The test apparatus further receives the first delayed clock signal from the first phase adjustment circuit, and receives the second delayed clock signal from the second phase adjustment circuit, and the dual port memory. And a built-in self-test circuit for generating two clock signals for accessing the two ports .

  The dual port memory can be easily and automatically tested for variations in the phase difference between the write clock and read clock. Since the test with the clock phase adjustment in fine units is easy, the test accuracy is also improved. Since the test can be performed while automatically shifting the phases of the write clock signal and the read clock signal, the labor for creating the test pattern and the amount of the test pattern are greatly reduced, and the test time is also shortened. As a result, significant effects can be obtained in terms of cost and delivery.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

  In the present invention, in the dual port memory test, the phase relationship between the write clock and the read clock can be controlled inside the phase adjustment circuit.

  A phase adjustment circuit 10 shown in FIG. 1 is used for testing a dual port memory, and receives a write clock signal or a read clock signal (hereinafter also simply referred to as a clock signal) and a phase division control signal for memory access, A clock signal whose phase (timing) is adjusted is output. The phase adjustment circuit 10 includes a DLL circuit 12, a phase difference control circuit 14, and a delay clock selection circuit 16.

  The DLL circuit 12 includes a predetermined number (for example, 9 stages) of delay buffers, and propagates a clock signal input from the outside through the delay buffer, and calculates how much of one cycle of the input clock corresponds to the delay buffer. It has a function to do. On the other hand, the delay clock selection circuit 16 also includes a delay buffer equivalent to the inside of the DLL circuit 12. Since the number of delay buffers for one cycle of the memory access clock can be calculated in the DLL circuit 12, it can be understood how much clock delay can be added in one cycle of the clock, and based on that, the delay clock selection circuit 16 Thus, the clock signal delayed by the required delay phase amount in the delay buffer can be selected and output as a delayed clock signal.

  FIG. 2 shows the configuration of the DLL circuit 12. The DLL circuit 12 includes a delay element 34 including a delay buffer 30 and a selection circuit 32 connected in series in a predetermined number (for example, 9 stages), a phase comparator 36, and a delay control circuit 38. A clock signal is input to the delay buffer 30 and the phase comparator 36 from the outside. The clock signal is delayed every time it passes through each delay buffer 30, thereby generating a clock signal delayed by 10 stages. These 10 delayed clock signals are input to the selection circuit 32. The delay control circuit 38 sequentially outputs a clock selection signal to the selector 32. In response to this, the selector 32 selects the delayed clock signal in the order of the phase delay amount and sends it to the phase comparator 36. The phase comparator sends the result of the phase comparison to the delay control circuit 38. From the phase comparison result, the delay control circuit 38 calculates the number of delay buffers, that is, how many of the delay clocks correspond to one period of the input clock, and sends it to the phase difference control circuit 14.

  Referring back to FIG. 1, the phase difference control circuit 14 inputs the output signal of the DLL circuit 12 (that is, the number of delay buffers corresponding to the clock cycle) and the delay setting value from the outside, and receives the delay clock. The selection signal is output to the delay clock selection circuit 16.

  The delay clock selection circuit 16 includes a predetermined number (for example, nine) of delay buffers 18 connected in series and a selection circuit 20. The same clock signal as that input to the phase adjustment circuit 10 is input to the delay clock selection circuit 16. The clock signal is delayed every time it passes through each delay buffer 16, thereby generating a clock signal delayed by 10 stages. A clock signal delayed in 10 steps is input to the selection circuit 20. The selection circuit 20 receives the delay setting value from the phase difference control circuit 14 as a delay clock selection signal, and selects and outputs the corresponding delay clock signal. That is, since the delayed clock selection signal output from the phase difference control circuit 14 corresponds to the phase delay amount of the clock signal, the delayed clock selection circuit 16 delays the clock signal in response to the delayed clock selection signal. .

  1 is assembled with a built-in self test (BIST) circuit 22 as shown in FIG. 3, thereby assembling a test apparatus for performing a test for the dual port memory 24. FIG. The test circuit 26, the BIST circuit 22 and the dual port memory 24 are arranged on one PCB board 28. The dual port memory 24 is a memory having two ports. In addition to the phase adjustment circuit 10 shown in FIG. 1, the test circuit 26 includes an input / output unit for outputting another write clock signal or read clock signal directly to the BIST circuit 22. The phase adjustment circuit 10 outputs the delayed write clock signal or read clock signal to the BIST circuit 22 as described above. The BIST circuit 22 generates a clock signal for accessing the dual port memory 24 based on the two input clock signals, and outputs it to the two ports of the dual port memory 24. The BIST circuit 22 is used for test automation, and can automatically generate test data and access the memory.

  FIG. 4 shows the configuration of the BIST circuit 22. Upon receiving the start signal, the BIST controller 40 generates a test pattern to be given to the test target circuit (dual port memory 24) and outputs the test pattern to the two ports of the memory 24. The comparator and test result compression circuit 42 compares the output pattern from the test target circuit 24 with the expected output pattern, and compresses and outputs the result. Since the configuration of the built-in self-test circuit 22 is the same as that of a normal built-in self-test circuit, its detailed description is omitted.

  The feature of this test apparatus is that the test target circuit can be tested by automatically shifting the phase difference. The phase difference control circuit 14 sets the phase delay amount so as to automatically shift the phase difference. For example, the phase delay amount automatically increases sequentially from 0 to the number of delay buffers calculated by the DLL circuit 12. Thereby, the test of the dual port memory can be repeatedly performed by automatically shifting the phase relationship of the clock signal. For this reason, the phase adjustment circuit 10 greatly reduces the labor and time required to create a test pattern for testing a dual port memory, and the test time. As a result, a great effect can be obtained in terms of test cost and delivery time.

Preferably, the phase difference control circuit 14 receives a delay setting value from the outside. The delay set value is used for selecting a delay amount in the delay clock selection circuit 16. For example, the delay setting value is a phase division control signal shown in FIG. For example, the number of delay buffers is divided by the phase division control signal using a divider, and the delay amount is set based on the quotient. For example, when the number of delay buffers that are clock cycles is 10, and the phase division control signal is 5, the clock cycle is divided into five. At this time, the phase difference control circuit 14 selects and outputs phase delay amounts corresponding to the five sub-periods. The delay setting value may not be the number of phase divisions. For example, a selection may be made at a predetermined phase interval from a plurality of clock signals input to the selection circuit. In this case, the phase interval is input. For example, when the phase interval is 2, every two clock signals are selected from the plurality of clock signals.

  When the number of divisions is used, for example, it is assumed that the delay clock selection circuit 16 has 10 delay clock selection signals as the input clock to the selection circuit 20. Here, according to the phase division control signal (number of divisions), it is possible to arbitrarily determine how much one period of the input clock is divided to shift the phase difference and whether to perform the memory test with the shifted clock. . This makes it possible to test the memory while automatically adjusting the clock phase simply by setting the number of divisions.

  As shown in FIG. 5, if the number of delay buffers (one cycle) is 10 and the division number is set to 10, the first input clock is set in order. Here, as shown in FIG. 6, after setting the first input clock, the memory test is performed, then after setting the second input clock, the memory test is performed, and then after setting the third input clock. A memory test is performed, and finally a memory test is performed after setting the tenth input clock. Thereby, a memory test is performed at a phase difference of 10 clocks. As shown in FIG. 7, when the number of delay buffers is 10 and the number of divisions is set to 5, a memory test is performed after setting the first input clock, and then after setting the third input clock. A memory test is performed, and then a memory test is performed after setting the fifth input clock, and finally a memory test is performed after setting the ninth input clock. In this way, a total of five memory tests are performed with the phase difference automatically shifted.

  Also, as shown in FIG. 8, an external phase adjustment signal may be input to the phase difference control circuit 14 in order to shift the phase delay amount by a specific value relative to the input clock. The phase difference control circuit 14 changes the phase of the delayed clock signal in response to the phase adjustment signal and outputs the delayed clock signal. For example, one or more delay elements are connected in series, and the clock phase is delayed in accordance with the set external phase adjustment signal. Thus, the dual port memory can be accessed at a specific clock phase without changing the phase of the external clock. The delay element may be provided in the phase difference control circuit 14 or may be provided on the output side of the delay clock selection circuit 20. Thus, a memory test at a specific clock phase is possible. Thus, debugging efficiency is improved when a specific clock phase can be specified. In addition, since the test with the clock phase adjustment in fine units is easy, the test accuracy is also improved.

  Also, usually, once a chip is attached to the PCB board, adjusting the clock phase is a laborious operation. However, since the clock phase can be controlled externally using an external phase adjustment signal, the internal clock phase relationship can be adjusted and tested without adjusting the clock phase outside the chip.

  The BIST circuit 22 generates a clock signal based on the phase adjustment clock generated by the test circuit 26 and accesses the dual port memory 24. Since the BIST circuit 22 is used for accessing the memory 24, the test data is automatically generated by the BIST circuit 22 and the memory can be accessed. In addition to this, the clock phase is also automatically shifted by the test circuit 26. Testing is possible.

  The test circuit 26 ′ shown in FIG. 9 includes two phase adjustment circuits 10 for the read clock and the write clock, respectively. The test circuit 26 ', the BIST circuit 22 and the dual port memory 24 are arranged on one PCB board 28'. Since the phase adjustment circuit 10 is used for each of the read clock and the write clock, the dual port memory 24 can be tested while simultaneously delaying the phases of both clocks.

Circuit diagram of phase adjustment circuit DLL circuit diagram Circuit diagram of dual port memory test equipment with timing adjustment BST circuit block diagram Block diagram in which the division signal is 10 in the DLL of the selection signal 10 Waveform diagram when the selection signal 10 is DLL and the division signal is 10 Waveform diagram when the division signal is 5 in the DLL of the selection signal 10 Dual port schematic with timing adjustment Schematic of dual port device with timing adjustment for read clock and write clock

Explanation of symbols

  10 phase adjustment circuit, 12 DLL circuit, 14 phase difference control circuit, 16 delay clock selection circuit, 18 delay buffer, 20 selection circuit, 22 built-in self test circuit, 24 dual port memory, 26 test circuit.

Claims (5)

A calculation circuit that includes a plurality of delay buffers connected in series, and that calculates the number of delay buffers according to the period of the clock signal when an input clock signal propagates through the plurality of delay buffers;
A plurality of delay buffers connected in series and a selection circuit; the clock signal input to the calculation circuit is input; and the plurality of delay buffers are propagated to phase the clock signal by a phase delay amount. A delay clock generating circuit that generates a plurality of delayed clock signals by delaying, and selects and outputs one of the plurality of delayed clock signals by the selection circuit ;
A phase difference control circuit that sets the phase delay amount not exceeding the number of delay buffers based on the number of delay buffers calculated by the calculation circuit and outputs the phase delay amount to a selection circuit of the delay clock generation circuit;
The phase difference control circuit can input a phase difference control signal for controlling the phase difference from the outside, and is generated by the delay clock generation circuit corresponding to the number of delay buffers and the phase difference control signal. Set a phase difference between the plurality of delay clock signals, sequentially generate the phase delay amount corresponding to the plurality of delay clock signals, and output to the selection circuit of the delay clock generation circuit,
The selection circuit selects one delayed clock signal from the plurality of delayed clock signals at a predetermined phase interval, and outputs the selected delayed clock signal to a dual port memory having two ports. A phase adjustment circuit for performing a test of a port memory. The phase difference control circuit further determines, based on a predetermined phase division control signal indicating the number of divisions, how much one period of the input clock signal is divided to shift the phase difference, and sets the phase interval. 2. The phase adjustment circuit according to claim 1, wherein the phase adjustment circuit is set in the selection circuit. The phase adjustment circuit according to claim 1 or 2,
The phase difference control circuit is further capable of inputting a phase adjustment signal from the outside, and changing the phase of the delayed clock signal in response to the phase adjustment signal and outputting the delayed clock signal. , Phase adjustment circuit. The phase adjustment circuit according to any one of claims 1 to 3, further comprising: a phase adjustment circuit that inputs a write clock signal or a read clock signal as the clock signal and outputs the clock signal after being delayed by the phase delay amount ; A test apparatus for a dual port memory having the two ports,
The test apparatus further includes
A clock signal delayed by the phase delay amount is input from the phase adjustment circuit, and a second write clock signal or a read clock signal is input to access each of the two ports of the dual port memory. A test apparatus comprising an embedded self-test circuit for generating two clock signals. A phase adjusting circuit according to claim 1, the first write clock signal or the read clock signal input as the clock signal, outputting the delayed clock signal as a first delayed clock signal A first phase adjustment circuit that
A phase adjusting circuit according to claim 1, the second write clock signal or the read clock signal input as the clock signal, outputting the delayed clock signal as a second delayed clock signal A test device for a dual port memory having the two ports, comprising:
The test apparatus further includes
The first delayed clock signal is input from the first phase adjustment circuit, and the second delayed clock signal is input from the second phase adjustment circuit to access two ports of the dual port memory. A test apparatus comprising an embedded self-test circuit that generates two clock signals for performing

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