JP4824228B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device using a chip size package (CSP), and more particularly to a semiconductor device capable of increasing the flexibility of circuit design by utilizing rewiring in the CSP. The present invention is particularly applicable to a phase compensation circuit for a voltage regulator mounted on a CSP and other various analog circuits mounted on a CSP.
[0002]
[Prior art]
Many types of LSI chip packages are known, but in recent years, in order to further reduce the size of the package, a package of almost the same size as the chip, that is, a chip size package (CSP) is known. Has been developed.
[0003]
11A and 11B are diagrams showing manufacturing processes of various conventional CSPs. FIG. 11A shows a manufacturing process of a lead frame package, FIG. 11B shows a manufacturing process of an FBGA (Fine-pitch Ball Grid Array), and FIG. FIG. 3C shows a manufacturing process of the wafer level CSP.
[0004]
The lead frame package of FIG. 11 (a) and the FBGA of FIG. 11 (b) are basically the same as the conventional processes (cutting chip A1, die bonding A2, wire bonding A3, sealing A4, lead formation A5 / lead surface). Process solidification A6 or electronic process solidification A7), that is, individual chips are cut out by dicing from a pre-processed wafer and assembled into a package. The wafer level CSP according to the present invention is As shown in FIG. 11C, package processing (Pi film formation A11, rewiring process A12, post formation A13, sealing A14, and grinding terminal process A15) is directly performed on the pre-processed wafer, and thereafter (Dicing A16).
[0005]
FIG. 12 is a diagram showing a detailed cross section of a chip manufactured using the wafer level CSP technology. In this figure, B1 is an IC chip (silicon chip), B2 is an aluminum electrode provided on the pad of the IC chip B1, B3 is a barrier metal layer, and B4 is a redistribution layer (copper copper) provided on the barrier metal layer B3. Cu) and B5 are posts made of copper, B6 is a solder bump (solder ball) placed on the copper post, B7 is a passivation film, and B8 is a mold (sealing resin such as epoxy).
[0006]
The above is the description of the configuration of the conventional wafer level CSP. In the conventional wafer level CSP, the IC pad and the aluminum electrode B2, the copper post B4, and the solder bump (solder ball) B6 provided on the IC pad are as much as possible. It was assumed that the rewiring B4 having a small resistance was connected in a one-to-one relationship.
[0007]
[Problems to be solved by the invention]
However, when it is assumed that the IC pad and the aluminum electrode B2 provided on the IC pad and the copper post B4 and the solder bump (solder ball) B6 are connected one-to-one by a redistribution layer having the smallest possible resistance, There is a problem that the specifications and performance of the CSP itself are limited by the structure of the IC chip.
[0008]
An object of the present invention, the solve the problems, a semiconductor device having a possible flexibility to extend the specification and performance with IC chips originally (Claim 1, 2), particularly easy voltage regulator suppression of oscillation to provide a semiconductor device including a circuit (claims 3, 4).
[0009]
The present invention employs the following configuration in order to achieve the above object. That is, the invention according to claim 1 is a semiconductor device including a CSP in which a redistribution layer is formed on a chip, and a gap between one bonding pad on the chip and a plurality of terminals of the CSP is within the CSP . different paths from each other, and wherein at least one path is connected by rewiring with a desired resistance value, according to a second aspect of the invention, the desired resistance of the redistribution, the width of the rewiring layer, the length It is characterized by being obtained by changing the layout of at least one of the materials.
[0010]
According to a third aspect of the present invention, a chip including a voltage regulator circuit is used as the chip, an output load is connected to a terminal to which a rewiring having a low resistance value is connected, and a resistance value is high. A capacitor for phase compensation is connected to a terminal to which the rewiring is connected, and the invention according to claim 4 sets the resistance value of the rewiring connected to the capacitor for phase compensation to 10 mΩ to 10Ω. It is characterized by that.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIG. 1 is a diagram for explaining a first embodiment of the present invention, and shows an example in which bonding pads of an IC chip and a plurality of solder bumps (CSP output terminals) are connected via a rewiring layer. .
[0012]
FIGS. 4A and 4B are a configuration example in which one bonding pad 1 of an IC chip and two solder bumps 2 and 3 which are output terminals of a CSP are connected by rewiring layers 4a and 4b, and an equivalent circuit diagram thereof. (C) and (d) are a configuration example in which one bonding pad 11 of an IC chip and three solder bumps 12 to 14 which are output terminals of a CSP are connected by rewiring layers 15a to 15c and an equivalent circuit diagram thereof. is there. Similarly, it goes without saying that a configuration in which one bonding pad and four or more solder bumps are connected by a rewiring layer is also possible.
[0013]
By adopting this configuration, a plurality of solder bumps are provided at desired positions, and a plurality of solder bumps and arbitrary bonding pads are connected by a rewiring layer, so that signals of arbitrary bonding pads are provided at desired positions. Therefore, it is possible to take out from the solder bumps, and the application range of the CSP can be greatly expanded.
[0014]
(Second embodiment)
In the first embodiment, the resistance of the redistribution layer is not considered (or on the assumption that the resistance is 0). However, in the second embodiment, a reconnection between any bonding pad and each solder bump is performed. The resistance of the wiring layer is designed to have a predetermined resistance value.
[0015]
FIG. 2 is a diagram for explaining the second embodiment. FIG. 2A shows the rewiring 4 in which one bonding pad 1 and two solder bumps 2 and 3 are connected in FIG. For example, the resistance values are equivalent circuit diagrams in the case where the resistance value is set to 0 and the resistance value r1, respectively. FIG. 1B shows a bonding pad 11 and three solder bumps 12 to 14 in FIG. It is an equivalent circuit diagram when the resistance values of the redistribution layers 15a to 15c to be connected are set to, for example, a resistance value 0 and resistance values r2 and r3, respectively. The value of the resistance value of each redistribution layer is a design matter that is determined by what kind of circuit is the target circuit. By adopting this configuration, the application range of the CSP can be further expanded compared to the first embodiment.
[0016]
(Third embodiment)
The present invention can be applied to various general analog circuits and various semiconductor devices. Here, an example applied to a voltage regulator will be described as a third embodiment.
FIG. 3 is a circuit diagram of a general voltage regulator in use.
In the figure, as an external element of the voltage regulator 20, a capacitor 21 for stabilizing the input voltage and the output voltage is inserted between Vin-GND and Vout-GND. For the capacitor 21 connected to the Vout terminal, ESR (Equivalent Series Resistance) which is the internal resistance of the capacitor itself is also shown.
[0017]
FIG. 4 is a diagram showing an internal configuration of a general voltage regulator. As shown in the figure, the general voltage regulator 30 is constituted by a negative feedback circuit composed of a constant voltage source 31, a differential amplifier 32, an output transistor 33, and resistors 34 and 35, and there is a risk of oscillation.
[0018]
That is, a normal voltage regulator has a total of two or three poles (a gain is lowered by 20 dB and a phase is delayed by 90 degrees) with a differential amplifier (which may be configured in two stages) and an output transistor. The frequency characteristics are as shown in FIG. FIG. 4A is a diagram showing a frequency-gain relationship, and FIG. 4B is a diagram showing a frequency-phase delay relationship. Therefore, there is a possibility that the phase is delayed by 180 degrees or more as shown in FIG. Therefore, it is necessary to suppress oscillation by performing phase compensation.
[0019]
Although the phase compensation is also performed in the internal circuit of the voltage regulator 20, the zero (the reverse of the pole) generated by the capacitance of the capacitor 21 attached to the output terminal and the resistance of the ESR is also used. Therefore, in the state of FIG. 3, zero appears at 1 / (2π · Cout · ESR) [Hz], so that the phase is advanced as shown in FIG. 6 and the phase delay at point C in the figure does not exceed 180 degrees. It becomes possible to do so. As a result, oscillation can be prevented.
[0020]
Examples of the capacitor 21 used in the voltage regulator 20 include a tantalum capacitor and a ceramic capacitor. The ESR (Equivalent Series Resistance) of these capacitors is about several Ω for a tantalum capacitor and about several tens of mΩ for a ceramic capacitor.
[0021]
When a tantalum capacitor is used, with a capacitance value (about several μF) that is generally used at present, the frequency where zero can be generated is near the frequency at which the gain becomes 0 dB (the phase is delayed as the frequency becomes higher, so it is inevitably 0 dB). In many cases, the phase margin can be eliminated), so that phase compensation is relatively easy.
[0022]
However, when the same capacitance value is used in the ceramic capacitor, since ESR is smaller than that of the tantalum capacitor, zero is generated on the high frequency side, and the effect of phase compensation is reduced. As a result, phase compensation becomes difficult. In other words, phase compensation is facilitated if the ESR of the ceramic capacitor can be compensated by some method to make it as large as a tantalum capacitor.
[0023]
Therefore, if the voltage regulator is mounted on the CSP as described in the first embodiment or the second embodiment, the ESR of the ceramic capacitor can be compensated by using the wiring resistance of the rewiring in the CSP. Thus, phase compensation of the voltage regulator can be easily performed.
[0024]
Hereinafter, an example in which the voltage regulator is mounted on the CSP will be specifically described.
As described above with reference to FIG. 11, the CSP has a protective film stacked on the passivation film B7 of the IC chip B1, and solder bumps serving as CSP output terminals from the aluminum electrode B2 of the bonding pad portion thereon. After rewiring using copper between the copper posts B5 formed below, sealing is performed with a sealing resin B8, and solder bumps (solder balls) are placed thereon.
[0025]
As described above, ESR needs to be compensated for facilitating the phase compensation of the ceramic capacitor. For this purpose, a resistor is added to the output terminal although it is a small value. However, when a resistor is added, when a load current is passed, the added resistor causes a voltage drop and the characteristics deteriorate, which is not preferable.
[0026]
However, as described with reference to FIG. 2A, the above problem is solved by connecting one bonding pad of the IC chip and two solder bumps (output terminals) using redistribution layers having different paths. Can do.
[0027]
That is, as shown in FIG. 7, a terminal (solder bump) 42 for connecting the output load 47 and a terminal (solder bump) 43 for connecting a capacitor (capacitor) 45 are provided separately, and the terminal 42 for connecting the output load 47 and the IC Wiring resistance Rout (several hundreds) for preventing ESR 46 between the terminal 43 for connecting the capacitor 45 and the bonding pad 41 of the IC chip is as small as possible between the bonding pad 41 of the chip. The copper redistribution layer is laid out so that the wiring length is intentionally increased or the wiring width is narrowed so that 44 is formed. As a result, the resistance value of the ESR 46 can be compensated while preventing a voltage drop when a current is passed, and as a result, phase compensation can be easily performed.
[0028]
In this case, since it is a CSP, the mounting area does not increase by increasing the number of terminals. Furthermore, it is possible to use a capacitor connection pin with an ESR having an optimum value added to the capacitor to be used by taking out a plurality of pins by changing the resistance value of the rewiring layer. A cross-sectional view and a top view of the rewiring pattern that realizes the above contents are shown in FIGS.
[0029]
Here, the value of the wiring resistance Rout44 formed by the rewiring layer in the circuit configuration of FIG.
Since the capacitance value of the capacitor connected to the commonly used output terminal is about 0.1 μF to 10 μF and the resistance Rout inserted into the output terminal in order to divide the output terminal into a plurality can be increased. In the case of the circuit configuration of FIG. 7, it seems appropriate that the resistance value Rout added between the output of the voltage regulator and the capacitor is a resistance value of about 10 mΩ to 10Ω. FIG. 10 is a diagram showing the relationship between the resistance value Rout and the stability of the circuit at this time. Oscillation can be stopped even with a resistance value of 10Ω or more, but it is not practical to make such a resistor in the rewiring layer because it requires a lot of space, so in this embodiment, the range is set to 10 mΩ to 10Ω.
[0030]
In the third embodiment, when a voltage regulator corresponding to a ceramic capacitor is mounted on a CSP, an example is shown in which phase compensation is performed by the CSP to suppress oscillation. The present invention in which the output can be taken out to a plurality of solder bumps (output terminals) of the CSP using the wiring layer is not limited to the voltage regulator but can be applied to the case where various analog circuits having various functions are mounted. Not too long.
[0031]
The resistance value of the rewiring can be set to a desired value by laying out by changing at least one of the width, length, and material of the rewiring layer.
[0032]
As described above, according to the present embodiment, the circuit characteristics can be determined by the circuit design in the manufacturing process of the CSP, so that the degree of freedom in circuit design at the wafer level is increased and satisfactory. Even if the characteristics cannot be obtained, the characteristics can be improved without changing the circuit at the wafer level.
[0033]
Furthermore, since it is a CSP, it is possible to increase the number of terminals without increasing the package size, so that it is possible to provide a plurality of output terminals for different applications, eliminating the disadvantage of characteristic degradation caused by adding resistors to the output terminal side. Is possible. In addition, since there are a plurality of terminals to which wiring resistance is added, the range of types of capacitors used for phase compensation is widened.
[0034]
【The invention's effect】
According to the present invention, a flexible semiconductor device capable of extending specifications and performance inherent in an IC chip (claims 1 and 2 ), particularly a semiconductor device including a voltage regulator circuit that can easily suppress oscillation ( Claims 3 and 4 ) can be obtained.
[0035]
In other words, since circuit constants (wiring resistance in this item) that can be determined in the manufacturing process of the chip size package (CSP) are used for phase compensation, the characteristics are improved by modifying the CSP without changing the circuit at the wafer level. (Claims 1 and 2 ). Further, the design margin at the wafer level is expanded (claims 1 and 2 ). In particular, it becomes easy to develop a voltage regulator that does not oscillate for ceramic capacitors (claims 3 and 4 ).
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a first embodiment of the present invention.
FIG. 2 is a diagram for explaining a second embodiment of the present invention.
FIG. 3 is a circuit diagram of a general voltage regulator in use.
FIG. 4 is a diagram showing an internal configuration of a general voltage regulator.
FIG. 5 is a diagram illustrating frequency characteristics of a voltage regulator that causes oscillation.
FIG. 6 is a diagram illustrating frequency characteristics of a voltage regulator that does not cause oscillation.
FIG. 7 is a diagram for explaining a third embodiment (voltage regulator) of the present invention.
8 is a cross-sectional view of the rewiring pattern of FIG. And top view,
9 is a top view of the rewiring pattern of FIG. 7. FIG.
10 is a diagram showing the relationship between the value of a resistor Rout and the stability of the circuit in the configuration of FIG.
FIG. 11 is a diagram showing manufacturing steps of various conventional CSPs.
FIG. 12 is a view showing a detailed cross section of a chip manufactured using a wafer level CSP technique.
[Explanation of symbols]
1, 11, 41: Bonding pads for IC chips,
2,3,12,13,14,42,43: Solder bumps (terminals of chip size package (CSP)),
4a, 4b, 15a, 15b, 15c: rewiring layer (or rewiring),
20, 30, 40: voltage regulator,
45: Capacitor
46: ESR (Equivalent Series Resistance),
47: Output load.

Claims (4)

A semiconductor device including a CSP in which a redistribution layer is formed on a chip, wherein a path between one bonding pad on the chip and a plurality of terminals of the CSP has different paths in the CSP, and at least one path Are connected by rewiring having a desired resistance value . Wherein the resistance value of the redistribution, the width of the redistribution layer, the length, the semiconductor device according to claim 1, characterized in that the desired value by laying by changing at least one material. The chip includes a voltage regulator circuit, and an output load is connected to a terminal to which a rewiring having a low resistance value is connected in the rewiring layer, and phase compensation is performed to a terminal to which a rewiring having a high resistance value is connected. the semiconductor device according to claim 1, characterized in that a capacitor of use. 4. The semiconductor device according to claim 3 , wherein a resistance value of the rewiring connected to the phase compensation capacitor is 10 mΩ to 10Ω.

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