JP4795736B2 - Wiring substrate, manufacturing method, drawing apparatus, and device manufacturing method - Google Patents

Description

The present invention relates to a wiring board including an array of openings through which charged particle beams pass and wirings for controlling the charged particle beams individually for each of the openings .

  A conventional raster scan type single electron beam exposure apparatus is shown in FIG. The electron beam from the electron source 1 that emits the electron beam forms an image of the electron source 1 by the electron lens 2. The electron source image is reduced and projected onto the wafer 8 through a reduction electron optical system including the electron lenses 4 and 7. The blanker 3 is an electrostatic deflector located at the position of the image of the electron source 1 formed by the electron lens 2, and deflects the electron beam and blocks it with a blanking aperture 5 located on the pupil of the reduction electron optical system. Control whether or not to irradiate the wafer with an electron beam. The electrostatic deflector 6 performs raster scanning of the electron beam, and controls the irradiation of the electron beam by the blanker 3 in synchronization with the scanning, thereby drawing a desired pattern on the wafer 8.

  However, the single electron beam exposure apparatus has a low throughput. As a device to solve this problem, by drawing a desired pattern in a plurality of minute areas that are a plurality of units using a plurality of electron beams, and drawing a pattern area of a certain size by combining these minute areas, There is a raster scan type multi-electron beam exposure apparatus with improved throughput.

An example of a conventional blanker array is shown in FIG. The multi-electron beam exposure apparatus is called a blanker array (BLA: Blanker Array) in which blankers 100 are arranged in an array at a pitch of several μm to several hundred μm, and a plurality of electron beam bundles that pass through an opening 99 are individually provided. Irradiation is controlled. Since the wiring 103 for transmitting an electrical signal for driving the BLA 102 is wired to the BLA electrodes 101 arranged at a high density, it has a high-density structure like the electrodes. Particularly, since the wiring area between the blankers 100 is narrow, the density becomes high. The wiring is realized by a wiring board in which the multilayer wiring structure 107 is formed on the board by semiconductor technology. FIG. 12 shows an example of a cross-sectional structure of a conventional multilayer wiring. In this structure, the SiO ₂ insulator layer 110 and the multilayer wiring 109 are alternately stacked on the Si substrate 108 to form a multilayer wiring having a wiring width of several μm and a high density with a wiring interval.
JP 2004-282038 A JP 7-297107 A JP-A-11-186144

  Conventionally, the wiring 103 for transmitting an electrical signal for driving the BLA has a wiring having a line width corresponding to the density of the BLA portion arranged radially to the blanker electrode lead pad 105 arranged around the BLA, as in the above example. High-density multilayer wiring. In such a structure, the wiring cross-sectional area is small, the line length is long, and the wiring interval is narrowed. Therefore, the wiring resistance is increased, the wiring capacity is increased, and noise is generated in the adjacent wiring. Further, since the structure does not take into account the characteristic impedance, reflection occurs and disturbs the waveform. Such wiring can transmit a low-speed (several hundreds KHz) control signal, but cannot transmit a higher-speed control signal. The time required for exposure largely depends on the control speed of the electron beam, and the low-speed control of the electron beam regulates the processing capability (throughput) of the apparatus to be low.

An object of the present invention is to provide a wiring board that is advantageous in terms of signal transmission speed .

  A first aspect of the present invention relates to a wiring board including an array of openings through which charged particle beams pass and wirings for controlling charged particle beams individually for each of the openings, and the wiring board includes the openings. A wiring connected to an electrode provided for each of the wirings is formed in multiple layers, and is connected to each wiring of the first wiring part, and is wider than a cross-sectional area of the wiring of the first wiring part And a second wiring portion formed with a wiring having a cross-sectional area.
  A second aspect of the present invention relates to a method of manufacturing a wiring board including an array of openings through which charged particle beams pass and wirings for controlling the charged particle beams individually for each of the openings. A first step of forming a first wiring part including a plurality of wirings connected to electrodes provided for each opening, and wiring connected to each wiring of the first wiring part, wherein the first wiring part A second step of forming a second wiring portion including a wiring having a cross-sectional area wider than the cross-sectional area of the wiring, wherein the first step and the second step are at least partially with respect to a common substrate It is performed in parallel.
A third aspect of the present invention relates to a drawing apparatus that performs drawing on a target with a plurality of charged particle beams, and the drawing apparatus includes the above-described wiring board for individually controlling the plurality of charged particle beams, It has an electrode provided for every opening of a wiring board, and a control part which applies a signal to the electrode via the wiring board.
A fourth aspect of the present invention relates to a device manufacturing method, which includes a step of drawing on an object using the above drawing apparatus, and a step of developing the object that has been drawn in the step , Including.

According to the present invention, it is possible to provide a wiring board that is advantageous in terms of signal transmission speed .

  Hereinafter, as a preferred embodiment of a charged particle beam exposure apparatus to which the present invention is applied, an example of an electron beam (electron beam) exposure apparatus when an exposure target is a wafer will be described below. Note that the present invention is not limited to an electron beam and can be similarly applied to an exposure apparatus using an ion beam.

<Description of components of electron beam exposure apparatus>
FIG. 1 is a schematic view of a main part of an electron beam (electron beam) exposure apparatus according to the present invention. In FIG. 1, an electron beam generated by an electron gun (not shown) forms a crossover image (hereinafter, this crossover image is referred to as an electron source 9). The electron beam emitted from the electron source 9 forms an image 11 of the electron source 9 via the beam shaping optical system 10. The electron beam from the image 11 becomes a substantially parallel electron beam by the collimator lens 12. The substantially parallel electron beam illuminates the aperture array 13 having a plurality of apertures.

The aperture array 13 has a plurality of openings and divides the electron beam into a plurality of electron beams. The plurality of electron beams divided by the aperture array 13 forms an intermediate image of the image 11 by the electrostatic lens array 14 in which a plurality of electrostatic lenses are formed. A blanker array 15 in which a plurality of blankers that are electrostatic deflectors are formed is disposed on the intermediate image plane.

  Downstream of the intermediate image plane, there is a reduction electron optical system 16 composed of two stages of symmetrical magnetic tablet lenses 16 a and 16 b, and a plurality of intermediate images are projected onto the wafer 17. At this time, since the electron beam deflected by the blanker array 15 is blocked by the blanking aperture 24, the wafer 17 is not irradiated. On the other hand, since the electron beam that is not deflected by the blanker array 15 is not blocked by the blanking aperture 24, it is irradiated onto the wafer 17.

  In the lower doublet lens 16b, a deflector 18 for simultaneously displacing a plurality of electron beams to desired positions in the X and Y directions and a focus coil 20 for simultaneously adjusting the focus of the plurality of electron beams are arranged. ing. Reference numeral 21 denotes an XY stage on which the wafer 17 is mounted and is movable in the XY directions orthogonal to the optical axis. On the XY stage 21, an electrostatic chuck 23 for fixing the wafer 17 and a semiconductor detector 22 having a knife edge on the electron beam incident side are arranged for measuring the shape of the electron beam.

<Description of system configuration and drawing method>
A system configuration diagram of this embodiment is shown in FIG. The blanker array control circuit 25 is a circuit that individually controls a plurality of blankers that constitute the blanker array 15, and the deflector control circuit 26 is a circuit that controls the deflector 18. The electron beam shape detection circuit 27 is a circuit that processes a signal from the semiconductor detector 22, and the focus control circuit 28 controls the focal position of the reduction electron optical system 16 by adjusting the focal length of the focus coil 20. Circuit. The stage drive control circuit 29 is a control circuit that drives and controls the stage 21 in cooperation with a laser interferometer (not shown) that detects the position of the stage. The main control system 30 controls the plurality of control circuits, and The entire beam exposure apparatus is managed.

  An explanatory view of the drawing method of this embodiment is shown in FIG. The main control system 30 commands the deflection control circuit 26 based on the exposure control data, commands the blanker array control circuit 25 in synchronism with deflecting the plurality of electron beams by the deflector 18, and exposes the wafer 17. The blankers 39 (see FIG. 5) of the blanker array 15 are individually turned on / off based on the command value corresponding to the pixel 33 to be processed. The upper limit of the speed at which the blanker 39 is controlled is regulated by the speed of the control signal that can be transmitted by the wiring board 35 (see FIG. 4), which regulates the processing capability of the apparatus.

  As shown in FIG. 3, each electron beam 34 performs raster scan exposure on the pixels 33 in the corresponding element exposure region 31 on the wafer 17. Since the element exposure areas 31 of each electron beam are set so as to be adjacent in two dimensions, as a result, a subfield 32a composed of a plurality of element exposure areas 31 exposed simultaneously is exposed.

  After exposing the subfield 32a, the main control system 30 commands the deflector control circuit 26 to cause the deflector 18 to deflect a plurality of electron beams in order to expose the next subfield 32b.

<Description of transmission line wiring structure>
FIG. 4 is a schematic diagram of a transmission line wiring board for control signals applied to the blanker array 15. As shown in FIG. 4, the wiring board 35 includes a blanker electrode serving as a connection portion between the blanker array 15 through which a plurality of electron beams divided by the aperture array 13 enter and pass in the Z-axis direction, and the blanker array control circuit 25. And a drawer pad 36. It is desirable that the blanker array 15 is disposed substantially at the center of the wiring board 35 and a blanker electrode lead pad 36 is disposed around the blanker array 15. The blanker electrode lead pad 36 is supplied with an electrical signal from the blanker array control circuit 25 via a probe card, a pogo pin unit or the like.

  FIG. 5 is a schematic view of the main part of the wiring structure of the wiring board 35. Blankers 39 having a plurality of blanker openings 38 through which an electron beam passes and blankers 39 having a plurality of blanker electrodes 37 for deflecting the passing electron beam are arranged in an array at equal intervals in the blanker array 15 at substantially the center of the wiring board 35. Is formed. The blanker electrodes 37a and 37b and the blanker electrode lead-out pad 36 of the blanker 39 are formed from a plurality of blanker electrodes 37a and 37b of the plurality of blankers 39 which are formed at a high density. They are electrically connected via a second wiring part 41 having a cross-sectional area larger than that of 40. It is preferable that the electrical length of the first wiring part 40 is approximately equal. The facing blanker electrodes 37a and 37b are preferably connected to the first wiring part 40 and the second wiring part 41 in pairs. Further, the wiring density may be reduced by electrically connecting one of the opposing blanker electrodes 37a and 37b to the GND layer, and the first wiring part 40 and the second wiring part 41 may have a large cross-sectional area.

FIG. 6 shows a cross-sectional structure diagram of the first wiring part 40 and the second wiring part 41. The wiring portions 40 and 41 can be simultaneously formed on the substrate 42 using a lithography technique or the like.
The first wiring section 40 has a common GND layer 43 on the substrate 42, a dielectric layer 44 that insulates the wiring from the wiring, a multilayer wiring 45, a surface GND layer 46, and a protective layer 48, and the multilayer wiring 45b is a common GND layer. 43, the multilayer wiring 45a is adjacent to the surface GND layer 46. The second wiring part 41 has a common GND layer 43 on the same substrate 42 as the first wiring part 40, a dielectric layer 44 that insulates the wiring from the wiring, a surface layer wiring 47, and a protective layer 48, and the surface layer wiring 47 is common. A structure adjacent to the GND layer 43 is adopted. A wiring having a structure in which the wiring is sandwiched between upper and lower GND layers is called a stripline, and a wiring having a GND layer only on one side is called a microstrip line. By taking such a structure, the characteristic impedance is controlled substantially uniformly.

  The dielectric layers 44a, 44b, and 44c have a predetermined thickness, and the dielectric layer 44b is preferably thicker than the predetermined thickness. That is, the interval between the multilayer wirings 45a and 45b is preferably wider than the interval between the multilayer wiring 45b and the common GND layer 43 and the interval between the multilayer wiring 45a and the surface GND layer 46 in order to reduce mutual interference due to crosstalk of control signals. For the same reason, it is preferable that the space between the multilayer wiring 45 and the surface wiring 47 be the same as or larger than the wiring width. It is preferable that the cross-sectional areas of the multilayer wiring 45 and the surface wiring 47 are wider as the wiring density permits. The material of the protective layer 48 and the dielectric layer 44 that protects the surface structure is preferably a material having a lower relative dielectric constant (for example, an SOG material) in order to reduce the wiring capacitance.

  The surface wiring 47 of the second wiring part 41 may be formed in the same layer as the multilayer wirings 45a and 45b of the first wiring part 40 to form a multilayer wiring. However, in order to reduce wiring capacity, The dielectric layer of the second wiring part 41 is preferably thicker than the dielectric layer of the first wiring part 40, and is best formed in the uppermost layer as shown in FIG. Further, a plurality of surface layer wirings 47 may be stacked to form a multilayer, but the interlayer dielectric film of the wiring layer is preferably thicker.

  As materials for the multilayer wiring 45 and the surface wiring 47, it is preferable to use materials having lower electrical resistivity (for example, gold, silver, aluminum, and copper) in order to reduce wiring resistance.

In order to form a higher density wiring, the number of layers of the multilayer wiring 45 may be larger than that of the two-layer structure shown in FIG.
The transmission line wiring structure is divided into two or more types including the first wiring portion 40 and the second wiring portion 41 shown in FIG. 6 as one embodiment, and the wiring cross-sectional area is gradually expanded to form a dielectric layer. It is also possible to make the structure thicker.

FIG. 7 shows a cross-sectional structure diagram of the first wiring part 40 and the second wiring part 41 of another example. The wiring portions 40 and 41 can be simultaneously formed on the substrate 42 using a lithography technique or the like.
The first wiring unit 40 includes a common GND layer 43 on the substrate 42, a dielectric layer 44 that insulates the wiring from each other, a multilayer wiring 45, a shielding GND layer 50, a shielding GND wiring 49, a surface GND layer 46, and a protective layer 48. The multi-layer wiring 45 b has a strip line structure in which the common GND layer 43 and the shielding GND wiring 49 are sandwiched, and the multilayer wiring 45 a is sandwiched between the surface GND layer 46 and the shielding GND wiring 49. The second wiring part 41 has a common GND layer 43 on the same substrate 42 as the first wiring part 40, a dielectric layer 44 that insulates the wiring from the wiring, a surface layer wiring 47, a shielded GND wiring 49, and a protective layer 48. The surface wiring 47 is adjacent to the common GND layer 43. In order to reduce mutual interference due to crosstalk of control signals, the multilayer wiring 45 and the surface layer wiring 47 have a coplanar structure sandwiched between shielded GND wirings 49 in the same layer. In addition, a structure in which the shield GND wiring 49 is eliminated may be used, but in order to reduce mutual interference due to crosstalk of control signals, it is preferable that the interval between the multilayer wiring 45 and the surface wiring 47 be equal to or larger than the wiring width. The dielectric layers 44d, 44e, 44f, and 44g have a predetermined thickness, and are preferably formed thicker. In order to form a higher-density wiring, the number of layers of the set of the shielding GND layer 50 sandwiching the multilayer wiring 45 and the dielectric layer may be more than the two-layer structure shown in FIG. It is preferable that the cross-sectional areas of the multilayer wiring 45 and the surface wiring 47 are wider as the wiring density permits. The material of the protective layer 48 and the dielectric layer 44 that protect the surface structure is preferably a material having a lower relative dielectric constant (for example, an SOG material).

  The surface wiring 47 of the second wiring part 41 may be formed in the same layer as the multilayer wirings 45a and 45b of the first wiring part 40 to form a multilayer wiring. However, in order to reduce wiring capacity, The dielectric layer of the second wiring portion 41 is preferably thicker than the dielectric layer of the first wiring portion, and is best formed in the uppermost layer as shown in FIG. Further, a plurality of surface layer wirings 47 may be stacked to form a multilayer, but the interlayer dielectric film of the wiring layer is preferably thicker.

  As materials for the multilayer wiring 45 and the surface wiring 47, it is preferable to use materials having lower electrical resistivity (for example, gold, silver, aluminum, and copper) in order to reduce wiring resistance.

  The transmission line wiring structure is divided into two or more types including the first wiring portion 40 and the second wiring portion 41 shown in FIG. 7 as one embodiment, and the wiring cross-sectional area is gradually expanded to form a dielectric layer. It is also possible to make the structure thicker. Moreover, the combination of the Example shown in FIG.6 and FIG.7 may be sufficient.

<Description of manufacturing method of transmission line wiring structure>
FIG. 8 is a process diagram for forming a wiring board according to an embodiment of the present invention. Here, reference numeral 60 denotes a first wiring part forming region, and 61 denotes a second wiring part forming region.
[Step 1] First, after forming a conductive film on the Si substrate 62 having a predetermined thickness, a resist film is applied, and a pattern pattern of the common GND 63 is exposed and patterned on the resist film. Next, using this as a mask, the conductive film is etched to form a common GND 63. The Si substrate 62 is an example of a substrate.

  In [Step 2], after forming a dielectric film on the common GND 63, a resist film is applied, and a contact hole shape (not shown) is exposed and patterned on the resist film. Next, using this as a mask, the dielectric film is etched to form a dielectric layer 64a having contact holes.

  In [Step 3], after forming a conductive film on the dielectric layer 64a, a resist film is applied, and the shape for the multilayer wiring 65a and the shape for the contact hole (not shown) of the first wiring part 60 are formed as a resist film. Exposure patterning. Next, using the mask as a mask, the conductive film is etched to form a multilayer wiring 65a.

  In [Step 4], after forming a dielectric film on the dielectric layer 64a so as to cover the multilayer wiring 65a, a resist film is applied, and a contact hole shape (not shown) is exposed and patterned on the resist film. Next, using this as a mask, the dielectric film is etched to form a dielectric layer 64b having contact holes.

  In [Step 5], after forming a conductive film on the dielectric layer 64b, a resist film is applied, and the shape for the shielding GND 66 and the shape for the contact hole (not shown) of the first wiring part 60 are used as the resist film. Perform exposure patterning. Next, using the mask as a mask, the conductive film is etched to form a shielding GND 66.

  In [Step 6], after forming a dielectric film on the dielectric layer 64b so as to cover the shielding GND 66, a resist film is applied, and a contact hole shape (not shown) is exposed and patterned on the resist film. Next, using this as a mask, the dielectric film is etched to form a dielectric layer 64c having contact holes.

  In [Step 7], after forming a conductive film on the dielectric layer 64c, a resist film is applied, and the shape for the multilayer wiring 65b of the first wiring portion 60 and the shape for contact holes (not shown) are formed as a resist film. Exposure patterning. Next, using the mask as a mask, the conductive film is etched to form a multilayer wiring 65b.

  In [Step 8], after forming a dielectric film on the dielectric layer 64c so as to cover the multilayer wiring 65b, a resist film is applied, and a contact hole shape (not shown) is exposed and patterned on the resist film. Next, using this as a mask, the dielectric film is etched to form a dielectric layer 64d having contact holes.

  In [Step 9], after forming a conductive film on the dielectric layer 64d, a resist film is applied, and the shape for the surface GND 67 of the first wiring portion 60, the shape of the surface wiring 68 of the second wiring portion, and the contact hole are formed. A pattern (not shown) is exposed and patterned on the resist film. Next, using the mask as a mask, the conductive film is etched to form the surface GND 67 and the surface wiring 68.

  In [Step 10], a dielectric film and a surface protective film (for example, SiN) are formed on the dielectric layer 64d so as to cover the surface GND 67 and the surface layer wiring 68, and then a resist film is applied to form a connection PAD shape ( (Not shown) is subjected to exposure patterning on the resist film. Finally, using the mask as a mask, the surface protective film and the dielectric film are etched to form a surface protective layer 69 having an opening in the connecting PAD portion.

  In the case of the embodiment without the shielding GND (FIG. 6), steps 5 and 6 may be omitted. Further, the first wiring unit 60 may be multi-layered by repeating Steps 3 to 6.

  The surface protective layer 69 in step 10 may be a dielectric film, and the second wiring unit 61 may be a multilayer wiring by repeating steps 9 and 10. In addition, the second wiring part 61 may be formed in the formation layer of the first wiring part 60 to form a multilayer wiring. However, in order to reduce the wiring capacity, the second wiring part 61 is formed in a higher layer and the second wiring part 61 The dielectric layer is preferably thicker than the dielectric layer of the first wiring part 60.

  As a main material of the conductive film, it is desirable to use aluminum or a metal having a lower resistivity than aluminum. Moreover, it is desirable to form it thicker.

The dielectric film is desirably made of a material having a lower relative dielectric constant than the CVD SiO ₂ film (for example, a low dielectric constant material such as SOG). Moreover, it is desirable to form it thicker.

  As a result, the first wiring part 60, the second wiring part 61, and the contact hole can be formed in the same process, and the dielectric layer of the second wiring part 61 is smaller than the dielectric layer of the first wiring part 60. Thicker structures can be formed.

<Example of control signal transmission waveform>
FIG. 9 shows an example in which the transmission waveforms of control signals having a period of 100 MHz are actually compared using the transmission line wiring of the prior art (FIGS. 11 and 12) and the transmission line wiring according to the embodiment of the present invention. Compared with the input waveform amplitude 51 of the transmission waveform 52 of the control signal by the transmission line wiring according to the embodiment of the present invention, the waveform 53 of the transmission line wiring of the prior art does not have a sufficient amplitude, but this embodiment The waveform 52 of the transmission line wiring has a sufficient amplitude to control the charged particle beam.

  Thus, it becomes possible to control a charged particle beam at a remarkably high speed by using the transmission line wiring of a present Example.

  Next, as a second embodiment of the present invention, a semiconductor device manufacturing process using the charged particle beam exposure apparatus according to the first embodiment will be described. FIG. 13 is a diagram showing a flow of an entire manufacturing process of a semiconductor device. In step 11 (circuit design), a semiconductor device circuit is designed. In step 12 (EB data conversion), exposure control data for the exposure apparatus is created based on the designed circuit pattern.

  On the other hand, in step 13 (wafer manufacture), a wafer is manufactured using a material such as silicon. Step 14 (wafer process) is called a pre-process, and an actual circuit is formed on the wafer using lithography using the exposure apparatus and wafer to which the exposure control data has been input. The next step 15 (assembly) is called a post-process, and is a process for forming a semiconductor chip using the wafer produced in step 14, and is an assembly process (dicing, bonding), packaging process (chip encapsulation), etc. Process. In step 16 (inspection), the semiconductor device manufactured in step 15 undergoes inspections such as an operation confirmation test and a durability test. A semiconductor device is completed through these processes, and is shipped in step 17.

  The wafer process in step 14 includes the following steps. An oxidation step for oxidizing the surface of the wafer, a CVD step for forming an insulating film on the wafer surface, an electrode formation step for forming electrodes on the wafer by vapor deposition, an ion implantation step for implanting ions on the wafer, and applying a photosensitive agent to the wafer The resist processing step, the exposure step for printing and exposing the circuit pattern onto the wafer after the resist processing step by the above-described exposure apparatus, the development step for developing the wafer exposed in the exposure step, and the etching for removing portions other than the resist image developed in the development step Step, resist stripping step to remove resist that is no longer needed after etching. By repeating these steps, multiple circuit patterns are formed on the wafer.

It is a figure which shows the principal part outline of the electron beam (electron beam) exposure apparatus which concerns on the Example of this invention. It is a figure which shows the system configuration | structure outline of the electron beam exposure apparatus which concerns on the Example of this invention. It is a figure for demonstrating the drawing method which concerns on the Example of this invention. It is a figure which shows the outline of the wiring board based on the Example of this invention. It is a figure which shows the principal part outline of the wiring board based on the Example of this invention. It is a figure which shows the cross-section of the wiring which concerns on the Example of this invention. It is a figure which shows the cross-section of the other example of the wiring which concerns on the Example of this invention. It is a figure for demonstrating the formation process of the wiring board based on the Example of this invention. It is the figure which compared the transmission waveform of the Example of this invention and the wiring of a prior art. It is a figure for demonstrating the conventional raster scan type | mold electron beam exposure apparatus. It is a figure which shows the principal part outline of the conventional wiring board. It is a figure which shows the cross-section of the conventional wiring. It is a figure which shows the flow of the whole manufacturing process of a semiconductor device.

Explanation of symbols

  1: electron source, 2: beam shaping electron lens, 3: blanker, 4: reduction optical system electron lens, 5: blanking aperture, 6: electrostatic deflector, 7: reduction optical system electron lens, 100: blanker, 101: BLA electrode, 102: Blanker array, 103: Wiring, 105: Blanker electrode lead pad, 107: Multilayer wiring structure, 108: Si substrate, 109: Multilayer wiring, 110: Insulator layer, 8: Wafer, 9: Electron Source: 10: Beam shaping optical system, 11: Electron source image, 12: Collimator lens, 13: Aperture array, 14: Electrostatic lens array, 15: Blanker array, 16a: Target magnetic tablet / lens a, 16b: Target magnetism Tablet lens b, 17: wafer, 18: electrostatic deflector, 20: focus coil, 21: XY stage, 22 Semiconductor detector 23: Electrostatic chuck 24: Blanking aperture 25: Blanker array control circuit 26: Deflector control circuit 27: Electron beam shape detection circuit 28: Focus control circuit 29: Stage drive circuit 30: Main control system, 32: Subfield, 32a: Subfield 1, 32b: Subfield 2, 32c: Subfield 3, 32d: Subfield 4, 33: Pixel, 34: Electron beam, 35: Wiring board, 36 : Blanker electrode lead pad, 37: Blanker electrode, 37a: Blanker electrode a, 37b: Blanker electrode b, 38: Blanker opening, 39: Blanker, 40: First wiring part, 41: Second wiring part, 42: Substrate 43: Common GND layer 44: Dielectric layer 44a: Dielectric layer a 44b: Dielectric layer 44c: Dielectric layer c, 44d: Dielectric layer d, 44e: Dielectric layer e, 44f: Dielectric layer f, 44g: Dielectric layer g, 45: Multilayer wiring, 45a: Multilayer wiring a, 45b: Multilayer Wiring b, 46: Surface GND layer, 47: Surface wiring, 48: Protection layer, 49: Shielding GND wiring, 50: Shielding GND layer, 51: Input waveform amplitude, 52: Transmission line wiring according to the embodiment of the present invention Waveform, 53: Waveform of conventional transmission line wiring, 60: First wiring portion forming region, 61: Second wiring portion forming region, 62: Si substrate, 63: Common GND, 64a: Dielectric layer a, 64b : Dielectric layer b, 64c: Dielectric layer c, 64d: Dielectric layer d, 65a: Multilayer wiring a, 65b: Multilayer wiring b, 66: Shielding GND, 67: Surface GND, 68: Surface wiring, 69: Surface Protective layer

Claims (7)

A wiring board including an array of openings through which charged particle beams pass and wiring for controlling the charged particle beams individually for each of the openings ;
A first wiring section wires connected to the electrodes provided on each of the opening formed in the multilayer,
A second wiring portion wiring having a wider cross-sectional area than the cross-sectional area of the wiring of the first wiring portion to a wiring connected to the wiring of the first wiring portion is formed,
A wiring board comprising: Claim 1, wherein the thick thickness of the dielectric layer for insulating the wiring in the second wiring portion than the thickness of the dielectric layer for insulating the wiring in the first wiring portion Wiring board as described in. The circuit board according to claim 1 or 2, wherein the first wiring in wiring portion is substantially equal length, it is characterized. 4. The wiring board according to claim 1, wherein the wiring in the second wiring portion is formed in multiple layers. 5. A method of manufacturing a wiring board including an array of openings through which charged particle beams pass and wirings for individually controlling charged particle beams for each of the openings ,
A first step of forming a first wiring portion including a wire connected to the electrode provided on each of the openings in the multilayer,
A second step of forming a second wiring portion including a wire having a larger cross-sectional area than the cross-sectional area of the wiring of the first wiring portion to a wiring connected to the wiring of the first wiring portion, Have
Manufacturing method of the first step and the second step is at least partially carried out in parallel on a common substrate, characterized in that. A drawing apparatus for drawing on a target with a plurality of charged particle beams,
The wiring board according to any one of claims 1 to 4, for individually controlling the plurality of charged particle beams,
An electrode provided for each opening of the wiring board;
A control unit for applying a signal to the electrode via the wiring board;
A drawing apparatus comprising: Drawing on a target using the drawing apparatus according to claim 6;
Developing the object drawn in the process;
Device manufacturing method comprising a.

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