JP4789753B2 - Image data buffer device, image transfer processing system, and image data buffer method - Google Patents

Description

  The present invention generally relates to an image data buffer device and an image transfer processing system, and more particularly to an image data buffer device and an image transfer processing system that transfer image data in units of blocks.

  In image processing, image data is often divided into a plurality of blocks, and processing such as filtering and compression encoding is performed on a block basis. When a filter process is performed on a certain block, data of pixels outside the block boundary is also required in order to obtain a value after the filter process for a pixel near the block boundary. For example, if the size of one block is n × m pixels, calculation image data having a size corresponding to the filter size of the filter processing is added outside the n × m pixels, and s × t (s > n and t> m) Prepare pixel image data. Image blocks of s × t pixels having a size larger than the original block size obtained in this way are sequentially supplied from the image data buffer to the image processing unit.

  FIG. 1 is a diagram showing an example of the configuration of a conventional image transfer / processing system. The image transfer / processing system of FIG. 1 includes an image memory unit 10, an image data buffer 11, and an image processing unit 12. The image memory unit 10 includes an image memory 15 and a memory interface 16 that controls data input / output of the image memory 15 and the like. The image data buffer 11 includes a RAM 17 and a FIFO control unit 18 that controls data input / output of the RAM 17. The FIFO control unit 18 controls a write pointer indicating a write position and a read pointer indicating a read position in the RAM 17 to realize a first-in first-out (FIFO) operation.

  The memory interface 16 of the image memory unit 10 stores, for example, 3 × 3 blocks of image data as image data 20. In this example, the image data 20 includes nine blocks B1 to B9, and each block includes n × m pixels (for example, 16 × 32 pixels).

  The memory interface 16 reads the block data from the image memory 15 in the order of B1 to B9 (that is, the order of raster scanning), and supplies the block data to the image data buffer 11 in order. At this time, for example, when reading the block B5, the memory interface 16 reads the image data of s × t pixels (for example, 28 × 37 pixels) larger than n × m by simultaneously reading the pixel data around the upper, lower, left, and right sides. The image data is supplied to the image data buffer 11 as image data corresponding to the block B5. Note that the data of each pixel of the s × t pixel image data is sequentially supplied in the raster scan order.

  The image data of s × t pixels supplied in this way is written in the RAM 17 by the FIFO control unit 18 in the image data buffer 11. In this example, the operation of the RAM 17 is controlled by the FIFO controller 18 as a FIFO capable of storing data for two blocks. As shown in FIG. 1, for example, s × t pixel image data corresponding to the block B5 and s × t pixel image data corresponding to the next block are stored in the RAM 17 as image data 21.

  The FIFO control unit 18 of the image data buffer 11 first reads the image data of the previously written block and supplies it from the RAM 17 to the image processing unit 12. As shown in FIG. 1, for example, image data 22 of s × t pixels corresponding to the block B5 is supplied from the image data buffer 11 to the image processing unit 12. The image processing unit 12 performs image processing including filter processing on the supplied image data 22 of s × t pixels.

  FIG. 2 is a diagram illustrating an example of a detailed configuration of the image data buffer 11. The image data buffer 11 shown in FIG. 2 includes a RAM 17, a FIFO control unit 18, a block counter 25, and a block counter 26. Image data from the image memory unit 10 is supplied to the RAM 17 as input data. The input data is written to the address in the RAM 17 indicated by the write pointer WP managed by the FIFO control unit 18. Input data from the image memory unit 10 is also supplied to the block counter 25 at the same time.

  The block counter 25 is supplied with information on the image size of image data per block. The block counter 25 counts the number of bits of input data and compares the count value with the image size to determine whether or not image data for one block has been supplied. Each time image data for one block is supplied, the block counter 25 supplies a signal for instructing the update of the write pointer WP to the FIFO controller 18. In response to this signal, the FIFO control unit 18 updates the write pointer WP (updates the pointer value indicating the write position of the next block).

  The output data read from the RAM 17 address indicated by the read pointer RP managed by the FIFO control unit 18 is supplied to the image processing unit 12. This output data is also supplied to the block counter 26 at the same time.

  The block counter 26 is supplied with image size information of image data per block (not shown). The block counter 26 counts the number of bits of the output data, and compares the count value with the image size to determine whether image data for one block has been output. Each time image data for one block is output, the block counter 26 supplies a signal for instructing the update of the read pointer RP to the FIFO controller 18. In response to this signal, the FIFO control unit 18 updates the read pointer RP (updates the pointer value indicating the read position of the next block).

When the size of one block is n × m pixels, the image data of s × t (s> n and t> m) pixels larger than the block size by the configuration shown in FIGS. Can be prepared and sequentially supplied from the image data buffer 11 to the image processing unit 12. However, with such a configuration, data of s × t pixels is read from the image memory 15 for each block instead of n × m pixels, and the amount of data transferred from the image memory 15 increases. Moreover, the calculation image data in the peripheral portion of the image data of s × t pixels is read out at least twice, and if it is large, it is read out four times, and data transfer is very inefficient. become. In a configuration in which the image memory 15 is also accessed from other devices, such an increase in the amount of data transfer is not preferable because it leads to a decrease in performance.
JP-A-8-9385 JP 2002-142149 A

  In view of the above, the present invention provides an image data buffer device and image transfer for realizing efficient data reading from the image memory in a configuration in which image data for each block is transferred from the image memory to the image processing device via the image data buffer. An object is to provide a processing system.

The image data buffer device includes a memory, a write pointer indicating a write position to the memory, and a read pointer indicating a read position from the memory, and includes a FIFO control unit that operates the memory as a FIFO. The unit stores the image data supplied as a continuous block in the image as a plurality of blocks at the position indicated by the write pointer of the memory, and stores the block of the plurality of blocks from the position indicated by the read pointer of the memory. it is one reads at least one partial data that is part of the second block at the same time adjacent to the first block when reading a first block of out, first block and the partial data configured to deliver as one block are collectively bets, partial data, the second block Characterized in that adjacent to the first block in located on the edge in the image.

An image transfer processing system includes a memory, a write pointer indicating a write position to the memory, and a read pointer indicating a read position from the memory, and a FIFO control unit that operates the memory as a FIFO, and an image processing unit. And the FIFO control unit stores the image data supplied as a continuous block in the image as a plurality of blocks in the position sequentially indicated by the write pointer of the memory, and from the position indicated by the read pointer of the memory. reading at least one partial data that is part of the second block adjacent to the first block when reading the first block, which is one of the plurality of blocks at the same time, the first configured to be sent to the image processing unit as one block are collectively blocks and the partial data, partial Chromatography data is characterized in that adjacent to the first block in located on the edge of the second block in the image.

  According to at least one embodiment of the present invention, it is possible to reduce the amount of data transfer by avoiding duplicate transfer of the same data as much as possible in the data transfer from the image memory to the FIFO. Compared with the prior art, assuming that the number of FIFO stages is the same, the amount of image data per block is small in at least one embodiment of the present invention, so that the size of the FIFO can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 3 is a diagram showing an example of the configuration of an image transfer / processing system according to the present invention. The image transfer / processing system of FIG. 3 includes an image memory unit 30, an image data buffer 31, an image processing unit 32, and a controller 33. The image memory unit 30 includes an image memory 35 and a memory interface 36 that controls data input / output of the image memory 35 and the like. The image data buffer 31 includes a RAM 37 and a FIFO control unit 38 that controls data input / output of the RAM 37 and the like. The FIFO control unit 38 controls a write pointer indicating a write position and a read pointer indicating a read position in the RAM 37 to realize a FIFO (First-In First-Out) operation. The controller 33 returns an acknowledge in response to the processing data request from the image processing unit 32 and controls the image memory unit 30 and the image data buffer 31 to transfer data from the image memory unit 30 to the image data buffer 31. Data transfer from the image data buffer 31 to the image processing unit 32 is realized. The position where the controller 33 is mounted is not limited to a specific location. For example, the function of the controller 33 may be provided inside the image data buffer 31 as an interface unit.

  FIG. 4 is a diagram for explaining the operation principle of the image transfer / processing system of FIG. The operation of the image transfer / processing system of FIG. 3 will be described with reference to FIGS.

  The memory interface 36 of the image memory unit 30 stores, for example, 3 × 3 blocks of image data as shown as the image data 20 in FIG. In this example, the image data 20 includes nine blocks B1 to B9, and each block includes n × m pixels (for example, 16 horizontal pixels × 32 vertical pixels).

  The memory interface 36 reads each block data from the image memory 35 in the order of B1 to B9 (that is, raster scanning order), and supplies each block data to the image data buffer 31 in order. At this time, for example, when reading out the block B5, the memory interface 36 reads out only the upper and lower pixel data at the same time, so that only n × t pixels having a size larger than n × m pixels in the vertical direction (sub-scanning direction) ( For example, image data of horizontal 16 pixels × vertical 37 pixels) is read and supplied to the image data buffer 11 as image data corresponding to the block B5. Note that the data of each pixel of the n × t pixel image data is sequentially supplied in the raster scan order.

  The n × t pixel image data supplied in this way is written into the RAM 37 by the FIFO control unit 38 in the image data buffer 31. In this example, the operation of the RAM 37 is controlled by the FIFO control unit 38 as a FIFO capable of storing data for four blocks. As shown in FIG. 4, for example, n × t pixel image data corresponding to the block B5 and n × t pixel image data corresponding to the blocks before and after the block B5 are stored as image data 41 in the RAM 37. .

  The FIFO control unit 38 of the image data buffer 31 first reads the image data of the previously written block and supplies it from the RAM 37 to the image processing unit 32. At this time, the FIFO control unit 38 generates image data of s × t pixels by adding calculation image data to the left and right necessary portions of the image data of n × t pixels to be output, and sends the image data to the image processing unit 32. Supply. This s × t pixel image data is shown in FIG. As will be described below, the size of data supplied to the image processing unit 32 is (n + (s−n) / 2) × t pixels for the leftmost or rightmost block of the entire image.

  For example, in the case of the block B5, since it is the middle block among the three blocks B4 to B6 arranged in a horizontal row, the image data 42 of n × t pixels corresponding to the block B5 and the block B4 on the left side are left. The image data of s × t pixels is read out from the RAM 37 by combining the partial data 43 of the right end portion of the image and the image portion data 44 of the left end portion of the block B6 adjacent to the right. Thereby, the calculation image data can be added to the right side and the left side of the block B5.

  Further, for example, in the case of the block B4, since it is the leftmost block among the three blocks B4 to B6 arranged in a horizontal row, the image data of n × t pixels corresponding to the block B4 and the block on the right side thereof By combining the partial data of the left end portion of B5, the calculation data can be added to the right portion of the block B4. No calculation data is added to the left side of the block B4. As a result, (n + (s−n) / 2) × t pixel image data is supplied from the RAM 37 to the image processing unit 32.

  Similarly, in the case of the block B6, since it is the rightmost block among the three blocks B4 to B6 arranged in a horizontal row, the image data of n × t pixels corresponding to the block B6 and the left adjacent to it By combining the partial data of the right end part of the block B5, the calculation data can be added to the left part of the block B6. No calculation data is added to the right side of the block B6. As a result, (n + (s−n) / 2) × t pixel image data is supplied from the RAM 37 to the image processing unit 32.

  When the memory interface 36 reads image data from the image memory 35, the calculation data may be added only to the lower side of each block for the blocks B1 to B3 at the upper end of the image. Similarly, for the blocks B7 to B9 at the lower end of the image, calculation data may be added only to the upper side of each block.

  FIG. 5 is a diagram illustrating an example of a detailed configuration of the image data buffer 31. The image data buffer 31 shown in FIG. 5 includes a RAM 37, a FIFO control unit 38, a block counter 45, a block counter 46, and a position buffer 47. Image data from the image memory unit 30 is supplied to the RAM 37 as input data. The input data is written to the address in the RAM 37 indicated by the write pointer WP managed by the FIFO control unit 38. Input data from the image memory unit 30 is also supplied to the block counter 45 at the same time.

  The block counter 45 is supplied with information on the image size of the image data per block. The block counter 45 counts the number of bits of the input data and compares the count value with the image size to determine whether or not image data for one block has been supplied. Each time image data for one block is supplied, the block counter 25 supplies a signal for instructing the update of the write pointer WP to the FIFO controller 38. In response to this signal, the FIFO control unit 38 updates the write pointer WP (updates the pointer value indicating the write position of the next block).

  The block counter 45 supplies information (position information) related to the position of the block to which the input data is currently supplied to the position buffer 47. The information regarding the position of the block is, for example, data indicating “left”, “middle”, and “right”. “Left” indicates that the corresponding block is the left end of a plurality of blocks arranged in a horizontal row. “Medium” indicates that the corresponding block is not located at the end among a plurality of blocks arranged in a horizontal row. “Right” indicates that the corresponding block is the right end of a plurality of blocks arranged in a horizontal row. Specifically, in the example of the image data 20 shown in FIG. 4, the blocks B1, B4, and B7 are “left”, the blocks B2, B5, and B8 are “middle”, and the blocks B3, B6, And B9 are “right”.

  Since the block counter 45 is supplied with information on the image size of each of the “left”, “middle”, and “right” blocks as input information, the block counter 45 counts the number of bits of the input data and counts the image size Can be used to identify the position of the block to which input data is currently supplied. Information relating to the position of the identified block (position information) is supplied from the block counter 45 to the position buffer 47. The position buffer 47 stores the position information supplied from the block counter 45 at the position indicated by the write pointer WP supplied from the FIFO control unit 38. Thereby, the position buffer 47 can record information (position information) regarding the position of each block stored in the FIFO.

  Further, the position buffer 47 supplies position information of the position indicated by the read pointer RP supplied from the FIFO control unit 38 to the FIFO control unit 38. Thereby, the FIFO control unit 38 can know the position information of the block indicated by the read pointer RP. Based on this position information, the FIFO control unit 38 determines whether to add partial data to both the left and right sides, to add partial data only to the right side, or to add partial data only to the left side when reading data. Can do.

  Output data read from the address of the RAM 37 indicated by the read pointer RP managed by the FIFO control unit 38 is supplied to the image processing unit 32. This output data is also supplied to the block counter 46 at the same time.

  The block counter 46 is supplied with the position information of the read block and the image size information of the image data per block (not shown). The block counter 46 counts the number of bits of the output data, and compares the count value with the image size to determine whether image data for one block has been output. Each time image data for one block is output, the block counter 46 supplies a signal for instructing the update of the read pointer RP to the FIFO control unit 38. In response to this signal, the FIFO control unit 38 updates the read pointer RP (updates the pointer value indicating the read position of the next block).

  FIG. 6 is a diagram illustrating an example of the contents of the FIFO and the position buffer 47 when block data is stored in a four-stage FIFO.

  By reading and writing to the RAM 37 under the control of the FIFO control unit 38, a four-stage FIFO is realized. Here, in the initial state, the contents of the FIFO and the contents of the position buffer 47 are indicated by buffer data 51. Four rectangular frames of the buffer data 51 indicate four block storage positions of a four-stage FIFO. In each rectangular frame, the storage block is shown on the upper side, and the position information for each block stored in the position buffer 47 is shown on the lower side. In the initial state, there is no storage block, and the position information is initialized to “left”. In the drawing, an arrow “RP” indicates a position indicated by the read pointer RP, and an arrow “WP” indicates a position indicated by the write pointer WP.

  When the write operation is repeated four times (WR × 4), the contents of the FIFO and the contents of the position buffer 47 are indicated by the buffer data 52. That is, blocks B1 to B4 are stored in the FIFO, and “left”, “middle”, “right”, and “left” are stored in the position buffer 47. Both the read pointer RP and the write pointer WP indicate the first (leftmost) storage position.

  In this state, when the block B1 written first is read (RD × 1), the position indicated by the read pointer RP becomes the second storage position (second from the left). At this time, the contents of the FIFO and the contents of the position buffer 47 are indicated by buffer data 53.

  In the case of a normal FIFO, after reading the block B1, the block B1 may be immediately overwritten with the next block to be written (in this case, B5). However, in the present invention, the block B1 cannot be erased immediately after the block B1 is read. This is because the block B2 to be read next needs to add the data of the block B1 to the left as calculation image data.

  Thus, in the image data buffer 31 according to the present invention, the FIFO control by the FIFO control unit 38 is different from the normal FIFO control. FIG. 7 is a diagram showing how the parameters used for FIFO control in the FIFO control unit 38 change.

  As shown in FIG. 7, in addition to the write pointer WP and the read pointer RP, the FIFO control unit 38 includes a valid data count AVL, a writable condition flag FULL, a readable condition flag RDY, and a flag indicating that the data is empty. EMP is provided. Each row starting from the reset in FIG. 7 corresponds to the seven states of the buffer data 51 to 57 shown in FIG.

  The number of valid data AVL is the number of data to be read from the stored data (the number of data that has not yet been read), and is a value calculated by WP-RP. In this example, the FIFO has four stages, and the FIFO is in a loop. Therefore, as shown in the buffer data 53 of FIG. 6, if WP is in the first position and RP is in the second position, AVL is 1-2 + 4 (one round of a four-stage loop) is 3. Correspondingly, in FIG. 7, the AVL of the RD × 1 row of the third row from the top is 3.

  In FIG. 7, “position” indicates position information of the storage position indicated by the read pointer RP. As shown in FIG. 5, the position buffer 47 supplies position information of the position indicated by the read pointer RP supplied from the FIFO control unit 38 to the FIFO control unit 38. The FIFO control unit 38 stores the position information supplied from the position buffer 47 in the internal register as “position”. Hereinafter, the “position” which is the contents of this register is referred to as a position flag.

  The writable condition flag FULL indicates whether the position flag indicates the left end (corresponding to “left” of the position information), the middle (corresponding to “middle” of the position information), or the right end (“ It has a different value depending on whether it indicates “right”. When the writable condition flag FULL is “1”, writing the next data to the FIFO is not permitted. When the writable condition flag FULL is “0”, it is permitted to write the next data in the FIFO.

  When the position flag indicates the left end, FULL is “1” if AVL? 4 is satisfied, and “0” otherwise. This is because when the position flag indicates the left end, the next data to be read from the FIFO is the left end block. The additional data for calculation requires the data of the block on the right side, and the FIFO block that the previously written data is erased first, the block on the right side is erased before the block to be read. Is not possible. Also, the data of the block written in the FIFO before the block to be read is unnecessary. Accordingly, in a state where AVL is 4 (a state where the FIFO is full of data that needs to be read), naturally, writing of the next data to the FIFO is not permitted, so FULL becomes “1”. In this case, FULL becomes “0”, and the writing is permitted.

  When the position flag indicates the middle, FULL is “1” when AVL? 3 is satisfied, and “0” otherwise. This is because when the position flag indicates the middle, the next data to be read from the FIFO is the middle block. Necessary as additional data for calculation is the data of the block adjacent to the left and right, and the FIFO block that the previously written data is erased first erases the block adjacent to the right before the block to be read. It is impossible. Further, the data of the block written in the FIFO immediately before the block to be read is necessary, but the data of the block written before that is unnecessary. When the AVL is 3, the next data to be erased is the block data written in the FIFO immediately before the block to be read. Therefore, in a state where AVL is 3 (and a full state of 4), writing of the next data to the FIFO is not permitted and FULL becomes “1”, but when AVL is smaller than that, FULL becomes “0”. "It becomes write permission state.

  When the position flag indicates the right end, FULL is “1” when AVL? 3 is satisfied, and “0” otherwise. This is because when the position flag indicates the right end, the next data to be read from the FIFO is the right end block. What is required as additional data for calculation is the data of the block on the left side, which is the data of the block written in the FIFO immediately before the block to be read. However, the data of the block written before that is unnecessary. When the AVL is 3, the next data to be erased is the block data written in the FIFO immediately before the block to be read. Therefore, in a state where AVL is 3 (and a full state of 4), writing of the next data to the FIFO is not permitted and FULL becomes “1”, but when AVL is smaller than that, FULL becomes “0”. "It becomes write permission state.

  The readable condition flag RDY also has a different value depending on whether the position flag indicates the left end, the middle, or the right end. When the readable condition flag RDY is “1”, it is permitted to read the next data from the FIFO. When the readable condition flag RDY is “0”, reading the next data from the FIFO is not permitted.

  When the position flag indicates the left end, RDY is “1” if AVL? 2 is satisfied, and “0” otherwise. This is because when the position flag indicates the left end, the next data to be read from the FIFO is the left end block. In this case, what is necessary as additional data for calculation is the data of the block on the right. Therefore, if the write pointer WP has advanced at least two points ahead of the read pointer RP by writing the data of the block on the right side, it is ready to read the data of the block indicated by the read pointer RP. It will be.

  When the position flag indicates the middle, RDY is “1” when AVL? 2 is satisfied, and “0” otherwise. This is because when the position flag indicates the middle, the next data to be read from the FIFO is the middle block. In this case, what is necessary as additional data for calculation is data of blocks adjacent to the left and right. Since the write order to the FIFO is written first from the left block, the block on the left is naturally stored in the FIFO. Therefore, if the write pointer WP advances at least two points ahead of the read pointer RP by writing the data of the block on the right side, it is ready to read the data of the block indicated by the read pointer RP. become.

  When the position flag indicates the right end, RDY is “1” when AVL? 1 is satisfied, and “0” otherwise. This is because when the position flag indicates the right end, the next data to be read from the FIFO is the right end block. In this case, what is necessary as additional data for calculation is the data of the block on the left side. Since the write order to the FIFO is written first from the left block, the block on the left is naturally stored in the FIFO. Therefore, if the data of the block to be read is written and the write pointer WP is at least one step ahead of the read pointer RP, the data of the block indicated by the read pointer RP is ready to be read. become.

  With reference to the writable condition flag FULL and the readable condition flag RDY determined as described above, the controller 33 controls data writing and data reading with respect to the image data buffer 31. That is, data writing is performed when the writable condition flag FULL permits, and data writing is not performed when the writable condition flag FULL is not permitted. Data is read when the readable condition flag RDY permits, and data is not read when the readable condition flag RDY does not permit. As a result, for example, as shown as buffer data 51 to buffer data 57 in FIG. 6, data of each block is written and read, and calculation data added to each block is securely added without loss of calculation data. It is possible to supply the block data.

  FIG. 8 is a diagram illustrating an example of the configuration of the FIFO control unit 38. The FIFO control unit 38 of FIG. 8 includes flip chips 61 to 65, adders 66 and 67, subtractor 68, decoders 69 and 70, and comparators 71 to 73.

  The flip chip 61 is a flip chip that stores the write pointer WP. In response to the write pointer WP update signal from the block counter 45, the flip chip 61 latches a value obtained by adding “1” to the current write pointer WP value by the adder 66.

  The flip chip 62 is a flip chip that stores the read pointer RP. In response to the read pointer RP update signal from the block counter 46, the flip chip 62 latches a value obtained by adding “1” to the current read pointer RP value by the adder 67. Note that the flip chips 61 and 62 may be configured to reset when the value indicated by the output reaches the number of FIFO stages.

  The subtracter 68 subtracts the value of the read pointer RP from the value of the write pointer WP, thereby calculating the valid data number AVL. The calculated effective data number AVL is supplied to one input of the comparators 71 to 73.

  The other inputs of the comparators 71 to 73 are supplied with the output of the decoder 69, the output of the decoder 70, and 0, respectively. The decoders 69 and 70 are supplied with the position information (the position flag) of the read target block indicated by the read pointer RP.

  The decoder 69 decodes the position information, and outputs 2 when the position information is “left” or “middle”, and outputs 1 when the position information is “right”. The comparator 71 asserts an output signal when AVL is equal to or higher than the output of the decoder 69. In response to the assertion of the output signal, the flip-flop 63 is set to “1”.

  The decoder 70 decodes the position information and outputs 4 when the position information is “left”, and outputs 3 when the position information is “middle” or “right”. The comparator 72 asserts an output signal when AVL is equal to or higher than the output of the decoder 70. In response to the assertion of the output signal, the flip-flop 64 is set to “1”.

  The comparator 73 asserts an output signal when AVL is equal to or greater than “0” output. In response to the assertion of the output signal, the flip-flop 65 is set to “1”.

  FIG. 9 is a flowchart showing an example of operations of the controller 33 and the image data buffer 31.

  In the initial state, the write pointer WP, the read pointer RP, the valid data number AVL, the readable condition flag RDY, and the readable condition flag FULL are all “0”, the empty flag EMP is “1”, and the position flag is “ "Left".

  In step S1, it is determined whether or not FULL is “0”. If FULL is "1", it is determined in step S2 whether RDY is "1". If FULL is "0", it is determined in step S3 whether or not EMP is "1". The operation after the EMP condition determination is not shown because it is not directly related to the present invention. In FIG. 9, the process returns to step S1 regardless of the value of EMP. The determination of these steps S1 to S3 is performed by the controller 33.

  If it is determined in step S1 that FULL is "0", data is input to the FIFO and position data is input to the position buffer 47 in step S4. That is, under the control of the FIFO control unit 38 based on the write instruction from the controller 33, the next block data is written to the position in the RAM 37 indicated by the write pointer WP, and the data in the position buffer 47 indicated by the write pointer WP is stored. The position information of this block is stored in the position.

  Thereafter, when the write pointer WP update signal from the block counter 45 is asserted, the write pointer WP is updated in step S5 in response thereto. Next, the effective data number AVL is calculated in step S6. After step S6, the process returns to step S1.

  If it is determined in step S2 that RDY is "1", data is output in step S7. That is, based on a read instruction from the controller 33, under the control of the FIFO control unit 38, the block data stored at the position indicated by the read pointer RP and the necessary data on the left and right are read from the RAM 37 and output. The data is supplied to the image processing unit 32 as data. In parallel with step S7, the position data is updated in step S8. That is, the content of the position flag held by the FIFO control unit 38 is updated to the position information in the position buffer 47 indicated by the updated read pointer RP. In step S9, the values of FULL and RDY are updated.

  Thereafter, when the read pointer RP update signal from the block counter 46 is asserted, the read pointer RP is updated in step S10 in response thereto. That is, the FIFO control unit 38 increments the read pointer RP. Next, the effective data number AVL is calculated in step S6. After step S6, the process returns to step S1.

  As can be seen from the above description, according to at least one embodiment of the present invention, the amount of data transfer can be reduced by avoiding duplicate transfer of the same data as much as possible in the data transfer from the image memory to the FIFO. Is obtained. In the present invention, the FIFO requires at least three stages. On the other hand, in the conventional configuration, the minimum number of stages required for the FIFO is one. However, when a DRAM is used as the image memory, the FIFO can be set to 3 in the conventional configuration so that the image processing unit can operate even if access to the DRAM is impossible during the period of several thousand cycles required for refreshing the DRAM. It is common to have a stage or about four stages. Therefore, for example, when both the prior art and the present invention are compared with each other in a three-stage configuration, the present invention with a smaller amount of image data per block can reduce the FIFO size.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

It is a figure which shows an example of a structure of the conventional image transfer and processing system. It is a figure which shows an example of a detailed structure of an image data buffer. It is a figure which shows an example of a structure of the image transfer and processing system by this invention. It is a figure for demonstrating the principle of operation of the image transfer and processing system of FIG. It is a figure which shows an example of a detailed structure of an image data buffer. It is a figure which shows an example of the content of FIFO and a position buffer in case block data is stored in 4-stage FIFO. It is a figure which shows a mode that the parameter used for FIFO control in a FIFO control part changes. It is a figure which shows an example of a structure of a FIFO control part. It is a flowchart which shows an example of operation | movement of a controller and an image data buffer.

Explanation of symbols

30 Image memory unit 31 Image data buffer 32 Image processing unit 33 Controller 35 Image memory 36 Memory interface 37 RAM
38 FIFO control unit 45 Block counter 46 Block counter 47 Position buffer

Claims (11)

Memory,
A FIFO control unit having a write pointer indicating a write position to the memory and a read pointer indicating a read position from the memory, and operating the memory as a FIFO, the FIFO control unit being a continuous block in an image; as the image data supplied stores as a plurality of blocks to the write pointer sequentially show positions of the memory, from the position indicated by the read pointer of the memory first is one of the plurality of blocks reading at least one partial data that is part of the second block adjacent to the first block when reading blocks simultaneously, collectively and the first block and the partial data transmitted as one block is configured to,
The partial data is located at an end of the second block and is adjacent to the first block in the image.   A position buffer for storing position information indicating a block position in the image for each block of the plurality of blocks, and the FIFO control unit includes the number of unread blocks stored in the memory and the number of unread blocks. 2. The image data buffer device according to claim 1, wherein a value of a first flag indicating whether or not data can be read is set according to the position information of the block at the position indicated by the read pointer.   The FIFO control unit indicates whether or not data writing is possible according to the number of unread blocks stored in the memory and the position information of the block at the position indicated by the read pointer. 3. The image data buffer device according to claim 2, wherein a flag value is set.   A controller configured to request the FIFO controller to read data in accordance with the value of the first flag, and to request to write data to the FIFO controller in accordance with the value of the second flag; The image data buffer device according to claim 3. Memory,
A FIFO control unit having a write pointer indicating a write position to the memory and a read pointer indicating a read position from the memory and operating the memory as a FIFO
The FIFO control unit stores the image data supplied as continuous blocks in the image as a plurality of blocks at the positions sequentially indicated by the write pointer of the memory, and the position indicated by the read pointer of the memory When reading one block from the plurality of blocks, partial data that is a part of at least one block adjacent to the one block is simultaneously read, and the one block and the partial data are combined. Configured to send as one block,
A position buffer for storing position information indicating a block position in the image for each block of the plurality of blocks;
The FIFO control unit indicates whether or not data can be read according to the number of unread blocks stored in the memory and the position information of the block at the position indicated by the read pointer. Set the flag value,
An image data buffer device further comprising: a block counter that counts the amount of the supplied image data and generates the position information in accordance with a comparison between the counted data amount and a block size.   6. The image data buffer device according to claim 5, wherein the position buffer stores the position information supplied from the block counter at a position indicated by the write pointer supplied from the FIFO control unit.   7. The image data buffer device according to claim 6, wherein the position buffer supplies the position information stored in the position indicated by the read pointer supplied from the FIFO control unit to the FIFO control unit. Memory,
A FIFO control unit having a write pointer indicating a write position to the memory and a read pointer indicating a read position from the memory, and operating the memory as a FIFO;
The FIFO control unit stores the image data supplied as continuous blocks in the image as a plurality of blocks at positions sequentially indicated by the write pointer of the memory, and the read pointer of the memory reading the plurality of at least one partial data that is part of the second block adjacent to the first block when reading the first block is one of the blocks at the same time from the position indicated, The first block and the partial data are combined and sent to the image processing unit as one block ,
The partial data is located at an end of the second block and is adjacent to the first block in the image.   A position buffer for storing position information indicating a block position in the image for each block of the plurality of blocks, and the FIFO control unit includes the number of unread blocks stored in the memory and the number of unread blocks. 9. The image transfer processing system according to claim 8, wherein a value of a first flag indicating whether or not data can be read is set according to the position information of the block at the position indicated by the read pointer.   The FIFO control unit indicates whether or not data writing is possible according to the number of unread blocks stored in the memory and the position information of the block at the position indicated by the read pointer. The image transfer processing system according to claim 9, wherein a flag value is set. An image data buffer method for operating the memory as a FIFO using a write pointer indicating a write position to the memory and a read pointer indicating a read position from the memory,
The image data supplied as a continuous block in the image is stored as a plurality of blocks at the positions sequentially indicated by the write pointer of the memory,
A portion that is a part of at least one second block adjacent to the first block when reading the first block that is one of the plurality of blocks from the position indicated by the read pointer of the memory Read data simultaneously
The first block and the partial data are collectively sent as one block
An image data buffer method comprising the steps, wherein the partial data is located at an end of the second block and is adjacent to the first block in the image.

Images