JP4788125B2 - Shift register - Google Patents

Description

  The present invention relates to a shift register, and is used in, for example, a liquid crystal data line driving circuit, a scanning line driving circuit, an electro-optical device using these driving circuits, and an electronic apparatus.

Conventionally, as an electro-optical device, for example, a driving circuit for a liquid crystal device is known. Examples of the driving circuit include a data line driving circuit and a scanning line driving circuit for supplying a data line signal, a scanning signal, and the like to data lines and scanning lines wired in the image display area at a predetermined timing. Each of the data line driving circuit and the scanning line driving circuit includes a shift register that sequentially shifts a start pulse according to a clock signal. This shift register has, for example, a plurality of stages of shift unit circuits each including a plurality of thin film transistors, and outputs one sampling signal for each shift unit circuit (see Patent Document 1).
JP 2002-55647 A

  Incidentally, in recent years, there has been a demand for an increase in size and resolution of a liquid crystal device. Therefore, an increase in the number of output signals of the drive circuit and an improvement in operation speed are required. As a method of increasing the number of output signals from the drive circuit, a method of increasing the number of shift unit circuits is conceivable, but in this case, power consumption of the drive circuit increases.

  On the other hand, as a method for improving the operation speed of the driving device, a method of increasing the clock frequency and shortening the gate length in the thin film transistor constituting the driving circuit can be considered. However, in this case, the manufacturing process of the thin film transistor needs to be significantly changed, and the manufacturing cost increases. In addition, when the gate length of the thin film transistor is shortened, the drain withstand voltage is lowered and the transistor may be damaged. Therefore, there is a limit to the speeding up of the transistor, and power consumption increases even when the clock frequency is increased.

  An object of the present invention is to provide a shift register that can realize high-speed operation with low power consumption.

  The shift register of the present invention includes a 2n + 1 (n is a natural number) shift unit circuit that sequentially shifts and outputs a start pulse in synchronization with a clock signal and an inverted clock signal obtained by inverting the clock signal, and a 2n-1th shift unit. The first signal from the circuit, the second signal from the 2n-th shift unit circuit, and the third signal from the 2n + 1-th shift unit circuit are input, and the first signal obtained by inverting the first signal A first sampling signal generating means for calculating a logical product of an inverted signal, the second signal, and a third inverted signal obtained by inverting the third signal, and outputting the result as a sampling signal; and the first signal And a second sampling signal generated by calculating a logical product of the second signal and the second signal and the third signal and outputting each of them as a sampling signal Shift register, characterized in that it comprises a stage, a.

  According to the present invention, every time the shift unit circuit is increased by two, the output sampling signal can be increased by three. That is, 3n sampling signals can be generated by performing a logical operation on the output signals from the 2n + 1 stage shift unit circuits. Therefore, the number of shift unit circuits constituting the shift register can be reduced, and as a result, the power consumption of the shift register can be reduced and high-speed operation can be realized.

  The first sampling signal generation means outputs a fourth signal by inverting the second signal, and outputs the fourth signal, the first signal, the third signal, and the fourth signal, respectively. It is preferable to have a NOR circuit that inverts, calculates a logical product of the inverted output signals, and outputs the result as a sampling signal. Thereby, the 1st sampling signal production | generation means which operate | moves by positive logic can be comprised.

  The first sampling signal generation means calculates and inverts the logical sum of the first signal, the second signal, and the third signal, and outputs the first NOR circuit as a fifth signal A second NOR circuit that inverts each of the first signal, the third signal, and the fifth signal, calculates a logical product of the inverted output signals, and outputs the result as a sampling signal; It is preferable to have. Thereby, the 1st sampling signal production | generation means which operate | moves by positive logic can be comprised.

  The clock signal includes a first clock signal having a duty ratio of 2: 1 and a second clock having the same waveform as the first clock signal and having a phase delayed by 1/3 period with respect to the first clock signal. And a signal. According to the present invention, the clock signal is composed of the first clock signal and the second clock signal having a frequency lower than that of the conventional clock signal. Therefore, since the clock frequency is reduced, the power consumption of the control circuit that supplies the clock to the shift register can be reduced.

  The shift unit circuit is preferably capable of controlling the transfer direction of the start pulse based on a transfer direction signal indicating the transfer direction. According to the present invention, since the transfer direction of the start pulse is controlled, for example, the display image on the liquid crystal can be reversed left and right or up and down without changing the supply order of the image signals.

  Further, based on an input signal and an output signal of the shift unit circuit, an operation time in which any one of the shift unit circuits is operating is specified, and only the clock signal and the shift unit circuit are operating. It is preferable to provide a control circuit for supplying an inverted clock signal. According to the present invention, since the clock signal and the inverted clock signal are supplied only to the shift unit circuit that is operating, it is possible to prevent the wasteful supply of signals to the shift unit circuit that is not operating, and to reduce power consumption.

  Preferably, the shift unit circuits are grouped, and the control circuit includes a plurality of unit control circuits that supply the clock signal and the inverted clock signal only to the grouped shift unit circuits.

  As described above, when the clock signal and the inverted clock signal are supplied only to the operating shift unit circuit, a circuit for selecting each shift unit circuit is required, which complicates the circuit configuration and reduces the circuit area. Increase. Therefore, according to the present invention, the control circuit is divided into a plurality of unit control circuits, and the unit control circuit supplies a clock signal and an inverted clock signal for each grouped shift unit circuit. Therefore, it is not necessary to individually select the shift unit circuit, so that the circuit area of the control circuit can be reduced.

<1. Overall configuration of electro-optical device>
First, the electro-optical device according to the present invention uses liquid crystal as an electro-optical material. The electro-optical device 1 includes a liquid crystal panel AA as a main part. The liquid crystal panel AA includes an element substrate on which a thin film transistor (hereinafter referred to as “TFT”) is formed as a switching element, a counter substrate disposed to face the element substrate at a predetermined interval, the element substrate, Liquid crystal provided between the counter substrates.

  FIG. 1 is a block diagram showing an overall configuration of an electro-optical device 1 to which a data line driving circuit 200 as a shift register according to this embodiment is applied. The electro-optical device 1 includes a timing generation circuit 300 and an image processing circuit 400 in addition to the liquid crystal panel AA. On the element substrate of the liquid crystal panel AA, an image display area A, a scanning line driving circuit 100, a data line driving circuit 200, a sampling circuit 240, and image signal supply lines L1 to L3 are formed.

  The input image data D supplied to the electro-optical device 1 has, for example, a 3-bit parallel format. The timing generation circuit 300 is synchronized with the input image data D and includes a Y clock signal YCK, an inverted Y clock signal YCKB, a first X clock signal XCK1, a first inverted X clock signal XCK1B, a second X clock signal XCK2, and a second inverted X clock. The signal XCK2B, the Y transfer start pulse DY, the X transfer start pulse DX, the transfer direction control signal DIR, and the inverted transfer direction control signal DIRB are generated and supplied to the scanning line driving circuit 100 and the data line driving circuit 200. The timing generation circuit 300 generates various timing signals for controlling the image processing circuit 400 and outputs them.

  Here, the Y clock signal YCK is a signal for specifying a period for selecting the scanning line 2, and the inverted Y clock signal YCKB is an inverted version of the logic level of the Y clock signal YCK. The first X clock signal XCK1 is a signal for specifying a period for selecting the data line 3, and the first inverted X clock signal XCK1B is an inversion of the logic level of the first X clock signal XCK1. The second X clock signal XCK2 is a signal for specifying a period for selecting the data line 3, and the second inverted X clock signal XCK2B is obtained by inverting the logic level of the second X clock signal XCK2. Specifically, the first X clock signal XCK1 has a duty ratio of 2: 1, and the second X clock signal XCK2 has the same waveform as the first X clock signal XCK1 and a phase of 1 with respect to the first X clock signal XCK1. / 3 is delayed. The Y transfer start pulse DY is a pulse for instructing the start of selection of the scanning line 2, and the X transfer start pulse DX is a pulse for instructing the start of selection of the data line 3.

  Further, the transfer direction control signal DIR is a signal for instructing the selection order of the scanning lines 2 and the data lines 3. Specifically, when the logical level of the transfer direction control signal DIR is high, the transfer direction control signal DIR sequentially selects each scanning line 2 from top to bottom and selects each data line 3 from left to right. Instruct to do. On the other hand, when the logical level of the transfer direction control signal DIR is low, the transfer direction control signal DIR instructs to select each scanning line 2 sequentially from the bottom to the top and select each data line 3 from the right to the left. To do.

  In this example, the common transfer direction control signal DIR and the inverted transfer direction control signal DIRB are supplied to the scanning line driving circuit 100 and the data line driving circuit 200. However, the timing generation circuit 300 selects the scanning line. Needless to say, the signal for selecting and the data line selecting signal may be separately generated and supplied to the scanning line driving circuit 100 and the data line driving circuit 200. The image processing circuit 400 subjects the input image data D to gamma correction and the like that considers the light transmission characteristics of the liquid crystal panel, and then D / A converts the RGB image data to obtain the image signals 40R, 40G, and 40B. Generated and supplied to the liquid crystal panel AA.

<1-2: Image display area>
Next, in the image display area A, as shown in FIG. 1, m (m is a natural number of 2 or more) scanning lines 2 are formed in parallel along the X direction, and n (n is A natural number of 2 or more) data lines 3 are formed in parallel along the Y direction. In the vicinity of the intersection of the scanning line 2 and the data line 3, the gate of the TFT 50 is connected to the scanning line 2, the source of the TFT 50 is connected to the data line 3, and the drain of the TFT 50 is connected to the pixel electrode 6. Each pixel includes a pixel electrode 6, a counter electrode (described later) formed on the counter substrate, and a liquid crystal disposed between the two electrodes. As a result, the pixels are arranged in a matrix corresponding to each intersection of the scanning line 2 and the data line 3.

  Further, scanning signals Y1, Y2,..., Ym are applied to each scanning line 2 to which the gate of the TFT 50 is connected in a pulse-by-line manner. Therefore, when a scanning signal is supplied to a certain scanning line 2, the TFT 50 connected to the scanning line is turned on, so that the image signals X1, X2,..., Xn supplied from the data line 3 at a predetermined timing are After being written in order to the corresponding pixels, they are held for a predetermined period.

  Since the orientation and order of liquid crystal molecules change according to the voltage level applied to each pixel, gradation display by light modulation becomes possible. For example, the amount of light passing through the liquid crystal is limited as the applied voltage increases in the normally white mode, whereas the amount of light that passes through the liquid crystal is reduced as the applied voltage increases in the normally black mode. As a whole, light having contrast according to the image signal is emitted for each pixel. For this reason, a predetermined display becomes possible.

  In order to prevent the held image signal from leaking, a storage capacitor 51 is added in parallel with a liquid crystal capacitor formed between the pixel electrode 6 and the counter electrode. For example, since the voltage of the pixel electrode 6 is held by the storage capacitor 51 for a time that is three orders of magnitude longer than the time when the source voltage is applied, the holding characteristics are improved, and as a result, a high contrast ratio is realized. Become.

<1-3: Data Line Driving Circuit and Sampling Circuit>
Next, the data line driving circuit 200 generates sampling signals S1 to Sn that are sequentially activated in synchronization with the first X clock signal XCK1 and the second X clock signal XCK2. Further, the data line driving circuit 200 can control the order in which the sampling signals S1 to Sn are activated by the transfer direction control signal DIR and the inverted transfer direction control signal DIRB. Specifically, the transfer direction control signal When DIR is at a high level and the inverted transfer direction control signal DIRB is at a low level, the sampling signal becomes active in the order of S1, S2,... Sn, the transfer direction control signal DIR is at a low level, and the inverted transfer direction control signal DIRB is at a high level. In this case, the sampling signal becomes active in the order of Sn → Sn−1 →... S1.

  The sampling circuit 240 includes n switches SW1 to SWn. Each of the switches SW1 to SWn is composed of a TFT, and when the sampling signals S1 to Sn supplied to the gate are sequentially activated, the switches SW1 to SWn are sequentially turned on. Then, the image signals 40R, 40G, and 40B supplied through the image signal supply lines L1 to L3 are sampled and sequentially supplied to the data lines 3. Therefore, if the sampling signal becomes active in the order of S1 → S2 →... Sn, the data line 3 is sequentially selected from the left to the right, while if the sampling signal becomes active in the order of Sn → Sn−1 →. The data line 3 is selected sequentially from right to left. Of course, the sampling circuit 240 may be included in the data line driving circuit 200.

  FIG. 2 is a circuit diagram showing a configuration of the data line driving circuit 200. The data line driving circuit 200 includes j circuit blocks BL1, BL2,..., BLj and n logical operation unit circuits B1, B2,. Here, j and n are natural numbers satisfying 3j = 2n + 1.

  FIG. 3 is a block diagram showing a configuration of a part of the circuit blocks BL of the data line driving circuit 200. As shown in FIG. That is, FIG. 3 shows the i−1th and ith circuit blocks BL (i−1) and BLi, and the m−2th, m−1th and mth logic operation unit circuits B (m−2). ), B (m−1), and Bm. Here, i and m are natural numbers satisfying 1 ≦ i ≦ j and 3i = 2m + 1.

  Each of the circuit blocks BL (i−1) and BLi includes a three-stage shift register unit circuit A and a control unit circuit C that controls the three-stage shift register unit circuit A. Specifically, the circuit block BLi includes three-stage shift register unit circuits Ai1, Ai2, and Ai3, and a control unit circuit Ci. Similarly, the circuit block BL (i-1) includes three-stage shift register unit circuits A (i-1) 1, A (i-1) 2, A (i-1) 3, and a control unit circuit C ( i-1). These shift register unit circuits A (i-1) 1 to A (i-1) 3 and Ai1 to Ai3 are shift registers from the 3i-5 (2m-4) th to the 3i (2m + 1) th counting from the beginning. It is a unit circuit.

  Hereinafter, although the circuit block BLi will be described in detail, the other circuit blocks BL have the same configuration. In the circuit block BLi, the shift register unit circuits Ai1 to Ai3 transfer the X transfer start pulse DX. Further, the transfer direction control signal DIR and the inverted transfer direction control signal DIRB are supplied to the shift register unit circuits Ai1 to Ai3, thereby controlling the transfer direction.

  The control unit circuit Ci specifies the operation period of each shift register unit circuit Ai1 to Ai3 based on the input signal and output signal of each shift register unit circuit Ai1 to Ai3. In this period, the first X clock signal XCK1, the first inverted X clock signal XCK1B, the second X clock signal XCK2, and the second inverted clock signal XCK2B are supplied from the control unit circuit Ci to the shift register unit circuits Ai1 to Ai3. . As described above, the control unit circuit Ci collectively controls the plurality of shift register unit circuits Ai1 to Ai3, so that the number of control unit circuits can be greatly reduced when viewed as a whole of the data line driving circuit 200.

  Each logical operation unit circuit B corresponds to a two-stage shift register unit circuit A. Specifically, there is no logical operation unit circuit corresponding to the first shift register unit circuit A11, and a logical operation unit circuit B is provided corresponding to the second and subsequent shift register unit circuits A. In FIG. 3, the logical operation unit circuit B (m−2) corresponds to the 2m−4 and 2m−3rd shift register unit circuits A (i−1) 1 and A (i−1) 2. The logical operation unit circuit B (m−1) corresponds to the 2m−2, 2m−1th shift register unit circuits A (i−1) 3 and Ai1. The logical operation unit circuit Bm corresponds to the 2m, 2m + 1th shift register unit circuits Ai2, Ai3.

  The logical operation unit circuit Bm generates sampling signals Sm1, Sm2, and Sm3 based on input signals and output signals of the shift register unit circuits Ai2 and Ai3. The other logical operation unit circuits Bm-1 and Bm-2 have the same configuration as the logical operation unit circuit Bm.

  FIG. 4 is a circuit diagram of the circuit block BLi. Each of the logical operation unit circuits Bm-1 to Bm includes a first sampling signal generation unit 510 and a second sampling signal generation unit 520. The first sampling signal generating means 510 includes a first signal P1 from the (2m-1) th shift register unit circuit Ai1, a second signal P2 from the 2mth shift register unit circuit Ai2, and a 2m + 1th shift. The third signal P3 from the register unit circuit Ai3 is input. The first sampling signal generation means 510 calculates the logical product of the first inverted signal obtained by inverting the first signal P1, the second signal P2, and the third inverted signal obtained by inverting the third signal P3. It calculates and outputs as sampling signal Sm2. Specifically, the first sampling signal generation unit 510 inverts the second signal P2 to output the fourth signal P2B, the first signal P1, the third signal P3, and And a NOR circuit 512 that inverts the fourth signal P2B and calculates a logical product of the inverted output signals.

  The second sampling signal generation means 520 calculates the logical product of the first signal P1 and the second signal P2 and the logical product of the second signal P2 and the third signal P3, and respectively obtains the sampling signal Sm1. , Sm3. Specifically, a NAND circuit 521 that calculates a logical product of the first signal P1 and the second signal P2, a knot circuit 522 that inverts and outputs a signal from the NAND circuit 521, and a second signal P2 And a NAND circuit 523 that calculates a logical product of the third signal P3 and a knot circuit 524 that inverts and outputs a signal from the NAND circuit 523.

  The shift register unit circuits Ai1 to Ai3 include clocked inverters 501 to 504, respectively. The clocked inverters 501 to 504 invert and output each input signal when the control terminal voltage is at a high level, and place the output terminal in a high impedance state when the control terminal voltage is at a low level. In the shift register unit circuit Ai1, the second X clock signal XCK2 and the second inverted clock signal XCK2B, which are active for a predetermined period, are supplied to the control terminals of the clocked inverters 501 and 502. In the shift register unit circuit Ai2, the first inverted X clock signal XCK1B and the first X clock signal XCK1, which are active only for a predetermined period, are supplied to the control terminals of the clocked inverters 501 and 502. . In the shift register unit circuit Ai3, the control terminals of the clocked inverters 501 and 502 are supplied with the second X clock signal XCK2 and the second inverted X clock signal XCK2B that are active for a predetermined period. In the shift register unit circuits Ai1 to Ai3, the inverted transfer direction control signal DIRB is supplied to the control terminal of the clocked inverter 503, and the transfer direction control signal DIR is supplied to the control terminal of the clocked inverter 504. .

  When the transfer direction control signal DIR is high and the inverted transfer direction control signal DIRB is low, the clocked inverter 503 is in a high impedance state, and the clocked inverter 504 functions as an inverter. Therefore, when the transfer direction control signal DIR is at a high level, the shift register unit circuits Ai1 to Ai3 are equivalent to the circuit shown in FIG. Conversely, when the transfer direction control signal DIR is low and the inverted transfer direction control signal DIRB is high, the clocked inverter 504 is in a high impedance state and the clocked inverter 503 functions as an inverter. Therefore, when the transfer direction control signal DIR is at a low level, the shift register unit circuits Ai1 to Ai3 are equivalent to the circuit shown in FIG.

  Here, it is assumed that the logical level of the transfer direction control signal DIR is high (see FIG. 5A). The clocked inverter 501 of each shift register unit circuit Ai1 to Ai3 is supplied with the first control signals Q1, Q2, and Q3, and the clocked inverter 502 is supplied with the second control signals Q1 ′ and Q2′Q3 ′. . The logic levels of the second control signals Q1 ', Q2'Q3' are those obtained by inverting the logic levels of the first control signals Q1, Q2, Q3.

  In the shift register unit circuit Ai1, when the first control signal Q1 is at a high level, the clocked inverter 501 inverts and outputs the X transfer start pulse DX. At this time, since the second control signal Q1 'is at a low level, the output terminal of the clocked inverter 502 is in a high impedance state. In this case, the X transfer start pulse DX is output via the clocked inverter 501 and the inverter 504. On the other hand, when the second control signal Q1 'is at a high level, the clocked inverter 502 inverts and outputs the X transfer start pulse DX. At this time, since the first control signal Q1 is at a low level, the output terminal of the clocked inverter 501 is in a high impedance state. In this case, the clocked inverter 502 and the inverter 504 constitute a latch circuit.

  That is, it can be considered that the shift register unit circuits Ai1 to Ai3 include a first logic circuit composed of clocked inverters 501 and 503 and a second logic circuit composed of clocked inverters 502 and 504. it can. That is, when the transfer direction control signal DIR is at a high level (transfer direction is from left to right), the first logic circuit functions as the clocked inverter 501 and the second logic circuit functions as a latch circuit. When the inverted transfer direction control signal DIRB is at a high level (transfer direction is from right to left), the first logic circuit functions as a latch circuit, and the second logic circuit functions as a clocked inverter.

  Returning to FIG. The control unit circuit Cj includes NOR circuits 531, 532, a NAND circuit 533, an inverter 534, and transfer gates 541, 542, 543, 544, 545, 546, 551, 552, 553, 554, 555, 556. FIG. 6 is a timing chart showing the operation of the circuit block BLi. However, it is assumed that the transfer direction control signal DIR is at a high level and the X transfer start pulse DX is transferred from left to right. Further, the input signal of the shift register unit circuit Ai1 is P0 (same as the X transfer start pulse DX), the output signal of the shift register unit circuit Ai1 is P1, the output signal of the shift register unit circuit Ai2 is P2, and the shift register unit circuit Ai3 The output signal is P3.

  When the signal P0 becomes high level at time T1, the output signal of the NOR circuit 531 becomes low level, and accordingly, the output signal of the NAND circuit 533 becomes high level. In the following description, the output signal of the NAND circuit 533 is referred to as a clock control signal CTLi. The subscript “i” following “CTL” designates a circuit block, and the clock control signal of the circuit block BLi + 1 at the next stage is CTL (i + 1). When the clock control signal CTLi becomes active (high level), the transfer gates 541 to 546 are turned on, and the second inverted X clock signal XCK2B, the first inverted X clock signal XCK1B, and the second X clock signal XCK2 are signals Q1, Q2. , Q3 are supplied to the shift register unit circuits Ai1-Ai3, and the second inverted X clock signal XCK2B, the first X clock signal XCK1, and the second X clock signal XCK2 are supplied as signals Q1 ′, Q2 ′, Q3 ′, respectively. This is supplied to the shift register unit circuits Ai1 to Ai3.

  As a result, the X transfer start pulse DX is sequentially transferred in the order of signal P0 → signal P1 → signal P2 → signal P3. Since the signal P2 is supplied to the NOR circuit 532, the output signal thereof becomes low level at time T2 when the signal P2 becomes high level. When the signal P3 transitions to the low level at time T3, the output signal of the NOR circuit 532 becomes the high level. Since the clock control signal CTLi is generated by the NAND circuit 533, the clock control signal CTLi becomes a high level during a period when one of the output signals of the NOR circuits 531 and 532 is at a low level. For this reason, the clock control signal CTLi becomes active during the period from time T1 to time T3.

  When the time T3 has elapsed, the clock control signal CTLi becomes inactive, so that the transfer gates 541 to 546 are turned off. On the other hand, the transfer gates 551 to 556 that are in the off state while the clock control signal CTLi is active are turned on. As a result, the signals Q1, Q2, and Q3 become low level, and the signals Q1 ', Q2', and Q3 'become high level. Then, in each shift register unit circuit Ai1 to Ai3, the clocked inverter 501 enters a high impedance state, and the inverter 504 and the clocked inverter 502 constitute a latch circuit. As a result, the level of each output signal of the shift register unit circuits Ai1 to Ai3 is kept low until the X transfer start pulse DX becomes high level again. In other words, when the X transfer start pulse DX arrives, the circuit block BLi autonomously detects this and starts a shift operation until the next X transfer start pulse DX arrives when the operation is completed. , Stop operation. As a result, power consumption can be reduced.

  Further, since the control unit circuit Cj controls the plurality of shift register unit circuits Ai1 to Ai3 at a time, the configuration is simplified compared to the case where the control unit circuit Cj is provided for each shift register unit circuit. be able to.

  Moreover, although the circuit block BLi described above is configured with positive logic, it may be configured with negative logic. That is, two NAND circuits are used in place of the NOR circuits 531 and 532, and a NOR circuit is used in place of the NAND circuit 533 to activate the clock control signal at a low level.

<1-4: Scan Line Drive Circuit>
Next, the scanning line driving circuit 100 will be described. FIG. 7 is a block diagram showing a configuration of the scanning line driving circuit 100. As shown in this figure, the scanning line driving circuit 100 includes a Y shift register 102, a level shifter 103, and a buffer 104. The Y shift register 102 is supplied with a Y clock signal YCK and an inverted Y clock signal YCKB instead of the first X clock signal XCK1, the first inverted X clock signal XCK1B, the second X clock signal XCK2, and the second inverted X clock signal XCK2B. The configuration is the same as that of the data line driving circuit 200 described above except for the above points and the number of shift stages. Therefore, the scanning line driving circuit 100 can be small in circuit size, similar to the data line driving circuit 200 described above.

  The level shifter 103 shifts the level of each output signal of the Y shift register 102 to convert it to a level suitable for driving the scanning line 2. Further, the buffer 104 converts each output signal of the level shifter 103 into a low impedance and outputs it to each scanning line 2 as scanning signals Y1, Y2,. In this scanning line driving circuit 100, it is needless to say that the Y shift register 102 configured with negative logic may be applied.

  According to this embodiment, there are the following effects. Each time the shift register unit circuit A is increased by two, the output sampling signal S can be increased by three. That is, 3n sampling signals S can be generated by performing a logical operation on the output signals P1, P2, and P3 from the 2n + 1 stage shift register unit circuit A. Therefore, the number of stages of the shift register unit circuit A constituting the data line driving circuit 200 can be reduced, and as a result, the power consumption of the data line driving circuit 200 can be reduced and high-speed operation can be realized.

  Since the first sampling signal generation means 510 is constituted by the knot circuit 511 and the NOR circuit 512, the first sampling signal generation means that operates in positive logic can be configured. The clock signal is composed of a first X clock signal XCK1 and a second X clock signal XCK2 having a frequency lower than that of the conventional clock signal. Therefore, since the clock frequency is reduced, the power consumption of the control circuit that supplies the clock to the data line driving circuit 200 can be reduced. Since the transfer direction of the X transfer start pulse DX is controlled using the transfer direction control signal DIR and the inverted transfer direction control signal DIRB, for example, the liquid crystal display is performed without changing the supply order of the image signals 40R, 40G, and 40B. The image can be flipped horizontally and vertically.

  The control unit circuit C is provided, and the first X clock signal XCK1, the first inverted X clock signal XCK1B, the second X clock signal XCK2, and the second inverted clock signal XCK2B are supplied only to the operating shift register unit circuit A. Therefore, it is possible to prevent unnecessary signals from being supplied to the shift register unit A circuit that does not operate, and to reduce power consumption. The control circuit is divided into a plurality of unit control circuits C, and each of the grouped shift register unit circuits A is divided into a first X clock signal XCK1, a first inverted X clock signal XCK1B, and a second X clock signal. XCK2 and the second inverted clock signal XCK2B were supplied. Therefore, since it is not necessary to individually select the shift register unit circuit A, the circuit area of the control circuit can be reduced.

<1-5: Configuration example of liquid crystal panel>
Next, the overall configuration of the electro-optical device 1 according to the above-described electrical configuration will be described with reference to FIGS. 8 and 9. 8 is a perspective view showing the configuration of the electro-optical device 1, and FIG. 9 is a cross-sectional view taken along line AA in FIG. The liquid crystal panel AA includes an element substrate 151 such as glass or semiconductor on which the pixel electrode 6 or the like is formed, and a transparent counter substrate 152 such as glass on which the common electrode 158 or the like is formed. The element substrate 151 and the counter substrate A liquid crystal 155 is sealed in the gap 152.

  A seal member 154 that seals the gap between the element substrate 151 and the counter substrate 152 is provided on the outer periphery of the counter substrate 152. The seal member 154 forms a space in which the liquid crystal 155 is sealed together with the element substrate 151 and the counter substrate 152. A spacer 153 is mixed in the seal member 154 in order to maintain a distance between the element substrate 151 and the counter substrate 152. Note that an opening for sealing the liquid crystal 155 is formed in the seal member 154, and the opening is sealed with a sealing material 156 after the liquid crystal 155 is sealed.

  Here, on the opposite surface of the element substrate 151 and on the outer side of the seal member 154, the data line driving circuit 200 described above is formed to drive the data line 3 extending in the Y direction. Yes. Further, a plurality of connection electrodes 157 are formed on one side, and various signals from the timing generation circuit 300 and image signals 40R, 40G, and 40B are input. Further, a scanning line driving circuit 100 is formed on one side adjacent to the one side, and the scanning line 2 extending in the X direction is driven from both sides. On the other hand, the common electrode 158 of the counter substrate 152 is electrically connected to the element substrate 151 by a conductive material provided in at least one of the four corners of the bonding portion with the element substrate 151. In addition, the counter substrate 152 is provided with, for example, a color filter arranged in a stripe shape, a mosaic shape, a triangle shape, or the like according to the use of the liquid crystal panel AA. A black matrix such as resin black in which a metal material such as nickel or nickel, carbon, titanium or the like is dispersed in a photoresist is provided, and thirdly, a backlight for irradiating light to the liquid crystal panel AA is provided. In the case of application, a black matrix is provided on the counter substrate 152 without forming a color filter.

  In addition, the opposing surfaces of the element substrate 151 and the counter substrate 152 are each provided with an alignment film or the like that is rubbed in a predetermined direction, and a polarizing plate (not shown) corresponding to the alignment direction on each back side. Are provided respectively. However, if a polymer-dispersed liquid crystal dispersed as fine particles in a polymer is used as the liquid crystal 155, the above-described alignment film, polarizing plate, and the like are not required. This is advantageous in terms of reducing power consumption. Instead of forming part or all of the peripheral circuits such as the data line driving circuit 200 and the scanning line driving circuit 100 on the element substrate 151, for example, they are mounted on a film using a TAB (Tape Automated Bonding) technique. The driving IC chip may be electrically and mechanically connected via an anisotropic conductive film provided at a predetermined position of the element substrate 151. The driving IC chip itself may be a COG (Chip On Grass). A technique may be used to electrically and mechanically connect to a predetermined position of the element substrate 151 via an anisotropic conductive film.

<2. Application example>
(1) In the above-described embodiment, in the circuit block BLi, the logical operation unit circuit Bm is configured by the first sampling signal generation unit 510 by the knot circuit 511 and the NOR circuit 512. As shown, two NOR circuits 611 and 612 may be used. That is, the first sampling signal generation means 610 calculates and inverts the logical sum of the first signal P1, the second signal P2, and the third signal P3, and outputs the first signal P1 as the fifth signal. The NOR circuit 611, the first signal P1, the third signal P3, and the fifth signal are inverted, and a second NOR that outputs a logical product of these inverted output signals and outputs it as a sampling signal. Circuit 612.

(2) In the above-described embodiment, the first X clock signal XCK1, the first inverted X clock signal XCK1B, the second X clock signal XCK2, and the second inverted X clock signal XCK2B are supplied to the circuit blocks BL1 to BLj. Not limited to. That is, only the first X clock signal and the second X clock signal may be supplied, and the first inverted X clock signal and the second inverted X clock signal may be generated inside each circuit block.

(3) In the above-described embodiment, each circuit block BL1 to BLj is provided with three shift register unit circuits. However, the present invention is not limited to this, and the number of shift register unit circuits included in the circuit block is appropriately determined. It's okay.

  Further, the number of shift register unit circuits included in the circuit block may not be constant. For example, a circuit block including three shift register unit circuits and a circuit block including four shift register unit circuits may be mixed. Assuming that the number of shift register unit circuits included in one circuit block is the number of unit circuits N, the number of unit circuits N can be arbitrarily set, so that even when the number of data lines or the number of colors N is not divisible, It can correspond to. For example, when the number of data lines is 362 and the unit circuit number N of the circuit block is only “4”, all the data lines cannot be connected to the circuit block. In this case, by using 89 circuit blocks with N = 4 and 2 circuit blocks with N = 3, 362 data lines can be supported.

  Further, all shift register unit circuits may be controlled by one control circuit without providing the control unit circuit. For example, in one control circuit, based on the input signal and the output signal of the shift register unit circuit, the operation time during which any one of the shift unit circuits is operating is specified, and only this operating shift unit circuit The first X clock signal, the second X clock signal, the first inverted X clock signal, and the second inverted X clock signal may be supplied.

(4) In the above-described embodiment, the transfer direction of the X transfer start pulse DX is controlled using the transfer direction control signal DIR and the inverted transfer direction control signal DIRB for instructing the transfer direction. However, the present invention is not limited to this. That is, the transfer direction may be set in advance, and the shift register unit circuit A may be configured as shown in FIG. 5A or 5B.

(5) In the above-described embodiments, the electro-optical device provided with the liquid crystal is exemplified, but the present invention is also applied to an electro-optical device using an electro-optical material other than the liquid crystal. An electro-optical material is a material whose optical characteristics such as transmittance and luminance change when an electric signal (current signal or voltage signal) is supplied. For example, a display panel using an OLED element such as an organic EL (Electro Luminescent) or a light emitting polymer as an electro-optical material, or a microcapsule containing a colored liquid and white particles dispersed in the liquid is used as an electro-optical material. The electrophoretic display panel used, the twist ball display panel using twist balls painted in different colors for different polarities as an electro-optical material, the toner display panel using black toner as an electro-optical material, or helium The present invention can be applied to various electro-optical devices such as a plasma display panel using a high-pressure gas such as or neon as an electro-optical material.

<3. Electronic equipment>
Next, an electronic apparatus to which the electro-optical device 1 according to the above-described embodiments and application examples is applied will be described. FIG. 11 shows the configuration of a mobile personal computer to which the electro-optical device 1 is applied. The personal computer 2000 includes the electro-optical device 1 as a display unit and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002. In the electro-optical device 1, the configuration of the data line driving circuit 200 is simplified, so that a high-definition image can be displayed at a narrow pitch.

  FIG. 12 shows a configuration of a mobile phone to which the electro-optical device 1 is applied. A cellular phone 3000 includes a plurality of operation buttons 3001, scroll buttons 3002, and the electro-optical device 1 as a display unit. By operating the scroll button 3002, the screen displayed on the electro-optical device 1 is scrolled. FIG. 13 shows a configuration of a portable information terminal (PDA: Personal Digital Assistants) to which the electro-optical device 1 is applied. The information portable terminal 4000 includes a plurality of operation buttons 3001, a power switch 4002, and the electro-optical device 1 as a display unit. When the power switch 4002 is operated, various types of information such as an address book and a schedule book are displayed on the electro-optical device 1.

  The electronic apparatus to which the electro-optical device 1 is applied includes, in addition to those shown in FIGS. 11 to 13, a digital still camera, a liquid crystal television, a viewfinder type, a monitor direct-view type video tape recorder, a car navigation device, a pager, Examples include electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, and devices equipped with touch panels. The electro-optical device 1 described above can be applied as a display unit of these various electronic devices.

1 is a perspective view illustrating an overall configuration of an electro-optical device to which a shift register according to an embodiment of the present invention is applied. It is a block diagram which shows the structure of the said shift register. It is a block diagram of a part of circuit block which constitutes the shift register. It is a circuit diagram of the circuit block. (A) is an equivalent circuit diagram of the shift unit circuit when the transfer control direction is high level, and (B) is an equivalent circuit diagram of the shift unit circuit when the transfer control direction is low level. It is a timing chart of the circuit block. FIG. 2 is a block diagram illustrating a configuration of a scanning line driving circuit of the electro-optical device. It is a perspective view for demonstrating the structure of the said electro-optical apparatus. FIG. 3 is a cross-sectional view taken along line AA for explaining the structure of the electro-optical device. It is a circuit diagram which shows the other structural example of the logical operation unit circuit which comprises the said shift register. FIG. 14 is a perspective view illustrating a configuration of a mobile personal computer to which the above-described electro-optical device is applied. It is a perspective view which shows the structure of the mobile telephone to which the electro-optical device mentioned above is applied. It is a perspective view which shows the structure of the information portable terminal to which the electro-optical device mentioned above is applied.

Explanation of symbols

  200: Data line driving circuit (shift register), Ai1 to Ai3: Shift register unit circuit (shift unit circuit), Ci: Control unit circuit (control circuit), 510: First sampling signal generating means, 520: Second Sampling signal generating means, 511 ... NOT circuit, 512 ... NOR circuit, 611 ... first NOR circuit, 612 ... second NOR circuit, DX ... X transfer start pulse, XCK1 ... first X clock signal (first clock signal) , XCK1B: first inverted X clock signal (first inverted clock signal), XCK2: second X clock signal (second clock signal), XCK2B: second inverted X clock signal (second inverted clock signal), P1: first , P2 ... second signal, P3 ... third signal, P2B ... fourth signal, Sm1-Sm3 ... sampling signal.

Claims (6)

A 2n (n is a natural number) shift unit circuit that sequentially shifts and outputs a start pulse in synchronization with a first clock signal having a duty ratio of 2: 1 and a first inverted clock signal obtained by inverting the first clock signal;
The start pulse is sequentially shifted in synchronization with a second clock signal having the same waveform as the first clock signal and a phase delayed by 1/3 of the first clock signal, and a second inverted clock signal obtained by inverting the second clock signal. 2n-1 and 2n + 1 shift unit circuits to be output,
A first signal from the 2n-1 th shift unit circuit, the second signal from the 2n-th shift unit circuit, and a third signal from the 2n + 1 th shift unit circuit is input, the First sampling for calculating a logical product of the first inverted signal obtained by inverting the first signal, the second signal, and the third inverted signal obtained by inverting the third signal and outputting the result as a sampling signal Signal generating means;
Second sampling signal generating means for calculating a logical product of the first signal and the second signal, and a logical product of the second signal and the third signal, and outputting each of them as a sampling signal; ,
A shift register comprising: The first sampling signal generation means includes:
A knot circuit that inverts the second signal and outputs a fourth signal;
A NOR circuit that inverts each of the first signal, the third signal, and the fourth signal, calculates a logical product of the inverted output signals, and outputs the result as a sampling signal. The shift register according to claim 1. The first sampling signal generation means includes:
A first NOR circuit that calculates and inverts a logical sum of the first signal, the second signal, and the third signal, and outputs the result as a fifth signal;
A second NOR circuit that inverts each of the first signal, the third signal, and the fifth signal, calculates a logical product of the inverted output signals, and outputs the result as a sampling signal. The shift register according to claim 1. The shift unit circuit includes a shift register according to any one of claims 1 to 3, characterized in that on the basis of the transfer direction signal indicating the transfer direction can control the transfer direction of the start pulse. Based on an input signal and an output signal of the shift unit circuit, an operation time in which any one of the shift unit circuits is operating is specified, and the clock signal and the inverted clock are only applied to the operating shift unit circuit. the shift register according to claim 1, characterized in that it comprises a control circuit for supplying a signal 4. The shift unit circuits are grouped,
Wherein the control circuit includes a shift register according to any one of claims 1 to 5, characterized in that it comprises a plurality of unit control circuit for supplying said clock signal and said inverted clock signal only to the grouped shifted unit circuit .

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