JP4784186B2 - Vertical Hall element and its magnetic detection sensitivity adjustment method - Google Patents

Description

  The present invention relates to a vertical Hall element that uses a Hall effect to detect a magnetic field component parallel to a substrate surface (chip surface) and a method for adjusting the magnetic detection sensitivity, which are useful when used as a magnetic sensor in a rotation detection device, for example. .

  As is well known, since the Hall element can detect the angle without contact, it is mounted on a so-called Hall IC or the like, for example, as a magnetic sensor, for detecting the rotation (angle) of the throttle valve opening of an in-vehicle internal combustion engine. It is used. First, the principle of magnetic detection by such a Hall element and the principle of rotation detection will be briefly described.

When a magnetic field (magnetism) perpendicular to the current flowing in the material is applied, an electric field (voltage) is generated in a direction perpendicular to both the current and the magnetic field. This phenomenon is called the Hall effect, and the voltage generated here is called the Hall voltage. Here, the width of the magnetic detection part (hall plate) of the Hall element (eg, conductor) is w, the length is L, the thickness is D, the angle between the element and the magnetic field is θ, and the applied magnetic flux density is B. When the supply (drive) current is Ih, the Hall voltage V _H is
V _H = (L · μh · Ih · B · cos θ / (D · 2w · σ) (A)
It can be expressed as “Μh” is carrier mobility, and “σ” is a coefficient.

As can be seen from this relational expression (A), the Hall voltage V _H changes in accordance with the angle θ formed by the Hall element and the magnetic field, so that the angle can be detected by using this. Thus, an angle detection sensor such as a throttle valve opening sensor can be realized by using the Hall element.

  As such a Hall element, a horizontal Hall element that detects a magnetic field component perpendicular to the substrate (wafer) surface is generally known. In recent years, however, in addition to this, it is parallel to the substrate (wafer) surface. Vertical Hall elements that detect magnetic field components have also been studied. Since this vertical Hall element has the feature that two elements having different phase differences can be integrated on one chip, according to such a Hall element, the two vertical Hall elements are formed at an angle of “90 °”. By arranging in the position, it is possible to realize a rotation sensor or the like that can obtain a linear output in an angle range of “0 to 360 (°)”. And as such a vertical Hall element, what is described, for example in patent documents 1 is known. Hereinafter, an example of the vertical Hall element will be described with reference to FIG. 6A is a plan view of the Hall element, FIG. 6B is a sectional view taken along line L1-L1 in FIG. 6A, and FIG. 6C is FIG. It is sectional drawing along the L2-L2 line of (a).

  As shown in FIGS. 6A to 6C, this Hall element is formed on a semiconductor substrate (epitaxial substrate) in which an epitaxial layer is formed on an appropriate substrate. Specifically, the Hall element includes a semiconductor layer (P-type substrate) 21 made of, for example, P-type silicon, and a buried layer BL formed in such a manner that an N-type conductive impurity is introduced into the surface. In addition, the semiconductor region 22 made of N-type silicon formed by epitaxial growth is further formed thereon. The buried layer BL functions as a lower electrode, and its impurity concentration is set higher than that of the semiconductor region 22.

The semiconductor region 22 is formed with, for example, a P-type diffusion layer (P-type diffusion separation wall) 24 that is connected to the semiconductor layer 21 so as to isolate the Hall element from other surrounding elements. ing. Then, in the region (active region) surrounded by the diffusion layer 24 on the surface of the semiconductor region 22, the contact region (N ⁺ diffusion layer is formed in such a manner that the impurity concentration (N type) on the surface is selectively increased. ) 23a to 23e are formed, and good ohmic contacts are formed between these contact regions 23a to 23e and the electrodes (wirings) disposed there. The contact regions 23a to 23e are electrically connected to terminals S, G1, G2, V1, and V2, respectively, through respective electrodes (wirings) disposed there.

  In addition, as shown in FIG. 6A, the region (active region) surrounded by the diffusion layer 24 is formed by a P-type diffusion layer (P-type diffusion separation wall) 24a through pn junction isolation by each diffusion layer. And 24b are divided into regions 22a to 22c that are separated from each other. And as FIG.6 (c) shows, in these area | regions 22a-22c, the area | region divided electrically also in the inside of a board | substrate is formed.

  More specifically, in these regions, the contact regions 23a, 23d and 23e are formed in the region (element region) 22a, the contact region 23b is formed in the region 22b, and the contact region 23c is formed in the region 22c. The contact region 23a located in the center of these is sandwiched between both the contact regions 23b and 23c and the contact regions 23d and 23e orthogonal to the contact regions.

  In the Hall element having the above structure, a region (a region indicated by a one-dot chain line in the drawing) that is located in the region of the region 22a that is electrically partitioned inside the substrate and sandwiched between the contact regions 23d and 23e. This is a so-called magnetic detection unit (hole plate) HP. That is, in this Hall element, a Hall voltage signal corresponding to the magnetic field applied here is generated between the terminals V1 and V2.

In such a Hall element, for example, when a constant driving current is supplied from the terminal S to the terminal G1 and from the terminal S to the terminal G2, the current is supplied from the contact region 23a formed on the substrate surface to the magnetic detection unit HP. Flows through the buried layer BL to the contact regions 23b and 23c, respectively. That is, in this case, a current mainly including a component perpendicular to the substrate surface (chip surface) flows through the magnetic detection unit HP. For this reason, in the state where this driving current is applied, a magnetic field (for example, a magnetic field indicated by an arrow B in FIG. 6) including a component parallel to the substrate surface (chip surface) is applied to the magnetic detection unit HP of the Hall element. If so, a Hall voltage corresponding to the magnetic field is generated between the terminal V1 and the terminal V2 by the Hall effect described above. Accordingly, by detecting the generated Hall voltage signal through these terminals V1 and V2, the magnetic field component to be detected based on the relational expression (A), that is, the surface (chip surface) of the substrate used for the Hall element. Therefore, a magnetic field component parallel to is required. In this Hall element, the dimension D shown in FIG. 6A corresponds to the thickness of the magnetic detection part (Hall plate) (“D” in the relational expression (A)). In addition, the direction in which the drive current flows in the Hall element is arbitrary, and the magnetic field (magnetism) can be detected with the direction of the drive current being reversed.
Japanese Patent Laid-Open No. 1-251763

  By the way, the sensitivity of such a vertical Hall element, that is, the magnitude of the voltage (Hall voltage) output with respect to the applied magnetic field of a predetermined magnitude, varies somewhat between the elements. For example, it varies from device to device due to differences in manufacturing conditions. In addition, the temperature dependence of element sensitivity also varies from element to element.

  Usually, it is not preferable that the sensitivity varies between elements. In particular, in a magnetic sensor (rotation detection device) in which two vertical Hall elements are arranged on the same substrate so as to form an angle of “90 °”, the sensitivity of these two vertical Hall elements should be equalized. Will be required. For this reason, in a vertical Hall element, correction is generally performed by a circuit to suppress this. Specifically, for example, as described in JP-T-2001-523429, the drive current supplied to the magnetic detection unit (Hall plate) and the gain of an amplifier (amplifier) provided for amplifying the Hall voltage signal ( (Amplification factor) is adjusted for each element.

  However, in the conventional vertical Hall element as shown in FIG. 6, in order to implement these, a variable gain amplifier, a variable output power supply circuit and the like are required, and a circuit provided in the Hall element. Specifically, signal processing circuits (for example, arithmetic circuits and amplifiers) and drive circuits (for example, driver circuits and power supply circuits) have been complicated.

  The present invention has been made in view of such circumstances, and has a structure capable of adjusting sensitivity as a magnetic detection element more easily and accurately, and can simplify the circuit related to the Hall element. An object of the present invention is to provide a mold Hall element and a magnetic detection sensitivity adjusting method thereof.

In order to achieve such an object, according to the first aspect of the present invention, in the state in which a current containing a component perpendicular to the surface of the substrate is supplied to the magnetic detection portion in the semiconductor substrate, the surface of the substrate is against this current. as a vertical Hall element that outputs a Hall voltage signal corresponding to the magnetic field component which is the applied when parallel magnetic field component is applied to the in the semiconductor substrate, as part of those the Hall element, the semiconductor substrate One or a plurality of electrodes made of a conductive film material embedded in a trench formed in the substrate is provided, and the potential of the electrode is changed through a width change of a depletion layer formed between the electrode and the substrate. Accordingly, the magnetic detection unit has a variable shape.

  Hereinafter, an embodiment in which a vertical Hall element and a magnetic detection sensitivity adjusting method according to the present invention are embodied will be described with reference to FIGS. The Hall element according to this embodiment is also a vertical Hall element that detects a magnetic field component parallel to the substrate (wafer) surface, like the Hall element illustrated in FIG. However, here, a case where the present invention is applied to a vertical Hall element formed on a substrate of a single conductivity type instead of an epitaxial substrate (see FIG. 6) will be described.

  First, the structure of this vertical Hall element will be described in detail with reference to FIG. In FIG. 1, (a) is a plan view showing the planar structure of the vertical Hall element, (b) is a cross-sectional view taken along line L1-L1 in (a), and (c) is (a). It is sectional drawing along the L2-L2 line | wire in the inside.

  As shown in FIGS. 1A to 1C, this Hall element is formed, for example, on a P-type silicon substrate (P-sub), that is, on a semiconductor substrate having a single conductivity type. Specifically, the Hall element is mainly configured to include a semiconductor layer 11 made of, for example, P-type silicon, and an N-type semiconductor region (N well) 12. Among these, the semiconductor region 12 has a concentration distribution in which, for example, an N-type conductivity impurity is introduced from the surface of the substrate, and as a so-called diffusion layer (well), the concentration gradually decreases from the substrate surface to the back surface side. It is formed with.

Also in this Hall element, similarly to the Hall element illustrated in FIG. 6, the semiconductor layer 11 has, for example, a P-type diffusion layer (P type) in order to isolate the Hall element from other surrounding elements. Mold diffusion separation wall) 14 is formed. In the region (active region) surrounded by the diffusion layer 14 on the surface of the semiconductor region 12, the contact region (N ⁺ diffusion layer is formed in such a manner that the impurity concentration (N type) on the surface is selectively increased. ) 13a to 13e are formed. As a result, a good ohmic contact is formed between each of these contact regions and the electrode (wiring) disposed there. Also in this case, these contact regions 13a to 13e are electrically connected to terminals S, G1, G2, V1, and V2, respectively, via respective electrodes (wirings) disposed there. Here, the contact regions 13b and 13c form a pair of the contact region 13a and supply a current into the substrate, that is, a current supply pair. On the other hand, the contact regions 13d and 13e have a voltage output pair. It corresponds to (the part that outputs the Hall voltage signal).

  Also in this case, as shown in FIG. 1A, the region surrounded by the diffusion layer 14 (active region) is a P-type diffusion layer (P-type diffusion separation wall) through pn junction isolation by each diffusion layer. ) 14a and 14b are divided into regions 12a-12c separating each other. However, in this embodiment, electrodes ED1 and ED2 made of P-type diffusion layers (wells) are further provided. As shown in FIG. 1 (c), the regions 12a to 12c are electrically partitioned even inside the substrate by these diffusion layers. Specifically, these diffusion layers (diffusion layers 14a and 14b, and electrodes ED1 and ED2) all have a diffusion depth shallower than that of the semiconductor region 12, and selectively narrow the vicinity of the bottom surface of the semiconductor region 12 so that current paths are formed. Is forming.

  In these regions as well, the contact regions 13a, 13d and 13e are formed in the region (element region) 12a, the contact regions 13b are formed in the region 12b, and the contacts are formed in the region 12c, similarly to the Hall element illustrated in FIG. Regions 13c are respectively formed. The contact region 13a located at the center of these is sandwiched between both the contact regions 13b and 13c and the contact regions 13d and 13e perpendicular to the contact regions.

  Also in this Hall element, a region (region indicated by a one-dot chain line in the drawing) in a region electrically partitioned inside the substrate of the region 12a (a region indicated by a one-dot chain line in the figure) is a so-called region. It becomes a magnetic detection part (hole plate) HP. However, in this embodiment, the electrodes ED1 and ED2 are further provided as part of the Hall element inside the substrate in the region 12a. Thus, the shape of the magnetic detection unit HP is variable according to the potentials of the electrodes ED1 and ED2. Specifically, for example, if the electrodes ED1 and ED2 are set to a potential lower than that of the semiconductor region 12 (for example, a negative bias is applied), a depletion layer formed between these electrodes and the semiconductor region 12 extends (the width of the depletion layer). 1), the thickness (corresponding to “D” in the relational expression (A)) of the magnetic detection part HP shown as the dimension D in FIG. 1A is substantially reduced. In this embodiment, the magnetic detector HP (length, thickness, width, etc.) is deformed by utilizing the change in the width of the depletion layer accompanying the change in potential of the electrodes ED1 and ED2, and the relational expression (A ) To adjust the magnetic detection sensitivity of the Hall element. Specifically, the magnetic detection sensitivity of the Hall element is adjusted (variably set) as desired by setting the potentials of the electrodes ED1 and ED2 as desired using the variable voltage source VE shown in FIG. .

  Thus, in this embodiment, the magnetic detection sensitivity of the Hall element is accurately adjusted according to the relational expression (A). For this reason, it is possible to limit the correction in the circuit (the circuit for sensitivity correction) to a smaller range (or to eliminate correction by the circuit itself), and to simplify the circuit related to the Hall element. Become.

  Although not shown here, the Hall element has a CMOS (complementary MOS) circuit in which the above substrate (semiconductor substrate including the semiconductor layer 11 and the like) is grounded as a peripheral circuit. It is integrated on one chip.

  Next, an example of the operation of the vertical Hall element having the above structure, that is, one aspect of magnetic detection by the Hall element will be described. Magnetic detection by such a vertical Hall element is basically performed in the same manner as in the case of the Hall element shown in FIG.

That is, when a constant drive current is passed from the terminal S to the terminal G1 and from the terminal S to the terminal G2, the current flows from the contact region 13a formed on the substrate surface to the magnetic detection unit HP and the electrodes ED1 and ED2. And through the diffusion layers 14a and 14b to the contact regions 13b and 13c, respectively. Also in this case, since a current including a component perpendicular to the substrate surface (chip surface) flows through the magnetic detection unit HP, a magnetic field including a component parallel to the substrate surface (for example, indicated by an arrow B in FIG. 1). when the magnetic field) is applied to the magnetic detector HP, the Hall voltage V _H corresponding to the magnetic field between the terminal V1 and the terminal V2 is generated. Therefore, by detecting the generated Hall voltage signal through these terminals V1 and V2, the magnetic field component to be detected based on the relational expression (A), that is, the surface (chip surface) of the substrate used for the Hall element. Therefore, a magnetic field component parallel to is required. Incidentally, in this Hall element, the dimensions D and w in FIG. 1A correspond to the thickness and width (“D” and “w” in the relational expression (A)) of the magnetic detection part (Hall plate). Each corresponds. Also in this Hall element, the direction of the drive current is arbitrary. For example, the magnetic field (magnetism) can be detected with the direction of the drive current reversed.

  Next, a method for manufacturing the vertical Hall element will be described in detail with reference to FIGS. 2A to 2C and FIGS. 3A to 3B are sectional views corresponding to the sectional view of FIG. 1C, and are the same as the elements shown in FIG. These elements are denoted by the same reference numerals. Further, here, a CMOS circuit (circuit part) as a peripheral circuit not shown in FIG. 1 is shown again, and a manufacturing method for manufacturing the Hall element (Hall element part) simultaneously with the formation of the circuit is shown. explain.

  In this manufacturing, first, as shown in FIG. 2A, for example, a substrate (semiconductor layer 11) made of P-type silicon having a (100) plane as a cut surface is prepared. Then, as shown in FIG. 2B, after performing ion implantation of N-type impurities such as phosphorus on the surface of the substrate (semiconductor layer 11) through an appropriate mask patterned by photolithography, for example. Then, an appropriate heat treatment is performed to form the N-type semiconductor regions 12 and C12 as diffusion layers (N wells).

  Then, as shown in FIG. 2C, ion implantation of a P-type impurity made of, for example, boron (boron) or the like is performed at a desired location through an appropriate mask patterned by, for example, photolithography. Then, an appropriate heat treatment is performed to form P-type diffusion layers 14 and 14a and 14b, electrodes ED1 and ED2, and diffusion layer C13 (both are P wells). At this time, the depths of the electrodes ED1 and ED2 may be set to be shallower than at least the semiconductor region 12 in a range where the parasitic transistors (bipolar transistors including the semiconductor layer 11 and the semiconductor region 12 and the electrodes ED1 and ED2) do not operate. desirable.

  Further, in order to obtain the structure shown in FIG. 3A, a field oxide film (LOCOS oxide film) CL1 having a LOCOS structure is selectively formed at a desired location by, for example, a well-known selective oxidation method. Subsequently, gate insulating films I1a to I1c made of silicon oxide or the like are formed by, for example, thermal oxidation. Thereafter, an N-type impurity made of, for example, arsenic, and a P-type impurity made of, for example, boron (boron) or the like are implanted into a desired portion through an appropriate mask patterned by, for example, photolithography, to thereby set the threshold of the CMOS circuit. A value adjusting diffusion layer (not shown) is formed, and gate electrodes G1a to G1c made of, for example, polycrystalline silicon are formed on the gate insulating films I1a to I1c, respectively. Specifically, when forming the gate electrodes G1a to G1c, a polycrystalline silicon film is formed by, for example, LP-CVD (low pressure chemical vapor deposition) and, for example, conductivity type such as phosphorus (P) is formed by thermal diffusion. Impurities are added to the formed polycrystalline silicon film. Then, the polycrystalline silicon film is selectively etched to form the gate electrodes G1a to G1c at desired locations.

  Next, ion implantation of, for example, an N-type impurity made of, for example, arsenic and a P-type impurity made of, for example, boron (boron) or the like is performed on a desired portion through an appropriate mask patterned by, for example, photolithography. Then, an appropriate heat treatment is applied thereto, and as shown in FIG. 3B, contact regions 13a to 13e (here, only contact regions 13a to 13c are shown for convenience) and diffusion layers (source / drain) C13a to C13f is formed. The diffusion layers C13a to C13f can also be formed in a self-aligned manner using the LOCOS oxide film CL1 or the gate electrodes G1a to G1c as a mask. At this time, sidewalls, silicide, and the like are also formed as necessary.

  Then, an interlayer insulating film is further formed on the substrate, a contact hole is formed at a desired location of the insulating film, and subsequently, a wiring material is formed, patterned, etc. The vertical Hall element and its peripheral circuit shown in FIG. 1 are completed.

  As described above, in the manufacturing method of the vertical Hall element according to this embodiment, the Hall element is manufactured in the form of sharing the manufacturing process of the CMOS circuit as the peripheral circuit. As a result, the number of manufacturing steps of the Hall element can be greatly reduced.

As described above, according to the vertical Hall element and the magnetic detection sensitivity adjusting method according to this embodiment, the following excellent effects can be obtained.
(1) For a vertical Hall element, electrodes ED1 and ED2 made of a P-type diffusion layer are provided in the substrate as a part of the Hall element, and between the electrodes ED1 and ED2 and the N-type semiconductor region 12 The structure in which the shape of the magnetic detection part HP is made variable according to the potentials of the electrodes ED1 and ED2 through the change in the width of the depletion layer formed in FIG. As a result, it is possible to limit the correction in the circuit to a smaller range (or to eliminate the correction by the circuit itself), and to simplify the circuit related to the Hall element.

  (2) Apart from the electrodes ED1 and ED2 that make the shape of the magnetic detection unit HP variable, the structure further includes separation walls (diffusion layers 14a and 14b) that electrically partition the magnetic detection unit HP in the substrate. Thereby, it becomes possible to make these electrodes and the separation wall have different potentials, and even if the diffusion layers 14a and 14b are in a structure in which the substrate is dropped to the ground side potential of the peripheral circuit (CMOS circuit), Sensitivity adjustment with a high degree of freedom is possible through the electrodes ED1 and ED2.

  (3) The electrodes ED1 and ED2 made of diffusion layers formed by adding conductive impurities to the semiconductor substrate are adopted as the electrodes for changing the shape of the magnetic detection part HP. Therefore, it can be easily formed by a normal CMOS process.

  (4) The magnetic detection part HP in the semiconductor substrate has a structure formed with a concentration distribution of conductive impurities so that the concentration gradually decreases from the front surface to the back surface of the substrate. Thereby, the extension of the depletion layer formed between the magnetic detection unit HP and the electrodes ED1 and ED2 becomes longer as it proceeds from the substrate surface to the back surface side. For this reason, the shape of the magnetic detection unit HP can be changed to a deeper position without increasing the depth for forming the electrodes ED1 and ED2, and thus the sensitivity adjustment described above can be performed more efficiently and accurately. To be done.

  (5) When adjusting the magnetic detection sensitivity of such a Hall element, electrodes ED1 and ED2 are provided as part of the Hall element in the semiconductor substrate, and the voltage applied through the electrodes ED1 and ED2 is adjusted. The width of the depletion layer formed between the electrodes ED1 and ED2 and the semiconductor region 12 is variable, so that the shape of the magnetic detector HP is variably set. This makes it possible to limit the correction in the circuit (the circuit for sensitivity correction) to a smaller range (or eliminate the correction itself by the circuit), and thus simplify the circuit related to the Hall element. It becomes like this.

  (6) Since the Hall element is manufactured while sharing the manufacturing process of the CMOS circuit as the peripheral circuit, the number of manufacturing processes of the Hall element can be greatly reduced.

The embodiment described above may be modified as follows.
In the above embodiment, the CMOS circuit is employed as the peripheral circuit. However, the present invention is not limited to this. For example, a bipolar circuit may be employed.

  In the above embodiment, the Hall element integrated on one chip together with the peripheral circuit is assumed. However, the present invention is not limited to this, and the circuit related to the Hall element is provided as another chip. Also good.

  In the above embodiment, the sensitivity adjustment is performed by changing and adjusting the thickness of the magnetic detection unit HP in consideration of the thickness (“D” in the relational expression (A)). Assumed. However, depending on the concentration profiles of the electrodes ED1 and ED2 and the semiconductor region 12 made of a diffusion layer, the depletion layer formed between the electrodes ED1 and ED2 and the semiconductor region 12 extends in the vertical direction (direction perpendicular to the substrate surface). It can also be stretched. That is, the sensitivity can be adjusted by adjusting the length of the magnetic detection unit HP (“L” in the relational expression (A)).

  The concentration profile of the magnetic detection unit HP is basically arbitrary. For example, the concentration profile (concentration distribution) is set such that the bottom portion has the highest concentration and gradually decreases toward the substrate surface side. Also good. In such a case, when a current is supplied (or taken out) from the substrate surface to the magnetic detection unit HP, the vicinity of the current supply port (or the outlet) on the surface of the substrate (near the contact region 13a) is more active. As a result, the sensitivity adjustment described above is performed more efficiently and accurately.

  The concentration profile of the electrodes ED1 and ED2 made of a diffusion layer is basically arbitrary, and may be formed to have a concentration peak (maximum concentration) at the bottom of the diffusion layer, for example.

The depths of the electrodes ED1 and ED2 are basically arbitrary, and may be formed deeper by using, for example, a high acceleration ion implantation apparatus as shown in FIG.
In addition, when a trench is formed in the substrate, such as when STI (trench isolation) is adopted as the separation wall instead of the diffusion layers 14 and 14a and 14b, the inner wall of the trench is prevented in order to prevent carrier traps due to the damage layer. In some cases, a diffusion layer is formed. In such a case, the diffusion layer on the inner wall of the trench may be used as the electrodes ED1 and ED2.

  Further, as the electrodes ED1 and ED2, those other than the diffusion layer can be appropriately employed. For example, as shown in FIG. 5, the electrodes ED1 and ED2 may be made of a conductive film material embedded in the trench T formed in the substrate, similarly to the effect (3). Or the effect according to it can be acquired. In this case, if a conductive film material made of polycrystalline silicon to which conductive impurities are added is used, it is widely used in semiconductor devices, for example, by well-known CVD (chemical vapor deposition). Thus, it is possible to easily form a highly reliable electrode.

  After all, these electrodes ED1 and ED2 are provided as a part of the Hall element in the substrate to form a depletion layer between the substrate and the magnetic detection unit (Hall plate through the width change of the depletion layer). It is sufficient if the shape of) is variable.

  In the above embodiment, two current supply pairs (contact region 13a and contact region 13b, contact region 13a and contact region 13c) are arranged symmetrically with respect to the voltage output pair (contact regions 13d and 13e). The case where the present invention is applied to the vertical Hall element of the type is mentioned. However, this is merely an example. For other types of vertical Hall elements, for example, a vertical Hall element composed of a pair of current supply pairs (for example, only one of the two pairs of current supply pairs) is used. In contrast, the present invention can be similarly applied to a vertical Hall element including a buried layer BL formed on an epitaxial substrate as shown in FIG. Further, the present invention can be similarly applied to a structure in which the conductivity type of each element constituting the Hall element is switched, that is, a structure in which the P type and the N type are switched.

  In the above embodiment, Si (silicon) is used as the substrate material, but an optimal material can be selected according to the manufacturing process, structural conditions, and the like. That is, for example, compound semiconductor materials such as GaAs, InSb, InAs, and SiC, and other semiconductor materials such as Ge (germanium) can also be used as the material of the substrate. In particular, GaAs and InAs are materials having excellent temperature characteristics, and are effective in increasing the sensitivity of the Hall element.

1A is a plan view showing an outline of the element structure of an embodiment of the vertical Hall element and its magnetic detection sensitivity adjusting method according to the present invention, and FIG. Sectional drawing along, (c) is sectional drawing along the L2-L2 line in (a). (A)-(c) is sectional drawing which shows the manufacturing process about the manufacturing method of the vertical Hall element based on the embodiment. (A) And (b) is sectional drawing which shows the manufacturing process about the manufacturing method of the vertical Hall element concerning the embodiment. (A)-(c) is the top view and sectional drawing which show typically the structure of the same Hall element about the modification of the vertical Hall element which concerns on the same embodiment. About another modification of the vertical Hall element concerning the embodiment, (a)-(c) is a top view and sectional view showing typically the structure of the Hall element. As for an example of a conventional vertical Hall element, (a) is a plan view showing an outline of the element structure, (b) is a cross-sectional view taken along line L1-L1 in (a), and (c) is (a). Sectional drawing along the L2-L2 line | wire in the inside.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Semiconductor layer (semiconductor substrate), 12 ... Semiconductor region, 12a-12c ... area | region, 13a-13e ... Contact region (N ⁺ diffusion layer), 14, 14a, 14b ... Diffusion layer, BL ... Buried layer, C10 ... Circuit (peripheral circuit), C12 ... semiconductor region, C13 ... diffusion layer, C13a to C13f ... diffusion layer (source / drain layer), CL1 ... LOCOS oxide film (field oxide film), ED1, ED2 ... electrode, G1a-G1c ... Gate electrode, HP ... magnetic detector (Hall plate), I1a to I1c ... gate insulating film, T ... trench, VE ... variable voltage source.

Claims (3)

A magnetic field applied when a magnetic field component parallel to the surface of the substrate is applied to the magnetic detection unit in the semiconductor substrate in a state where a current including a component perpendicular to the surface of the substrate is supplied to the magnetic detection unit. In the vertical Hall element that outputs the Hall voltage signal according to the component,
In the semiconductor substrate, as part of those the Hall element, the semiconductor substrate One or more electrodes made of internally embedded conductive film material of the formed trench is provided Rutotomoni, and the electrode wherein A vertical Hall element, wherein the shape of the magnetic detection unit is made variable according to the potential of the electrode through a change in the width of a depletion layer formed between the substrate and the substrate. The Hall element is integrated in one chip together with the CMOS circuit as a peripheral circuit, and the separation wall that electrically partitions the magnetic detection part in the substrate is dropped to the ground side potential of the CMOS circuit in the substrate. The vertical Hall element according to claim 1. 3. The vertical Hall element according to claim 1, wherein the conductive film material is made of polycrystalline silicon to which a conductive impurity is added .

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