JP4772089B2 - Multilayer printed wiring board and method for producing multilayer printed wiring board - Google Patents

Description

The present invention relates to a build-up multilayer printed wiring board, and more particularly to a multilayer printed wiring board containing electronic components such as IC chips and a method for manufacturing the multilayer printed wiring board.

Conventionally, an IC chip and a printed wiring board are electrically connected using a mounting method such as wire bonding, TAB (Tape Automated Bonding), or flip chip bonding.
In wire bonding, an IC chip is die-bonded to a printed wiring board with an adhesive, the pad of the printed wiring board and the pad of the IC chip are connected with a wire such as a gold wire, and then the IC chip and the wire are protected. In addition, sealing with a resin such as a thermosetting resin or a thermoplastic resin was performed.

In TAB, a tape on which many conductors called leads are formed is used. The bumps of the IC chip and the pads of the printed wiring board are collectively connected by solder or the like and then sealed with resin.
In flip chip bonding, the IC chip and the pad portion of the printed wiring board are connected via bumps, and the gap between the bumps is filled with resin. Moreover, the electronic component mounted by these methods was driven through the printed wiring board.

As described above, in these mounting methods, the IC chip and the printed wiring board are electrically connected via the connecting lead parts (wires, leads, bumps). For this reason, if each of these lead parts is cut or corroded, the connection between the IC chip and the printed wiring board may be interrupted, or the IC chip may malfunction. It was.

Also, in each mounting method, sealing is performed with a resin such as an epoxy resin resin to protect the IC chip and the lead component, and if bubbles are contained when filling the resin, the bubbles As a starting point, destruction of lead parts, corrosion of IC pads, and deterioration of reliability may occur. In addition, when sealing with thermoplastic resin, etc., it is necessary to create a resin-filled plunger, mold, etc. according to each part. With sealing with thermosetting resin, materials such as lead parts, solder resist, etc. Since the resin must be selected in consideration of the above, it has been a cause of high cost.

In recent years, in order to solve such problems, a multilayer printed wiring board in which a semiconductor element such as an IC chip is built in or stored in a substrate has been disclosed.
Patent Document 1 discloses a multilayer printed wiring board in which a semiconductor element in which a stud bump is formed on a die pad is embedded in a substrate and the stud bump and an upper conductor circuit are electrically connected via a via hole. .

However, in this multilayer printed wiring board, the stud bump shape is onion-like, and due to variations in its height, the interlayer insulating layer formed on the substrate is not uniform in thickness. The surface may not be flat, and in this case, a connection failure may occur in the electrical connection through the via hole.
In addition, this multilayer printed wiring board has a poor productivity because it cannot form via hole openings at a time due to its structure.

Patent Document 2 discloses a multilayer wiring board in which a semiconductor element is housed in a ceramic substrate and the semiconductor element is electrically connected to a conductor circuit by a flip chip.
A ceramic substrate made of alumina, aluminum nitride, or the like used in this multilayer wiring board is inferior in external formability, so that the semiconductor element does not fit well. For this reason, the pad height of the semiconductor element becomes non-uniform, and as a result, connection failure may occur between the pad and the conductor circuit.

Patent Document 3 discloses a multilayer printed wiring board in which a gap is formed in a substrate and a semiconductor element is accommodated in the gap.
However, even in such a multilayer printed wiring board incorporating a semiconductor element, when the semiconductor element and a conductor circuit are connected via lead parts such as solder, TAB, wire bonding, etc., the above-mentioned problems Could not be resolved.
In addition, when a semiconductor element is stored in the gap of the substrate, if there is a gap between the semiconductor element and the substrate, the semiconductor element is likely to be misaligned, leading to a decrease in connection reliability. was there.

In addition, the present inventors have previously disclosed a multilayer printed wiring board that can be directly electrically connected to an electronic component such as an IC chip without using a lead component. Alternatively, an IC chip or the like is built in or accommodated in the counterbore part (hereinafter simply referred to as both together), and an interlayer resin insulating layer and a conductor circuit are laminated on the substrate, and the IC chip and the conductor circuit are interposed. In addition, a multilayer printed wiring board was proposed in which the upper and lower conductor circuits via the interlayer resin insulation layer were electrically connected via via holes.

In such a multilayer printed wiring board incorporating an IC chip or the like, since lead parts and sealing resin are not used for the connection between the IC chip and the multilayer printed wiring board, the connection reliability is excellent. Since an IC chip can be mounted when manufacturing a multilayer printed wiring board, the cost is reduced.
In such a multilayer printed wiring board, since it is necessary to incorporate an IC chip or the like in the substrate, a resin substrate excellent in external formability is used as the substrate material.
Therefore, when the interlayer resin insulation layer is formed on the substrate, the formation temperature thereof cannot be made higher than the temperature at which the resin substrate is softened. It is required that the formed interlayer resin insulating layer has excellent formability and workability, and has excellent shape retention and insulating properties.

In conventional printed wiring boards, photosensitive polyimide resin has been disclosed as an interlayer resin insulation layer material that has excellent heat resistance and insulation properties, and excellent opening properties when forming openings for via holes. It is disclosed in Document 4, Patent Document 5, Patent Document 6, Patent Document 7, Patent Document 8, and the like.

JP-A-9-321408 JP-A-10-256429 Japanese Patent Laid-Open No. 11-126978 JP 59-151498 A JP-A-5-304362 JP-A-5-304367 JP-A-6-132409 JP-A-8-23166

However, in these multilayer printed wiring boards, since the substrate material is ceramic, alumina or glass substrate, even if the interlayer resin insulation layer is formed by curing at a high curing temperature of 350 ° C. or higher, the substrate softens. In the multilayer printed wiring board using the resin substrate, when the conventionally known photosensitive polyimide resin is used as the interlayer resin insulating layer material, the curing temperature is too high. If the resin substrate is softened, melts, or is severely carbonized, it may be carbonized. On the other hand, if the curing temperature is lowered, the photosensitive polyimide resin is not sufficiently cured and the interlayer resin insulation layer is formed. However, it was inferior in shape retainability and the like and did not have sufficient connection reliability.

Therefore, as a result of further studies to solve these problems, the present inventors have found that a photosensitive cardo type polymer is suitable as a material for an interlayer resin insulating layer, and completed the present invention. The cured product of the photosensitive cardo type polymer has a rigid chemical structure and a high crosslink density, so that it has excellent shape retention, and even when cured at a curing temperature of around 200 ° C., the glass transition point is 250- Since it is maintained at 350 ° C., it has excellent heat resistance and the curing temperature does not rise to 350 ° C. or higher, so that it does not adversely affect the resin substrate. In addition, cardotype polyimide resin to which photosensitivity is imparted by (meth) acrylate formation, etc. has good resolution, excellent shape retention and film thickness retention at the time of forming via hole openings, and after exposure / development processing, Since no resin residue is generated at the bottom of the hole opening, the electrical connection and reliability through the via hole are excellent.

In the present invention, an interlayer resin insulating layer and a conductor circuit are sequentially formed on a substrate in which an electronic component is built-in or accommodated, and the pad and conductor circuit of the electronic component and the upper and lower conductor circuits are connected via holes. A multilayer printed wiring board connected to each other,
A multilayer printed wiring board, wherein a via hole connecting the pad of the electronic component and the conductor circuit is formed in an interlayer resin insulating layer made of a photosensitive cardo type polymer.

In the multilayer printed wiring board of the present invention, the photosensitive cardo type polymer is preferably a photosensitive cardo type polyimide resin.
The photosensitive cardo polymer preferably has a glass transition temperature of 250 to 300 ° C.

Further, it is desirable that a transition layer composed of a metal film and a plating layer is formed on the pad portion of the electronic component, and the electronic component and the conductor circuit are connected via the transition layer and a via hole.
The via hole preferably has a field via structure, a roughened surface is formed on the surface of the interlayer resin insulating layer, and a conductor circuit and a field via structure are formed on the interlayer resin insulating layer having the roughened surface. It is desirable that a via hole having

Further, according to the method of manufacturing a multilayer printed wiring board of the present invention, an interlayer resin insulating layer and a conductor circuit are sequentially formed on a substrate in which an electronic component is incorporated or accommodated, and the electronic component pad and the conductor circuit, and A method for producing a multilayer printed wiring board in which upper and lower conductor circuits are connected via via holes,
It includes at least the following steps (1) to (4).
(1) A step of applying a photosensitive cardo type polymer solution onto a substrate in which the electronic component is built-in or stored;
(2) forming a semi-cured layer of the photosensitive cardo type polymer;
(3) After placing a photo-etching mask on the semi-cured layer of the photosensitive cardo polymer, the via-hole opening is formed by exposing and developing the semi-cured layer of the photosensitive cardo polymer. Forming, and
(4) A step of forming an interlayer resin insulating layer by main-curing the semi-cured layer of the photosensitive cardo type polymer in which the opening for the via hole is formed.

In the production method of the present invention, the photosensitive cardo type polymer is preferably a photosensitive cardo type polyimide resin.
Further, it is desirable that the fully cured photosensitive cardo polymer layer has a glass transition temperature of 250 to 300 ° C.
Moreover, in the manufacturing method of this invention, it is desirable to further include the process of forming the via hole and the metal film for conductor circuits by sputtering on the formed interlayer resin insulation layer.

Moreover, in the manufacturing method of this invention, before apply | coating the solution of a photosensitive cardo type polymer, a transition layer can be formed in the pad part of an electronic component by performing the following process (a)-(e). desirable.
(A) forming a metal film on a substrate in which an electronic component is built-in or stored;
(B) a step of attaching a photosensitive dry film on the metal film;
(C) forming a plating resist by subjecting the photosensitive dry film to exposure and development; and
(D) forming a plating layer on the plating resist non-forming portion;
(E) A step of forming the transition layer by removing the plating resist and the metal film existing under the plating resist.

Moreover, in the manufacturing method of this invention, before apply | coating the solution of a photosensitive card | curd type polymer, a transition layer may be formed in the pad part of an electronic component by performing the process of the following (a)-(e). desirable.
(A) forming a metal film on a substrate in which an electronic component is built-in or stored;
(B) forming a plating layer on the metal film;
(C) a step of attaching a photosensitive dry film on the plating layer;
(D) a step of forming an etching resist by exposing and developing the photosensitive dry film;
(E) A step of forming the transition layer by removing the metal film and the plating layer under the etching resist non-forming portion by an etching process.

Since the multilayer printed wiring board of the present invention has the above-described configuration, it is not necessary to use a lead component or a sealing resin when connecting the electronic component and the printed wiring board, and the interlayer resin insulation layer is photosensitive. Since it is made of a cardo type polymer, it has excellent shape retention and has a via hole opening of a desired shape, and is excellent in electrical connectivity and reliability.

In addition, the multilayer printed wiring board manufacturing method of the present invention forms an interlayer resin insulation layer using a photosensitive cardo type polymer, and therefore has a relatively low curing temperature, a high crosslinking density, and shape retention and heat resistance. An excellent interlayer resin insulation layer can be formed, and the substrate is not softened or dissolved when the interlayer resin insulation layer is formed.
Further, since the photosensitive cardo type polymer used in the production method of the present invention is excellent in opening property by exposure / development processing, there is no resin residue in the opening for via hole, and a via hole having a desired shape can be formed. .

In the multilayer printed wiring board of the present invention, an interlayer resin insulating layer and a conductor circuit are sequentially formed on a substrate in which an electronic component is incorporated or accommodated, and the pad and conductor circuit of the electronic component, and upper and lower conductor circuits are formed. Is a multilayer printed wiring board connected via via holes,
A via hole connecting the pad of the electronic component and the conductor circuit is formed in an interlayer resin insulating layer made of a photosensitive cardo type polymer.

According to the multilayer printed wiring board of the present invention, since electronic components such as IC chips are built in the substrate, no lead component or sealing resin is used in the connection between the electronic component and the multilayer printed wiring board. Accordingly, the multilayer printed wiring board is excellent in electrical connectivity and reliability because it eliminates various problems that occur when an IC chip is mounted via a lead component.

In the multilayer printed wiring board of the present invention, the interlayer resin insulation layer is made of a photosensitive cardo type polymer, so that the interlayer resin insulation layer can be formed at a relatively low curing temperature of 150 to 250 ° C. The interlayer resin insulation layer has excellent shape retention and film thickness retention, and the via hole opening provided in the interlayer resin insulation layer has a desired shape. Excellent electrical connectivity and reliability.

The cardo polymer is a general term for polymers having a structure in which a cyclic group is directly bonded to a polymer main chain. The cardo polymer is a bulky substituent perpendicular to the structure, that is, the main chain. Phenomenon such as rotation restraint of the polymer main chain, conformation regulation of the main chain and side chain, inhibition of intermolecular packing, increase in aromaticity due to introduction of aromatic substituents in the side chain, etc. And therefore the glass transition temperature after curing is high.
In addition, the cardo type polymer having such a structure suppresses the mobility of the main chain due to its bulky substituent, and has a high crosslinking density and excellent heat resistance even when cured at less than 300 ° C. Have sex. Further, the bulky substituent inhibits the proximity of the molecular chain and thus has excellent solvent solubility.

The cardo type polymer can be obtained by copolymerizing a cyclic compound having a carbonyl group (ketone, ester, acid anhydride, imide, etc.) with an aromatic compound such as phenol or aniline or a derivative thereof. .

The photosensitive cardo type polymer has photosensitivity among the cardo type polymers having the structure as described above, and specific examples thereof include, for example, a compound represented by the following chemical formula (1),

A compound represented by the following general formula (2):

（式中、Ｒ¹ は、酸素、カルボニル基、テトラフルオロエチレン基、または、単結合を表す。）

(In the formula, R ¹ represents oxygen, a carbonyl group, a tetrafluoroethylene group, or a single bond.)

Examples thereof include photosensitive cardo type polyesters obtained by copolymerizing pyromellitic anhydride and at least one selected from terephthalic acid and acid chlorides thereof.

Moreover, the compound represented by the above general formula (1),
A compound represented by the following general formula (3);

（式中、Ｒ² 、Ｒ³ 、Ｒ⁴ 、Ｒ⁵ は、それぞれ同一または異なって、水素または炭素数１〜５の炭化水素基を表し、Ｒ⁶ は、水素、カルボキシル基または炭素数２〜８のアルコキシカルボニル基を表す。）

Wherein R ² , R ³ , R ⁴ and R ⁵ are the same or different and each represents hydrogen or a hydrocarbon group having 1 to 5 carbon atoms, and R ⁶ represents hydrogen, a carboxyl group or 2 to 2 carbon atoms. 8 represents an alkoxycarbonyl group.)

Examples thereof include photosensitive cardotype polyimides obtained by copolymerizing the compound represented by the general formula (2), pyromellitic anhydride, and at least one selected from terephthalic acid and acid chlorides thereof. It is done.
Among these, a photosensitive cardo type polyimide resin is desirable. This is because even a cured product obtained by curing at a relatively low temperature has a high glass transition temperature.

The glass transition temperature after curing of the photosensitive cardo polymer is preferably 250 to 300 ° C. Since the glass transition temperature in the above range can be achieved by curing the photosensitive cardo type polymer at a curing temperature of around 200 ° C., it adversely affects the resin substrate during the formation of the interlayer resin insulation layer (softening and dissolution of the resin substrate) This is because the formed interlayer resin insulation layer is excellent in shape retention and heat resistance.

In the multilayer printed wiring board, it is desirable that a transition layer is formed on a pad portion of the electronic component.
The transition layer is a conductor layer provided to increase the diameter of the pad disposed on the IC chip, and the purpose of the formation is to eliminate various problems that occur in the IC chip pad described below. It is in.

That is, the opening diameter of the via hole opening is usually 60 to 80 μm, whereas the pad portion of the electronic component has a diameter of about 40 μm. Therefore, when the pad and the via hole are directly connected, In this case, the via hole is displaced due to the small pad diameter, which may cause conduction failure and disconnection. However, by forming the transition layer, the horizontal direction of the transition layer is reduced. The diameter (hereinafter simply referred to as “diameter”) is larger than the diameter of the pad, and the connection with the via hole can be reliably performed.
In addition, when manufacturing the multilayer printed wiring board, an acid, an oxidizing agent, an etching solution, or the like may be used. Therefore, when these acids come into contact with a pad of an electronic component, the discoloration or dissolution of the pad is caused. However, by forming the transition layer, it is possible to prevent the pad layer and the acid or the like from coming into direct contact with each other.

The diameter of the transition layer is not particularly limited, and may be appropriately selected in consideration of the opening diameter of the via hole opening and the like, and is preferably 60 to 80 μm, which is about the same as the opening diameter of the via hole opening.

Examples of the material for the transition layer include copper, chromium, nickel, zinc, gold, silver, tin, and iron.
Among these, the same material as that of the conductor circuit (via hole) formed in the upper layer is desirable. Since the material of the conductor circuit is usually copper, copper is desirable.
The transition layer may be composed of a single layer or may be composed of two or more layers, but is preferably composed of two or more layers.
In particular, when the material of the pad of the IC chip is aluminum, it is preferable that the IC chip pad is composed of two layers of a lower layer made of zinc, chromium or nickel and an upper layer made of copper.

The thickness of the transition layer is preferably 1 to 35 μm. When the thickness of the transition layer exceeds 35 μm, the shape may be an undercut shape, which may cause a decrease in connection reliability between the IC chip and the via hole.
When the transition layer is composed of two or more layers, the lower layer preferably has a thickness of 0.01 to 0.5 μm.
The method of forming the transition layer will be described in detail later when the manufacturing method of the present invention is described.

The multilayer printed wiring board of the present invention will be described below with reference to the drawings.
FIG. 1 is a sectional view schematically showing an example of the multilayer printed wiring board of the present invention.
As shown in FIG. 1, the multilayer printed wiring board 10 includes a resin substrate 30 in which an IC chip 20 is incorporated, an interlayer resin insulation layer 50, and an interlayer resin insulation layer 150. Via hole 60 and conductor circuit 58 are formed in interlayer resin insulation layer 50, and via hole 160 and conductor circuit 158 are formed in interlayer resin insulation layer 150.

The IC chip 20 is covered with a passivation film 22, and an aluminum pad 24 that constitutes an input / output terminal and a positioning mark (not shown) are disposed in the opening of the passivation film 22. A transition layer 38 composed of a metal film 36 and a plating layer 37 is formed on the pad 24.

A solder resist layer 70 is disposed on the interlayer resin insulating layer 150. The conductor circuit 158 under the opening 71 of the solder resist layer 70 is provided with solder bumps 76 for connection to an external substrate (not shown) such as a daughter board or a mother board via a nickel plating layer 72 and a gold plating layer 74. .

In the multilayer printed wiring board 10, the IC chip 20 is built in a resin substrate in advance, and a transition layer 38 is disposed on the pad 24 of the IC chip 20. For this reason, an IC chip and a multilayer printed wiring board can be electrically connected without using a lead component or a sealing resin.

The resin substrate is not particularly limited as long as it is generally used in a printed wiring board. For example, an epoxy resin, a BT resin, a phenol resin, or the like is impregnated with a reinforcing material such as a glass epoxy resin or a core material. Examples thereof include a substrate made of a resin and a substrate in which a prepreg impregnated with an epoxy resin is laminated. Moreover, you may use a double-sided copper clad laminated board, a single-sided board, the resin board which does not have a metal film, a resin film, etc.
The resin substrate and an electronic component such as an IC chip are bonded with an adhesive or the like.

The interlayer resin insulations 50 and 150 are made of the above-described photosensitive cardo type polymer.
The interlayer resin insulation layer preferably has a thickness of 5 to 50 μm, and more preferably 15 to 35 μm. This is because sufficient insulation between the conductor circuits can be ensured and a via hole opening having a desired shape can be formed, so that the connection reliability through the via hole is excellent.

In addition, the multilayer printed wiring board of this invention can be manufactured using the manufacturing method of the multilayer printed wiring board of this invention mentioned later, for example.

Next, the manufacturing method of the multilayer printed wiring board of this invention is demonstrated.
In the method for producing a multilayer printed wiring board according to the present invention, an interlayer resin insulation layer and a conductor circuit are sequentially formed on a substrate in which an electronic component is incorporated or housed, and the pad and conductor circuit of the electronic component are Is a method of manufacturing a multilayer printed wiring board in which the conductor circuit is connected through a via hole,
It includes at least the following steps (1) to (4).
(1) A step of applying a photosensitive cardo type polymer solution onto a substrate in which the electronic component is built-in or stored;
(2) forming a semi-cured layer of the photosensitive cardo type polymer;
(3) After placing a photo-etching mask on the semi-cured layer of the photosensitive cardo polymer, the via-hole opening is formed by exposing and developing the semi-cured layer of the photosensitive cardo polymer. Forming, and
(4) A step of forming an interlayer resin insulating layer by main-curing the semi-cured layer of the photosensitive cardo type polymer in which the opening for the via hole is formed.

According to the method for producing a multilayer printed wiring board of the present invention, since an interlayer resin insulation layer is formed using a photosensitive cardo type polymer, the crosslinking density is high at a relatively low curing temperature (150 to 250 ° C.), and the shape An interlayer resin insulating layer having excellent holding properties and heat resistance can be formed, and the substrate is not softened or dissolved when the interlayer resin insulating layer is formed.
In addition, the photosensitive cardo type polymer used in the production method of the present invention is excellent in opening property by exposure and development processing, and therefore there is no resin residue in the opening for via hole, and a via hole having a desired shape can be formed. .

Furthermore, in the method for manufacturing a multilayer printed wiring board according to the present invention, a multilayer printed wiring board excellent in connection reliability between the pad and the conductor circuit is formed by forming a transition layer on the pad of the IC chip built in the substrate. Can be manufactured.

Here, the steps (1) to (4) described above, that is, the step of forming the interlayer resin insulation layer will be described first, and the entire manufacturing process of the multilayer printed wiring board will be described in detail later.

In the production method of the present invention, when forming an interlayer resin insulation layer, first, a substrate in which an electronic component such as an IC chip is built, or an already lower interlayer resin insulation layer and a conductor circuit are formed at least one layer at a time. A photosensitive cardo polymer solution is applied to the resulting substrate.
The viscosity of the photosensitive cardo type polymer solution is preferably adjusted to 5 to 49 Pa · s. This is because it is easy to apply on the substrate and to form uniformly. The viscosity can be adjusted by diluting with a solvent such as xylene.

The method for applying the photosensitive cardo type polymer solution is not particularly limited as long as the solution can be uniformly applied onto the substrate. For example, the curtain coater method, the roll coater method, and the normal printing. The method of apply | coating using a machine etc. is mentioned.

Next, a semi-cured layer of a photosensitive cardo polymer is formed.
The semi-cured layer is formed by drying the applied photosensitive cardo type polymer at a temperature of 80 to 200 ° C. for 10 to 60 minutes. Here, the semi-cured layer of the photosensitive cardo type polymer refers to a layer of a photo-cured cardo polymer in a semi-cured state or a B stage state that is hardened to some extent but can be dissolved by a solvent or the like.

Next, after placing a photoetching mask on the semi-cured layer of the photosensitive cardo polymer, exposure / development treatment is performed on the semi-cured layer of the photo-sensitive cardo polymer to open a via hole opening. Form.
The exposure / development treatment can be performed, for example, by irradiating ultraviolet rays under a condition of 100 to 800 mj / cm ² and then developing using an organic type or inorganic type developer.

Subsequently, the photosensitive cardo type polymer semi-cured layer in which the opening for via hole is formed is fully cured to form an interlayer resin insulating layer.
The temperature at which the main curing is performed is preferably 150 to 300 ° C. If the temperature is less than 150 ° C., the semi-cured layer of the photosensitive cardo type polymer cannot be sufficiently cured. On the other hand, if the temperature exceeds 300 ° C., the material resin of the IC-embedded substrate may be softened or dissolved. May end up.
Moreover, the desirable glass transition temperature of the interlayer resin insulating layer (mainly cured cardo type polymer layer) formed in the production method of the present invention is 250 to 300 ° C., and by performing the main curing at a temperature in the above range, This is because cross-linking of the polymers proceeds and an interlayer resin insulating layer having the glass transition temperature as described above can be formed.

Further, the main curing may be performed by step cure in which the temperature is increased after being kept for a certain time in each temperature section. This is because the solvent content and moisture remaining in the photosensitive cardo type polymer semi-cured layer can be completely removed. By passing through such a process, the interlayer resin insulation layer which consists of a cardo type polymer excellent in shape maintenance nature and heat resistance can be formed.

Next, the whole manufacturing process of the multilayer printed wiring board of this invention is demonstrated in order of a process, referring FIGS.
(1) First, a substrate (hereinafter also referred to as an IC-embedded substrate) 30 made of glass epoxy resin, BT (bismaleimide triazine) resin or the like in which an electronic component such as an IC chip is built is used as a starting material (FIG. 5 ( A)). The upper part of the IC chip 20 is covered with a passivation film 22, and a pad 24 made of aluminum or the like constituting an input / output terminal is formed in the opening of the passivation film 22.

There is no particular limitation on a method for incorporating an IC chip or the like into the substrate. For example, a concave portion for incorporating an IC chip is formed on one side of the substrate by counterboring, and then the IC chip is fixed to the concave portion through an adhesive material. And a method of forming a through hole for housing an IC chip in a substrate, housing the IC chip in the through hole, and then laminating the substrate and a substrate having no through hole. .

(2) Next, the IC chip is positioned with respect to the substrate by the following method. That is, the positioning marks arranged at the four corners of the IC chip are photographed with a camera, and the positioning of the IC chip is performed by forming positioning marks with the laser at the four corners of the IC built-in substrate with the positioning marks as a reference.

(3) Next, if necessary, a transition layer is formed on the pad formed on the IC chip. The transition layer may be formed as necessary.However, when the transition layer is formed, the transition layer has a diameter larger than the pad diameter, so that there is a displacement between the transition layer and the via hole. It is difficult to connect the pad and the via hole more reliably.

As a specific method for forming the transition layer, a method including the following steps (a) to (e) (hereinafter referred to as a first transition layer forming method) can be used. That is, (a) First, a metal film 36 is formed on the entire surface of the IC-embedded substrate 30 (see FIG. 5B).
The metal film 36 is desirably formed by performing physical vapor deposition such as sputtering. The metal film 36 is formed using, for example, one or more kinds of metals such as chromium, copper, nickel, zinc, gold, tin, and iron. In some cases, two or more metal films 36 may be formed using different metals.

Alternatively, the metal film 36 having two or more layers may be formed by performing electroless plating after sputtering or the like. In this case, it is desirable to form a layer made of chromium, nickel or zinc by sputtering or the like and then form a layer made of copper by electroless plating.
Considering that the material of the conductor circuit formed on the metal film 36 is usually copper, it is desirable that the material of the metal film 36 is also copper, but when the pad 24 of the IC chip 20 is made of aluminum, As described above, forming the metal film 36 made of copper directly on the pad is not preferable because it may cause discoloration of the pad 24 or the like. On the other hand, by forming a layer made of chromium, nickel, or zinc directly on the pad 24 and forming a layer made of copper on the upper layer, discoloration of the pad 24 is prevented and connection reliability with the via hole is improved. The metal film 36 can be made excellent.

When the metal film 36 is formed by sputtering or the like and electroless plating, the thickness of the layer formed by sputtering or the like is preferably 0.01 to 0.5 μm. This is because it is difficult to uniformly form a layer having a thickness exceeding 0.5 μm by physical vapor deposition such as sputtering. Moreover, the thickness of the layer formed by electroless plating is desirably 0.01 to 5.0 μm. If the thickness is less than 0.01 μm, a plating film cannot be formed on the entire surface. If the thickness exceeds 5.0 μm, it may be difficult to remove by etching, or the positioning mark may be buried and the positioning mark may not be recognized. is there. A more desirable range is 0.1 to 1.0 μm.

(B) Next, a photosensitive dry film is affixed on the metal film.
It does not specifically limit as said photosensitive dry film, The commercial item conventionally used in order to form a plating resist can be used.
(C) Next, a mask in which a pattern corresponding to the pad 24 of the IC chip 20 is placed on the photosensitive dry film, and an exposure / development process is performed so that the upper part of the pad 24 is opened. A resist 35 is formed.

(D) Thereafter, a plating layer 37 is formed by plating on the plating resist non-forming portion (see FIG. 6A).
The plating treatment may be electroless plating, electrolytic plating, or a combination of both. Examples of the material of the plating layer 37 include those made of copper, nickel, gold, silver, zinc, iron, and the like.
Among these, copper is preferable because it is excellent in electrical characteristics and economy, and copper is also preferable as the material of the conductor circuit of the multilayer printed wiring board formed in the subsequent process. Moreover, as for the thickness of the plating layer 37, 1-15 micrometers is desirable.

(E) Next, after the plating resist 35 is removed, the transition layer 38 is formed by removing the metal film 36 existing under the plating resist 35 (see FIG. 6B).
The removal of the metal film 36 is performed using an etching solution such as a mixed solution of sulfuric acid and hydrogen peroxide, sodium persulfate, ammonium persulfate, ferric chloride, and cupric chloride.

As described above, when the transition layer is formed by the first transition layer forming method, it is possible to prevent the resin residue from being generated on the pad when the interlayer resin insulating layer is formed in the subsequent process. In addition, it is possible to prevent the discoloration and dissolution of the pad when immersed in an oxidant or an etching solution or through various annealing processes, thereby making the connection between the pad and the via hole more reliable. be able to.

(4) Next, if necessary, a roughened surface or a roughened layer (hereinafter simply referred to as a roughened surface) 38α is formed on the surface of the transition layer 38 (see FIG. 6C). . This is because by forming the roughened surface, the connection between the transition layer 38 and the interlayer resin insulating layer or via hole becomes more reliable. The roughened surface 38α can be formed by an etching process, a blackening reduction process, a plating process, or the like.

The said etching process can be performed using the etching liquid containing an organic acid and a cupric complex, for example.
Examples of the organic acid include formic acid, acetic acid, propionic acid, butyric acid, valeric acid, caproic acid, acrylic acid, crotonic acid, oxalic acid, malonic acid, succinic acid, glutaric acid, maleic acid, benzoic acid, glycolic acid, Examples include lactic acid, malic acid and sulfamic acid. These may be used alone or in combination of two or more. In the mixed solution, the content of the organic acid is preferably 0.1 to 30% by weight. This is because the solubility of oxidized copper can be maintained and catalyst stability can be ensured.

The cupric complex is preferably an azole cupric complex. This cupric complex of azoles acts as an oxidizing agent that oxidizes metallic copper and the like. Examples of azoles include diazole, triazole, tetrazole and the like. Among these, imidazole, 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, and 2-undecylimidazole are desirable. In the etching solution, the content of the cupric complex is preferably 1 to 15% by weight. This is because it is excellent in solubility and stability and can also dissolve noble metals such as Pd constituting the catalyst nucleus.

As a specific method of the blackening reduction treatment, a blackening treatment using an aqueous solution containing NaOH (10 g / l), NaClO ₂ (40 g / l), Na ₃ PO ₄ (6 g / l) as a blackening bath. And a method of performing a reduction treatment using an aqueous solution containing NaOH (10 g / l) and NaBH ₄ (6 g / l) as a reducing bath.

Specific methods of the plating treatment include copper sulfate (1-40 g / l), nickel sulfate (0.1-6.0 g / l), citric acid (10-20 g / l), sodium hypophosphite. (= 10-100 g / l), boric acid (10-40 g / l) and surfactant (manufactured by Nissin Chemical Industry Co., Surfinol 465) (0.01-10 g / l), electroless at pH = 9 The method etc. which perform electroless plating with a plating bath are mentioned.

(5) Next, as described above, the photosensitive cardo type polymer solution is applied onto the IC-embedded substrate 30 and then dried under heating, whereby the photosensitive cardo type polymer semi-cured layer 50 'is formed. After forming a via hole opening 48 in the semi-cured layer 50 'of the photosensitive cardo type polymer (see FIG. 7A), the interlayer resin insulation layer 50 is formed by carrying out main curing (see FIG. 7). 7 (B)).

(6) Next, a roughened surface 50α is formed on the surface of the interlayer resin insulation layer 50 as necessary (see FIG. 7C). The roughened surface 50α is formed, for example, by performing plasma processing. Further, sputtering described later may be directly performed without forming the roughened surface 50α.

(7) Next, if necessary, a thin film conductor layer 52 made of copper, nickel, tin, zinc, cobalt, thallium, lead, an alloy thereof or the like is formed on the surface of the interlayer resin insulating layer 50 (FIG. 8A). reference).
The thin film conductor layer 52 may be a single layer or may be composed of two or more layers. The thickness of the thin film conductor layer 52 is desirably 0.1 to 1.0 μm.

Examples of the method for forming the thin film conductor layer 52 include sputtering, electroless plating, and the like.
For example, when the sputtering is performed using Ni-Cu alloy as a target, SV-4540 is used, argon gas is used as an inert gas, pressure is 0.6 Pa, temperature is 80 ° C., power is 200 W, and time is 5 minutes. Can be done. Further, when the thin film conductor layer 52 is formed by electroless plating, for example, a surface of the interlayer resin insulation layer is provided by previously applying a palladium catalyst (manufactured by Atotech) to the surface of the interlayer resin insulation layer 50. An electroless plating layer (thin film conductor layer) 52 can be formed by attaching catalyst nuclei to the inner wall surface of the via hole opening and then immersing the substrate in an electroless plating aqueous solution.

(8) Next, a plating resist 54 is formed using a dry film on a part of the interlayer resin insulation layer 50 on which the thin film conductor layer 52 is formed, and then electrolytic plating is performed using the thin film conductor layer 52 as a plating lead. An electrolytic plating layer 56 is formed on the plating resist non-forming portion (see FIG. 8B). As the electrolytic plating, it is desirable to use copper plating.
At this time, the via hole opening may be filled with electrolytic plating to form a field via structure, or after filling the via hole opening with a conductive paste or the like, a lid plating layer is formed thereon to form the field via structure. Good. By forming the field via structure, a via hole can be provided immediately above the via hole.

(9) Next, after removing the plating resist 54, the thin film conductor layer 52 existing under the plating resist 54 is dissolved and removed by etching, and a conductor circuit 58 comprising the thin film conductor layer 52 and the electrolytic plating layer 56 and A via hole 60 is formed. When the thin film conductor layer 54 is formed by electroless plating after depositing the catalyst, the catalyst on the interlayer resin insulating layer 50 may be removed using an acid or an oxidizing agent. By removing palladium used as the catalyst, it is possible to prevent a reduction in electrical characteristics.

Further, roughened surfaces 58α and 60α are formed on the surfaces of the conductor circuit 58 and the via hole 60 as necessary (see FIG. 8C). The roughened surfaces 58α and 60α can be formed by a method similar to the method used when forming the roughened surface on the surface of the transition layer 38.

(10) Next, if necessary, steps (6) to (9) are repeated to further form interlayer resin insulation layer 150 and conductor circuit 158 (including via hole 160) (FIG. 9A). )reference).

(11) Next, the solder resist layer 70 is formed on the substrate surface including the outermost conductor circuit 158. Examples of the solder resist layer include those made of polyphenylene ether resin, polyolefin resin, fluororesin, thermoplastic elastomer, solder resist resin composition, and the like.
The solder resist layer is formed by applying an uncured resin (resin composition) by a roll coater method, etc., or thermocompression bonding an uncured resin film, and then performing an opening process by laser processing, exposure / development processing, etc. It is formed by performing a curing process or the like (see FIG. 9B).

Examples of the solder resist resin composition include (meth) acrylates of novolak-type epoxy resins, imidazole curing agents, bifunctional (meth) acrylate monomers, and heavy (meth) acrylate esters having a molecular weight of about 500 to 5,000. Examples include thermosetting resins composed of coalesced bisphenol-type epoxy resins, photosensitive monomers such as polyvalent acrylic monomers, paste-like fluids containing glycol ether solvents, and the like. It is desirable that the pressure is adjusted to 10 Pa · s.

Examples of the (meth) acrylate of the novolak type epoxy resin include an epoxy resin obtained by reacting a glycidyl ether of phenol novolak or cresol novolak with acrylic acid or methacrylic acid.
Moreover, it does not specifically limit as said bifunctional (meth) acrylic acid ester monomer, For example, various diols, ester of acrylic acid, methacrylic acid, etc. are mentioned.

(12) Thereafter, by forming a nickel plating layer 72, a gold plating layer 74, etc. on the conductor circuit 158 in the opening 71 of the solder resist layer 70, a solder pad is provided, and a solder paste is provided on the solder pad. Is printed and reflowed at 200 ° C. to form solder bumps 76. Thus, a multilayer printed wiring board having the IC chip 20 built in the substrate and having solder bumps can be obtained (see FIG. 1).
In addition, after printing solder paste on the opening of the solder resist layer, a conductive pin is placed on the opening and reflowed at 200 ° C., thereby connecting to an external terminal (PGA (Pin Grid Array)). It is good also as a multilayer printed wiring board by which is arranged.

Moreover, in the manufacturing method of this invention, it replaced with the 1st transition layer formation method (process of said (3)), and the method (henceforth 2nd transition layer formation) including the process of following (a)-(e). The transition layer 38 may be formed using a method). In addition, also when using the said 2nd transition layer formation method, what is necessary is just to use said manufacturing method except the process of forming the transition layer 38. FIG.
The second transition layer forming method will be described with reference to FIG.

(A) First, a metal film 36 'is formed on the entire surface of the IC-embedded substrate in the same manner as in step (a) of the first transition layer forming method described above (see FIG. 12A).
(B) Next, a plating layer 37 'is formed on the entire surface of the metal film by electroless plating and / or electrolytic plating. As the plating layer 37 ′, an electrolytic copper plating layer is desirable (see FIG. 12B).
The thickness of the plating layer 37 ′ is preferably 1 to 15 μm. If the thickness exceeds 15 μm, an undercut occurs during etching, which will be described later, and a gap is generated at the interface between the formed transit layer and the pad 24, which may cause separation between the two. Because there is.

(C) Next, a photosensitive dry film is affixed on the plating layer. It does not specifically limit as said photosensitive dry film, What is necessary is just to use the commercial item conventionally used in order to form an etching resist.
(D) Next, by placing a mask on which a pattern corresponding to the transition layer to be formed is placed on the photosensitive dry film, and performing exposure / development processing, a portion corresponding to the transition layer non-formation portion An etching resist 39 having an opening is formed (see FIG. 12C).

(E) Furthermore, the transition layer 38 is formed by removing the metal film 36 ′ and the plating layer 37 ′ under the portion where the etching resist 39 is not formed by an etching process (see FIG. 12D).
The etching treatment may be performed using an etching solution such as a sulfuric acid / hydrogen peroxide aqueous solution, an aqueous solution of persulfate such as ferric chloride, cupric chloride, or ammonium persulfate.

Thus, even when the transition layer is formed by the second transition layer forming method, it is possible to prevent the resin residue from being generated on the pad when forming the interlayer resin insulation layer in a later step. It is possible to prevent the discoloration and dissolution of the pad when immersed in an acid, oxidant or etching solution or through various annealing processes, so that the connection between the pad and the via hole is made more reliable. can do.

It should be noted that plasma treatment with oxygen, carbon tetrachloride, or the like may be performed in a timely manner for a character printing process for forming a product recognition character or the like or a solder resist layer modification. The above method is based on the semi-additive method, but the full additive method may be adopted.

As described above, by using the manufacturing method of the present invention, an electronic component such as an IC chip is built in the substrate, and the IC chip and the multilayer printed wiring board are directly electrically connected without a lead component. A multilayer printed wiring board can be manufactured.
In the production method of the present invention, since a photosensitive cardo type polymer is used for forming an interlayer resin insulation layer, the crosslinking density is high at a relatively low curing temperature (150 to 250 ° C.), and shape retention and heat resistance An interlayer resin insulating layer having excellent properties can be formed, and the substrate is not softened or dissolved when the interlayer resin insulating layer is formed.
Further, since the photosensitive cardo type polymer is excellent in the opening property by exposure / development processing, the manufacturing method of the present invention can form a via hole having a desired shape without any resin residue in the via hole opening. it can.

Hereinafter, the present invention will be described in more detail.

Example 1
(1) BT (bismaleimide triazine) having a thickness of 0.8 μm in which an IC chip 20 in which an upper portion thereof is covered with a passivation film 22 and an aluminum pad 24 is formed as an input / output terminal in the opening of the passivation film 22 is incorporated. ) A resin substrate (hereinafter also referred to as an IC built-in BT substrate) 30 was used as a starting material. (See FIG. 2A).
First, the positioning marks (not shown) arranged at the four corners of the IC chip 20 are photographed by a camera, and the positioning marks are formed by lasers at the four corners of the IC-embedded substrate 30 using the positioning marks as a reference. Positioning was performed.

(2) Next, a photosensitive cardo polymer solution whose viscosity has been adjusted to 30 Pa · s in advance is applied to the substrate surface including the IC chip with a curtain coater, and then dried at a temperature of 150 ° C. for 20 minutes. Thus, a semi-cured layer 50 'of the photosensitive cardo type polymer was formed (see FIG. 2B).

The photosensitive cardo type polymer used here is R ² , R ³ , R ⁴ , R ^{5 in the} bis-phenolfluorene-hydroxyacrylate represented by the chemical formula (1) and the general formula (3). And R ⁶ is a random copolymer obtained by reacting bis-aniline-fluorene and pyromellitic anhydride in a molar ratio = 1: 4: 5.

Next, a photoetching mask having a black circle drawn on a portion corresponding to a via hole opening forming portion is placed on the semi-cured layer 50 'of the photosensitive cardo polymer, and then ultraviolet rays are applied at 400 mj / cm ^2. By irradiating under the conditions, exposure / development processing was performed, and a via hole opening 48 was formed. Thereafter, main curing was performed at 250 ° C. for 120 minutes to form an interlayer resin insulating layer 50 (see FIG. 2C). The glass transition temperature of the interlayer resin insulating layer formed here was 260 ° C.

(3) Next, using SV-4540 manufactured by Nippon Vacuum Technology Co., Ltd., using argon gas as the inert gas, plasma treatment for 2 minutes under the conditions of power 200 W, gas pressure 0.6 Pa, temperature 70 ° C. Then, a roughened surface 50α was formed on the surface of the interlayer resin insulating layer 50 (see FIG. 2D).

(4) Further, using the same apparatus, after replacing the argon gas inside, sputtering using Zn as a target is performed under conditions of atmospheric pressure 0.6 Pa, temperature 80 ° C., power 200 W, time 5 minutes, and consists of Zn. A thin film conductor layer 52 having a thickness of 0.1 μm was formed on the surface of the interlayer resin insulation layer 50 (see FIG. 3A).

(5) Next, a plating resist 54 is formed on a part of the interlayer resin insulation layer 50 on which the thin film conductor layer 52 is formed using a dry film, and then electrolysis is performed under the following conditions using the thin film conductor layer 52 as a plating lead. Copper plating was performed to form an electrolytic copper plating layer 56 in the plating resist non-forming portion (see FIG. 3B).

[Electrolytic copper plating aqueous solution]
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive (manufactured by Atotech Japan Co., Kaparaside HL) 19.5 ml / l
[Electrolytic plating conditions]
Current density 1A / dm ²
Time 65 minutes Temperature 22 ℃ ± 2 ℃

(6) Next, after removing the plating resist, the thin film conductor layer 52 existing under the plating resist is dissolved and removed by etching, and a conductor having a thickness of 16 μm composed of the thin film conductor layer 52 and the electrolytic plating layer 56 is removed. Circuit 58 and via hole 60 were formed.
Thereafter, an etching solution was sprayed onto the substrate on which the conductor circuit 58 (including the via hole 60) was formed, and a roughened surface 58α was formed on the surface of the conductor circuit 58 (see FIG. 3C). Here, as an etching solution, a mixture of 10 parts by weight of imidazole copper (II) complex, 7 parts by weight of glycolic acid, 5 parts by weight of potassium chloride and 78 parts by weight of ion-exchanged water was used.

(7) Next, by repeating the steps (2) to (6), the upper interlayer resin insulation layer 150 and the conductor circuit 158 (including the via hole 160) were further formed (see FIG. 4A). .

(8) Next, a photosensitizing agent obtained by acrylating 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 46.67 parts by weight of oligomer (molecular weight 4000), 15 parts by weight of 80% by weight of bisphenol A type epoxy resin (manufactured by Yuka Shell Co., Ltd., trade name: Epicoat 1001) dissolved in methyl ethyl ketone, imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd.) , Trade name: 2E4MZ-CN) 1.6 parts by weight, polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., trade name: R604) which is a photosensitive monomer, polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., product) Name: DPE6A) 1.5 parts by weight, dispersion antifoaming agent (manufactured by San Nopco, trade name: S-65) 0.71 An amount part is placed in a container, and the mixture composition is prepared by stirring and mixing. 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photoweight initiator and Michler's ketone as a photosensitizer are mixed with this mixture composition. (Kanto Chemical Co., Ltd.) 0.2 parts by weight was added to obtain a solder resist composition having a viscosity adjusted to 2.0 Pa · s at 25 ° C. Viscosity measurement was performed using a B-type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.). In the case of 4 or 6 rpm, the rotor No. 3 according.

(9) Next, the solder resist composition is applied to the substrate 30 at a thickness of 20 μm, and after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, the solder resist resist opening is formed. A photomask having a thickness of 5 mm on which a pattern of 1 mm is drawn was brought into close contact with the solder resist layer 70 and exposed to 1000 mJ / cm ² of ultraviolet light, and developed with a DMTG solution to form an opening 71 having a diameter of 200 μm (FIG. 4). (See (B)).

(10) Next, the substrate on which the solder resist layer 70 is formed is made of nickel chloride (2.3 × 10 ⁻¹ mol / l), sodium hypophosphite (2.8 × 10 ⁻¹ mol / l), A nickel plating layer 72 having a thickness of 5 μm was formed in the opening 71 by dipping in an electroless nickel plating solution containing sodium acid (1.6 × 10 ⁻¹ mol / l) at pH = 4.5 for 20 minutes. Further, the substrate was made of potassium gold cyanide (7.6 × 10 ^-3 mol / l), ammonium chloride (1.9 × 10 ^-1 mol / l), sodium citrate (1.2 × 10 ^-1 mol). / L), and immersed in an electroless plating solution containing sodium hypophosphite (1.7 × 10 ⁻¹ mol / l) for 7.5 minutes at 80 ° C., a thickness of 0 on the nickel plating layer 72 A solder pad 75 was formed on the conductor circuit 158 by forming a 0.03 μm gold plating layer 74 (see FIG. 4C).

(11) Thereafter, solder bumps 76 were formed by printing solder paste in the openings 71 of the solder resist layer 70 and reflowing at 200 ° C. As a result, the multilayer printed wiring board 100 having the IC chip 20 and having the solder bumps 76 was obtained (see FIG. 10).

(Example 2)
In step (4) of Example 1, instead of sputtering using Zn as a target, sputtering using Cr as a target was performed under the conditions of atmospheric pressure 0.6 Pa, temperature 80 ° C., power 200 W, and time 5 minutes. A multilayer printed wiring board was obtained in the same manner as in Example 1 except that a thin film conductor layer 52 having a thickness of 0.1 μm was formed on the surface of the interlayer resin insulation layer 50.

(Example 3)
In step (2) of Example 1, bis-phenolfluorene-hydroxyacrylate, bis-aniline-fluorene, pyromellitic anhydride, and R ¹ in the general formula (2) are carbonyl as the photosensitive cardo type polymer. Sputtering using Zn as a target in the step (4) using a random copolymer obtained by reacting the group benzophenonetetracarboxylic dianhydride with a molar ratio = 1: 4: 3: 2. Instead, sputtering using Ni as a target is performed under the conditions of atmospheric pressure 0.6 Pa, temperature 80 ° C., power 200 W, and time 5 minutes, and a 0.1 μm-thick thin film conductor layer 52 made of Ni is formed as an interlayer resin insulation layer. A multilayer printed wiring board was obtained in the same manner as in Example 1 except that it was formed on the surface of 50. The glass transition temperature of the interlayer resin insulation layer was 260 ° C.

Example 4
(1) The IC built-in BT substrate 30 having a thickness of 0.8 μm similar to that in Example 1 was used as a starting material (see FIG. 5A). First, the positioning marks arranged at the four corners of the IC chip 20 were photographed with a camera, and the IC chip was positioned by forming the positioning marks with the laser at the four corners of the IC-embedded substrate 30 using the positioning marks as a reference. .

(2) Next, sputtering using Zn as a target is performed using SV-4540 manufactured by Nippon Vacuum Technology Co., Ltd. under the conditions of gas pressure 0.6 Pa, temperature 80 ° C., power 200 W, and time 5 minutes. By forming a Zn film with a thickness of 0.1 μm on the entire surface of the BT substrate 30 and further forming an electroless copper plating film with a thickness of 0.7 μm on the Zn film by electroless copper plating, A metal film 36 is formed (see FIG. 5B).

(3) Next, after a photosensitive dry film is stuck on the metal film 36, a mask on which a pattern corresponding to the pad 24 is formed is placed on the photosensitive dry film, and exposure / development processing is performed. As a result, a plating resist 35 having an opening above the pad 24 was formed. Furthermore, electrolytic copper plating was performed on the portion where the plating resist 35 was not formed under the following conditions to provide an electrolytic copper plating layer 37 (see FIG. 6A).

[Electrolytic copper plating aqueous solution]
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive (manufactured by Atotech Japan Co., Kaparaside HL) 19.5 ml / l
[Electrolytic plating conditions]
Current density 1A / dm ²
Time 65 minutes Temperature 22 ℃ ± 2 ℃

(4) Further, after removing the plating resist 35, the metal film 36 under the plating resist 35 is removed by etching to form a transition layer 38 having a diameter of 60 μm on the pad 24 of the IC chip (FIG. 6B). )reference). Note that a mixed solution of sulfuric acid and hydrogen peroxide was used as the etching solution.

(5) Next, an etching solution was sprayed onto the IC built-in BT substrate 30 on which the transition layer 38 was formed, to form a roughened surface 38α on the surface of the transition layer 38 (see FIG. 6C). Here, as an etching solution, a mixture of 10 parts by weight of imidazole copper (II) complex, 7 parts by weight of glycolic acid, 5 parts by weight of potassium chloride and 78 parts by weight of ion-exchanged water was used.

(6) Next, a photosensitive cardo polymer solution whose viscosity has been adjusted to 30 Pa · s in advance is applied to the IC built-in BT substrate 30 on which the transition layer 38 is formed with a curtain coater. By drying at 180 ° C. for 20 minutes, a semi-cured layer 50 ′ of a photosensitive cardo type polymer was formed (see FIG. 7A). In addition, as the photosensitive cardo type polymer, the same photosensitive cardo type polymer as in Example 1 was used.

Next, after placing a photoetching mask with black circles drawn on the portion corresponding to the via hole opening forming portion on the semi-cured layer 50 ′ of the photosensitive cardo type polymer, ultraviolet rays were applied at 400 mj / cm ^2. After the irradiation under the conditions, exposure and development are performed by developing, and the via hole opening 48 is formed, followed by main curing by drying at 270 ° C. for 120 minutes, and the interlayer resin insulation layer 50 was formed (see FIG. 7B).

(7) Next, using SV-4540 manufactured by Nippon Vacuum Technology Co., Ltd., using argon gas as the inert gas, plasma treatment for 2 minutes under the conditions of power 200 W, gas pressure 0.6 Pa, temperature 70 ° C. Then, a roughened surface 50α was formed on the surface of the interlayer resin insulating layer 50 (see FIG. 7C).

(8) Further, by applying a palladium catalyst (manufactured by Atotech) to the surface of the substrate on which the roughened surface has been formed, catalyst nuclei are formed on the surface of the interlayer resin insulation layer 50 and the inner wall surface of the via hole opening 48. Attached.

(9) Next, the substrate was immersed in an electroless copper plating aqueous solution having the following composition to form a thin film conductor layer 52 having a thickness of 0.6 to 0.9 μm over the entire surface of the roughened surface 50α (FIG. 8 (A)).

[Electroless plating aqueous solution]
NiSO ₄ 0.003 mol / l
Tartaric acid 0.200 mol / l
Copper sulfate 0.030 mol / l
HCHO 0.050 mol / l
NaOH 0.100 mol / l
α, α'-bipyridyl 40 mg / l
Polyethylene glycol (PEG) 0.10 g / l
[Electroless plating conditions]
40 minutes at 35 ° C liquid temperature

(10) Next, a plating resist is formed on a part of the interlayer resin insulation layer 50 on which the thin film conductor layer 52 is formed by using a dry film, and then the thin film conductor layer 52 is used as a plating lead as in the above (3). Electrolytic copper plating was performed under the above conditions, and an electrolytic copper plating layer 56 was formed on the plating resist non-forming portion (see FIG. 8B).

(11) Next, after removing the plating resist, the thin-film conductor layer 52 existing under the plating resist is dissolved and removed by etching, and a conductor having a thickness of 16 μm composed of the thin-film conductor layer 52 and the electrolytic plating film 56 is removed. Circuit 58 and via hole 60 were formed. Thereafter, an etching solution is sprayed on the substrate on which the conductor circuit 58 (including the via hole 60) is formed by spraying to form roughened surfaces 58α and 60α on the surfaces of the conductor circuit 58 and the via hole 60 (FIG. 8C )reference). As the etching solution, the same etching solution as used in forming the roughened surface on the surface of the transition layer in the step (5) was used.

(12) Next, by repeating the steps (6) to (11), an upper interlayer resin insulation layer 150 and a conductor circuit 158 (including the via hole 160) are further formed (see FIG. 9A). .

(13) Next, a solder resist composition was obtained in the same manner as in Example 1.
Further, the solder resist composition is applied to the IC-embedded substrate 30 having the conductor circuit 158 formed on the outermost layer in a thickness of 20 μm, and dried at 70 ° C. for 20 minutes and 70 ° C. for 30 minutes. After that, a photomask having a thickness of 5 mm on which a pattern of the opening of the solder resist resist is drawn is brought into close contact with the solder resist layer 70, exposed to 1000 mJ / cm ² of ultraviolet light, developed with DMTG solution, and 200 μm in diameter. An opening 71 was formed (see FIG. 9B).

(14) Next, the substrate on which the solder resist layer 70 is formed is made of nickel chloride (2.3 × 10 ⁻¹ mol / l), sodium hypophosphite (2.8 × 10 ⁻¹ mol / l), A nickel plating layer 72 having a thickness of 5 μm was formed in the opening 71 by dipping in an electroless nickel plating solution containing sodium acid (1.6 × 10 ⁻¹ mol / l) at pH = 4.5 for 20 minutes. Further, the substrate was made of potassium gold cyanide (7.6 × 10 ^-3 mol / l), ammonium chloride (1.9 × 10 ^-1 mol / l), sodium citrate (1.2 × 10 ^-1 mol). / L), and immersed in an electroless plating solution containing sodium hypophosphite (1.7 × 10 ⁻¹ mol / l) for 7.5 minutes at 80 ° C., a thickness of 0 on the nickel plating layer 72 A solder pad 75 was formed on the conductor circuit 158 by forming a .03 μm gold plating layer 74 (see FIG. 9C).

(15) Thereafter, solder paste 76 is printed in the opening 71 of the solder resist layer 70 and reflowed at 200 ° C. to form solder bumps 76. As a result, the multilayer printed wiring board 10 including the IC chip 20 and having the solder bumps 76 was obtained (see FIG. 1).

(Example 5)
In Step (2) of Example 4, the same random copolymer as in Example 3 was used as the photosensitive cardo type polymer. Further, in Step (2), instead of sputtering using Zn as a target, Cr was used. Sputtering as a target was performed under the conditions of atmospheric pressure 0.6 Pa, temperature 80 ° C., power 200 W, time 5 minutes, and a 0.1 μm thick metal film 36 made of Cr was formed on the entire surface of the BT substrate 30 with built-in IC. Obtained a multilayer printed wiring board in the same manner as in Example 4.

(Example 6)
(1) The IC built-in BT substrate 30 having a thickness of 0.8 μm similar to that in Example 1 was used as a starting material (see FIG. 5A). First, the positioning marks arranged at the four corners of the IC chip 20 were photographed with a camera, and the IC chip was positioned by forming the positioning marks with the laser at the four corners of the IC-embedded substrate 30 using the positioning marks as a reference. .

(2) Next, sputtering using Ni as a target is performed using SV-4540 manufactured by Nippon Vacuum Technology Co., Ltd. under conditions of gas pressure 0.6 Pa, temperature 80 ° C., power 200 W, and time 5 minutes. By forming an Ni film having a thickness of 0.1 μm on the entire surface of the BT substrate 30 and further forming an electroless copper plating film having a thickness of 0.7 μm on the Ni film by electroless copper plating, nickel and A metal film 36 'made of copper was formed (see FIG. 12A).

(3) Next, electrolytic copper is plated on the metal film 36 'under the same conditions as in step (3) of Example 4, and an electrolytic copper plating layer 37' is provided on the entire surface of the metal film 36 '. (See FIG. 12B).

(4) Further, a photosensitive dry film is stuck on the electrolytic copper plating layer 37 ', and a mask on which a pattern corresponding to the transition layer is formed is placed on the photosensitive dry film, and exposure / development processing is performed. As a result, etching resist 39 having an opening corresponding to the transition layer non-forming portion was formed (see FIG. 12C).

(5) Further, the metal film 36 ′ and the electrolytic copper plating layer 37 ′ under the portion where the etching resist 39 is not formed are removed by etching, thereby forming a transition layer 38 having a diameter of 60 μm on the IC chip (FIG. 12D )reference). In this etching process, an etching solution composed of sulfuric acid and an aqueous hydrogen peroxide solution was used.

(6) A substrate having a conductor circuit 158 formed on the outermost layer was produced in the same manner as in the steps (5) to (12) of Example 4 (see FIG. 9A).

(7) Next, a solder resist composition was obtained in the same manner as in Example 1.
Further, the solder resist composition is applied to the IC-embedded substrate 30 having the conductor circuit 158 formed on the outermost layer in a thickness of 20 μm, and dried at 70 ° C. for 20 minutes and 70 ° C. for 30 minutes. After that, a photomask having a thickness of 5 mm on which a pattern of the opening of the solder resist resist is drawn is brought into close contact with the solder resist layer 70, exposed to 1000 mJ / cm ² of ultraviolet light, developed with DMTG solution, and 200 μm in diameter. An opening 71 was formed (see FIG. 9B).

(8) Next, the substrate on which the solder resist layer 70 is formed is made of nickel chloride (2.3 × 10 ⁻¹ mol / l), sodium hypophosphite (2.8 × 10 ⁻¹ mol / l), A nickel plating layer 72 having a thickness of 5 μm was formed in the opening 71 by dipping in an electroless nickel plating solution containing sodium acid (1.6 × 10 ⁻¹ mol / l) at pH = 4.5 for 20 minutes. Further, the substrate was made of potassium gold cyanide (7.6 × 10 ^-3 mol / l), ammonium chloride (1.9 × 10 ^-1 mol / l), sodium citrate (1.2 × 10 ^-1 mol). / L), and immersed in an electroless plating solution containing sodium hypophosphite (1.7 × 10 ⁻¹ mol / l) for 7.5 minutes at 80 ° C., a thickness of 0 on the nickel plating layer 72 A solder pad 75 was formed on the conductor circuit 158 by forming a .03 μm gold plating layer 74 (see FIG. 9C).

(9) Thereafter, after printing the solder paste on the opening 71 of the solder resist layer 70, the conductive pins 176 are placed on the solder pads via the solder paste, and reflowed at 200 ° C. A multilayer printed wiring board 110 in which an IC chip 20 was incorporated and a PGA (Pin Grid Array) was disposed was obtained (see FIG. 11).

Regarding the multilayer printed wiring board manufactured in this way, observation of the pad surface of the IC chip, presence of occurrence of peeling between the conductor circuit and the interlayer resin insulating layer before and after the reliability test, The following evaluation methods were used to evaluate the presence or absence of delamination between the via holes and the presence or absence of occurrence of short circuits and disconnections during the continuity test.

(1) Observation of pad surface The multilayer printed wiring board was cut with a blade, and the cut section was observed with a microscope. Here, the multilayer printed wiring board was cut so as to pass through the pad portion of the IC chip.

(2) Reliability test The obtained multilayer printed wiring board was maintained in an atmosphere at −65 ° C. for 3 minutes, and then a cycle of maintaining in an atmosphere at 130 ° C. for 3 minutes was repeated 1000 times.

(3) Presence or absence of peeling between the conductor circuit and the interlayer resin insulation layer The multilayer printed wiring board was cut with a cutter in the same manner as in (1) above, and the cut section was observed with a microscope.
(4) Presence or absence of peeling between IC chip pad and via hole In the same manner as in (1) above, the multilayer printed wiring board was cut with a cutter, and the cut section was observed with a microscope.

(5) Conductivity test of the obtained multilayer printed wiring board with built-in IC chip was performed, and the conduction state was evaluated from the results displayed on the monitor.

As a result of the above evaluation, the multilayer printed wiring boards of Examples 1 to 3 are not formed with a transition layer, and therefore, a resin that is misaligned between the via hole and the IC chip pad or the pad surface Although there was some remaining, it was seen in part, but the via hole and the pad were connected and did not affect the performance of the product.
Further, no separation occurred between the conductor circuit and the interlayer resin insulation layer, or between the pad and the via hole, and no short circuit or disconnection occurred in the continuity test.

Further, in the multilayer printed wiring boards of Examples 4 to 6, since the transition layer was formed on the pad, there was no positional displacement between the via hole and the IC chip pad and no resin residue on the pad surface. It was.
Further, no separation occurred between the conductor circuit and the interlayer resin insulation layer or between the pad and the via hole, and no short circuit or disconnection occurred in the continuity test.

FIG. 1 is a sectional view schematically showing an example of the multilayer printed wiring board of the present invention. (A)-(D) are the cross sections which show typically the manufacturing process of the multilayer printed wiring board of this invention. (A)-(C) are the cross sections which show typically the manufacturing process of the multilayer printed wiring board of this invention. (A)-(C) are the cross sections which show typically the manufacturing process of the multilayer printed wiring board of this invention. (A), (B) is a cross section which shows typically the manufacturing process of the multilayer printed wiring board of this invention. (A)-(C) are the cross sections which show typically the manufacturing process of the multilayer printed wiring board of this invention. (A)-(C) are the cross sections which show typically the manufacturing process of the multilayer printed wiring board of this invention. (A)-(C) are the cross sections which show typically the manufacturing process of the multilayer printed wiring board of this invention. (A)-(C) are the cross sections which show typically the manufacturing process of the multilayer printed wiring board of this invention. FIG. 10 is a cross section schematically showing another example of the multilayer printed wiring board of the present invention. FIG. 11 is a cross-sectional view schematically showing still another example of the multilayer printed wiring board of the present invention. (A)-(D) are the cross sections which show typically the manufacturing process of the multilayer printed wiring board of this invention.

Explanation of symbols

20 IC chip 24 Pad 30 IC built-in substrate 38 Transition layer 50, 150 Interlayer resin insulation layer 58, 158 Conductor circuit 60, 160 Via hole 70 Solder resist layer 76 Solder bump

Claims (10)

An interlayer resin insulation layer and a conductor circuit are sequentially formed on a substrate in which the electronic component is embedded or stored, and the pad and the conductor circuit of the electronic component and the upper and lower conductor circuits are connected via via holes. A multilayer printed wiring board comprising:
A via hole connecting the pad of the electronic component and the conductor circuit is formed in an interlayer resin insulating layer made of a photosensitive cardo polymer ,
A passivation film having an opening on the pad is formed so as to cover the electronic component and the pad,
On the pad, connected to the pad through the opening, a diameter of 60 to 80 μm is larger than the diameter of the pad, and a transition layer made of a metal film and a plating layer is formed,
Via holes connected to the transition layer are formed on the transition layer,
A multilayer printed wiring board, wherein a roughened surface is formed on a surface of the transition layer . The multilayer printed wiring board according to claim 1, wherein the photosensitive cardo type polymer is a photosensitive cardo type polyimide resin. The multilayer printed wiring board according to claim 1 or 2, wherein the photosensitive cardo type polymer has a glass transition temperature of 250 to 300 ° C. The via holes, the multilayer printed wiring board according to any one of claims 1 to 3, characterized in that it has a field via structure. Said being roughened surface on the surface of the interlayer resin insulating layer is formed, any of claims 1 to 4, via holes having a conductor circuit and a field via structure in the interlayer resin insulating layer having the roughened surface is formed 2. The multilayer printed wiring board according to 1. It is a manufacturing method of the multilayer printed wiring board according to claim 1 ,
The manufacturing method of the multilayer printed wiring board characterized by including the process of following (a)-(f) and (1)-(4) at least.
(A) forming a metal film on a substrate in which an electronic component having a passivation film having an opening formed on the pad so as to cover the pad is built-in or stored;
(B) attaching a photosensitive dry film on the metal film;
(C) forming a plating resist by subjecting the photosensitive dry film to exposure and development;
(D) forming a plating layer on the plating resist non-forming portion;
(E) forming a transition layer having a diameter of 60 to 80 μm by removing the plating resist and the metal film present under the plating resist;
(F) roughening the surface of the transition layer;
(1) A step of applying a photosensitive cardo type polymer solution onto a substrate in which the electronic component is built-in or stored;
(2) forming a semi-cured layer of the photosensitive cardo type polymer;
(3) A photoetching mask is placed on the semi-cured layer of the photosensitive cardo polymer, and then a via-hole opening is formed by exposing and developing the semi-cured layer of the photosensitive cardo polymer. Forming, and
(4) A step of forming an interlayer resin insulation layer by main-curing the semi-cured layer of the photosensitive cardo type polymer in which the opening for via hole is formed. It is a manufacturing method of the multilayer printed wiring board according to claim 1,
The manufacturing method of the multilayer printed wiring board characterized by including the process of following (a)-(f) and (1)-(4) at least.
(A) forming a metal film on a substrate on which an electronic component having a passivation film having an opening formed on the pad so as to cover the pad is embedded or housed;
(B) forming a plating layer on the metal film;
(C) a step of attaching a photosensitive dry film on the plating layer;
(D) a step of forming an etching resist by subjecting the photosensitive dry film to exposure and development;
(E) a step of forming a transition layer having a diameter of 60 to 80 μm by removing the metal film and the plating layer under the etching resist non-forming portion by an etching process;
(F) roughening the surface of the transition layer;
(1) A step of applying a photosensitive cardo type polymer solution onto a substrate in which the electronic component is built-in or stored;
(2) forming a semi-cured layer of the photosensitive cardo type polymer;
(3) A photoetching mask is placed on the semi-cured layer of the photosensitive cardo polymer, and then a via-hole opening is formed by exposing and developing the semi-cured layer of the photosensitive cardo polymer. Forming, and
(4) A step of forming an interlayer resin insulation layer by main-curing the semi-cured layer of the photosensitive cardo type polymer in which the opening for via hole is formed. The method for producing a multilayer printed wiring board according to claim 7, wherein the photosensitive cardo type polymer is a photosensitive cardo type polyimide resin. The method for producing a multilayer printed wiring board according to claim 7 or 8, wherein the fully cured photosensitive cardo polymer layer has a glass transition temperature of 250 to 300 ° C. Furthermore, the manufacturing method of the multilayer printed wiring board of any one of Claims 7-9 including the process of forming the via hole and the metal film for conductor circuits by sputtering on the formed interlayer resin insulation layer.

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