JP4768231B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having an insulated gate bipolar transistor.

  As one of power transistors used as switching elements such as a power amplifier circuit and a power supply circuit, for example, a power transistor called IGBT (Insulated Gate Bipolar Transistor) is known. This IGBT is an element in which a bipolar transistor and a power MISFET (Metal Insulator Semiconductor Field Effect Transistor) are combined in one semiconductor substrate, and a planar type or a trench type is known as a structure. The planar IGBT is disclosed in, for example, Japanese Patent Application Laid-Open No. 2003-59856. The trench type IGBT is disclosed in, for example, Japanese Patent Application Laid-Open No. 2003-318399.

JP 2003-59856 A JP 2003-318399 A

  As a result of studying a semiconductor device having a trench type IGBT, the present inventor has found the following problems.

  In the trench type IGBT, for example, a groove is formed in the depth direction from the main surface of the n-type semiconductor substrate, and a conductor embedded in the groove with a gate insulating film interposed therebetween is used as a gate electrode. The p-type semiconductor region formed on the main surface of the semiconductor substrate is an emitter region, and the p-type semiconductor region formed on the back surface opposite to the main surface of the n-type semiconductor substrate is a collector region. In manufacturing a semiconductor device having a trench type IGBT having such a structure, a p-type semiconductor region (emitter region), an n-type semiconductor region, a gate electrode, and the like are mainly formed on the main surface of an n-type semiconductor substrate, and thereafter Then, a wiring is formed on the main surface of the n-type semiconductor substrate, and then a final protective film is formed on the main surface of the n-type semiconductor substrate, and then impurities are ion-implanted into the back surface of the n-type semiconductor substrate. A semiconductor region and a p-type semiconductor region (collector region) are formed, and then a heat treatment for activating impurities in the n-type semiconductor region and the p-type semiconductor region formed on the back surface of the n-type semiconductor substrate is performed. An electrode (collector electrode) is formed on the back surface of the semiconductor substrate.

  The characteristics of the trench IGBT influence the activation of impurities in the n-type semiconductor region and the p-type semiconductor region (collector region) formed on the back surface of the n-type semiconductor substrate, and damage recovery on the back surface of the n-type semiconductor substrate. It is necessary to sufficiently activate the impurities and recover the damage. Heat treatment at a high temperature is effective for sufficient activation of impurities and recovery of damage. However, in conventional semiconductor devices, an aluminum film is used as a wiring material, and a polyimide-based resin is used as a final protective film. Since the film is used, it is difficult to perform high-temperature heat treatment after the wiring and the final protective film are formed.

An object of the present invention is to provide a technique capable of improving the impurity activation rate of a semiconductor region formed by ion implantation on the back surface of a semiconductor substrate and improving damage recovery on the back surface of the semiconductor substrate.
Another object of the present invention is to provide a technique capable of improving the characteristics of an insulated gate bipolar transistor.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  The purpose is to form a wiring made of a refractory metal film on the main surface of the semiconductor substrate, and then ion-implant impurities into the back surface opposite to the main surface of the semiconductor substrate to form a semiconductor region, This is achieved by performing a heat treatment for activating impurities in the semiconductor region, and then forming a final protective film on the main surface of the semiconductor substrate.

  Also, the above object is to form a semiconductor region by ion-implanting impurities into the back surface opposite to the main surface of the semiconductor substrate, and then performing a heat treatment for activating the impurities in the semiconductor region, and then performing main processing on the semiconductor substrate. This is achieved by forming a wiring on the surface and then forming a final protective film on the main surface of the semiconductor substrate.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the present invention, it is possible to improve the impurity activation rate of the semiconductor region formed by ion implantation on the back surface of the semiconductor substrate and improve the damage recovery of the back surface of the semiconductor substrate.
Another object of the present invention is to improve the characteristics of an insulated gate bipolar transistor.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment of the invention, and the repetitive description thereof is omitted.
In this embodiment, an example in which the present invention is applied to a semiconductor device having a trench IGBT will be described.

FIG. 1 is an equivalent circuit diagram of a trench type IGBT mounted on the semiconductor device of the present embodiment.
FIG. 2 is a schematic cross-sectional view showing the structure of the trench IGBT of FIG.
3 to 10 are schematic cross-sectional views showing the manufacturing process of the semiconductor device of this embodiment.

  The semiconductor device of this embodiment has a trench IGBT-20 shown in FIG. Although not limited to this, the trench type IGBT-20 is, for example, an element in which a pnp bipolar transistor Tr and an n-channel conductive power MISFET-Q are combined in an equivalent circuit on one semiconductor substrate.

  As shown in FIG. 2, the semiconductor device according to the present embodiment is mainly composed of an n-type semiconductor substrate 1 made of single crystal silicon (hereinafter simply referred to as an n-type substrate). A trench type IGBT-20 shown in FIG. 1 is mounted on the n-type substrate 1. The trench type IGBT-20 is mainly a conductor in which a groove 3 is formed in the depth direction from the main surface 1x of the n-type substrate 1, and a gate insulating film 4 is embedded in the groove 3 (For example, a polycrystalline silicon film) is used as the gate electrode 5, the p-type semiconductor region 2 formed on the main surface 1x of the n-type substrate 1 is used as the emitter region, and the back surface 1y opposite to the main surface 1x of the n-type substrate 1 is formed. The formed p-type semiconductor region 10b is used as a collector region.

  In the n-channel conductivity type power MISFET-Q, an n-type semiconductor formed in the p-type semiconductor region 2 with the conductor embedded in the trench 3 with the gate insulating film 4 interposed therebetween is used as the gate electrode 5. Using the region 6 as a source region, the n-type semiconductor region 10a formed on the back surface of the n-type substrate 1 on the main surface 1x side of the n-type substrate 1 relative to the p-type semiconductor region 10b, and the n-type semiconductor region of the n-type substrate 1 Is the drain region, and the p-type semiconductor region 2 is the channel formation region.

  On the main surface 1x of the n-type substrate 1, a wiring 9 made of a refractory metal film is formed. Although not limited to this, the wiring 9 of the present embodiment is formed of a multilayer film in which a TiW (titanium tungsten) film 9 a and a Ti (titanium) film 9 b are sequentially arranged from the main surface 1 x side of the n-type substrate 1. ing.

  The wiring 9 is electrically connected to the p-type semiconductor region 2 formed on the main surface 1x of the n-type substrate 1, and an insulating film (for example, formed between the wiring 9 and the main surface 1x of the n-type substrate 1). The gate electrode 5 is electrically insulated and separated by a silicon oxide film 7.

  On the main surface 1x of the n-type substrate 1, a final protective film 12 is formed so as to cover the wiring 9, and a bonding opening 12a for exposing a part of the wiring 9 is formed in the final protective film 12. An electrode 14 electrically connected to the wiring 9 is formed in the bonding opening 12a. As the final protective film 12, for example, a polyimide resin is used. The electrode 14 is not limited to this. For example, the electrode 14 is formed of a multilayer film in which a metal film 13 a and a metal film 13 b are sequentially arranged from the main surface 1 x side (wiring 9 side) of the n-type substrate 1. For example, a Ni (nickel) film or a Ni / Cu (copper) film is used as the metal film 13a, and an Au (gold) film is used as the metal film 13b.

  The protruding electrode 16 is electrically and mechanically connected to the electrode 14 through the bonding opening 12a. As the protruding electrode 16, for example, a solder bump having a Pb-free composition (for example, Sn (tin) -Ag (silver) -Cu composition) is used.

  An electrode 15 is formed on the back surface 1 y of the n-type substrate 1 with a base metal film 11 interposed. The base metal film 11 is not limited to this, but is formed of a multilayer film in which, for example, the metal film 11a and the metal film 11b are sequentially arranged from the back surface 1y side of the n-type substrate 1. For example, a Ni (nickel) film or a Ni / Cu (copper) film is used as the metal film 13a, and an Au (gold) film is used as the metal film 13b. The electrode 15 is not limited to this. For example, the electrode 15 is formed of a multilayer film in which a metal film 13a and a metal film 13b are sequentially arranged from the back surface 1y side of the n-type substrate 1, for example.

Next, the manufacture of the semiconductor device of this embodiment will be described with reference to FIGS.
First, as shown in FIG. 1, an n-type semiconductor substrate 1 made of single crystal silicon having a specific resistance of about 60 [Ωcm] is prepared, and then a p-type semiconductor shown in FIG. Region 2 and n-type semiconductor region 6 are formed. These semiconductor regions (2, 6) are formed by ion-implanting impurities into the main surface 1x of the n-type substrate 1 and then performing heat treatment for activating the impurities.

  Next, a groove 3 (see FIG. 4) is formed from the main surface 1x of the n-type substrate 1 in the depth direction, and then a gate insulating film 4 (for example, a silicon oxide film) is formed on the inner wall surface of the groove 3 (FIG. 4). And a gate electrode 5 (see FIG. 4) is formed by selectively embedding a conductor made of, for example, polycrystalline silicon in the groove 3, and then the n-type substrate 1 is formed. An insulating film 7 made of, for example, a silicon oxide film is formed on the main surface 1x, and then the insulating film 7 is patterned so that the insulating film 7 remains on the gate electrode 5.

  Next, as shown in FIG. 5, the wiring 9 is formed on the main surface 1 x of the n-type substrate 1. The wiring 9 is formed by sequentially forming, for example, a TiW film 9a and a Ti film 9b as refractory metal films, and then patterning these films. The melting point of the TiW film 9a is about 1800 ° C., and the melting point of the Ti film 9b is about 1680 ° C. In this step, the wiring 9 is electrically connected to the p-type semiconductor region 2.

  Next, the back surface 1y of the n-type substrate 1 is subjected to processing such as etching or grinding to reduce the thickness t of the n-type substrate 1 as shown in FIG. The n-type substrate 1 is thinned for the purpose of reducing thermal resistance.

Next, as shown in FIG. 7, a first impurity (for example, P (phosphorus)) for forming an n-type semiconductor region and a p-type semiconductor region are formed on the back surface 1 y of the n-type substrate 1. A second impurity (for example, B (boron)) is ion-implanted to form an n-type semiconductor region 10a and a p-type semiconductor region 10b on the back surface 1y of the n-type substrate 1 as shown in FIG. The ion implantation of the first impurity is performed, for example, under the conditions of an acceleration energy of about 300 KeV and a dose of about 1 to 10 × 10 ¹² [atoms / cm ² ]. The ion implantation of the second impurity is performed, for example, under the conditions of an acceleration energy of about 40 KeV and a dose of about 1 to 5 × 10 ¹⁵ [atoms / cm ² ].

  Next, a heat treatment is performed to activate each impurity in the n-type semiconductor region 10a and the p-type semiconductor region 10b. The heat treatment sufficiently activates impurities in the semiconductor regions (10a, 10b) and recovers crystal defects (damage recovery) generated on the back surface 1y of the n-type substrate 1 by ion implantation in these semiconductor region forming steps. It is performed at a temperature that can be performed, for example, a temperature of about 800 to 900 ° C. By this process, the trench type IGBT is almost completed.

  Next, a final protective film 12 made of, for example, polyimide resin is formed on the main surface 1x of the n-type substrate 1, and then a part of the wiring 9 is exposed to the final protective film 12 as shown in FIG. For this purpose, a bonding opening 12a is formed.

  Next, as shown in FIG. 10, an electrode 14 is formed in the bonding opening 12a, and an electrode 15 in contact with the base metal film 11 on the back surface 1y of the n-type substrate 1 is formed. The electrodes 14 and 15 are formed of, for example, a multilayer film in which a metal film 13a made of a Ni film or a Ni / Cu film and a metal film 13a made of an Au film are sequentially arranged.

Next, a protruding electrode 16 made of, for example, a solder bump is formed on the electrode 14. By this step, the structure shown in FIG. 1 is obtained.
Here, the characteristics of the trench type IGBT-20 are the activation of impurities in the n-type semiconductor region 10a and the p-type semiconductor region (collector region) 10b formed on the back surface 1y of the n-type substrate 1, and these semiconductor regions. Since it affects the recovery of crystal defects (damage) generated on the back surface 1y of the n-type substrate 1 by the ion implantation in the forming step (10a, 10b), it is necessary to sufficiently activate the impurities and recover the damage.

  In the present embodiment, the TiW film 9a and the Ti film 9b having a melting point higher than that of aluminum are used as the material of the wiring 9, and the heat resistance is improved after the heat treatment process for activating the impurities in the semiconductor regions (10a, 10b). Since the final protective film 12 made of an organic material that is inferior to an inorganic material such as a silicon oxide film, for example, a polyimide resin, is formed, the activation of impurities in the semiconductor regions (10a, 10b), and these Heat treatment can be performed at a temperature at which crystal defects (damage) generated on the back surface 1y of the n-type substrate 1 can be sufficiently recovered by ion implantation in the semiconductor region forming step, for example, at a temperature of 800 to 900 ° C. . Therefore, it is possible to improve the impurity activation rate of the semiconductor regions (10a, 10b) formed on the back surface 1y of the n-type substrate 1 by ion implantation and improve the damage recovery of the back surface 1y of the n-type substrate 1.

  Further, by improving the impurity activation rate of the semiconductor regions (10a, 10b) and improving the damage recovery of the back surface 1y of the n-type substrate 1, the p-type semiconductor region 10b to the n-type substrate 1 can be operated during the operation of the trench IGBT-20. Since the amount of holes injected into the n-type semiconductor region increases, the characteristics of the trench IGBT-20 can be improved.

  In this embodiment, the TiW film 9a and the Ti film 9b are used as the material of the wiring 9, but the material of the wiring 9 is a temperature at which the impurity is sufficiently activated in the heat treatment for activating the impurity in the semiconductor region. Any material having a melting point higher than (800 to 900 ° C.) and good conductivity may be used.

11 and 12 are schematic cross-sectional views showing the manufacturing steps of a semiconductor device that is a modification of the above-described embodiment.
In the above-described embodiment, the heat treatment for activating the impurities in the semiconductor regions (10a, 10b) is performed after the wiring 9 is formed. However, as shown in FIG. 11, the impurities in the semiconductor regions (10a, 10b) are removed. A heat treatment for activation may be performed, and then the wiring 9 may be formed on the main surface of the n-type substrate 1 as shown in FIG. In this case, even if a conventional aluminum film or Al alloy film having a low melting point is used as the material of the wiring 9, the same effect as in the above-described embodiment can be obtained.

Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.
For example, the present invention can be applied to a semiconductor device having a planar IGBT.

1 is an equivalent circuit diagram of a trench IGBT mounted in a semiconductor device according to an embodiment of the present invention. It is typical sectional drawing which shows the structure of the trench type IGBT of FIG. It is typical sectional drawing which shows the manufacturing process of the semiconductor device which is one Embodiment of this invention. FIG. 4 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 3; FIG. 5 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 4; FIG. 6 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 5; FIG. 7 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 6; FIG. 8 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 7; FIG. 9 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 8; FIG. 10 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 9; It is typical sectional drawing which shows the manufacturing process of the semiconductor device which is a modification of one Embodiment of this invention. 12 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 11; FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... n-type semiconductor substrate, 2 ... p-type semiconductor region, 3 ... groove | channel, 4 ... gate insulating film, 5 ... gate electrode, 6 ... n-type semiconductor region, 7 ... insulating film, 9 ... wiring, 9a ... TiW film, 9b ... Ti film, 10a ... n-type semiconductor region, 10b ... p-type semiconductor region, 11a ... Ni film, 11b ... Ti film, 12 ... final protective film, 12a ... bonding opening, 13a ... Ni film, 13b ... Au film, 14, 15 ... Electrodes

Claims (7)

(A) a step of forming a wiring on a main surface of a semiconductor substrate having a constant impurity concentration;
(B) step after forming the semiconductor region by ion-implanting impurities into the back surface opposite to the main surface of the semiconductor substrate after the (a) step;
(C) a step of performing a heat treatment for activating impurities in the semiconductor region after the step (b);
And (d) a step of forming a protective film made of a resin on the main surface of the semiconductor substrate after the step (c). In the manufacturing method of the semiconductor device according to claim 1,
The wiring method of manufacturing a semiconductor device characterized by comprising the semiconductor region impurity activated causing the metal film is higher melting point than the temperature of the heat treatment of. In the manufacturing method of the semiconductor device according to claim 1 or 2,
A method of manufacturing a semiconductor device, comprising the step of processing the back surface of the semiconductor substrate to reduce the thickness of the semiconductor substrate after the step (a) and before the step (b). . In the manufacturing method of the semiconductor device of any one of Claim 1, Claim 2, and Claim 3,
The method of manufacturing a semiconductor device, wherein the semiconductor region is a collector region of an insulated gate bipolar transistor. (A) a step of forming a semiconductor region by ion-implanting impurities into the back surface opposite to the main surface of the semiconductor substrate having a constant impurity concentration;
(B) a step of performing a heat treatment for activating impurities in the semiconductor region after the step (a);
(C) a step of forming wiring on the main surface of the semiconductor substrate after the step (b);
And (d) a step of forming a protective film made of a resin on the main surface of the semiconductor substrate after the step (c). In the manufacturing method of the semiconductor device according to claim 5,
Before the step (a), a method for manufacturing a semiconductor device, comprising a step of reducing the thickness of the semiconductor substrate by processing a back surface of the semiconductor substrate. In the manufacturing method of the semiconductor device according to claim 5 or 6,
The wiring Ri Do a high metal film melting point than the temperature of the heat treatment for activating the impurity of the semiconductor region,
The method of manufacturing a semiconductor device, wherein the semiconductor region is a collector region of an insulated gate bipolar transistor.

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