JP4767676B2 - Optical receiver - Google Patents

Description

  The present invention relates to an optical receiver capable of receiving a multi-level phase modulation signal, and particularly to an optical receiver capable of accurately and accurately decoding data included in a received signal.

  In the long-haul optical transmission system, an optical repeater amplification transmission system using an erbium-doped fiber amplifier (hereinafter abbreviated as “EDFA”) capable of directly amplifying light in the 1.5 μm band is mainly used. In recent years, a large-capacity optical transmission system using a wavelength division multiplexing transmission system has been realized by realizing an EDFA that can be amplified in a wide band.

  Also, in recent years when a further increase in capacity is required, effective use of the amplification band (for example, narrowing of the wavelength multiplexing interval) can be considered as one of means for realizing a large-capacity optical transmission system. In the case of a signal, the upper limit of frequency utilization efficiency of about 1 bit / s / Hz cannot be an effective solution.

  On the other hand, a multi-level modulation method has attracted attention as one of means for increasing frequency use efficiency. Among them, attention is particularly increasing on a differential quadrature phase shift keying (hereinafter abbreviated as “DQPSK”) method.

  In this DQPSK modulation method, a modulated signal obtained by modulating the phase of an optical carrier with an in-phase component and a quadrature component is transmitted, and on the receiving side, for example, delay detection by two 1-bit delay detectors is performed, so that two different intensities are obtained. This is a method of converting to a signal.

For example, light that transmits and receives differential M-phase shift keying (Differential M-ary Phase Shift Keying: hereinafter abbreviated as “DMPSK”) signal (M = 2 ⁿ : n is a natural number (DBPSK signal when n = 1)). An optical transceiver comprising optical filtering means for optically filtering each wavelength channel signal before generating a multiplexed signal obtained by wavelength multiplexing the DMPSK signal. (For example, Patent Document 1).

  Here, the optical transceiver shown in Patent Document 1 includes a light source, an integrated Mach-Zehnder modulator, an encoder, an optical coupler, and the like on the transmission side, and an optical coupler and two 1-bits on the reception side. A delay interferometer, two differential light receivers, and the like are provided.

Note that, as in Patent Document 1, two 1-bit delay interferometers and two differential optical receivers are provided on the receiving side because the bit rate of the optical transceiver is that of the optical signal processing unit. One reason is that it is determined not by the bit rate but by the bit rate of the electric signal processing unit. Therefore, for example, as can be seen in FIG. 3 of the same document, the input signal to the electric signal processing unit is made into two systems of signals x ₁ (t) and y ₂ (t), and the electric signal processing unit The bit rate is configured to be half that of the optical signal processing unit.

  In addition to the above items, the above-described two 1-bit delay interferometers are required to have high accuracy and stability with respect to the optical phase from the viewpoint of realizing a large-capacity and high-speed optical transmission system. The reason is that in the 1-bit delay interferometer, the quality of the output signal is greatly deteriorated due to a phase error caused by an internal factor (such as composition change) or an external factor (temperature, pressure change, etc.). For this reason, in realizing a large-capacity and high-speed optical transmission system, it is essential to apply advanced phase stabilization control technology to a receiving system including a 1-bit delay interferometer.

  On the other hand, as one of stabilization control methods applicable to the transmission of DPSK signals, the technique is disclosed in Non-Patent Document 1 below. If the technique shown in this document is applied to the above-mentioned Patent Document 1, it is expected to contribute to the phase stabilization of the optical signal. Specifically, phase stabilization control is performed on one 1-bit delay interferometer of the two 1-bit delay interferometers provided in the reception system of Patent Document 1, and the other 1-bit delay interferometer is used. On the other hand, by performing phase shift control of −π / 2, it is expected to stabilize the phase of the optical signal in the optical signal processing unit of the receiving system.

JP-T-2004-516743 B. Milivojevic et al. , “Practical 40 Gbit / s CSRZ-DPSK transmission system with signed online chromatographic detection detection”, ECOC2003, TU364

  However, in the optical transmitter / receiver disclosed in Patent Document 1, an optical signal branched by an optical coupler is input to two 1-bit delay interferometers, and signals processed by two differential optical receivers are output. In addition, it is undefined which signal of these two signals is processed by which differential optical receiver, and the logic (positive logic, inverted logic) is also undefined. The received data cannot be correctly and accurately decoded.

  The technique disclosed in Non-Patent Document 1 is a technique for ensuring the phase stabilization of the optical signal in the optical signal processing unit, and thus cannot be a solution to this type of problem.

  The present invention has been made in view of the above, and an object of the present invention is to provide an optical receiver capable of correctly and accurately decoding an optical modulation signal transmitted at high speed.

In order to solve the above-described problems and achieve the object, an optical receiver according to the present invention photoelectrically converts a received optical M-ary signal (M = 2 ^k : k is a natural number) into k electrical signals. M-ary signal receiving means for outputting k-system electrical signals from its output port; Demultiplexing means for demultiplexing the k-system electrical signals into m-bit (m is a natural number) parallel data; The m-bit parallel is based on the identification result for identifying the logic (positive logic, inverted logic) for each bit constituting the m-bit parallel data and the system to which each bit constituting the m-bit parallel data belongs. Receiving phase synchronization means for synchronizing the phase of data; and frame processing means for receiving a transmission frame composed of m-bit parallel data output from the reception phase synchronization means. To.

According to the optical receiver of the present invention, k-system electrical signals obtained by photoelectric conversion of optical M-ary signals (M = 2 ^k : k is a natural number) are output in parallel of m bits (m is a natural number). When data is demultiplexed and output, the logic (positive logic, inverted logic) for each bit constituting m-bit parallel data output after being demultiplexed and each bit constituting m-bit parallel data belong Since the phase synchronization of the m-bit parallel data is achieved based on the identification results for identifying the systems, the effect is obtained that the optical modulation signal transmitted at high speed can be correctly and accurately decoded.

  Embodiments of an optical receiver according to the present invention will be described below in detail with reference to the drawings. In addition, this invention is not limited by this embodiment.

Embodiment 1 FIG.
First, the optical receiver according to the first embodiment will be described. FIG. 1 is a diagram of a configuration of the optical receiving apparatus according to the first embodiment of the present invention. The optical receiver shown in the figure includes a DQPSK receiving unit 2 connected to a transmission line 1, a demultiplexing unit 3 that uses the output of the DQPSK receiving unit 2 as an input signal, and an output of the demultiplexing unit 3 as an input signal. The reception phase synchronization means 4 and the frame processing means 5 using the output of the reception phase synchronization means 4 as an input signal are provided.

  Next, the operation of the optical receiver shown in FIG. 1 will be described. In the figure, the optical DQPSK signal input from the transmission line 1 is photoelectrically converted into two systems of electric signals (Vk, Uk) by the DQPSK receiving means 2. These two electric signals are demultiplexed by the demultiplexing means 3 into m (m is a positive integer) bit parallel signals. This demultiplexed m-bit parallel signal is processed by the reception phase synchronization means 4 to invert / non-invert the logic of the odd bits and the logic of the even bits, and the one of the even bits (Vk, Uk). (Bit output) and odd bits (bit output of the other of Vk and Uk) are exchanged. In the frame processing means 5, predetermined reception processing is performed in which a m-bit parallel signal subjected to logic inversion / non-inversion processing and / or output system switching processing in the reception phase synchronization means 4 is used as a transmission frame. Note that the DQPSK signal transmitted at high speed is correctly and accurately decoded by the processing of the reception phase synchronization means 4.

  Next, the DQPSK signal input to the optical receiver as shown in FIG. 1 will be described with reference to FIG. FIG. 2 is a diagram illustrating a configuration example of an optical transmission device used as a pair with the optical reception device illustrated in FIG. 1. The optical transmission device receives a light source 28 and output light from the light source 28 as input. An integrated Mach-Zehnder modulator 29, and an encoder 30 that outputs a differential signal (modulated signal) to the integrated Mach-Zehnder modulator 29.

  In FIG. 2, the CW light output from the light source 28 is input to the integrated Mach-Zehnder modulator 29, and the integrated Mach-Zehnder modulator 29 converts the two differential signals (Ik, Qk) output from the encoder 30. Based on this, DQPSK modulation is performed and sent out to the transmission line. Note that two differential signals (Ik, Qk) for performing DQPSK modulation are generated by the encoder 30 based on the two systems of data signals (Vk, Uk). Further, in the integrated Mach-Zehnder modulator 29, for example, in the two waveguides 34 and 36 constituting itself, for example, an optical signal transmitted through the waveguide 34 and a waveguide whose optical phase is advanced by π / 2 with respect to this optical signal. A predetermined optical DQPSK signal is obtained by multiplexing the optical signal of the waveguide 36. In the encoder 30, for example, the following logical operation is performed.

  FIG. 3 is a diagram showing a configuration example of the DQPSK receiving unit 2 shown in FIG. In FIG. 3, the DQPSK receiving means 2 includes an optical coupler 6 connected to the transmission line 1, 1-bit delay interferometers 7 and 8 into which branch outputs of the optical coupler 6 are individually input, and a 1-bit delay interferometer 7 , 8 are connected to the respective differential optical receivers 9 and 10.

  Next, the operation of the DQPSK receiving unit 2 shown in FIG. 3 will be described. In the figure, the optical DQPSK signal input from the transmission line 1 is equally branched by the optical coupler 6 and input to the two 1-bit delay interferometers 7 and 8, respectively. In the 1-bit delay interferometers 7 and 8, optical phase difference information with adjacent bits is converted into optical intensity information. At this time, the phase shift amount imparted to one optical DQPSK signal input to the 1-bit delay interferometer 7 and the phase shift amount imparted to the other optical DQPSK signal input to the 1-bit delay interferometer 8 are “ Processing is performed to obtain a phase difference of “π / 2”. In the example shown in the figure, phase shifts of “π / 4” and “−π / 4” are applied to the optical phases of the optical DQPSK signals input to the two 1-bit delay interferometers 7 and 8, respectively. Has been. The outputs of the 1-bit delay interferometers 7 and 8 are photoelectrically converted by the two differential light receivers 9 and 10 arranged in the subsequent stages, respectively, and processed in the subsequent stage as two data signals (Vk, Uk). Is output.

  In FIG. 3, for the sake of convenience, the output of the differential photoreceiver 9 is Vk and the output of the differential photoreceiver 10 is Uk. However, in reality, these outputs are two systems defined on the transmission side. There is no guarantee that the data signals (Vk, Uk) will match exactly. It should be noted that this situation has already occurred.

  This situation will be described in detail with reference to FIG. 3. First, it is undefined which of the 1-bit delay interferometers 7 and 8 decodes the two systems of data signals (Vk, Uk) (hereinafter, This property is called “output port uncertainty”). Furthermore, whether each logic of the two systems of data signals (Vk, Uk) is output as positive logic or inverted logic is undefined (similarly, this property is referred to as “logic uncertainty”). Called). The data output from the DQPSK receiving means 2 is output with these “output port uncertainties” and “logic uncertainties”, and the subsequent demultiplexing means 3 Processing is performed while maintaining the characteristics. Further, these characteristics are eliminated by processing of the reception phase synchronization means 4 described later.

  Next, processing performed by the demultiplexing unit 3 shown in FIG. 1 will be described using a specific format example. FIG. 4 shows an ITU-T (International Telecommunication Union Telecommunication Standardization Sector) G. 709 is a configuration diagram showing a 40 Gbit / s transmission frame in OTN (Optical Transport Unit) shown in the 709 recommendation, and overhead (OH: Over Head) carrying payload for carrying actual user data and information for maintenance operation And a redundant area (FEC: Forward Error Correction) of an error correction code for improving transmission quality. As shown in the figure, in OH, a FA (Frame Alignment) OH area in which a fixed pattern for frame synchronization is stored, and an OTU3 (Optical Transport Unit -3) OH area in which other maintenance operation information is stored. , ODU3 (Optical Data Unit-3) OH region and OPU3 (Optical Payload Unit-3) OH region.

  FIG. 5 is a diagram showing a detailed format of FAOH, which is composed of a 3-byte bit string “11110110”, a 3-byte bit string “00101001”, and a 1-byte multiframe identification byte called MFAS (MultiFrame Alignment Signal). ing. On the receiving side, frame synchronization is established by examining the fixed pattern composed of these “11110110” and “00101000”.

  The transmission frame shown in FIG. 3 is output to the demultiplexing unit 3 after being received by the DQPSK receiving unit 2. The demultiplexing means 3 outputs an m-bit data string subjected to demultiplexing.

  Further, as described above, both of the two systems of data signals (Vk, Uk) output from the DQPSK receiving means 2 are output with “output port uncertainty” and “logic uncertainty”. Therefore, the signal output from the demultiplexing means 3 is also a signal having these characteristics. That is, it is undefined which of the odd and even bits of the m-bit parallel data output from the demultiplexing means 3 is Vk or Uk, and the logic of the odd and even bits is also undefined.

  FIG. 6 is a diagram showing a detailed configuration of the optical receiver shown in FIG. 1, and in particular, a diagram showing a detailed configuration of the frame synchronization circuit 12 that embodies the reception phase synchronization means 4 in FIG. In FIG. 6, the frame synchronization circuit 12 receives the output of the 2: m demultiplexing circuit 11 that implements the demultiplexing means 3 of FIG. 1 as an input signal, and outputs the phase determination result to the phase control circuit 1209. And a frame provided corresponding to eight types of frame patterns determined by “output port uncertainty” and “logic uncertainty” at the output of the phase determination circuit 1210 and the 2: m demultiplexing circuit 11 The pattern detection circuits 1201 to 1208, a synchronization protection circuit 1211 that protects frame synchronization, and a frame counting circuit 1212 that counts the number of frames and generates a predetermined timing signal.

  Next, the operation of the frame synchronization circuit 12 shown in FIG. 6 will be described. In the figure, two data signals output from DQPSK receiving means 2 (because they have uncertainties, they are expressed as “Vk / Uk” and “Uk / Vk”, respectively): 2: m demultiplexing The data is converted into m-bit parallel data by the circuit 11 and input to the frame synchronization circuit 12. The frame synchronization circuit 12 is input to eight types of frame pattern detection circuits 1201 to 1208 and a phase control circuit 1209. These frame pattern detection circuits 1201 to 1208 detect phase patterns corresponding to the respective phases, and output the detection results to the phase determination circuit 1210. For example, when the upper end output and the lower end output of the DQPSK signal means 2 in FIG. 6 are Vk and Uk, respectively, and the logic of both outputs is positive logic, the detection result in the frame pattern detection circuit 1201 is the phase determination circuit. It is output to 1210.

  The phase determination circuit 1210 determines at which phase the frame pattern is detected based on the frame pattern detection results from the frame pattern detection circuits 1201 to 1208 and instructs the phase control circuit 1209 to perform the corresponding phase control. At the same time, the determination result of the frame pattern detection is output to the frame synchronization protection circuit 1211. The frame synchronization protection circuit 1211 performs control corresponding to the front protection state / rear protection state / hunting state for the frame counting circuit 1212 and the phase determination circuit 1210 in accordance with the timing signal from the frame counting circuit 1212.

  The operation of the frame synchronization circuit 12 shown in FIG. 6 will be described based on the state of the FAOH pattern shown in FIG. FIG. 7 is a diagram illustrating the state of the bits of the FAOH pattern that change in accordance with “output port uncertainty” and “logic uncertainty”.

  First, in a light input cutoff state, frame synchronization is lost, and the frame synchronization circuit 12 enters a hunting state, and the frame patterns are sequentially verified. When the optical input is restored, the two data signals (Vk, Uk) from the DQPSK receiving means 2 have “output port uncertainty” and “logic uncertainty”. It is undefined whether odd-numbered bits or even-numbered bits of m-bit parallel data input to Vk is Vk or Uk, and the logic of odd-numbered bits and even-numbered bits is also undefined.

  On the other hand, in the frame synchronization circuit 12, for example, the frame pattern detection circuit 1201 detects the FAOH pattern of FIG. 7A that appears when the odd bits are Vk and positive logic, and the even bits are Uk and positive logic. The frame pattern detection circuit 1202 detects the FAOH pattern shown in FIG. 7 (2) which appears when the bit is Vk and positive logic, and the even bit is Uk and inverted logic, and the odd bit is Vk and inverted logic and even bit The frame pattern detection circuit 1203 detects the FAOH pattern shown in FIG. 7 (3) that appears when Uk is positive logic and Uk. In the same manner, when odd bits are Uk and inverted logic, and even bits are Vk and inverted logic. The frame pattern detection circuit 1208 detects the FAOH pattern shown in FIG. Here, a case where the DQPSK signal multiplexed on the transmission side on the transmission side is transmitted to the transmission line as an odd bit of the transmission frame is Vk and positive logic and an even bit is Uk and positive logic will be described as an example. is doing.

  As described above, the phase determination circuit 1210 determines which of the frame pattern detection circuits 1201 to 1208 having the eight types of frame patterns has been detected, and for example, when the frame pattern detection circuit 1201 detects the frame pattern. Indicates that the phase control circuit 1209 does not perform inversion control or odd-numbered and even-numbered bit swapping control, and when detected from the frame pattern detection circuit 1208, the phase control circuit 1209 causes the odd-numbered and even-numbered bits to be controlled. By instructing to perform the inversion control and the odd-numbered bit and even-numbered bit switching control, the transmission frame shown in FIG. 4 is output from the frame synchronization circuit in the normal bit order and logic.

  When a frame pattern is detected several times continuously from any one of the frame pattern detection circuits 1201 to 1208, the synchronization protection circuit 1211 changes the control state of the phase control circuit 1209 to shift to the forward protection state. The phase determination circuit 1210 is instructed to hold the state at the end of the rear protection state. In the forward protection state, only one output of the frame pattern detection circuits 1201 to 1208 in which the frame pattern is detected at the end of the rear protection state is monitored, and the frame pattern is not detected continuously for a plurality of frames. Then, it is determined that the frame is out of synchronization, the state is shifted to the hunting state, and the same operation as described above is performed again.

  As described above, the frame synchronization circuit according to this embodiment is configured to provide frame synchronization by providing a plurality of frame pattern detection circuits corresponding to the order and logic of Vk and Uk as the outputs of the two systems. Therefore, for example, ITU-T G. It becomes possible to apply the DQPSK optical transmission system to the transmission system of the OTN frame as shown in 709.

  In this embodiment, the OTN frame has been described as an example, but the same effect can be obtained for an SDH (Synchronous Digital Hierarchy) frame. Further, it goes without saying that the same effect can be obtained as long as the transmission frame is based on the assumption that a fixed pattern is detected and frame synchronization is taken regardless of these frames.

  In this embodiment, the configuration example in the case of receiving the DQPSK signal modulated based on the two data signals (Vk, Uk) transmitted from the transmitting device side is shown. It is not limited to. For example, it is possible to receive a DQPSK signal modulated based on three systems of data signals (Vk, Uk, Wk) from the transmission device side. In this case, in the configuration of the optical receiving apparatus shown in FIG. 6, three data signals (Vk, Uk, Wk) having uncertainty are output from the three ports of the DQPSK receiving means. Instead of the: m demultiplexing circuit 11, a 3: m demultiplexing circuit may be provided. If only one system data signal (Vk) is used, a 1: m demultiplexing circuit may be provided.

In addition, when three types of data signals are used, the bit rate of the electrical signal processing unit can be reduced to 1/3 that of the optical signal processing unit. Similarly, when any M-ary signal satisfying M = 2 ^k (k is a natural number) is used in the optical signal processing unit, the electrical signal processing unit can process the k-system data signals in parallel. The bit rate of the processing unit can be set to 1 / k of the optical signal processing unit. When any M-ary signal satisfying M = 2 ^k (k is a natural number) is used, it is not necessary to set the number of systems of data signals to be processed in parallel by the electric signal processing unit to k, and the number of k or less Any natural number can be used.

If three data signals are used, the frame synchronization circuit 12 shown in FIG. 6 may be provided with several types of frame pattern detection circuits corresponding to the order of bit strings output from the 3: m demultiplexing circuit. Good.
For example, when the output is performed in the order of Vk, Uk, Wk from the 3: m demultiplexing circuit, the following eight frame pattern detection circuits corresponding to this case may be provided.
(1) Vk positive logic / Uk positive logic / Wk positive logic frame pattern detection circuit (2) Vk positive logic / Uk positive logic / Wk inversion logic frame pattern detection circuit (3) Vk positive logic / Uk inversion logic / Wk positive logic Frame pattern detection circuit (4) Vk positive logic / Uk inversion logic / Wk inversion logic Frame pattern detection circuit (5) Vk inversion logic / Uk positive logic / Wk positive logic Frame pattern detection circuit (6) Vk inversion logic / Uk positive logic / Wk inversion logic frame pattern detection circuit (7) Vk inversion logic / Uk inversion logic / Wk positive logic frame pattern detection circuit (8) Vk inversion logic / Uk inversion logic / Wk inversion logic frame pattern detection circuit Vk, Wk, Uk), (Uk, Vk, Wk), (Uk, Wk, Vk), (Wk, Uk, Vk), (Wk, Vk, Uk) In One sequence pattern, the eight frame pattern detection circuits corresponding to the respective order may be as provided for each ordering pattern.

Further, throughout the present embodiment, one configuration for processing a DMPSK signal has been described as an example. For example, as shown in FIG. 6, frame pattern detection from frame pattern detection circuits 1201 to 1208 is performed. Based on the result, it is determined at which phase the frame pattern is detected, and the application target of this method for performing the corresponding phase control is not limited to the DMPSK signal, and two or more modulations are performed. The present invention can also be applied to the binary and multi-level modulated signals, for example, it can be applied to k-system electrical signals of M-ary modulated signals (M = 2 ^k : k is a natural number). Is possible.

Embodiment 2. FIG.
FIG. 8 is a diagram illustrating the configuration of the optical receiving apparatus according to the second embodiment of the present invention, and more specifically illustrates the configuration for processing the OTN frame, corresponding to FIG. 8 includes a DQPSK receiving unit 2 that receives an optical reception signal, a deserializer 13 that receives two output signals (Vk, Uk) of the DQPSK receiving unit 2, and an output signal of the deserializer 13. And an OTN framer 16 having the input signal as an input signal. Further, as its detailed configuration, the deserializer 13 includes an output of the 2:16 bit demultiplexing circuit 14 to which two output signals (Vk, Uk) of the DQPSK receiving unit 2 are input and the output of the 2:16 bit demultiplexing circuit 14. SFI-5 (SERDES (SERializer DEserializer) Framer interface level-5) transmission circuit 15, and the OTN framer 16 is an SFI-5 reception circuit to which the output signal of the SFI-5 transmission circuit 15 is input. 17, the frame synchronization circuit 12 using the output of the SFI-5 reception circuit 17 as an input signal, the OTNOH processing circuit 18 using the output of the frame synchronization circuit 12 as an input signal, and the output of the OTNOH processing circuit 18 as an input signal. SFI-5 transmission circuit 15.

  Next, the operation of the optical receiver shown in FIG. 8 will be described. In the figure, the deserializer 13 expands two data signals from the DQPSK receiving means 2 in parallel to 16 bits, and then adds one bit of the deskew channel as SFI-5 standardized in OIF (Optical Internet Forum). 17 parallel data is output to the OTN framer 16. The OTN framer 16 absorbs 17 data delay differences between the deserializer 13 and the OTN framer 16 in the SFI-5 receiving circuit, and outputs 16-bit parallel data excluding the deskew channel to the frame synchronization circuit 12 To do. The frame synchronization circuit 12 performs the operation shown in the first embodiment, and sets Vk and Uk to normal logic and order. Thereafter, the OTN framer 16 performs OTN OH processing and the like, and again adds a deskew channel in the SFI-5 transmission circuit 15 and outputs 17 data.

  As described above, in the optical receiving apparatus of this embodiment, the OTN framer is configured to include the frame synchronization circuit described in the first embodiment. It is possible to correctly and accurately decode the DQPSK signal mounted in the OTN frame indicated in the 709 recommendation.

Embodiment 3 FIG.
FIG. 9 is a diagram of a configuration of the optical receiving apparatus according to the third embodiment of the present invention. The optical receiver shown in FIG. 9 is configured to include a deserializer 19 including the frame synchronization circuit 12 shown in the first embodiment, instead of the configuration of the deserializer 13 shown in FIG. Also, with this configuration, the OTN framer 20 is provided with a frame synchronization circuit 21 having a normal frame synchronization function, which is used for general binary transmission. Other configurations are the same as or equivalent to those of the second embodiment shown in FIG. 8, and the same reference numerals are given to these common components, and the description thereof is omitted.

  As in this embodiment, the frame synchronization circuit shown in the first embodiment may be provided not only in the OTN framer but also in the deserializer, and an optical receiver capable of correctly and accurately decoding the DQPSK signal is obtained. In addition, it is possible to ensure design flexibility when configuring the optical receiver.

Embodiment 4 FIG.
FIG. 10 is a diagram of a configuration of the optical receiving apparatus according to the fourth embodiment of the present invention. In the configuration of FIG. 6 according to the first embodiment, the optical receiving device shown in FIG. 6 includes a frame synchronization circuit 21 having a normal frame synchronization function as the frame synchronization circuit. A phase synchronization circuit 22 is provided between 21 and the 2: m demultiplexing circuit 11. The phase synchronization circuit 22 includes a phase search circuit 23 that uses the output of the frame synchronization circuit 21 as an input signal, and a phase control circuit 24 that uses the output of the phase search circuit 23 as an input signal. In addition, about another structure, it is the same as that of the structure shown in FIG. 6, or the same code | symbol is attached | subjected to these common components, and the description is abbreviate | omitted.

  Next, the operation of the optical receiver shown in FIG. 10 will be described with reference to FIG. 10 and FIG. FIG. 11 is a flowchart showing a processing procedure for establishing frame synchronization in the phase synchronization circuit 22 shown in FIG.

  In FIG. 10, the phase search circuit 23 detects a loss of frame synchronization based on the status signal of the frame synchronization circuit 21. The phase search circuit 23 that has detected the loss of frame synchronization performs phase control at the input to the phase control circuit 24, corresponding to the states “Vk is an odd bit and positive logic” and “Uk is an even bit and positive logic”. This is performed for the circuit 24 (step 101 in FIG. 11), and this state is maintained for a predetermined search time. At this time, if the out-of-frame synchronization generated in the frame synchronization circuit 21 is canceled within a predetermined search time, it is assumed that the frame synchronization is established (step 102, Yes in FIG. 11), and this control is performed. Complete. On the other hand, if the out of frame synchronization generated in the frame synchronization circuit 21 within the predetermined search time is not canceled, it is assumed that the frame synchronization has not been established (step 102, No in FIG. 11), that is, the following state: At the input of the phase control circuit 24, control corresponding to each state of “Vk is an odd bit and positive logic” and “Uk is an even bit and inverted logic” is performed on the phase control circuit 24 (step 103 in FIG. 11). ). Subsequently, the control based on the flow of steps 104 to S116 in FIG. 11 is sequentially performed to search for a state in which the frame synchronization loss is released. In each state, the search time for searching whether or not frame synchronization is lost may be set to a value larger than N times (N is a positive integer) the average synchronization establishment time of the transmission frame, for example.

  As described above, in the phase synchronization circuit in the optical receiver of this embodiment, when the synchronization of the frame synchronization circuit is out of sync, for example, the order and logic of Vk and Uk of the data signal are searched and controlled. ITU-T G. It becomes possible to apply the DQPSK optical transmission system to the transmission system of the OTN frame as shown in 709.

  Also in this embodiment, regardless of the above-mentioned OTN frame, if the transmission frame is based on the assumption that a fixed pattern is detected and frame synchronization is achieved, the same effect as in the above case can be obtained. Needless to say.

  Moreover, in this embodiment, although the example of a structure in the case of receiving the DQPSK signal modulated based on the data signal (Vk, Uk) of 2 systems transmitted from the transmitter side was shown, arbitrary 3 systems or more It can be applied to other data signals.

Further, the application target of the phase control method according to this embodiment is not limited to the DMPSK signal including the DQPSK signal, and the binary and multilevel phase modulation signals subjected to two or more modulations are applied. For example, the present invention can be applied to k-system electrical signals of M-ary modulation signals (M = 2 ^k : k is a natural number).

Embodiment 5 FIG.
FIG. 12 is a diagram of a configuration of the optical receiving apparatus according to the fifth embodiment of the present invention. The optical receiver shown in FIG. 8 is configured to include the phase synchronization circuit 22 shown in FIG. 10 according to the fourth embodiment on the output side of the SFI-5 receiver circuit 17 in the OTN framer 16 shown in FIG. The With this configuration, the OTN framer 20 can be provided with a simple frame synchronization circuit 21 having a normal frame synchronization function used for general binary transmission. Other configurations are the same as or equivalent to those of the second embodiment shown in FIG. 8, and the same reference numerals are given to these common components, and the description thereof is omitted.

  Even in the optical receiver configured as described above, it is possible to receive a DMPSK signal such as a DQPSK signal and decode it correctly and accurately, as in the first to fourth embodiments. The present embodiment can also be applied to a multi-level phase modulation signal that has been subjected to two or more phase modulations, and can obtain the same effects as those of the first to fourth embodiments.

Embodiment 6 FIG.
FIG. 13 is a diagram of a configuration of the optical receiving apparatus according to the sixth embodiment of the present invention. The optical receiver shown in FIG. 9 is configured to include a deserializer 26 including the phase synchronization circuit 22 shown in FIG. 10 according to the fourth embodiment, instead of the configuration of the deserializer 13 shown in FIG. That is, the function of the frame synchronization circuit 12 provided in the deserializer 13 according to the third embodiment shown in FIG. 9 is replaced with the function of the phase synchronization circuit 22 according to the fourth embodiment. The other configuration is the same as or equivalent to the configuration of the third embodiment shown in FIG. 9, and the common components are denoted by the same reference numerals and the description thereof is omitted.

  Even in the optical receiving apparatus configured as described above, the DMPSK signal including the DQPSK signal can be received and decoded correctly and accurately, as in the first to fifth embodiments. The present embodiment can also be applied to a multi-level phase modulation signal that has been subjected to two or more phase modulations, and can obtain the same effects as those of the first to fifth embodiments.

Embodiment 7 FIG.
FIG. 14 is a diagram illustrating a configuration of a frame synchronization circuit of the optical reception device according to the seventh embodiment of the present invention. The frame synchronization circuit 27 shown in the figure is configured such that the mode setting signal is input to the frame synchronization circuit 27 in the configuration of the frame synchronization circuit 12 shown in FIG. The other configuration is the same as that of the frame synchronization circuit 27 shown in FIG. 6, and the common components are denoted by the same reference numerals and description thereof is omitted.

  According to the configuration shown in FIG. 14, for example, normal binary modulation is enabled by enabling only the frame pattern detection circuit 1201 corresponding to the case where the odd bits are Vk and positive logic and the even bits are Uk and positive logic. It can be applied to an optical transmission system using

  Similarly, the frame pattern detection circuit 1201 corresponding to the case where the odd bits are Vk and positive logic, and the even bits are Uk and positive logic, and the odd bits are Vk and inverted logic, and the even bits are Uk and inverted logic. By enabling both of the frame pattern detection circuit 1204 corresponding to the case, it is possible to correspond to an optical transmission system using DPSK, and by enabling all the frame pattern detection circuits 1201 to 1208, the DQPSK signal It is possible to correspond to an optical transmission system that receives a signal.

  Further, in order to further reduce the bit rate of the electrical signal processing unit, for example, when using the three data signals (Vk, Uk, Wk) as described above, the 48 types shown in the first embodiment are used. All of them may be validated by using the frame pattern detection circuit.

  As described above, the frame synchronization circuit of the optical receiver according to this embodiment is configured to select a frame pattern detection circuit that is effective based on the mode setting signal, so that an optical transmission system using various modulation schemes. Can be obtained.

  As described above, the optical receiving apparatus according to the present invention is useful as an optical receiving apparatus that can receive a multi-level phase modulation signal correctly and accurately.

It is a figure which shows the structure of the optical receiver concerning Embodiment 1 of this invention. It is a figure which shows the example of 1 structure of the optical transmitter used by a pair with the optical receiver shown in FIG. It is a figure which shows one structural example of the DQPSK receiving means 2 shown in FIG. ITU-T G. FIG. 7 is a configuration diagram showing a 40 Gbit / s transmission frame in the OTN indicated in the 709 recommendation. It is a figure which shows the detailed format of FAOH. It is a figure which shows the detailed structure of the optical receiver shown in FIG. It is a figure which shows the state of the bit of FAOH which changes according to "output port uncertainty" and "logic uncertainty". It is a figure which shows the structure of the optical receiver concerning Embodiment 2 of this invention. It is a figure which shows the structure of the optical receiver concerning Embodiment 3 of this invention. It is a figure which shows the structure of the optical receiver concerning Embodiment 4 of this invention. It is a flowchart which shows the process sequence of the frame synchronization establishment in the phase synchronization circuit shown in FIG. It is a figure which shows the structure of the optical receiver concerning Embodiment 5 of this invention. It is a figure which shows the structure of the optical receiver concerning Embodiment 6 of this invention. It is a figure which shows the structure of the frame synchronizing circuit of the optical receiver concerning Embodiment 7 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Transmission path 2 DQPSK receiving means 3 Demultiplexing means 4 Reception phase synchronizing means 5 Frame processing means 6 Optical coupler 7,8 1-bit delay interferometer 9,10 Differential light receiver 11 2: m demultiplexing circuit 12 Frame synchronizing circuit 13 Deserializer 14 2: 16-bit demultiplexing circuit 15 SFI-5 transmission circuit 16, 20 OTN framer 17 SFI-5 reception circuit 18 OTNOH processing circuit 19, 26 Deserializer 21, 27 Frame synchronization circuit 22 Phase synchronization circuit 23 Phase retrieval circuit 24 Phase Control circuit 28 Light source 29 Integrated Mach-Zehnder modulator 30 Encoder 34, 36 Waveguide 1201-1208 Frame pattern detection circuit 1209 Phase control circuit 1210 Phase determination circuit 1211 Synchronization protection circuit 1212 Frame counting circuit

Claims (12)

M-ary signal receiving means for photoelectrically converting the received optical M-ary signal (M = 2 ^k : k is a natural number) into k electrical signals and outputting them as k-system electrical signals from its own output port;
Demultiplexing means for demultiplexing the k-system electrical signals into m-bit (m is a natural number) parallel data;
Based on the identification results for identifying the logic (positive logic, inverted logic) for each bit in each bit string of the demultiplexed m-bit parallel data and the system to which each bit in each bit string belongs, respectively, The m-bit parallel data is configured by appropriately selecting a logic inversion / non-inversion process for each of the odd and even bits in the bit string and a swap process between the odd and even bits. Receiving phase synchronization means for synchronizing transmission frames;
Frame processing means for receiving a transmission frame output from the reception phase synchronization means;
Equipped with a,
The demultiplexing means is composed of a 1: m demultiplexing circuit that converts a 1-input data signal into m-bit parallel data,
The reception phase synchronization means includes
A frame pattern detection circuit for detecting a predetermined frame pattern included in the transmission frame by using a transmission frame composed of m-bit parallel data output from the 1: m demultiplexing circuit as an input;
A phase determination circuit for determining in which phase the predetermined frame pattern detected by the frame pattern detection circuit is detected;
Normal by performing control to appropriately select a logic inversion process or non-inversion process for a bit string constituting the m-bit parallel data based on the determination result of the phase determination circuit, which is arranged at the subsequent stage of the frame pattern detection circuit A phase control circuit that outputs a transmission frame constituted by a bit string having a certain logic as a transmission frame that is received and processed by the frame processing means;
An optical receiver characterized by comprising: M-ary signal receiving means for photoelectrically converting the received optical M-adic signal (M is an integer of 2 or more) into two electric signals and outputting the two electric signals from its output port;
Demultiplexing means for demultiplexing the two electric signals into m-bit (m is a natural number) parallel data;
Based on the identification results for identifying the logic (positive logic, inverted logic) for each bit in each bit string of the demultiplexed m-bit parallel data and the system to which each bit in each bit string belongs, respectively, It is configured by the m-bit parallel data by appropriately selecting a logic inversion process or non-inversion process for each of the odd and even bits in the bit string and a swap process between the odd and even bits. Receiving phase synchronization means for synchronizing transmission frames;
Frame processing means for receiving a transmission frame output from the reception phase synchronization means;
With
The demultiplexing means is composed of a 2: m demultiplexing circuit for converting a 2-input data signal into m-bit parallel data,
The reception phase synchronization means includes
A frame pattern detection circuit for detecting a predetermined frame pattern included in the transmission frame by using a transmission frame composed of m-bit parallel data output from the 2: m demultiplexing circuit as an input;
A phase determination circuit for determining in which phase the predetermined frame pattern detected by the frame pattern detection circuit is detected;
Logic inversion processing or non-inversion processing for each of odd bits and even bits of a bit string that is arranged in a subsequent stage of the frame pattern detection circuit and forms the m-bit parallel data based on a determination result of the phase determination circuit ; output as a transmission frame in which the frame processing unit a transmission frame composed of a normal logic and bit ordering the bit stream is received treatment by controlling appropriately selecting the replacement process between the odd bits and the even bits A phase control circuit to
Optical receiver you comprising the. The frame pattern detection circuit includes an odd bit logic (positive logic, inverted logic), an even bit logic (positive logic, inverted logic), and an odd bit and an even bit in a bit string constituting the predetermined frame pattern. 3. The optical receiving apparatus according to claim 2 , comprising eight types of frame pattern detection circuits corresponding to combinations of eight frame patterns with respect to the order. Before SL frame pattern detection circuit, a logic (positive logic, inverted logic) in the bit string constituting said predetermined frame pattern being constituted by two corresponding to the combination of a frame pattern of two types with respect to the frame pattern detection circuit The optical receiver according to claim 1. Claim 3 or 4, characterized in that a settable whether to enable or disable a specific frame pattern detection circuit of the plurality of frame pattern detection circuit constituting the frame sync circuit individually Optical receiver. M-ary signal receiving means for photoelectrically converting the received optical M-adic signal (M is an integer of 2 or more) into two electric signals and outputting the two electric signals from its output port;
Demultiplexing means for demultiplexing the two electric signals into m-bit (m is a natural number) parallel data;
Based on the identification results for identifying the logic (positive logic, inverted logic) for each bit in each bit string of the demultiplexed m-bit parallel data and the system to which each bit in each bit string belongs, respectively, The m-bit parallel data is configured by appropriately selecting a logic inversion / non-inversion process for each of the odd and even bits in the bit string and a swap process between the odd and even bits. Receiving phase synchronization means for synchronizing transmission frames;
Frame processing means for receiving a transmission frame output from the reception phase synchronization means;
With
The demultiplexing means is composed of a 2: m demultiplexing circuit for converting a 2-input data signal into m-bit parallel data,
The reception phase synchronization means includes
A phase synchronization circuit that performs synchronization control according to a frame synchronization loss of a transmission frame configured by m-bit parallel data output from the 2: m demultiplexing circuit;
A frame synchronization circuit for synchronizing transmission frames output from the phase synchronization circuit;
With
The phase synchronization circuit includes:
A phase search circuit for searching for a logic and a signal sequence when a frame synchronization loss of a transmission frame constituted by the m-bit parallel data is canceled based on a state signal output from the frame synchronization circuit;
And inversion processing or noninverting processing logic for each of the odd bits and even bits of the bit string constituting the m-bit parallel data according to the control instruction from the phase search circuit, and a switching process between the odd bits and the even bits A phase control circuit that outputs a transmission frame constituted by a bit string in a normal logic and bit order by performing appropriate selection control as a transmission frame for reception processing by the frame processing unit ;
Optical receiver you comprising the. M-ary signal receiving means for photoelectrically converting the received optical M-ary signal (M = 2 ^k : k is a natural number) into k electrical signals and outputting them as k-system electrical signals from its own output port;
Demultiplexing means for demultiplexing the k-system electrical signals into m-bit (m is a natural number) parallel data;
Based on the identification results for identifying the logic (positive logic, inverted logic) for each bit in each bit string of the demultiplexed m-bit parallel data and the system to which each bit in each bit string belongs, respectively, The m-bit parallel data is configured by appropriately selecting a logic inversion / non-inversion process for each of the odd and even bits in the bit string and a swap process between the odd and even bits. Receiving phase synchronization means for synchronizing transmission frames;
Frame processing means for receiving a transmission frame output from the reception phase synchronization means;
Equipped with a,
The demultiplexing means is composed of a 1: m demultiplexing circuit that converts a 1-input data signal into m-bit parallel data,
The reception phase synchronization means includes
A phase synchronization circuit that performs synchronization control according to a frame synchronization loss of a transmission frame composed of m-bit parallel data output from the 1: m demultiplexing circuit;
A frame synchronization circuit for synchronizing transmission frames output from the phase synchronization circuit;
With
The phase synchronization circuit includes:
A phase search circuit for searching for a logic and a signal sequence when a frame synchronization loss of a transmission frame constituted by the m-bit parallel data is canceled based on a state signal output from the frame synchronization circuit;
A transmission frame constituted by a bit string having a normal logic by performing control to appropriately select a logic inversion process or non-inversion process for the bit string constituting the m-bit parallel data according to the control instruction of the phase search circuit. A phase control circuit that outputs a transmission frame to be received and processed by the frame processing means ;
Optical receiver you comprising the. The optical receiving apparatus according to claim 6 or 7 , wherein a control instruction from the phase search circuit to the phase control circuit is held for a predetermined search time. The phase search circuit performs logic inversion processing / non-inversion processing for each of an odd bit and an even bit of a bit string constituting the m-bit parallel data until the loss of frame synchronization is canceled when the frame synchronization is lost. 7. The optical receiver according to claim 6 , wherein the replacement process between the odd bits and the even bits is sequentially changed at predetermined search times. The phase search circuit sequentially changes logic inversion processing / non-inversion processing for the bit string constituting the m-bit parallel data at every predetermined search time until the frame synchronization loss is canceled when the frame synchronization is lost. optical receiver according be carried out in the claim 7 or 8, wherein. The search time for searching whether or not the frame synchronization is lost is set to a value larger than N times (N is a positive integer) the average synchronization establishment time of the transmission frame composed of the m-bit parallel data. The optical receiver according to any one of claims 6 to 10 , wherein the optical receiver is configured as described above. A mode setting signal for setting an operation mode according to the type of the optical M signal is input to the frame synchronization circuit, and the validity / invalidity of the frame pattern detection circuit is controlled based on the mode setting signal. The optical receiver according to claim 5 .

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