JP4763218B2 - Method for manufacturing gate electrode - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a gate electrode capable of efficiently manufacturing a fine gate electrode by thickening a resist opening for a gate electrode formed by normal electron beam drawing and reducing the opening size, and the gate electrode A gate electrode suitable for a field effect transistor, which is manufactured by the above manufacturing method and has excellent high-frequency characteristics and is useful as a device for transmitting / receiving quasi-millimeter / millimeter-wave charged waves or for high-speed signal processing (for optical communication), and the date electrode The present invention relates to a semiconductor device using the semiconductor device and a manufacturing method thereof.
[0002]
[Prior art]
A field effect transistor having excellent high frequency characteristics is useful as a device for transmitting / receiving quasi-millimeter / millimeter-wave charged waves or a device for high-speed signal processing (for optical communication). Among these, in the development of gate electrodes that are used in devices that require particularly high-frequency characteristics, it is possible to make gate openings as short as possible by forming fine openings for gate formation using electron beam drawing. It has been actively performed.
Conventionally, in order to finely form an opening for forming a gate by using electron beam drawing, (1) the size of the electron beam itself used for drawing is made fine and drawing is performed, and (2) the gate forming is made. It has been considered to reduce the size of the opening by heat-treating the resist for forming the opening to thermally soften it.
[0003]
However, these cases have the following problems. That is, in the case of the above (1), although the electron beam diameter can be miniaturized to about 0.04 μm with the existing technology, it is still sufficient in consideration of the manufacturing stability when thousands of transistors are integrated. It's hard to say technology. In the case of (2), the amount of reduction of the opening dimension that can be stably obtained is within 0.04 μm, and the significant reduction of the opening dimension exceeding this has a problem in terms of uniformity and is mass-produced. Not suitable for. In addition, it is difficult to use the same opening for the recess forming opening and the gate electrode forming opening having a large opening size difference.
[0004]
[Problems to be solved by the invention]
An object of the present invention is to solve the conventional problems and achieve the following objects. That is, the present invention provides a gate electrode manufacturing method capable of efficiently manufacturing a fine gate electrode by increasing the thickness of a gate electrode resist opening formed by normal electron beam lithography and reducing the opening size. The purpose is to do. The present invention is also suitable for a field effect transistor which is manufactured by the method for manufacturing a gate electrode, has excellent high frequency characteristics, and is useful as a device for transmitting / receiving quasi-millimeter / millimeter-wave charged waves or for high-speed signal processing (for optical communication). An object is to provide a simple gate electrode. Furthermore, an object of the present invention is to provide a high-performance semiconductor device using the date electrode and an efficient manufacturing method thereof.
[0005]
[Means for Solving the Problems]
The method for manufacturing a gate electrode according to the present invention includes a step of forming a resist layer including a resist layer including an electron beam resist layer at least on the lowermost layer on the gate electrode forming surface, and an opening forming an aperture in a layer other than the lowermost layer. A gate electrode opening forming step for forming a gate electrode opening in the lowermost layer exposed from the opening; a gate electrode opening reducing step for selectively reducing the gate electrode opening; and the gate electrode. And a gate electrode forming step of forming a gate electrode in the opening for use.
In the method for manufacturing a gate electrode of the present invention, in the multilayer resist forming step, a multilayer resist including an electron beam resist layer at least in the lowest layer is formed on the gate electrode formation surface. In the opening forming step, an opening is formed in a layer other than the lowermost layer. In the gate electrode opening forming step, a gate electrode opening is formed in the lowermost layer exposed from the opening. In the gate electrode opening reduction process, the gate electrode opening is selectively reduced. In the gate electrode formation step, a gate electrode is formed in the gate electrode opening. As described above, a high-performance and fine gate electrode is manufactured.
In the case where an electron beam incident step for causing an electron beam to enter the vicinity of the gate electrode opening is included before the gate electrode opening reducing step, the gate electrode is changed by changing the incident amount of the electron beam. The reduction amount of the opening size of the gate electrode opening in the opening reduction process is adjusted.
In addition, when a gate electrode formation surface digging step for digging a gate electrode formation surface using the gate electrode opening as a mask after the gate electrode opening formation step and before the gate electrode opening reduction step is included. By forming the recess region using the gate electrode opening formed in the gate electrode opening forming step as it is as a mask, the gate electrode can be easily formed at a predetermined position without causing a positional shift in the recess region. The
[0006]
The gate electrode of the present invention is manufactured by the method for manufacturing a gate electrode. The gate electrode has a short gate length and a fine structure, so it has excellent high frequency characteristics and is suitable for a field effect transistor useful as a device for transmitting / receiving quasi-millimeter / millimeter-wave charged waves or for high-speed signal processing (for optical communication) Can be used for
[0007]
A method of manufacturing a semiconductor device according to the present invention includes the method of manufacturing the gate electrode. In the method for manufacturing a semiconductor device of the present invention, a fine gate electrode can be formed. Therefore, a large number of field effect transistors using the gate electrode can be stably integrated to efficiently manufacture a high-performance semiconductor device. . In addition, the gate electrode manufacturing method can form a plurality of gate electrodes with different degrees of fineness, and can also form a plurality of offset gates with arbitrarily adjusted offset amounts. High performance semiconductor devices are efficiently and easily manufactured.
[0008]
The semiconductor device of the present invention is manufactured by the method for manufacturing a semiconductor device. Since the semiconductor device of the present invention has a fine gate electrode suitable for a field effect transistor or the like, it has high performance. Further, when a plurality of gate electrodes having different degrees of miniaturization are provided, or when a plurality of offset gates whose offset amounts are arbitrarily adjusted are provided, the multi-function and high performance are obtained.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
(Gate electrode and manufacturing method thereof)
The manufacturing method of a gate electrode of the present invention includes a laminated resist forming step, an opening forming step, a gate electrode opening forming step, a gate electrode opening reducing step, and a gate electrode forming step, and further if necessary. Other processes selected as appropriate are included.
The gate electrode of the present invention is manufactured by the method for manufacturing a gate electrode of the present invention. Hereinafter, the contents of the gate electrode of the present invention will be clarified through the description of the method for manufacturing the gate electrode of the present invention.
[0010]
-Multilayer resist formation process-
The laminated resist forming step is a step of forming a laminated resist including an electron beam resist layer as at least the lowest layer on the gate electrode forming surface.
[0011]
The gate electrode formation surface is not particularly limited and may be appropriately selected according to the purpose. Examples thereof include a gate electrode formation surface in various semiconductor devices. Among these, a quasi-millimeter / millimeter wave band A gate electrode formation surface of a field effect transistor useful as a device for radio wave transmission / reception or high-speed signal processing (for optical communication) is particularly preferable.
[0012]
An ohmic electrode or the like is preferably formed on the gate electrode formation surface. The ohmic electrode is not particularly limited and can be appropriately selected from known ones. For example, a buffer layer, an InGaAs electron transit layer, an AlGaAs electron supply layer, and a GaAs low resistance are provided on a semi-insulating GaAs substrate. Examples thereof include a laminate of layers. Lamination of each layer in the ohmic electrode can be performed by, for example, MOCVD. In order to electrically isolate the elements from each other, an active region can be formed by oxygen implantation.
A nitride film such as SiN may be formed on the gate electrode formation surface for the purpose of improving the adhesion between the gate electrode formation surface and the laminated resist.
Further, a low resistance layer may be formed on the gate electrode forming surface, and the recess region may be formed by removing the low resistance layer portion by an etching process or the like.
[0013]
The laminated resist is not particularly limited except that at least the lowermost layer includes an electron beam resist layer, and the number of laminated layers, the type of resist, the thickness of each layer, the opening diameter, and the like can be appropriately selected according to the purpose. .
[0014]
The structure of the laminated resist is not particularly limited and may be appropriately selected depending on the purpose. However, the bottom layer in which the gate electrode opening for forming the base portion of the gate electrode is formed, and lift-off ease Preferred examples include a three-layer structure composed of an intermediate layer for achieving the above and an uppermost layer.
[0015]
The lowermost layer material is not particularly limited as long as it is an electron beam resist, and can be appropriately selected according to the purpose, but is preferably one that can be thickened by the resist pattern thickening material, for example, Polymethyl methacrylate (PMMA) resist is particularly preferable.
When the lowermost layer is the polymethyl methacrylate (PMMA) resist, it is advantageous in that the thickening effect by the resist pattern thickening material is excellent.
[0016]
The material for the intermediate layer is not particularly limited and may be appropriately selected depending on the intended purpose. However, a material that is not thickened by the resist pattern thickening material is preferable, and the efficiency of the overgate portion of the gate electrode is preferred. From the viewpoint of typical formation, a material that can be side-etched is more preferable. For example, a polydimethylglutarimide (PMGI) resist is preferable.
[0017]
The material of the uppermost layer is not particularly limited and can be appropriately selected depending on the purpose, and the resist pattern thickening material is thicker than the lowermost layer in which the gate electrode opening is formed. A material with a low degree is preferable, and can be appropriately selected from known electron beam resists, photoresists, and the like, but a polystyrene polymer-containing resist containing a polystyrene polymer and an acrylic resin is preferable.
[0018]
As a material of each layer in the multilayer resist, commercially available products can be used as appropriate.
Each layer in the laminated resist can be formed by applying a resist material or the like of each layer and drying. In addition, there is no restriction | limiting in particular as said application | coating method, According to the objective, it can select suitably from well-known methods, For example, a spin coat method etc. are mentioned.
[0019]
In the present invention, as the multilayer resist, the lowermost layer is formed of the polymethylmethacrylate (PMMA) resist, the intermediate layer is formed of the polydimethylglutarimide (PMGI) resist, and the uppermost layer is The three-layer structure formed of the polystyrene polymer-containing resist can stably form the gate electrode opening (fine gate opening), and can stably and efficiently manufacture the gate electrode. This is preferable.
[0020]
-Opening process-
The opening forming step is a step of forming an opening in a layer other than the lowermost layer.
[0021]
A method for forming an opening in a layer other than the lowermost layer is not particularly limited and may be appropriately selected depending on the purpose. For example, the multilayer resist is formed from the lowermost layer, the intermediate layer, and the uppermost layer. When the uppermost layer has the three-layer structure, an uppermost layer opening is formed in the uppermost layer by electron beam drawing, and the intermediate layer is subjected to an alkali development treatment from the uppermost layer opening to the intermediate layer. A method of forming the opening and performing side etching (set back formation) on the opening of the intermediate layer is preferable.
[0022]
The electron beam drawing can be performed using a known electron beam drawing apparatus. Moreover, the said alkali image development process can be performed according to well-known conditions etc. using a well-known alkali developing solution.
Note that it is preferable to perform side etching (set back formation) on the opening of the intermediate layer because a space for forming an overgate portion of the gate electrode can be formed and lift-off can be easily performed.
[0023]
There is no restriction | limiting in particular as an opening dimension of the uppermost layer opening formed in the uppermost layer in the said multilayer resist, Although it can select suitably according to the objective, For example, it is about 0.20-1.00 micrometer. preferable.
[0024]
-Gate electrode opening formation process-
The gate electrode opening forming step is a step of forming a gate electrode opening (fine gate opening) in the lowermost layer.
The gate electrode opening (fine gate opening) can be formed by performing electron beam drawing on the lowermost layer.
There is no restriction | limiting in particular as the method of the said electron beam drawing, According to a known condition according to the objective, it can carry out using a well-known electron beam drawing apparatus.
The opening size of the gate electrode opening formed by the electron beam drawing is about 0.1 to 0.2 μm.
[0025]
-Gate electrode opening reduction process-
The gate electrode opening reduction step is a step of selectively reducing the gate electrode opening.
[0026]
The method for reducing the size of the gate electrode opening is not particularly limited and may be appropriately selected depending on the intended purpose. For example, a resist pattern thickening material is applied to the gate electrode opening. Particularly preferred is a method in which the treatment for reducing the opening size (diameter) is performed at least once.
The resist pattern thickening material is excellent in the thickening effect even when the lowermost layer is a neutral resist material such as the polymethyl methacrylate (PMMA) resist, and is efficiently formed in the lowermost layer. This is preferable in that the gate electrode opening can be thickened.
[0027]
In the opening reduction process for the gate electrode, the resist pattern thickening material can be suitably used.In this case, when the resist pattern thickening material is applied to the opening for the gate electrode and crosslinked, The gate electrode opening is thickened, a surface layer is formed on the gate electrode opening, and the opening dimension (size) of the uppermost layer opening is reduced. As a result, a finer gate electrode opening is formed exceeding the irradiation limit of the electron beam used when forming the uppermost layer opening.
[0028]
At this time, the amount of increase in the thickness of the gate electrode opening, that is, the amount of reduction in the opening size of the gate electrode opening is the composition, composition ratio, blending amount, concentration, viscosity of the resist pattern thickening material, By appropriately adjusting the coating thickness, baking temperature, baking time, etc., it can be controlled within a desired range.
The composition, composition ratio, blending amount, concentration, viscosity, and the like of the resist pattern thickening material are not particularly limited and may be appropriately selected depending on the intended purpose. Other than water in the resist pattern thickening material The total content of these components is preferably 5 to 40% by mass from the viewpoint of controlling the thickening amount of the gate electrode opening, that is, the reduction amount of the opening size of the gate electrode opening. The reduction amount of the opening dimension can be adjusted by the concentration of the resin, surfactant, crosslinking agent, etc. in the resist pattern thickening material.
[0029]
--Resist pattern thickening material--
The resist pattern thickening material contains a resin, a crosslinking agent, and a surfactant, and further includes a water-soluble aromatic compound and an aromatic compound, which are appropriately selected as necessary. Resin, organic solvent, and other components.
[0030]
The resist pattern thickening material is water-soluble or alkali-soluble.
The resist pattern thickening material is in the form of an aqueous solution, but may be in the form of a colloidal liquid or an emulsion, but is preferably in the form of an aqueous solution.
[0031]
The resin is not particularly limited and may be appropriately selected depending on the intended purpose, but is preferably water-soluble or alkali-soluble, and can cause a crosslinking reaction or does not cause a crosslinking reaction, but a water-soluble crosslinking agent. More preferably, it can be mixed with.
[0032]
When the resin is a water-soluble resin, the water-soluble resin is preferably a water-soluble resin that dissolves 0.1 g or more in water at 25 ° C.
Examples of the water-soluble resin include polyvinyl alcohol, polyvinyl acetal, polyvinyl acetate, polyacrylic acid, polyvinyl pyrrolidone, polyethyleneimine, polyethylene oxide, styrene-maleic acid copolymer, polyvinylamine, polyallylamine, and oxazoline group-containing water-soluble resins. Examples thereof include resins, water-soluble melamine resins, water-soluble urea resins, alkyd resins, and sulfonamide resins.
[0033]
When the resin is alkali-soluble, the alkali-soluble resin is preferably an alkali-soluble resin that dissolves 0.1 g or more in a 2.38% TMAH aqueous solution at 25 ° C.
Examples of the alkali-soluble resin include novolak resins, vinylphenol resins, polyacrylic acid, polymethacrylic acid, poly p-hydroxyphenyl acrylate, poly p-hydroxyphenyl methacrylate, and copolymers thereof.
[0034]
The said resin may be used individually by 1 type, and may use 2 or more types together. Among these, polyvinyl alcohol, polyvinyl acetal, polyvinyl acetate and the like are preferable.
[0035]
The content of the resin in the resist pattern thickening material varies depending on the type and content of the cross-linking agent and the like, and cannot be specified unconditionally, but can be appropriately determined according to the purpose.
[0036]
There is no restriction | limiting in particular as said crosslinking agent, Although it can select suitably according to the objective, The water-soluble thing which bridge | crosslinks with a heat | fever or an acid is preferable, For example, an amino type crosslinking agent is mentioned suitably.
Suitable examples of the amino crosslinking agent include melamine derivatives, urea derivatives, uril derivatives, and the like. These may be used individually by 1 type and may use 2 or more types together.
Examples of the urea derivative include urea, alkoxymethylene urea, N-alkoxymethylene urea, ethylene urea, ethylene urea carboxylic acid, and derivatives thereof.
Examples of the melamine derivative include alkoxymethylmelamine and derivatives thereof.
Examples of the uril derivative include benzoguanamine, glycoluril, and derivatives thereof.
[0037]
The content of the cross-linking agent in the resist pattern thickening material differs depending on the type and content of the resin and cannot be defined unconditionally, but can be appropriately determined according to the purpose.
[0038]
The surfactant is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include nonionic surfactants, cationic surfactants, anionic surfactants, and amphoteric surfactants. It is done. These may be used individually by 1 type and may use 2 or more types together. Among these, nonionic surfactants are preferable in that they do not contain metal ions.
[0039]
The nonionic surfactant is preferably selected from an alkoxylate surfactant, a fatty acid ester surfactant, an amide surfactant, an alcohol surfactant, and an ethylenediamine surfactant. Can be mentioned. Specific examples of these include polyoxyethylene-polyoxypropylene condensate compounds, polyoxyalkylene alkyl ether compounds, polyoxyethylene alkyl ether compounds, polyoxyethylene derivative compounds, sorbitan fatty acid ester compounds, glycerin fatty acid ester compounds, Primary alcohol ethoxylate compound, phenol ethoxylate compound, nonylphenol ethoxylate, octylphenol ethoxylate, lauryl alcohol ethoxylate, oleyl alcohol ethoxylate, fatty acid ester, amide, natural alcohol, ethylenediamine, Secondary alcohol ethoxylates and the like can be mentioned.
[0040]
The cationic surfactant is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include alkyl cationic surfactants, amide type quaternary cationic surfactants, and ester type quaternary cationic types. Surfactant etc. are mentioned.
[0041]
There is no restriction | limiting in particular as said amphoteric surfactant, According to the objective, it can select suitably, For example, an amine oxide type surfactant, a betaine type surfactant, etc. are mentioned.
[0042]
The content of the surfactant in the resist pattern thickening material differs depending on the type and content of the resin, the cross-linking agent, etc., and cannot be specified unconditionally. You can choose.
[0043]
It is preferable that the resist pattern thickening material contains a water-soluble aromatic compound because the etching resistance of the gate electrode opening can be remarkably improved.
The water-soluble aromatic compound is not particularly limited as long as it is an aromatic compound and exhibits water-solubility, and can be appropriately selected according to the purpose. However, 1 g or more is dissolved in 100 g of water at 25 ° C. Those exhibiting water solubility are preferable, those exhibiting water solubility of 3 g or more with respect to 100 g of water at 25 ° C. are more preferable, and those having water solubility of 5 g or more with respect to 100 g of water at 25 ° C. are particularly preferable.
[0044]
Examples of the water-soluble aromatic compound include polyphenol compounds, aromatic carboxylic acid compounds, naphthalene polyhydric alcohol compounds, benzophenone compounds, flavonoid compounds, porphine, water-soluble phenoxy resins, aromatic-containing water-soluble dyes, derivatives thereof, These glycosides are exemplified. These may be used alone or in combination of two or more.
[0045]
Examples of the polyphenol compound and derivatives thereof include catechin, anthocyanidin (pelargosine type (4′-hydroxy), cyanidin type (3 ′, 4′-dihydroxy), delphinidin type (3 ′, 4 ′, 5′-trihydroxy). )), Flavan-3,4-diol, proanthocyanidins, resorcin, resorcin [4] arene, pyrogallol, gallic acid, derivatives or glycosides thereof, and the like.
[0046]
Examples of the aromatic carboxylic acid compound and derivatives thereof include salicylic acid, phthalic acid, dihydroxybenzoic acid, tannin, derivatives and glycosides thereof, and the like.
[0047]
Examples of the naphthalene polyhydric alcohol compound and derivatives thereof include naphthalenediol, naphthalenetriol, derivatives or glycosides thereof, and the like.
[0048]
Examples of the benzophenone compound and derivatives thereof include alizarin yellow A, derivatives or glycosides thereof, and the like.
[0049]
Examples of the flavonoid compound and derivatives thereof include flavone, isoflavone, flavanol, flavonone, flavonol, flavan-3-ol, aurone, chalcone, dihydrochalcone, quercetin, derivatives or glycosides thereof, and the like.
[0050]
Among the water-soluble aromatic compounds, those having two or more polar groups are preferable, those having three or more are more preferable, and those having four or more are particularly preferable in terms of excellent water solubility.
There is no restriction | limiting in particular as said polar group, Although it can select suitably according to the objective, For example, a hydroxyl group, a carboxyl group, a carbonyl group, a sulfonyl group etc. are mentioned.
[0051]
The content of the water-soluble aromatic compound in the resist pattern thickening material can be appropriately determined according to the type and content of the resin and the crosslinking agent.
[0052]
It is preferable that the resist pattern thickening material contains a resin partly containing an aromatic compound because the etching resistance of the uppermost layer opening can be remarkably improved.
The resin partially containing the aromatic compound is not particularly limited and may be appropriately selected depending on the intended purpose. However, it is preferable that a crosslinking reaction can occur, for example, a polyvinyl aryl acetal resin. , Polyvinyl aryl ether resins, polyvinyl aryl ester resins, derivatives thereof, and the like are preferable, and at least one selected from these is preferable, and is an acetyl group in that it exhibits moderate water solubility or alkali solubility. It is more preferable to have These may be used individually by 1 type and may use 2 or more types together.
[0053]
The polyvinyl aryl acetal resin is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include β-resorcin acetal.
There is no restriction | limiting in particular as said polyvinyl aryl ether resin, According to the objective, it can select suitably, For example, 4-hydroxybenzyl ether etc. are mentioned.
There is no restriction | limiting in particular as said polyvinyl aryl ester resin, According to the objective, it can select suitably, For example, benzoic acid ester etc. are mentioned.
[0054]
There is no restriction | limiting in particular as a manufacturing method of the said polyvinyl aryl acetal resin, Although it can select suitably according to the objective, For example, the manufacturing method using a well-known polyvinyl acetal reaction etc. are mentioned suitably. The production method is, for example, a method in which an acetalization reaction is performed between polyvinyl alcohol and a stoichiometrically required amount of aldehyde under an acid catalyst. Specifically, USP 5,169, Preferable examples include the methods disclosed in U.S. Patent No. 897, No. 5,262,270, and Japanese Patent Laid-Open No. 5-78414.
[0055]
The method for producing the polyvinyl aryl ether resin is not particularly limited and may be appropriately selected depending on the intended purpose. For example, the copolymerization reaction of the corresponding vinyl aryl ether monomer and vinyl acetate, the presence of a basic catalyst Examples include etherification reaction between polyvinyl alcohol and an aromatic compound having a halogenated alkyl group (Williamson's ether synthesis reaction). Specific examples include JP-A-2001-40086 and JP-A-2001-181383. A method disclosed in JP-A-6-116194 is preferable.
[0056]
The method for producing the polyvinyl aryl ester resin is not particularly limited and may be appropriately selected depending on the intended purpose. For example, the copolymerization reaction of the corresponding vinyl aryl ester monomer and vinyl acetate, the presence of a basic catalyst Below, esterification reaction of polyvinyl alcohol and an aromatic carboxylic acid halide compound, etc. are mentioned.
[0057]
The aromatic compound in the resin partially containing the aromatic compound is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include monocyclic aromatic benzene derivatives and pyridine derivatives. Preferred examples include compounds in which a plurality of aromatic rings are linked (polycyclic aromatics such as naphthalene and anthracene).
[0058]
Examples of the aromatic compound in the resin partially containing the aromatic compound include a hydroxyl group, a cyano group, an alkoxyl group, a carboxyl group, an amino group, an amide group, an alkoxycarbonyl group, a hydroxyalkyl group, a sulfonyl group, and an acid. From the viewpoint of water solubility, it is preferable to have at least one functional group such as an anhydride group, a lactone group, a cyanate group, an isocyanate group, a ketone group, or a sugar derivative. A hydroxyl group, an amino group, a sulfonyl group, a carboxyl group More preferably, it has at least one functional group selected from the group and groups derived from these derivatives.
[0059]
The molar content of the aromatic compound in the resin having a part of the aromatic compound is not particularly limited as long as the etching resistance is not affected, and can be appropriately selected according to the purpose. Is required, it is preferably 5 mol% or more, more preferably 10 mol% or more.
In addition, the molar content of the aromatic compound in the resin partially including the aromatic compound can be measured using, for example, NMR.
[0060]
The content of the resin containing the aromatic compound in the resist pattern thickening material can be appropriately determined according to the type and content of the resin, the crosslinking agent, and the like.
[0061]
By adding the organic solvent to the resist pattern thickening material, the solubility of the resin, the crosslinking agent, etc. in the resist pattern thickening material can be improved.
[0062]
The organic solvent is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include alcohol-based organic solvents, chain ester-based organic solvents, cyclic ester-based organic solvents, ketone-based organic solvents, and chain ethers. And organic ether solvents and cyclic ether organic solvents.
[0063]
Examples of the alcohol organic solvent include methanol, ethanol, propyl alcohol, isopropyl alcohol, butyl alcohol, and the like.
Examples of the chain ester organic solvent include ethyl lactate and propylene glycol methyl ether acetate (PGMEA).
Examples of the cyclic ester organic solvent include lactone organic solvents such as γ-butyrolactone.
Examples of the ketone organic solvent include ketone organic solvents such as acetone, cyclohexanone, and heptanone.
Examples of the chain ether organic solvent include ethylene glycol dimethyl ether.
Examples of the cyclic ether include tetrahydrofuran, dioxane, and the like.
[0064]
These organic solvents may be used individually by 1 type, and may use 2 or more types together. Among these, the thing which has a boiling point of about 80-200 degreeC is preferable at the point which can thicken finely.
[0065]
The content of the organic solvent in the resist pattern thickening material can be appropriately determined according to the type and content of the resin, the crosslinking agent, the surfactant, and the like.
[0066]
The other components are not particularly limited as long as they do not impair the effects of the present invention, and can be appropriately selected according to the purpose. Various known additives such as thermal acid generators, amines, amides, Quenchers such as ammonium chlorine are listed.
The content of the other components in the resist pattern thickening material can be appropriately determined according to the type and content of the resin and the crosslinking agent.
[0067]
When the resist pattern thickening material is applied to the gate electrode opening and crosslinked, the gate electrode opening is thickened, and a surface layer is formed on the gate electrode opening. The dimension (diameter) is reduced. A finer gate electrode opening is formed beyond the irradiation limit of the electron beam in the electron beam lithography apparatus used for forming the gate electrode opening.
[0068]
At this time, the amount of increase in the thickness of the opening for the gate electrode, that is, the amount of reduction in the opening dimension (diameter) of the opening for the gate electrode is the composition, composition ratio, blending amount, and concentration of the resist pattern thickening material. By adjusting the viscosity, coating thickness, baking temperature, baking time, etc., the desired range can be controlled.
The composition, composition ratio, blending amount, concentration, viscosity, and the like of the resist pattern thickening material are not particularly limited and may be appropriately selected depending on the intended purpose. Other than water in the resist pattern thickening material The total content of these components is preferably 5 to 40% by mass from the viewpoint of controlling the thickness of the gate electrode opening, that is, the reduction of the opening size (diameter) of the gate electrode opening. .
[0069]
Development processing can be performed after the application. By performing the developing treatment, it is possible to remove the excessive resist pattern thickening material that did not form a mixing layer with the lowermost layer.
The development treatment may be water development or development with a weak alkaline aqueous solution, but water development is preferable in that the development treatment can be efficiently performed at low cost.
[0070]
In the gate electrode opening reduction process, the above-described processing from the application to the development is performed at least once, and the process is performed a plurality of times as necessary, so that the opening size of the gate electrode opening is set to a desired size. Can be controlled to a degree.
[0071]
The method for applying the resist pattern thickening material is not particularly limited, and can be appropriately selected from known application methods according to the purpose. For example, a spin coating method or the like is preferable. . In the case of the spin coating method, for example, the rotational speed is about 100 to 10000 rpm, preferably 800 to 5000 rpm, the time is about 1 to 10 minutes, and preferably 1 to 90 seconds.
The coating thickness at the time of coating is usually about 100 to 10,000 mm, and preferably about 2000 to 5000 mm.
In addition, at the time of the application, the surfactant may not be contained in the resist pattern thickening material but may be separately applied before applying the resist pattern thickening material.
[0072]
Pre-baking (heating and drying) the applied resist pattern thickening material during or after the coating is performed at the interface between the lowermost layer and the resist pattern thickening material. This is preferable in that the mixing (impregnation) of the material into the lowermost layer can be efficiently generated.
The pre-baking (heating / drying) conditions and method are not particularly limited as long as the lowermost layer is not softened, and can be appropriately selected according to the purpose. For example, the temperature is 40 to 120. It is about 70 degreeC, 70-100 degreeC is preferable, time is about 10 second-about 5 minutes, and 40 second-100 second is preferable.
[0073]
Further, after the pre-baking (heating / drying), the applied resist pattern thickening material is subjected to cross-linking baking (cross-linking reaction) at the interface between the lowermost layer and the resist pattern thickening material. This is preferable in that the crosslinking reaction of the mixed (impregnated) portion can be efficiently advanced.
The conditions and method for the cross-linking bake (cross-linking reaction) are not particularly limited and can be appropriately selected according to the purpose. However, a temperature condition generally higher than that of the pre-bake (heating / drying) is adopted. Is done. The conditions for the crosslinking baking (crosslinking reaction) are, for example, a temperature of about 70 to 150 ° C., preferably 90 to 130 ° C., a time of about 10 seconds to 5 minutes, and preferably 40 seconds to 100 seconds.
[0074]
Further, after the cross-linking bake (cross-linking reaction), the applied resist pattern thickening material is preferably developed. In this case, of the applied resist pattern thickening material, a portion that is not cross-linked with the lowermost layer or a portion that is weakly cross-linked (highly water-soluble portion) is dissolved and removed, and the thickened resist pattern is developed (obtained). ) Is preferable.
[0075]
-Gate electrode formation process-
The gate electrode forming step is a step of forming a gate electrode in the gate electrode opening.
There is no restriction | limiting in particular as a formation method of the said gate electrode, Although it can select suitably according to the objective, For example, a vapor deposition method etc. are mentioned suitably.
The metal material to be deposited by the deposition method can be appropriately selected from those known as electrode materials. For example, Al, Ti, Pt, Au, and the like are preferable. These may be used individually by 1 type and may use 2 or more types together. These metals may be laminated to form the T-type electrode. In this case, for example, an embodiment in which the T-type electrode is formed of a laminated film of Ti, Pt, and Au is preferable.
[0076]
Further, after the formation of the gate electrode, it is necessary to remove the multilayer resist. Examples of the method for removing the multilayer resist include a lift-off method and an etching method. Among these, the lift-off method is used. Preferably mentioned. The conditions of these methods are not particularly limited and can be appropriately selected from known conditions.
[0077]
In the gate electrode forming step, a T-type electrode is formed in an opening formed through the multilayer resist. Specifically, a base portion of the gate electrode is formed in the opening portion for the gate electrode, and an overgate portion in the gate electrode is formed in the opening formed by side etching. Then, the laminated resist is removed to obtain a gate electrode.
[0078]
-Other processes-
The other process is not particularly limited and may be appropriately selected depending on the purpose. For example, an electron beam incident process in which an electron beam is incident in the vicinity of the gate electrode opening in the lowermost layer, the gate A gate electrode formation surface digging step for digging a gate electrode formation surface using the electrode opening as a mask is preferable.
The gate electrode forming surface portion dug in the gate electrode forming surface digging step may be referred to as a “recess region”, and an end wall surface in the “recess region” may be referred to as a “recess end”.
[0079]
-Electron beam injection process-
The electron beam incident step is a step that is performed before the gate electrode opening reduction step and causes an electron beam to enter the vicinity of the gate electrode opening in the lowermost layer.
The electron beam incident step may be performed either before or after the opening forming step or before or after the gate electrode opening forming step.
[0080]
The amount of electron beam incident on the lowermost layer in the electron beam incident step is preferably a dose amount equal to or less than development Eth. It is preferable that the incident amount is equal to or less than the development Eth in that the lowermost layer can be efficiently thickened without patterning the lowermost layer.
[0081]
In the present invention, when the electron beam is applied to the lowermost layer in the electron beam incident step, the lowermost layer portion on which the electron beam is incident is easily thickened by the resist pattern thickening material. As shown in FIG. 1, the incident amount of the electron beam to the lowermost layer and the thickening amount by the resist pattern thickening material are substantially proportional. Therefore, the amount of reduction of the opening size of the gate electrode opening in the gate electrode opening reduction step can be arbitrarily adjusted by appropriately changing the amount of electron beam incident in the electron beam incidence step, and the lowest layer Among the plurality of gate electrode openings formed by the electron beam drawing, those having different opening dimensions can be formed, and gate electrodes having different degrees of fineness can be arbitrarily formed on the same gate electrode forming surface. This is advantageous in that
[0082]
In the electron beam incident step, the electron beam may be incident on the lowermost layer by causing the electron beam to be incident uniformly or symmetrically in the vicinity of the opening for the gate electrode, or may be incident unevenly or asymmetrically. It may be done by.
[0083]
In the case where an electron beam is incident uniformly or symmetrically in the vicinity of the gate electrode opening, the vicinity of the gate electrode opening can be made substantially uniform or symmetrically thickened, and when the gate electrode forming step is performed, the opening When the transistor is designed by providing the source electrode and the drain electrode together with the obtained gate electrode, the gate electrode side end and the gate electrode are The distance between the recesses on the source electrode side in the formed recess region is the same as the distance between the recesses on the drain electrode side in the recess region where the gate electrode is formed and the end on the drain electrode side in the gate electrode. can do.
[0084]
When an electron beam is incident non-uniformly or asymmetrically in the vicinity of the gate electrode opening, the vicinity of the gate electrode opening can be thickened non-uniformly or asymmetrically, and the gate electrode forming step is performed. When the transistor is designed by providing the source electrode and the drain electrode together with the obtained gate electrode and the opening formed in the opening forming step and the gate electrode opening are not located concentrically, the source in the gate electrode The distance between the electrode side end and the source electrode side recess end in the recess region in which the gate electrode is formed, and the distance between the drain electrode side recess end in the recess region in which the gate electrode is formed, and the drain electrode side end in the gate electrode Can be made different from each other (a so-called offset gate or offset recess is manufactured).
[0085]
Here, the manufacturing of the offset gate will be described in detail. For example, when it is desired to increase the distance between the gate electrode end and the recess end in the recess region on the drain electrode side, that is, the source electrode side end and the gate electrode are formed. When the distance between the recess edges in the recessed area formed is desired to be shorter than the distance between the drain electrode side recess edge and the drain electrode side edge in the recess area (low resistance layer removal area) where the gate electrode is formed. After the gate electrode opening is formed in the gate electrode opening forming step, and before the gate electrode opening reducing step, the gate electrode opening has a source electrode side periphery. An electron beam incidence step for performing more electron beam incidence (dose) is performed.
Next, using the gate electrode opening that determines the length of the low resistance layer removal region (recess region) as a mask, the low resistance layer existing in the vicinity of the gate electrode formation surface is dug and removed, and the low resistance layer removal region A gate electrode formation surface digging step for forming the (recess region) is performed.
[0086]
Then, when the gate electrode opening reduction process is performed using the resist pattern thickening material, the drain electrode side in the gate electrode opening is thicker than the source electrode side, and the drain electrode The reduction amount of the opening dimension on the side is larger than the reduction amount of the opening dimension on the source electrode side, the opening dimension is reduced asymmetrically in the recess region, and the gate electrode opening is the source in the recess region. It is formed (displaced) at a position shifted to the electrode side.
Next, when the gate electrode is formed in the gate electrode formation step, the offset gate is manufactured.
[0087]
-Gate electrode formation surface digging process-
The gate electrode formation surface digging step is a step of digging the gate electrode formation surface using the gate electrode opening as a mask.
The gate electrode formation surface digging step can be suitably performed by, for example, an etching process, and the etching process is not particularly limited, and for example, dry etching is preferable.
There is no restriction | limiting in particular as the conditions of the said etching process, According to the objective, it can select suitably.
[0088]
The gate electrode forming surface digging step is preferably performed after the gate electrode opening forming step and before the gate electrode opening reducing step, and when the electron beam incident step is performed, the gate electrode forming step is performed. It is particularly preferable that this is performed after the electrode opening forming step and before the gate electrode opening reducing step and the electron beam incident step.
In the case where the gate electrode forming surface digging step is performed after the gate electrode opening forming step and before the gate electrode opening reducing step, conventionally, a recess region forming opening is formed to form a recess region. To form an extremely fine and highly accurate offset gate (offset recess) that could not be realized later by the method of forming the gate electrode opening, two openings, a recess region forming opening and a gate electrode opening, are used. Instead, it can be performed using one opening.
[0089]
When the gate electrode formation surface digging step is performed after the gate electrode opening forming step and before the gate electrode opening reducing step, first, the gate electrode opening is formed, and this is used as a mask. After the recess region is dug, the gate electrode opening is reduced, and the gate electrode is formed using the reduced gate electrode opening as a mask. Therefore, there is no positional deviation between the recess region and the gate electrode (fine gate electrode). Since patterning for forming a recess region (low resistance layer removal region) where the gate electrode is formed and patterning for forming the gate electrode opening are performed at the same time, opening alignment at the time of patterning is unnecessary. is there. When this opening alignment is necessary, the formation accuracy of the peripheral structure of the gate electrode is determined and limited by the alignment accuracy, and when the alignment accuracy is not sufficient and there is a positional deviation, There is a problem that misalignment occurs between the recess region and the gate electrode to be formed. In the ultra-high frequency device, the distance from the end of the gate electrode (fine gate electrode) to the recess end in the recess region is about 0.1 μm or less, and if the distance varies based on the positional deviation, There is a problem that the device characteristics are reduced, the frequency of the circuit operation is lowered, and the device characteristics vary. However, when the gate electrode formation surface digging step is performed after the gate electrode opening forming step and before the gate electrode opening reducing step, alignment is not required, and the electron beam lithography apparatus There is no need for layer superposition, and there is no problem as described above.
[0090]
In order to form the recess region and the gate electrode opening by using one opening, the opening size of the opening for forming the recess region is set to about 0.2 μm, and then the opening size of the opening is set. In the present invention, the gate electrode opening having an opening size of about 0.2 μm is used in the gate electrode opening reducing step, using the resist pattern thickening material. By increasing the thickness, the opening size of the date electrode opening can be easily reduced to about 0.1 μm.
[0091]
Further, the reduction amount of the opening size of the gate electrode opening may vary depending on the function and role of a semiconductor device such as a transistor to be manufactured. By appropriately changing the incident amount of the electron beam, it can be easily controlled to a desired level.
[0092]
In addition, it is advantageous in terms of device design that an offset gate can be formed only at an arbitrary position. However, in the present invention, in the electron beam incident step, the gate electrode opening is not uniform or non-uniform. By making the electron beam incident asymmetrically, the offset amount can be arbitrarily changed to a desired level. Therefore, a large number of offset gates having different offset amounts can be separately formed in the device circuit to be manufactured.
[0093]
The gate electrode of the present invention produced by the method for producing a gate electrode of the present invention may or may not be an offset gate, and can be suitably used for various semiconductor devices. It can be preferably used for a field effect transistor, and can be particularly preferably used for a semiconductor device of the present invention.
[0094]
(Semiconductor device and manufacturing method thereof)
The method for manufacturing a semiconductor device according to the present invention includes at least the above-described method for manufacturing a gate electrode according to the present invention, and includes other processes appropriately selected.
There is no restriction | limiting in particular as said other process, According to the semiconductor device to manufacture, it can select suitably from well-known processes.
The semiconductor device of the present invention is manufactured by the method for manufacturing a semiconductor device of the present invention. The semiconductor device of the present invention can be suitably used as a field effect transistor or an integrated circuit thereof.
[0095]
【Example】
Examples of the present invention will be specifically described below, but the present invention is not limited to these examples.
[0096]
Example 1
On the semi-insulating GaAs substrate, a buffer layer, an InGaAs electron transit layer, an AlGaAs electron supply layer, and a GaAs low resistance layer are sequentially stacked by MOCVD, and an active region is formed by oxygen implantation. An ohmic electrode was formed using a 20 nm) / Au (200 nm) electrode. The surface of this semi-insulating GaAs substrate was used as a gate electrode formation surface 1 as shown in FIG.
[0097]
Next, in the active region on the gate electrode formation surface 1, the low resistance layer portions in the region having a width of about 0.1 μm are dug and removed at both ends of the portion where the fine gate (gate electrode) is formed. Thus, a recess region was formed. The above is the gate electrode formation surface digging step.
[0098]
Next, as shown in FIG. 2, a PMMA-based resist (ZEP2000, manufactured by Nippon Zeon Co., Ltd.) is applied on the gate electrode formation surface 1 by a spin coat method so as to have a thickness of 300 nm, and is heat-treated at 180 ° C. for 5 minutes. By doing so, the lowermost layer 2 was formed. On top of that, PMGI (manufactured by MCC) was applied by spin coating so as to have a thickness of 500 nm, and heat treatment was performed at 180 ° C. for 3 minutes to form the intermediate layer 3. On top of that, a polystyrene polymer-containing resist (ZEP520-A7, manufactured by Nippon Zeon Co., Ltd.) was applied by spin coating so as to have a thickness of 300 nm, and heat-treated at 180 ° C. for 3 minutes to form the uppermost layer 4. Thus, a multilayer resist 5 having a three-layer structure was formed. The above is the laminated resist forming step.
[0099]
Next, as shown in FIG. 2, electron beam drawing was performed on the uppermost layer 4 in the multilayer resist 5, and an opening having a width of 0.7 μm was formed in the uppermost layer 4 in the current direction. Subsequently, the intermediate layer 3 exposed from the opening was subjected to a side etching process using an alkali developer. The above is the opening forming step.
[0100]
Next, electron beam drawing was performed on the lowermost layer 2 exposed from the opening formed in the opening forming step to form a gate electrode opening having a width of 0.12 μm in the current direction. The above is the gate electrode opening forming step.
[0101]
Next, a dose (60 μC) equal to or lower than development Eth, which is a dose amount for developing the lowermost layer 2, is incident in the vicinity of the periphery of the formed gate electrode opening to form an electron beam incident region 7. The above is the electron beam incident step.
The dose in Example 1 is 60 μC, but the lowermost layer 2 is not exposed, and the multilayer resist 5 is formed together with the intermediate layer 3 and the uppermost layer 4. For example, as shown in FIG. 3, the electron beam incident regions 7 a, 7 b and 7 c are formed by changing the amount of incident electron beams from above the laminated resist 5 to the laminated resist 5. In this case, the dose is preferably about 90 μC. In this case, patterning can be completed only by performing development processing at once.
[0102]
Next, the gate electrode opening reduction process was performed. First, a resist pattern thickening material was prepared. That is, 16 parts by mass of polyvinyl acetal resin (manufactured by Sekisui Chemical Co., Ltd., KW-3) as the resin, 1 part by mass of tetramethoxymethyl glycoluril (manufactured by Sekisui Chemical Co., Ltd.) as the crosslinking agent, and the surfactant Polyoxyethylene monoalkyl ether surfactant (manufactured by Asahi Denka Co., Ltd., TN-80, nonionic surfactant) 0.0625 parts by mass. Further, as a main solvent component excluding the resin, the crosslinking agent and the surfactant, a mixed solution of pure water (deionized water) and isopropyl alcohol (mass ratio is pure water (deionized water): isopropyl alcohol = 82.6: 0.4) was used. Next, as shown in FIG. 4, this resist pattern thickening material is applied by spin coating at 3000 rpm for 60 seconds, and then pre-baked at 85 ° C. for 70 seconds to form the gate electrode opening and the resist pattern thickness. The meatizing material was mixed to form a mixing layer 6 as shown in FIG. Thereafter, crosslinking baking was performed at 95 ° C. for 70 seconds to crosslink the mixing layer 6 to form a crosslinked mixing layer 20. Then, the resist pattern thickening material other than the crosslinked part was dissolved and removed by developing with water for 60 seconds.
As a result, the resist pattern thickening material can be easily and efficiently simply applied to the gate electrode opening, and in a specific one of the gate electrode openings, that is, in the electron beam incident process, more In the opening into which the dose was incident, the opening size was finely reduced to 0.08 μm, and the opening size of the others was also finely reduced to 0.1 μm. During the gate electrode opening reduction process, the opening dimensions of the openings in the intermediate layer 3 and the uppermost layer 4 did not change.
[0103]
Next, the gate electrode forming step was performed. That is, an electrode having a Ti thickness of 10 nm, a Pt thickness of 10 nm, and an Au thickness of 300 nm was formed by vapor deposition using a high vacuum deposition apparatus. Thereafter, the laminated resist was removed by a lift-off method (N-methyl-2-pyrrolidinone, 75 ° C., 60 minutes) to form a fine T-type gate electrode.
[0104]
(Example 2)
Example 1 is the same as Example 1 except that the gate electrode formation surface digging step is performed after the gate electrode opening forming step and before the electron beam incident step and the gate electrode opening reducing step. The same was done.
Specifically, as shown in FIG. 4A, the source electrode S and the drain electrode D were formed at regular intervals on the surface of the semi-insulating GaAs substrate, and an SiN film was formed. Then, a multilayer resist 5 composed of the lowermost layer 2, the intermediate layer 3, and the uppermost layer 4 was formed on the SiN film by the multilayer resist forming step. Next, openings were formed in the uppermost layer 4 and the intermediate layer 3 in the multilayer resist 5 by the opening forming step. Then, the gate electrode opening 10 having an opening size of 0.2 μm was formed by the gate electrode opening forming step.
[0105]
Next, as shown in FIG. 4B, the low resistance layer portion on the surface of the semi-insulating GaAs substrate is dug and removed using the gate electrode opening 10 as a mask by the step of digging the gate electrode formation surface. As a result, a recess region (low resistance layer removal region) 10a was formed.
[0106]
Next, in the same manner as in Example 1, the electron beam incidence step and the gate electrode reduction step were performed, and as shown in FIG. 4C, the opening of the gate electrode opening 10 having an opening size of 0.2 μm. The size was reduced to 0.1 μm. Next, in the same manner as in Example 1, the gate electrode formation step was performed to form a gate electrode 30 as shown in FIG. Then, the multilayer resist 5 was dissolved and removed by a lift-off method, and a fine gate electrode (mushroom gate electrode) 30 was formed on the gate electrode formation surface.
In Example 2, the pre-baking was performed at 95 ° C. for 70 seconds, and the crosslinking baking was performed at 105 ° C. for 70 seconds. Further, the dose in Example 2 is 60 μC as in Example 1, but in the state where the lowermost layer 2 is not exposed and the laminated resist 5 is formed together with the intermediate layer 3 and the uppermost layer 4. The electron beam can be incident on the multilayer resist 5. For example, the electron beam incident areas 7 a, 7 b, and 7 c are formed by changing the amount of electron beam incident on the multilayer resist 5 from above the multilayer resist 5. In this case, the dose is preferably about 90 μC. In this case, patterning can be completed only by performing development processing at once.
[0107]
Thus, a field effect transistor having a fine gate electrode was obtained. In the field effect transistor, the recess length on the source electrode S side and the recess length on the drain electrode D side are the same with respect to the gate electrode 30.
[0108]
Example 3
In Example 2, in the electron incident step, in order to selectively reduce the size of the opening on the drain electrode D side in the gate electrode opening, a dose (60 μC) equal to or less than the development Eth is incident only on the drain electrode D side. (See FIGS. 5A to 5C).
As a result, as shown in FIG. 5D, the field effect provided with the offset gate, in which the recess length on the drain electrode D side is 0.04 μm longer than the recess length on the source electrode S side with respect to the gate electrode 30. A transistor was obtained.
[0109]
Here, it will be as follows if the preferable aspect of this invention is appended.
(Additional remark 1) On the gate electrode formation surface, the lamination resist formation process which forms the lamination resist which contains an electron beam resist layer at least in the lowest layer, the opening formation process which forms an opening in layers other than the lowest layer, and the said opening Forming a gate electrode opening in the lowermost layer exposed from the gate electrode; forming a gate electrode opening in the gate electrode opening; and a gate electrode opening reducing process for selectively reducing the gate electrode opening; And a gate electrode forming step for forming the gate electrode.
(Supplementary Note 2) The gate electrode opening reducing step includes applying a resist pattern thickening material on the surface of the lowermost layer to reduce the opening size of the gate electrode opening formed in the lowermost layer at least once. The method for manufacturing a gate electrode according to attachment 1, which is a step to be performed.
(Additional remark 3) The manufacturing method of the gate electrode of Additional remark 1 or 2 including the electron beam incident process which injects an electron beam into the vicinity of the opening for gate electrodes before the opening reduction process for gate electrodes.
(Additional remark 4) The manufacturing method of the gate electrode of Additional remark 3 whose incident amount of an electron beam is a dose amount below development Eth.
(Additional remark 5) The manufacturing method of the gate electrode of Additional remark 3 or 4 which makes an electron beam inject into the vicinity of the opening for gate electrodes symmetrically in an electron beam incident process.
(Additional remark 6) The manufacturing method of the gate electrode of Additional remark 3 or 4 which makes an electron beam inject in the vicinity of the opening for gate electrodes in an electron beam incident process.
(Supplementary note 7) The amount according to any one of supplementary notes 3 to 6, wherein the reduction amount of the opening size of the gate electrode opening in the gate electrode opening reduction step is adjusted by changing the incident amount of the electron beam in the electron beam injection step. A method for manufacturing a gate electrode.
(Supplementary note 8) Supplementary note 1 including a gate electrode formation surface digging step for digging a gate electrode formation surface using the gate electrode opening as a mask after the gate electrode opening formation step and before the gate electrode opening reduction step 8. A method for producing a gate electrode according to any one of items 1 to 7.
(Additional remark 9) The manufacturing method of the gate electrode of Additional remark 8 in which a gate electrode formation surface digging process is performed by either dry etching or wet etching.
(Additional remark 10) The manufacturing method of the gate electrode in any one of Additional remark 1 to 9 in which the lowest layer was formed with the material which can be thickened with a resist pattern thickening material.
(Additional remark 11) The manufacturing method of the gate electrode in any one of additional remarks 1-10 in which the lowest layer was formed with the electron beam resist.
(Additional remark 12) The manufacturing method of the gate electrode in any one of additional remarks 1-11 in which the lowest layer was formed with the polymethylmethacrylate (PMMA) type resist.
(Additional remark 13) The manufacturing method of the gate electrode in any one of additional remarks 1-12 whose intermediate layer right above a lowermost layer is side-etchable.
(Additional remark 14) The manufacturing method of the gate electrode in any one of additional remark 1 to 13 in which the intermediate layer immediately above the lowest layer was formed with the photoresist.
(Additional remark 15) The manufacturing method of the gate electrode formed in any one of additional remarks 1-14 in which the intermediate layer immediately above the lowest layer was formed with the polydimethylglutarimide (PMGI) type resist.
(Additional remark 16) The manufacturing method of the gate electrode in any one of additional remarks 1-15 in which the uppermost layer was formed with the electron beam resist.
(Additional remark 17) The manufacturing method of the gate electrode in any one of additional remarks 1-16 in which the uppermost layer was formed with the polystyrene polymer containing resist.
(Supplementary note 18) The laminated resist is composed of three layers, the lowermost layer is formed of a polymethylmethacrylate (PMMA) resist, the intermediate layer immediately above the lowermost layer is formed of a polydimethylglutarimide (PMGI) resist, 18. The method for producing a gate electrode according to any one of appendices 1 to 17, wherein the uppermost layer immediately above the intermediate layer is formed of a polystyrene polymer-containing resist.
(Supplementary note 19) The method for manufacturing a gate electrode according to any one of supplementary notes 1 to 18, wherein when the gate electrode forming step is performed, the opening and the gate electrode opening are not concentrically positioned.
(Supplementary note 20) The method for producing a gate electrode according to any one of supplementary notes 1 to 19, wherein in the gate electrode formation step, the laminated resist is removed after the gate electrode is formed by an evaporation method.
(Supplementary note 21) The method for producing a gate electrode according to supplementary note 20, wherein the removal of the laminated resist is performed by a lift-off method.
(Supplementary note 22) The method for producing a gate electrode according to any one of supplementary notes 1 to 21, wherein the resist pattern thickening material contains a resin, a crosslinking agent, and a surfactant.
(Supplementary note 23) The method for producing a gate electrode according to supplementary note 22, wherein the resist pattern thickening material is water-soluble or alkali-soluble.
(Additional remark 24) The manufacturing method of the gate electrode of Additional remark 22 or 23 whose surfactant is a nonionic surfactant.
(Additional remark 25) The manufacturing method of the gate electrode in any one of Additional remark 22 to 24 whose resin is at least 1 sort (s) selected from polyvinyl alcohol, polyvinyl acetal, and polyvinyl acetate.
(Additional remark 26) The manufacturing method of the gate electrode in any one of Additional remark 22 to 25 whose crosslinking agent is at least 1 sort (s) selected from a melamine derivative, a urea derivative, and a uril derivative.
(Additional remark 27) The manufacturing method of the gate electrode in any one of Additional remark 22 to 26 containing at least 1 sort (s) selected from the resin which has a water-soluble aromatic compound and an aromatic compound in part.
(Supplementary Note 28) The water-soluble aromatic compound is selected from a polyphenol compound, an aromatic carboxylic acid compound, a naphthalene polyhydric alcohol compound, a benzophenone compound, a flavonoid compound, a derivative thereof, and a glycoside thereof. 28. The method for producing a gate electrode according to appendix 27, wherein the resin included in the portion is selected from a polyvinyl aryl acetal resin, a polyvinyl aryl ether resin, and a polyvinyl aryl ester resin.
(Additional remark 29) The manufacturing method of the gate electrode in any one of additional marks 22-28 containing an organic solvent.
(Supplementary Note 30) In Supplementary Note 29, the organic solvent is at least one selected from alcohol solvents, chain ester solvents, cyclic ester solvents, ketone solvents, chain ether solvents, and cyclic ether solvents. The manufacturing method of the gate electrode of description.
(Appendix 31) A gate electrode manufactured by the method for manufacturing a gate electrode according to any one of appendices 1 to 30.
(Supplementary Note 32) The distance between the source electrode side end in the gate electrode and the source electrode side recess end in the recess region where the gate electrode is formed, the drain electrode side recess end in the recess region where the gate electrode is formed, and 32. The gate electrode according to appendix 31, wherein the distance between the drain electrode side ends of the gate electrode is the same.
(Supplementary Note 33) The distance between the source electrode side end in the gate electrode and the source electrode side recess end in the recess region where the gate electrode is formed, the drain electrode side recess end in the recess region where the gate electrode is formed, and 32. The gate electrode according to appendix 31, wherein the distance between the drain electrode side ends of the gate electrode is different.
(Additional remark 34) The gate electrode in any one of additional remarks 31-33 used for a field effect transistor.
(Additional remark 35) The manufacturing method of the semiconductor device characterized by including the manufacturing method of the gate electrode in any one of Additional remark 1-30.
(Appendix 36) A semiconductor device manufactured by the method for manufacturing a semiconductor device according to Appendix 35.
(Supplementary Note 37) A source electrode and a drain electrode are provided, and the distance between the source electrode side end in the gate electrode and the source electrode side recess end in the recess region in which the gate electrode is formed, and the gate electrode is formed. 37. The semiconductor device according to appendix 36, wherein a distance between the drain electrode side recess end in the recess region and a distance between the drain electrode side end in the gate electrode are the same.
(Supplementary Note 38) A source electrode and a drain electrode are provided, and the distance between the source electrode side end in the gate electrode and the source electrode side recess end in the recess region in which the gate electrode is formed, and the gate electrode is formed. 37. The semiconductor device according to appendix 36, wherein a distance between the recess electrode side recess end in the recessed region and a distance between the drain electrode side end in the gate electrode are different.
[0110]
【The invention's effect】
According to the present invention, conventional problems can be solved, and the gate electrode resist opening formed by normal electron beam drawing is thickened to reduce the opening size, thereby effectively producing a fine gate electrode. An object of the present invention is to provide a method for manufacturing a possible gate electrode. The present invention is also suitable for a field effect transistor which is manufactured by the method for manufacturing a gate electrode, has excellent high frequency characteristics, and is useful as a device for transmitting / receiving quasi-millimeter / millimeter-wave charged waves or for high-speed signal processing (for optical communication). An object is to provide a simple gate electrode. Furthermore, the present invention can provide a high-performance semiconductor device using the date electrode and an efficient manufacturing method thereof.
[Brief description of the drawings]
FIG. 1 is a graph showing a relationship between an electron beam incident amount and a resist thickening amount.
FIG. 2 is a schematic explanatory diagram for explaining an example of a method for manufacturing a gate electrode according to the present invention.
FIG. 3 is a schematic explanatory diagram for explaining an example of an electron beam incident step in the method of manufacturing a gate electrode according to the present invention.
FIG. 4 is a schematic explanatory diagram for explaining an example of manufacturing the gate electrode of the present invention by using the method for manufacturing the gate electrode of the present invention (an example in which one opening is used and opening alignment is not required). It is.
FIG. 5 is a schematic explanatory diagram for explaining an example of manufacturing the gate electrode (offset gate) of the present invention by the gate electrode manufacturing method of the present invention.
[Explanation of symbols]
1 Gate electrode formation surface
2 Bottom layer (PMMA resist)
3 Intermediate layer (PMGI resist)
4 Top layer (polystyrene polymer-containing resist)
5 Multilayer resist
6 Mixing layer
7 Electron beam incidence area
7a First electron beam incident area
7b Second electron beam incident area
7c Third electron beam incident area
10 Gate electrode opening
10a Recess area
20 Cross-linking mixing layer
30 Gate electrode
50 electron beam
S source electrode
D Drain electrode

Claims (4)

A laminated resist forming step of forming a laminated resist including an electron beam resist layer at least on the lowest layer on the gate electrode forming surface;
Layers other than the lowermost layer are formed by forming an opening in the uppermost layer of the laminated resist and performing side etching on an intermediate layer other than the lowermost layer to form a space for forming an overgate portion of the gate electrode. Forming an opening in the opening forming step;
Electron beam drawing is performed on the lowermost layer exposed from the opening, and after forming an opening for a gate electrode in the lowermost layer, a resist pattern thickening material is applied to the surface of the lowermost layer, and the lowermost layer A gate electrode opening forming step of performing at least one process of reducing the opening size of the gate electrode opening formed in
An electron beam incident process in which more electron beams are incident on the drain electrode side periphery than on the source electrode side periphery ,
A gate electrode opening reduction process for selectively reducing the gate electrode opening;
An offset gate electrode forming an offset gate electrode in the gate electrode opening , wherein an interval between the gate electrode end and the drain electrode on the drain electrode side is longer than that between the gate electrode end and the source electrode on the source electrode side and the formation process only contains,
A method of manufacturing an offset gate electrode, comprising: adjusting an amount of reduction of an opening size of a gate electrode opening in a gate electrode opening reduction step by changing an amount of incident electron beams in the electron beam incidence step . The gate electrode formation surface digging step of digging the gate electrode formation surface using the gate electrode opening as a mask after the gate electrode opening formation step and before the gate electrode opening reduction step. Manufacturing method of offset gate electrode. The laminated resist consists of three layers, the lowermost layer is formed of a polymethylmethacrylate (PMMA) resist, the intermediate layer immediately above the lowermost layer is formed of a polydimethylglutarimide (PMGI) resist, and immediately above the intermediate layer The manufacturing method of the offset gate electrode in any one of Claim 1 to 2 with which the uppermost layer of this was formed with the polystyrene polymer containing resist. The method for producing an offset gate electrode according to claim 1, wherein the resist pattern thickening material contains a resin, a crosslinking agent, and a surfactant.

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