JP4760168B2 - Display panel and manufacturing method thereof - Google Patents

Description

The present invention relates to a display panel manufactured by the manufacturing method and manufacturing method thereof display panel using a method of patterning the wiring.

  In recent years, as a display device using a new video display method replacing CRT (Cathode Ray Tube), a liquid crystal display using a liquid crystal panel (LCD: Liquid Crystal Display), an electroluminescence (EL) phenomenon is used. Plasma displays using an EL display and a plasma display panel (hereinafter referred to as “PDP”) have been developed.

  Among these, the EL display is roughly classified into an inorganic EL display using an inorganic compound as an electroluminescence element (hereinafter referred to as an EL element) and an organic EL display using an organic compound. Development of an organic EL display has been promoted from the viewpoint that operation at a lower voltage and higher definition are possible as compared with an EL display.

  The driving method of the organic EL display panel used in such an organic EL display includes a passive matrix driving method and an active matrix driving method. An organic EL display panel adopting the active matrix driving method has a high contrast and a high contrast. This is superior to the passive matrix driving method because of the advantage that the light emission luminance per unit time can be suppressed.

The above-described active matrix display panel, semiconductor circuit, and other circuits are manufactured by patterning wiring on a substrate. As a method for patterning wiring, a liquid containing conductive fine particles is ink-jetted by an ink jet apparatus. As a result, a method of directly patterning wiring by discharging onto a substrate has been developed.
Specifically, as a wiring patterning method capable of preventing the occurrence of problems such as disconnection and short circuit and improving electrical conductivity, ink is discharged toward the entire surface of the liquid-repellent substrate. A method for forming a film pattern has been developed (see, for example, Patent Document 1).
In addition, as a wiring patterning method capable of more reliably and simply manufacturing a substrate having high-density wiring, a fine groove is formed in the substrate by pressing a mold against the substrate, and a conductive substance is formed in the groove. A manufacturing method of a high-density wiring board in which wiring is formed by implantation has been developed (see, for example, Patent Document 2).
JP 2003-80694 A JP 2004-356255 A

  However, in the case of the patterning method described in Patent Document 1 described above, since the familiarity between the substrate and the ink is insufficient, the wiring formed by the conductive fine particles in the ink does not adhere to the substrate, and the wiring peels off. There is a problem such as.

Further, in the case of the patterning method described in Patent Document 2, a groove can be formed by a method of pressing a mold if it is a soft substrate that can be easily deformed, but if the substrate is a hard substrate that is difficult to deform, It is difficult to form a groove by the pressing method.
For this reason, the ink adheres to the substrate without forming the groove, but there is a problem that it is difficult to accurately form the wiring because the landed ink is diffused or blotted.

The present invention has been made in view of the above, and aims to provide as well as preventing peeling from the substrate, the de-spray panel and a manufacturing method thereof capable of improving the arrangement positional accuracy To do.

In order to solve the above problems, a method of manufacturing a display panel according to the invention described in claim 1 includes:
In a method for manufacturing a display panel in which wiring is patterned in a display region of a display panel by a wiring patterning method of patterning high-density wiring on an upper surface of a substrate,
Forming a first metal film and a second metal film on the non-metal film provided on the upper surface of the substrate in the display panel so that the non-metal film is exposed in the surroundings;
Applying a liquid repellent treatment to the non-metal film around the first metal film and the second metal film;
A step of attaching the conductive fine particle-containing droplets or metal fine particles to the upper surface of the first metal film using an inkjet head or a dispenser, and forming the wiring to be a metal partition that partitions the pixels ;
Forming a liquid repellent conductive film selectively on the surface of the wiring;
After the step of forming the liquid repellent conductive film, forming an organic EL layer and a third metal film on the upper surface of the second metal film;
It is characterized by comprising.
Here, as the non-metal film, a material that easily bonds to fluorine, such as a cured photosensitive resin, silicon nitride, or silicon oxide, is preferable.
In the method of manufacturing the display panel according to the invention of claim 2, wherein the step of forming the liquid repellent conductive film by applying an aqueous solution of the triazine derivative to the entire surface of the display panel, selectively on the wiring surface And a step of forming a liquid repellent conductive film.

According to a third aspect of the present invention, there is provided a method for producing a display panel , wherein the liquid repellent treatment exposes the substrate in plasma generated using a fluorine-based gas.

According to a fourth aspect of the present invention, there is provided a display panel manufacturing method, wherein the liquid repellent treatment exposes the substrate in F2 gas.

According to a fifth aspect of the present invention, there is provided a display panel manufacturing method, wherein the conductive fine particle-containing droplets are deposited on the metal film by a droplet discharge method.

The method for manufacturing a display panel according to a sixth aspect of the invention is characterized in that the metal fine particles are adhered by directly spraying the metal fine particles.

According to a seventh aspect of the present invention, there is provided a display panel manufacturing method, wherein the first metal film has a thickness of 1 nm to 30 nm.
A display panel according to an eighth aspect of the present invention is manufactured by the manufacturing method according to any one of the first to seventh aspects.

According to the present invention, since the conductive fine particle-containing droplets or the metal film having high adhesion to the metal fine particles is formed on the upper surface of the substrate, the conductive fine particle-containing droplets or the like are not attached to the substrate. Even when it is difficult to adhere, it is possible to easily form a wiring made of conductive fine particle-containing droplets. Therefore, the adhesion of the wiring to the substrate is improved, the peeling of the wiring is prevented, the wiring can be easily formed at a desired position on the substrate, and the patterning accuracy of the wiring can be improved.
In addition, since the peripheral portion of the metal film on the substrate has been subjected to a liquid repellent treatment, it is possible to selectively deposit conductive fine particle-containing droplets on the upper surface of the metal film, and more effective for wiring. The patterning accuracy can be improved.

The best mode for carrying out the present invention will be described below with reference to the drawings. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples.
Hereinafter, the wiring according to the present invention, the patterning method thereof, the display panel and the manufacturing method thereof will be described with reference to FIGS.

First, a wiring patterning method will be described with reference to FIGS. 1A to 1G.
First, as shown in FIG. 1A, a substrate 550 is prepared. As the substrate 550, an insulating substrate such as a plastic substrate or a glass substrate can be used. When the display panel has a top emission structure, the substrate 550 does not need to be transparent, but when the display panel has a bottom emission structure, the substrate 550 is required to have high transparency with respect to the wavelength range of light emitted by the organic EL. As the substrate 550, a transistor array panel in which one or a plurality of thin film transistors is formed for each pixel can be used. Then, an interlayer insulating film 555 such as silicon nitride or silicon oxide is coated on the entire surface of the substrate 550 so as to cover the thin film transistor.

Next, a thin film of chromium or the like is formed on the surface of the interlayer insulating film 555 on the substrate 550 by a vapor deposition method (for example, PVD method such as sputtering, ion plating, vacuum deposition, etc.), and the thin film is formed by a photolithography method. Then, as shown in FIG. 1B, a thin film pattern 551 is formed on the surface of the interlayer insulating film 555, and then tin-doped indium oxide (ITO), zinc-doped indium oxide, and indium oxide. A transparent conductive film such as (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), or cadmium-tin oxide (CTO) is coated on the interlayer insulating film 555 and then on a predetermined thin film pattern 551. The transparent electrode 556 is formed by patterning so as to leave only. The transparent electrode 556 becomes a pixel electrode connected to the transistor. At this time, when the panel has a top emission structure, the thin film pattern 551 may be coated to a thickness that becomes opaque with respect to the wavelength range of light emitted by the organic EL, but in the case of the bottom emission structure, the organic EL It is preferable that the film be an extremely thin film that can maintain high transparency with respect to the wavelength range of light emitted, for example, about 1 nm to 30 nm. Thereafter, as shown in FIG. 1C, a resist 552 is applied to the entire surface of the substrate 550, and the thin film pattern 551 and the transparent electrode 556 are covered with the applied resist 552.

  Further, as shown in FIG. 1D, by exposing and developing the resist 552, a part of the resist 552 is removed, and the thin film pattern 551 and the interlayer insulating film 555 around the thin film pattern 551 are exposed. Let The height of the resist 552 is preferably about 1 μm to 2 μm.

  Note that in order to expose the above-described thin film pattern 551 and the interlayer insulating film 555 in the peripheral portion of the thin film pattern 551, when the resist 552 is a positive type, the thin film pattern 551 and its peripheral portion are irradiated with light, and the resist When 552 is a negative type, light is irradiated to other than the thin film pattern 551 and its peripheral part. As the positive resist, there is a novolak type (manufactured by Nagase Smo Chemtech: NPR3510PG).

  After the exposure and development processing, as shown in FIG. 1E, the above-described substrate 550 is exposed to plasma generated using a fluorine-based gas, so that the interlayer insulating film 555 around the thin film pattern 551 is exposed. A liquid repellent treatment is performed on the surface and the surface of the resist 552. At this time, remarkable liquid repellency is not exhibited on the surface of the thin film pattern 551 which is a metal and the surface of the transparent electrode 556.

As the fluorine-based gas in this embodiment, carbon tetrafluoride _(CF 4), hexafluoride butadiene _{(C 4 F} 6), eight fluoride butylene _{(C 4 F} 8), eight fluoride cyclopentene _{(C 5} F ₈ ), octafluoropropane (C ₃ F ₈ ) or hexafluoroethane (C ₂ F ₆ ) can be suitably used.

In addition, as the liquid repellent treatment method in the present embodiment, a method of exposing the substrate 550 to plasma generated using a fluorine-based gas is used, but there is no particular limitation, and fluorine (F ₂₎ is not particularly limited. ) By exposing the substrate 550 to the gas, the periphery of the thin film pattern 551 on the substrate 550 may be subjected to a liquid repellent treatment.

  After the liquid repellent treatment, as shown in FIG. 1 (f), a conductive material composed of a metal nano ink or metal nano paste in which conductive fine particles having an average particle diameter of about 1 nm to 1 μm are dispersed from the inkjet head 560 toward the thin film pattern 551. The fine particle-containing droplets 553 are discharged. Here, at least one of the inkjet head 560 and the substrate 550 is moved along the surface of the substrate 550, and the conductive fine particle-containing droplets 553 are ejected from the inkjet head 560 so as to be superimposed on the thin film pattern 551. The wiring 554 is patterned. As described above, since the thin film pattern 551 having high adhesion to the conductive fine particle-containing droplets is patterned on the upper surface of the substrate 550, the conductive fine particle-containing droplets are hardly adhered to the substrate 550. Even in this case, the wiring 554 made of conductive fine particle-containing droplets can be easily formed. Since the surface 571 of the interlayer insulating film 555 exposed around the thin film pattern 551 is made liquid-repellent by the plasma treatment 570 using a fluorine-based gas, the conductive fine particle-containing droplets 553 can be easily played. ing. Here, since the surface energy generated when the conductive fine particle-containing droplet 553 comes into contact with the thin film pattern 551 is lower than the surface energy generated when the conductive fine particle-containing droplet 553 comes into contact with the interlayer insulating film 555, The conductive fine particle-containing droplets 553 are positioned only on the surface of the thin film pattern 551.

  As the conductive fine particle-containing liquid droplets in the present embodiment, those obtained by dispersing metal fine particles such as silver, copper, aluminum, or an alloy mainly composed of these in a dispersion medium such as a curable liquid resin are used. In particular, silver nano ink (manufactured by ULVAC Material Co., Ltd .: Ag1-TeH) is preferably used.

  Further, instead of using the inkjet head 560 to discharge the conductive fine particle-containing liquid droplets 553 as liquid droplets, the conductive fine particle-containing liquid droplets 553 or the metal fine particles are directly sprayed using a carrier gas dispenser. A method of patterning the wiring 554 by adhering may be used. In the case where the conductive fine particle-containing droplets 553 are a paste that is viscous with a binder resin or the like, patterning may be performed by screen printing.

  Finally, as shown in FIG. 1G, the wiring 554 formed on the upper surface of the substrate 550 is solidified to complete a series of wiring patterning operations.

  Note that in the case where the dispersion medium of the conductive fine particle-containing droplets is a photocurable resin, the wiring 554 can be solidified by irradiating the wiring 554 with ultraviolet rays. On the other hand, when the dispersion medium of the conductive fine particle-containing droplets is a thermosetting resin, the wiring 554 can be solidified by heating the wiring 554. Thereafter, a solution or dispersion containing the organic EL layer material is attached onto the transparent electrode 556. At this time, since the height of the liquid surface of the solution or dispersion containing the organic EL layer material is lower than the height of the wiring 554, the liquid does not enter the adjacent transparent electrode 551 beyond the wiring 554.

  Further, since the surface 571 around the transparent electrode 556 and the surface 571 around the wiring 554 are liquid repellent, the solution or dispersion containing the organic EL layer material gathers on the more stable transparent electrode 556. It becomes easy. At this time, if the amount of the solution or dispersion containing the organic EL layer material is sufficient, it will be attached not only on the transparent electrode 556 but also around the transparent electrode 556. Therefore, the solution or dispersion containing the organic EL layer material is dried on the transparent electrode 556 to become the organic EL layer 557. Next, a display panel can be manufactured by providing the counter electrode 558 so as to straddle the plurality of organic EL layers 557. In the case where the thin film pattern 551 can be used as an electrode, the transparent electrode 556 is not necessarily required. In the case of top emission, the thin film pattern 551 that functions as a reflector under the transparent electrode 556 can be manufactured together with the thin film pattern 551 that is the base of the wiring 554.

Next, the planar configuration of the display panel will be described with reference to FIG.
As shown in FIG. 2, the display panel 1 in the present embodiment has pixels arranged in a matrix. These pixels are composed of a substantially rectangular 1-dot red sub-pixel P, 1-dot green sub-pixel P, and 1-dot blue sub-pixel P. The red subpixel P, the green subpixel P, and the blue subpixel P are arranged in the direction perpendicular to the longitudinal direction (hereinafter, horizontal direction) so that the longitudinal directions (hereinafter, vertical direction) are parallel to each other. It is arranged to be.

  In the display panel 1, a plurality of scanning lines X, signal lines Y, and supply lines Z are provided to output various signals to the subpixels P. The scanning lines X and the supply lines Z extend in the horizontal direction, and the signal lines Y extend in the vertical direction. Here, when the m-dot sub-pixels P are arranged in the horizontal direction (where m is a multiple of 3), the m signal lines Y are provided in parallel to each other, and the n-dot sub-pixels P are provided. Are arranged in the vertical direction (where n is an integer of 2 or more), the n scanning lines X and the n supply lines Z are provided in parallel to each other. Further, the scanning lines X and the supply lines Z are alternately arranged along the horizontal direction.

Next, the circuit configuration of the subpixel P will be described with reference to FIG.
Each sub-pixel P is configured in the same manner. As shown in FIG. 3, the 1-dot sub-pixel P includes an organic EL element 20 and a switch transistor 21 that is an N-channel amorphous silicon thin film transistor. A transistor 22 and a driving transistor 23 and a capacitor 24 are provided.

  The organic EL element 20 includes a sub-pixel electrode 20a as a pixel electrode, an organic EL layer 20b (shown in FIG. 4), and a counter electrode 20c, and the counter electrode 20c is electrically connected to the metal partition wall W. ing.

  The switch transistor 21 has a source 21s, a drain 21d, and a gate 21g. Among these, the source 21 s is electrically connected to the signal line Y, the drain 21 d is electrically connected to the subpixel electrode 20 a of the organic EL element 20, the source 23 s of the drive transistor 23, and the electrode 24 b of the capacitor 24, and the gate 21 g is The gate 22g of the holding transistor 22 is electrically connected to the scanning line X.

  The holding transistor 22 includes a source 22s, a drain 22d, and a gate 22g. Among these, the source 22s is electrically connected to the gate 23g of the driving transistor 23 and the electrode 24A of the capacitor 24, the drain 22d is electrically connected to the drain 23d of the driving transistor 23 and the supply line Z, and the gate 22g is electrically connected to the switch transistor 21. The gate 21g is electrically connected to the scanning line X. Note that the drain 22d of the holding transistor 22 may be connected to the scanning line X without being electrically connected to the drain 23d of the driving transistor 23.

  The drive transistor 23 has a source 23s, a drain 23d, and a gate 23g. Among these, the source 23s is electrically connected to the subpixel electrode 20a of the organic EL element 20, the drain 21d of the switch transistor 21, and the electrode 24b of the capacitor 24. The drain 23d is connected to the drain 22d of the holding transistor 22 and the supply line. The gate 23g is electrically connected to the source 22s of the holding transistor 22 and the electrode 24a of the capacitor 24.

  Note that the relationship between the source and drain of the switch transistor 21, the holding transistor 22, and the drive transistor 23 in FIG. 3 may be reversed.

Next, the layer structure of the display panel 1 will be described with reference to FIG.
As shown in FIG. 4, the display panel 1 in this embodiment includes an insulating substrate 2, and a switch transistor 21, a holding transistor 22, and a driving transistor 23 are provided on the upper surface of the insulating substrate 2. Yes.
The switch transistor 21, the holding transistor 22, and the driving transistor 23 are covered with a common transistor protective insulating film 32.

  The above-described switch transistor 21, holding transistor 22, and drive transistor 23 are all thin film transistors having an inverted stagger structure, and among these, the switch transistor 21 is formed on the gate 21g formed on the upper surface of the insulating substrate 2 and on the gate 21g. The formed gate insulating film 31, the semiconductor film 21c facing the gate 21g with the gate insulating film 31 in between, the channel protective film 21p formed on the central portion of the semiconductor film 21c, and on both ends of the semiconductor film 21c The impurity semiconductor films 21a and 21b are formed so as to be separated from each other and partially overlap the channel protective film 21p, the drain 21d formed on the impurity semiconductor film 21a, and the source formed on the impurity semiconductor film 21b. 21 s.

The driving transistor 23 includes a gate 23g formed on the upper surface of the insulating substrate 2, a gate insulating film 31 formed on the gate 23g, and a semiconductor film 23c facing the gate 23g with the gate insulating film 31 interposed therebetween. A channel protective film 23p formed on the central portion of the semiconductor film 23c, and impurity semiconductor films 23a and 23b formed on both ends of the semiconductor film 23c so as to be separated from each other and partially overlapping the channel protective film 23p; The drain 23d is formed on the impurity semiconductor film 23a, and the source 23s is formed on the impurity semiconductor film 23b.
Further, the holding transistor 22 (not shown) is configured similarly to the switch transistor 21 and the drive transistor 23 described above.

  The gate 21g of the switch transistor 21, the gate 22g of the holding transistor 22, the gate 23g of the drive transistor 23, and the electrode 24a of the capacitor 24 are formed on the insulating substrate 2 by vapor phase growth methods such as sputtering, PVD, and CVD, for example. A conductive gate layer (for example, a film made of Al and Ti) formed thereon is formed by patterning using a photolithography method and an etching method. Further, the scanning line X and the supply line Z are formed simultaneously with the gates 21g, 22g, and 23g by patterning the gate layer, and are formed by the gate insulating film 31 that is common to the gates 21g, 22g, and 23g and the electrode 24a. It is covered.

  On the other hand, the drain 21d and source 21s of the switch transistor 21, the drain 22d and source 22s of the holding transistor 22, the drain 23d and source 23s of the driving transistor 23, and the electrode 24b of the capacitor 24 are formed on the gate insulating film 31 by vapor deposition. Formed by patterning a conductive drain layer (for example, a Cr film laminated with a film made of Al and Ti) using a photolithography method and an etching method. It is. The signal line Y is formed at the same time as each of the sources 21s, 22s, 23s and the drains 21d, 22d, 23d by patterning the drain layer, and the source 21s, 22s, 23s, the electrode 24b, and the drains 21d, 22d. , 23d and a common transistor protective insulating film 32.

A planarizing film 33 obtained by curing a photosensitive resin such as polyimide is laminated on the upper surface of the transistor protective insulating film 32. By planarizing the surface of the planarizing film 33, the switch transistor 21 and the holding transistor 22 are laminated. Unevenness caused by the drive transistor 23, the scanning line X, the signal line Y, and the supply line Z is eliminated.
A contact hole 91 is formed in the planarization film 33 and the transistor protection insulating film 32 in each subpixel P. A conductive pad 92 is buried in the contact hole 91, and the sub-pixel electrode 20 a and the source 23 s of the drive transistor 23 are connected by the conductive pad 92.
Here, the stacked structure from the insulating substrate 2 to the planarization film 33 in this embodiment is referred to as a transistor array panel 50.

In addition, on the upper surface of the planarizing film 33 described above, subpixel electrodes 20a that are anodes of the organic EL elements 20 are arranged in a matrix. In FIG. 2, the position of the rectangular subpixel P represents the position of the subpixel electrode 20a (shown in FIG. 4 and the like). That is, between the adjacent signal lines Y, the subpixel electrodes 20a are arranged in a line in the vertical direction. Between the scanning line X and the adjacent supply line Z, the subpixel electrodes 20a are arranged in the horizontal direction. Are arranged in a row. When the display panel 1 has a bottom emission structure, these subpixel electrodes 20a are formed of a transparent conductive film (for example, tin-doped indium oxide (ITO), formed on the upper surface of the planarization film 33 by a vapor deposition method). By patterning zinc-doped indium oxide, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO) or cadmium-tin oxide (CTO) using photolithography and etching methods It may be formed, and when it has a top emission structure, it may have a structure in which the above-described transparent conductive film is laminated on a light reflective metal film. In the case of a laminated structure of a light reflective metal film and a transparent conductive film, the etchant that etches the transparent conductive film may cause a battery reaction and the light reflective metal film may be eroded. FIG. Like the transparent electrode 556 and the thin film pattern 551, the side wall of the light reflective metal film is preferably covered with a transparent conductive film.

Furthermore, an insulating film 34 made of silicon nitride (SiN) or silicon oxide (SiO ₂ ) is formed on the upper surface of the planarizing film 33. A part of the insulating film 34 overlaps a part of the outer edge portion of the subpixel electrode 20a, and the subpixel electrode 20a is surrounded by the insulating film 34 in a plan view.

Further, a thin film pattern 35 made of, for example, chromium is formed on the upper surface of the planarizing film 33. The thin film pattern 35 is laminated with a metal partition wall W made of copper, silver, aluminum, or an alloy containing them as a main component. As shown in FIG. 2, the thin film pattern 35 and the metal partition wall W extend in the vertical direction between the column of the subpixel electrodes 20a in the vertical direction and the column of the adjacent subpixel electrodes 20a. When viewed, the signal line Y is superimposed.
The above-described metal partition wall W is obtained by curing a droplet containing conductive fine particles, and has a thickness dimension larger than that of each electrode of the transistors 21, 22, 23, the scanning line X, the signal line Y, and the supply line Z, It functions as an auxiliary wiring. Further, the metal partition walls W are connected to each other outside the region where the subpixels P are arranged.

  Note that the width dimension of the metal partition wall W in FIG. 4 is smaller than the width dimension of the signal line Y so that the signal line Y and the metal partition wall W can be easily distinguished from each other. The width dimension is substantially the same.

  A liquid repellent conductive film 36 having liquid repellency is formed on the surface of the metal partition wall W. In the liquid repellent conductive film 36, the hydrogen atom (H) of the mercapto group (—SH) of triazyltrithiol represented by the following chemical formula (1) is reduced and released, and the sulfur atom (S) is oxidized on the surface of the metal partition wall W. Adsorbed.

  In the present embodiment, a state where the contact angle with respect to a certain liquid is 50 ° or more is defined as liquid repellency, and a state where the contact angle with respect to a certain liquid is 40 ° or less is defined as lyophilic.

  The liquid repellent conductive film 36 is an extremely thin layer whose thickness approximates to the thickness of a single molecule of triazyltrithiol. That is, the liquid repellent conductive film 36 is an extremely thin film composed of a molecular layer in which triazyltrithiol molecules are regularly arranged on the surface of the metal partition wall W, and therefore has a very low resistance and conductivity. In order to make the liquid repellency remarkable, instead of triazyltrithiol, as shown in the following chemical formula (2), one or two mercapto groups of triazyltrithiol are substituted with fluorinated alkyl groups. Zirthiol compounds may be used. The fluorinated alkyl group may be other than that shown in the following chemical formula (2). In addition, the compound of the following chemical formula (2) is a fluorine-based triazine thiol derivative having a molecular weight of 423.08, the hydrogen atom (H) of the mercapto group (—SH) is reduced and released, and the sulfur atom (S) is the metal partition wall W. The liquid repellent conductive film 36 is formed by oxidative adsorption on the surface.

  An organic EL layer 20b including a charge transporting layer and a light emitting layer is stacked on the upper surface of the subpixel electrode 20a. The organic EL layer 20b is formed by stacking two or more organic compound-containing layers. Here, the organic EL layer 20b has a two-layer structure in which a sub-pixel electrode 20a, a hole transport layer 20d, and a light-emitting layer 20e are sequentially stacked, and the hole transport layer is a conductive polymer PEDOT (Poly Poly). (3,4-Ethylene Dioxy Thiophene)) and PSS (Poly Styrene Sulfonate) as a dopant, and the light emitting layer is made of a polyfluorene light emitting material.

  Note that the organic EL layer 20b may have a three-layer structure including a hole transport layer, a light emitting layer, and an electron transport layer in order from the subpixel electrode 20a, or a light emitting layer, an electron transport layer, and the like in order from the subpixel electrode 20a. It may be a two-layer structure or a single-layer structure composed of a light emitting layer.

  Further, a multilayer structure in which an electron transport layer, an electron transport layer, a hole transport layer, or another charge transport control layer is interposed between appropriate layers in these layer structures may be used.

  The organic EL layer 20b described above is formed by a wet coating method such as an ink jet method after the liquid repellent conductive film 36 is formed. In this case, an organic compound-containing liquid containing PEDOT and PSS is applied to the subpixel electrode 20a to form the hole transport layer 20d, and then the polyfluorene-based light emission is formed on the upper surface of the hole transport layer 20d. The light emitting layer 20e is formed by applying an organic compound-containing liquid containing a material, but a thick metal partition wall W is provided and the surface of the metal partition wall W is liquid repellent. Since the conductive film 36 is formed, the organic compound-containing liquid applied to the adjacent subpixel electrode 20a can be prevented from mixing beyond the metal partition wall W.

  When the subpixel P is red, the organic EL layer 20b, in particular, the light emitting layer 20e emits red light. When the subpixel P is green, the organic EL layer 20b emits green light, When P is blue, the organic EL layer 20b emits blue light.

  A counter electrode 20c that is a cathode of the organic EL element 20 is formed on the upper surface of the organic EL layer 20b. The counter electrode 20c is a common electrode formed in common for all the subpixels P, is formed on the entire surface, and covers the metal partition wall W with the liquid repellent conductive film 36 interposed therebetween. .

  The counter electrode 20c described above is formed of a material having a work function lower than that of the subpixel electrode 20a. For example, the counter electrode 20c is formed of a simple substance or an alloy containing at least one of indium, magnesium, calcium, lithium, barium, and a rare earth metal. Yes.

The counter electrode 20c may have a laminated structure in which layers of the above various materials are laminated, or may have a laminated structure in which a metal layer is deposited in addition to the above layers of various materials. Specifically, a laminated structure composed of a low-work function high-purity barium layer provided on the organic EL layer 20b side and an aluminum layer provided so as to cover the barium layer, or on the organic EL layer 20b side. A laminated structure including a lithium layer provided and an aluminum layer provided so as to cover the barium layer can be given.
Here, in the present embodiment, the organic EL element 20 is formed by laminating the subpixel electrode 20a, the organic EL layer 20b, and the counter electrode 20c in this order.

Next, the width dimension, cross-sectional area and resistivity of the metal partition wall W will be defined with reference to FIGS.
In the following, the desirable width dimension and cross-sectional area of the above-described metal partition wall W when the number of pixels of the display panel 1 is WXGA (768 × 1366) are defined.

  In FIG. 5, the vertical axis represents the current value of the write current flowing between the source 23 s and the drain 23 d of one drive transistor 23 or the current value of the drive current flowing between the anode and the cathode of one organic EL element 20. The axis is the voltage between the source 23s and the drain 23d of one drive transistor 23 (at the same time, the voltage between the gate 23g and the drain 23d of one drive transistor 23). In the figure, solid line Ids max is a write current and drive current at the maximum luminance gradation (brightest display), and alternate long and short dash line Ids mid is an intermediate luminance between the highest luminance gradation and the lowest luminance gradation. The two-dot chain line Vpo is a threshold value, that is, a pinch-off voltage between the unsaturated region (linear region) and the saturated region of the driving transistor 23, and the three-dot chain line Vds is the driving transistor 23. The write current that flows between the source 23s and the drain 23d of FIG.

  Here, the voltage VP1 is a pinch-off voltage of the driving transistor 23 at the maximum luminance gradation, and the voltage VP2 is a source-drain voltage when a writing current of the maximum luminance gradation flows through the driving transistor 23. VELmax (voltage VP4−voltage VP3) is a voltage between the anode and the cathode when the organic EL element 20 emits light with the driving current of the maximum luminance gradation equal to the writing current of the maximum luminance gradation. The voltage VP2 ′ is a source-drain voltage when the driving transistor 23 receives a write current having an intermediate luminance gradation, and the voltage (voltage VP4′−voltage VP3 ′) is an organic EL element 20 having an intermediate luminance gradation. This is the anode-cathode voltage when light is emitted with a drive current of an intermediate luminance gradation whose current value is equal to the write current.

  Since both the drive transistor 23 and the organic EL element 20 are driven in the saturation region, a value VX obtained by subtracting (the voltage Vcom during the light emission period of the metal barrier W) from (the voltage VH during the light emission period of the supply line Z) is The following formula (1) is satisfied.

VX = Vpo + Vth + Vm + VEL (1)
Here, Vth (equal to VP2-VP1 in the case of the highest luminance) is a threshold voltage of the driving transistor 23, VEL (equal to VELmax in the case of the highest luminance) is an anode-cathode voltage of the organic EL element 20, Vm Is an allowable voltage that is displaced according to the gradation.

  As is clear from FIG. 5, the voltage (Vpo + Vth) required between the source and drain of the transistor 23 increases as the luminance gradation increases in the voltage VX, and the voltage required between the anode and cathode of the organic EL element 20. VEL increases. Therefore, the higher the luminance gradation, the lower the allowable voltage Vm, and the minimum allowable voltage Vmmin becomes VP3-VP2.

  The organic EL element 20 generally deteriorates with time regardless of the low-molecular EL material and the high-molecular EL material, and increases in resistance. It has been confirmed that the anode-cathode voltage after 10,000 hours is about 1.4 times the initial voltage. That is, the voltage VEL becomes higher as time passes even at the same luminance gradation. For this reason, the higher the allowable voltage Vm at the beginning of driving, the more stable the operation over a long period of time. Therefore, the voltage VX is set so that the voltage VEL is 8V or higher, more preferably 13V or higher.

  This allowable voltage Vm includes not only the increase in resistance of the organic EL element 20 but also the voltage drop caused by the supply line Z.

  Due to the influence of the wiring resistance of the supply line Z, the power consumption of the display panel 1 is significantly increased if the voltage drop is large. For this reason, the voltage drop of the supply line Z is particularly preferably set to 1 V or less.

As a result of considering the pixel width Wp, which is the length of one subpixel P in the row direction, and the number of pixels in the row direction (1366), when the panel size of the display panel 1 is 32 inches or 40 inches, the supply line Z The total length is 706.7 mm and 895.2 mm, respectively. Here, when the line width WL of the metal partition wall W is widened, the area of the organic EL layer 20b is structurally reduced, and further, a parasitic capacitance with other wiring is generated to cause a further voltage drop. The line width WL is desirably suppressed to one fifth or less of the pixel width Wp. Considering this, when the panel size of the display panel 1 is 32 inches and 40 inches, the line widths WL are within 34 μm and within 44 μm, respectively. In addition, the maximum film thickness Hmax of the metal partition wall W is 1.5 times the minimum processing dimension 4 μm of the transistors 21 to 23, that is, 6 μm, considering the aspect ratio. Thus, the maximum cross-sectional area Smax of the metal barrier wall W 32 inch, 40 inches, respectively 204Myuemu ^2, a 264μm ^2.

  For such a 32-inch display panel 1, in order to make the maximum voltage drop of the metal partition wall W 1 V or less when fully lit so that the maximum current flows, the wiring resistance of the metal partition wall W as shown in FIG. The ratio ρ / cross-sectional area S needs to be set to 4.7 Ω / cm or less. FIG. 7 shows the correlation between the cross-sectional area of the metal partition wall W of the 32-inch display panel 1 and the current density. Note that the resistivity allowed at the maximum cross-sectional area Smax of the metal partition wall W is 9.6 μΩcm at 32 inches and 6.4 μΩcm at 40 inches.

  For the 40-inch display panel 1, in order to make the maximum voltage drop of the metal partition wall W 1 V or less when fully lit so that the maximum current flows, the wiring resistance of the metal partition wall W as shown in FIG. The ratio ρ / cross-sectional area S needs to be set to 2.4 Ω / cm or less. FIG. 9 shows the correlation between the cross-sectional area of the metal partition wall W of the 40-inch display panel 1 and the current density.

  The failure life MTF that stops operating due to the failure of the metal partition wall W satisfies the following formula (2).

MTF = A exp (Ea / K _b T) / ρJ ² (2)
Here, Ea is the activation energy, K _b T = 8.617 × 10 ⁻⁵ eV, ρ is the resistivity of the metal partition wall W, and J is the current density.

The failure life MTF of the metal partition wall W is limited by an increase in resistivity and electromigration. When the metal partition wall W is set to Al (single Al or an alloy such as AlTi or AlNd) and the MTF is estimated for 10,000 hours at an operating temperature of 85 ° C., the current density J is 2.1 × 10 ⁴ A / cm ² or less. It is necessary to. Similarly, when the metal partition wall W is set to Cu, it is necessary to make it 2.8 × 10 ⁶ A / cm ² or less. It is assumed that materials other than Al in the Al alloy have a lower resistivity than Al.
Taking these into consideration, in the 32-inch display panel 1, the cross-sectional area S of the Al-based metal partition wall W that does not cause the metal partition wall W to fail in 10,000 hours in the fully lit state is as shown in FIG. 57 μm ² or more is required, and similarly, the cross-sectional area S of the Cu metal partition wall W is 0.43 μm ² or more as shown in FIG.

In the 40-inch display panel 1, the cross-sectional area S of the Al-based metal partition wall W is required to be 92 μm ² or more as shown in FIG. . Similarly, the cross-sectional area S of the Cu metal partition wall W is required to be 0.69 μm ² or more as shown in FIG.

In the Al-based metal partition wall W, if the Al-based resistivity is 4.00 μΩcm, the 32-inch display panel 1 has a wiring resistivity ρ / cross-sectional area S of 4.7 Ω / cm or less as described above. The area Smin is 85.1 μm ² . At this time, as described above, since the wiring width WL of the metal partition wall W is within 34 μm, the minimum film thickness Hmin of the metal partition wall W is 2.50 μm.

Further, in the 40-inch display panel 1 with the Al-based metal partition wall W, the wiring resistivity ρ / cross-sectional area S is 2.4 Ω / cm or less as described above, so the minimum cross-sectional area Smin is 167 μm ² . At this time, since the wiring width WL of the metal partition wall W is within 44 μm as described above, the minimum film thickness Hmin of the metal partition wall W is 3.80 μm.

On the other hand, if the Cu metal partition wall W has a Cu resistivity of 2.10 μΩcm, the 32-inch display panel 1 has a wiring resistivity ρ / cross-sectional area S of 4.7 Ω / cm or less as described above. The minimum cross-sectional area Smin is 44.7 μm ² . At this time, as described above, since the wiring width WL of the metal partition wall W is within 34 μm, the minimum film thickness Hmin of the metal partition wall W is 1.31 μm.

Further, in the 40-inch display panel 1 with the Cu metal partition wall W, the wiring resistivity ρ / cross-sectional area S is 2.4 Ω / cm or less as described above, so the minimum cross-sectional area Smin is 87.5 μm ^2. . At this time, since the wiring width WL of the metal partition wall W is within 44 μm as described above, the minimum film thickness Hmin of the metal partition wall W is 1.99 μm.

  From the above, in order to operate the display panel 1 normally and with low power consumption, it is preferable to set the voltage drop at the metal partition wall W to 1 V or less. In an Al-based 32-inch panel, the thickness dimension H is 2.50 μm to 6 μm, the width dimension WL is 14.1 μm to 34.0 μm, the resistivity is 4.0 μΩcm to 9.6 μΩcm, and the metal partition wall W is an Al system. When the metal partition wall W is made of Al, the thickness dimension H is 3.80 μm to 6 μm, the width dimension WL is 27.8 μm to 44.0 μm, and the resistivity is 4.0 μΩcm to 9.6 μΩcm. Become.

In general, in the case of the Al-based metal partition wall W, the thickness dimension H is 2.50 μm to 6 μm, the width dimension WL is 14.1 μm to 44 μm, and the resistivity is 4.0 μΩcm to 9.6 μΩcm.
Similarly, in a 32-inch panel having a metal partition wall W of Cu, the thickness dimension H is 1.31 μm to 6 μm, the width dimension WL is 7.45 μm to 34 μm, and the resistivity is 2.1 μΩcm to 9.6 μΩcm. In a 40-inch panel in which W is Cu, when the metal partition wall W is Cu-based, the thickness dimension H is 1.99 μm to 6 μm, the width dimension WL is 14.6 μm to 44.0 μm, and the resistivity is 2.1 μΩcm to 9 .6 μΩcm.

In general, in the case of the Cu metal partition wall W, the thickness dimension H is 1.31 μm to 6 μm, the width dimension WL is 7.45 μm to 44 μm, and the resistivity is 2.1 μΩcm to 9.6 μΩcm.
Accordingly, when an Al-based material or Cu is applied as the metal partition wall W, the metal partition wall W of the display panel 1 has a thickness dimension H of 1.31 μm to 6 μm, a width dimension WL of 7.45 μm to 44 μm, and a resistivity of 2. .1 μΩcm to 9.6 μΩcm.

Next, a display panel manufacturing method will be described with reference to FIGS.
First, the transistor array panel 50 is formed by appropriately performing a vapor phase growth method, a photolithography method, and an etching method several times. A contact hole 91 is formed in each subpixel P in the transistor array panel 50, and then a conductive pad 92 is embedded in the formed contact hole 91 by electrolytic plating or the like, and a vapor phase growth method, a photolithography method, an etching method is performed. By sequentially performing the method, the subpixel electrode 20a as shown in FIG. 10 is patterned. Thereafter, as shown in FIG. 11, a solid insulating film 34 is formed on the upper surface of the transistor array panel 50 including the subpixel electrodes 20a by vapor deposition.

Next, as shown in FIG. 12, the insulating film 34 formed on the entire surface by the photolithography method and the etching method is removed except for a part above the signal line Y, so that one part of the planarizing film 33 is formed. After the portion and most of the subpixel electrode 20a are exposed, a thin film pattern 35 is formed on a part of the exposed portion of the planarization film 33 as shown in FIG. Note that the thin film pattern 35 is formed together with a part or all of the subpixel electrode 20a by collectively patterning a material to be a conductive film constituting part or all of the subpixel electrode 20a in the stage of FIG. May be. Thereafter, the transistor array panel 50 is exposed to plasma generated using a fluorine-based gas such as methyl tetrafluoride to make the exposed surfaces of the planarizing film 33 and the insulating film 34 liquid repellent.
On the other hand, the subpixel electrode 20a and the thin film pattern 35 do not show strong liquid repellency because they contain a metal and have poor bonding with fluorine or fluoride.

Furthermore, as shown in FIG. 14, by using an inkjet head or a dispenser, metal fine particles containing at least one of gold, silver, copper, aluminum, and an alloy containing these as main components are used as a dispersion medium such as a curable liquid resin. The dispersed droplets containing conductive fine particles are attached while aiming at the upper surface of the thin film pattern 35. At this time, since the flattening film 33 around the thin film pattern 35 exhibits liquid repellency, the conductive fine particle-containing liquid droplets are selectively attached to the thin film pattern 35 because the conductive fine particle-containing liquid droplets can be easily repelled. It will be. Thereafter, the conductive fine particle-containing liquid droplets are heated to evaporate the dispersion medium, and then sintered to melt the fine particles to form a lump of metal partition walls W.
Instead of attaching the conductive fine particle-containing liquid droplets, the metal partition wall W may be patterned by spraying and attaching metal fine particles at least partially molten with a carrier gas.

  After the metal partition walls W are stacked, the transistor array panel 50 is cleaned by an ultraviolet / ozone cleaning method, and an aqueous solution of a triazine derivative represented by the following chemical formula (1) or the following chemical formula (2) is applied to the entire surface of the transistor array panel 50. The metal partition wall W is subjected to surface treatment by immersing the transistor array panel 50 in an aqueous triazine derivative solution. At this time, due to the property of the triazine derivative, a reductive desorption reaction is selectively caused on the surface of the metal partition wall W, and the liquid repellent conductive film is selectively formed on the surface of the metal partition wall W as shown in FIG. However, the liquid repellent conductive film 36 is not formed on the surface of the conductive oxide or the surface of the planarizing film 33 to the extent that the liquid repellent conductive film 36 exhibits liquid repellency. It has become.

Here, the fluorine-based triazine thiol derivative represented by the chemical formula (2) is insoluble in water, but if dissolved together with the same molar amount of NaOH or KOH, it is dissolved in water to prepare a fluorine-based triazine thiol derivative aqueous solution. be able to. At this time, the concentration of the aqueous solution is in the range of 1 × 10 ⁻⁴ to 1 × 10 ⁻² mol / L.
In addition, when using fluorine-type triazine thiol derivative aqueous solution, it is preferable that the temperature of aqueous solution shall be 20-30 degreeC, and immersion time shall be 1 to 30 minutes.

  Thereafter, the transistor array panel 50 is immersed in an aqueous solution of triazine derivative, and then the transistor array panel 50 is taken out. The transistor array panel 50 is washed with alcohol, so that excess triazine derivative is removed.

Further, the transistor array panel 50 is washed again with water, and the transistor array panel 50 is dried by blowing an inert gas such as nitrogen gas (N ₂ ) to the transistor array panel 50.

  Next, the sub-pixel electrode 20a is exposed by patterning the insulating film 34 in a mesh pattern by sequentially performing a photolithography method and an etching method on the insulating film 34.

  Next, as a hole injection material, for example, an organic compound-containing liquid in which PEDOT and PSS are dispersed in water is applied to the subpixel electrode 20a to form the hole transport layer 20d. At this time, as a coating method, a droplet discharge method such as an ink jet method or other printing method may be used, or a coating method such as a dip coating method or a spin coating method may be used. In order to form the hole transport layer 20d independently for each electrode 20a, a printing method such as an inkjet method is preferably used.

  After the hole transport layer 20d is formed, the transistor array panel 50 is heat-treated at a temperature of 160 to 180 ° C. using a hot plate. Then, red, green, and blue light emitting materials such as polyphenylene light emitting materials and polyfluorene light emitting materials are dissolved in organic solvents (eg, tetralin, tetramethylbenzene, mesitylene), respectively, and red, green, and blue organics are dissolved. A compound-containing solution is prepared. Then, a red organic compound-containing liquid is applied on the hole transport layer 20d of the red subpixel P, and a green organic compound-containing liquid is applied on the hole transport layer 20d of the green subpixel P, On the hole transport layer 20d of the blue subpixel P, a blue organic compound-containing liquid is applied. Thereafter, the light emitting layer 20e is formed on the upper surface of the hole transport layer 20d for each color by using an inkjet method (droplet discharge method) or other printing methods.

  Before forming the light emitting layer 20e, an interlayer layer may be laminated on the upper surface of the hole transport layer 20d by a wet coating method such as an inkjet method, and the light emitting layer 20e may be further laminated on the upper surface of the interlayer layer. Good.

Next, for example, the transistor array panel 50 is dried using a hot plate in an atmosphere of an inert gas such as nitrogen gas, and the residual solvent is removed.
In addition, you may dry in a vacuum using a season heater.

After drying, the counter electrode 20c is formed on the entire surface of the light emitting layer 20e by vapor phase growth. Specifically, a conductive thin film having a work function of 4.0 eV or less, such as Ca, Ba, Li, Mg, etc., is formed on the entire surface by vacuum deposition, and the sheet resistance is higher than the thin film on this thin film. A conductive film having a high work function such as Al or ITO deposited at a low thickness is formed on the entire surface.
Finally, for example, an ultraviolet curable or thermosetting adhesive is applied to a sealing substrate such as a metal cap or a glass substrate, and the sealing substrate and the counter electrode 20c are adhered to each other by the adhesive. As shown in FIG. 4, the display panel 1 is completed.

  At this time, since the thin film pattern 35 having high adhesion to the metal nanopace is patterned on the upper surface of the planarizing film 33, the conductive fine particle-containing droplets are difficult to adhere to the planarizing film 33. Even so, the metal partition wall W made of the conductive fine particle-containing droplets can be easily formed on the upper surface of the planarizing film 33.

  Further, the exposed portion of the planarizing film 33 and the peripheral portion of the thin film pattern 35 are subjected to a liquid repellency treatment by exposure to plasma generated in a fluorine-based gas atmosphere, and thus are discharged from the inkjet head. Even when the conductive fine particle-containing liquid droplets landed away from the upper surface of the thin film pattern 35, the conductive fine particle-containing liquid droplets move from the periphery of the thin film pattern 35 to the upper surface of the thin film pattern 35. Conductive fine particle-containing droplets can be stacked only on the upper surface of the pattern 35.

Further, when the hole transport layer 20d is formed by the wet coating method as described above, a thick metal partition wall W is provided, and a liquid repellent conductive film having liquid repellency on the surface of the metal partition wall W is provided. 36 is coated, the organic compound-containing liquid applied to the adjacent subpixel electrode 20a is prevented from mixing over the metal partition wall W, so that an independent hole transport layer is provided for each subpixel electrode 20a. 20d can be formed.
Further, the hole transport layer 20d can be formed with a uniform film thickness by preventing the organic compound-containing liquid applied to the subpixel electrode 20a from becoming thick at the outer edge of the upper surface of the subpixel electrode 20a. Can do.

  Further, when the light emitting layer 20e is formed by the wet coating method as described above, a thick metal partition wall W is provided, and a liquid repellent conductive film 36 having liquid repellency is provided on the surface of the metal partition wall W. Since it is coated, the organic compound-containing liquid applied to the adjacent subpixel P is prevented from mixing beyond the metal partition wall W, whereby an independent light emitting layer 20e can be formed for each subpixel P. it can.

  As described above, according to the wiring, the patterning method thereof, the display panel, and the manufacturing method thereof in the present embodiment, the thin film pattern 35 having high adhesion to the conductive fine particle-containing droplets is formed on the upper surface of the insulating substrate 2. Therefore, even when the conductive fine particle-containing droplets are difficult to adhere to the insulating substrate 2, the metal partition wall W made of the conductive fine particle-containing droplets can be easily formed. For this reason, the adhesion of the metal partition wall W to the insulating substrate 2 is improved, the peeling of the metal partition wall W is prevented, and the metal partition wall W can be easily formed at a desired position on the insulating substrate 2. The patterning accuracy of the metal partition wall W can be improved.

  Further, the peripheral portion of the thin film pattern 35 on the insulating substrate 2 has been subjected to a liquid repellent treatment, so that the conductive fine particle-containing liquid droplets ejected from the ink jet head have landed off the top surface of the thin film pattern 35. However, the conductive fine particle-containing droplets can be laminated only on the upper surface of the thin film pattern 35 by preventing the droplets containing the conductive fine particles from adhering to the periphery of the thin film pattern 35 that has been subjected to the liquid repellent treatment. Therefore, the patterning accuracy of the metal partition wall W can be improved more effectively.

  In the above-described embodiment, the switch transistor 21, the holding transistor 22, and the drive transistor 23 are not limited to amorphous silicon TFTs, and may be polysilicon TFTs, or some or all of them may be P-channels even if they are not all N-channels. But you can.

  In this embodiment, the subpixel electrode 20a is an anode and the counter electrode 20c is a cathode. However, the subpixel electrode 20a may be a cathode and the counter electrode 20c may be an anode.

It is a longitudinal cross-sectional view which shows a series of processes in the patterning process of wiring. It is a top view which shows the outline of the structure of a display panel. It is an equivalent circuit diagram of a subpixel. It is a longitudinal cross-sectional view which shows the surface IV-IV in FIG. It is a graph which shows the current-voltage characteristic of the drive transistor and organic EL element in a subpixel. It is a graph which shows the correlation with the maximum voltage drop of a metal partition in 32 inch display panel, and wiring resistivity (rho) / cross-sectional area S. It is a graph which shows the correlation with the cross-sectional area of a metal partition in a 32-inch display panel, and a current density. It is a graph which shows the correlation with the maximum voltage drop of a metal partition in 40-inch display panel, and wiring resistivity (rho) / sectional area S. FIG. It is a graph which shows the correlation with the cross-sectional area of a metal partition in a 40-inch display panel, and an electric current density. It is a longitudinal cross-sectional view which shows the aspect of the insulated substrate in the manufacturing process of a display panel. It is a longitudinal cross-sectional view which shows the aspect of the insulated substrate in the manufacturing process of a display panel. It is a longitudinal cross-sectional view which shows the aspect of the insulated substrate in the manufacturing process of a display panel. It is a longitudinal cross-sectional view which shows the aspect of the insulated substrate in the manufacturing process of a display panel. It is a longitudinal cross-sectional view which shows the aspect of the insulated substrate in the manufacturing process of a display panel. It is a longitudinal cross-sectional view which shows the aspect of the insulated substrate in the manufacturing process of a display panel.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Display panel 2 Insulating substrate 33 Flattening film 34 Insulating film 35 Thin film pattern 50 Transistor array panel 550 Transistor array panel 551 Thin film 552 Resist 553 Conductive microparticle containing droplet 554 Wiring 560 Inkjet head W Metal partition

Claims (8)

In a method for manufacturing a display panel in which wiring is patterned in a display region of a display panel by a wiring patterning method of patterning high-density wiring on an upper surface of a substrate,
Forming a first metal film and a second metal film on the non-metal film provided on the upper surface of the substrate in the display panel so that the non-metal film is exposed in the surroundings;
Applying a liquid repellent treatment to the non-metal film around the first metal film and the second metal film;
A step of attaching the conductive fine particle-containing droplets or metal fine particles to the upper surface of the first metal film using an inkjet head or a dispenser, and forming the wiring to be a metal partition that partitions the pixels;
Forming a liquid repellent conductive film selectively on the surface of the wiring;
After the step of forming the liquid repellent conductive film, forming an organic EL layer and a third metal film on the upper surface of the second metal film;
A method for manufacturing a display panel, comprising: The step of forming the liquid repellent conductive film is a step of applying an aqueous solution of a triazine derivative to the entire surface of the display panel and selectively forming the liquid repellent conductive film on the wiring surface. The manufacturing method of the display panel of Claim 1 .   The method for manufacturing a display panel according to claim 1, wherein the liquid repellent treatment exposes the substrate in plasma generated using a fluorine-based gas.   3. The method of manufacturing a display panel according to claim 1, wherein the liquid repellent treatment exposes the substrate in F2 gas.   5. The display panel manufacturing method according to claim 1, wherein the conductive fine particle-containing liquid droplets are deposited on the metal film by a liquid droplet ejection method. 6.   The method of manufacturing a display panel according to claim 1, wherein the metal fine particles are attached by directly spraying the metal fine particles.   5. The display panel manufacturing method according to claim 1, wherein the first metal film has a thickness of 1 nm to 30 nm.   A display panel manufactured by the manufacturing method according to claim 1.

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