JP4756701B2 - Power supply voltage detection circuit - Google Patents

Description

  The present invention relates to a power supply voltage detection circuit, and more particularly to a power supply voltage detection circuit used in a semiconductor integrated circuit having a standby mode.

  In a microcomputer, when the power supply voltage drops below a certain reference voltage, the circuit operation becomes unstable and malfunctions. From the viewpoint of preventing this, the microcomputer has a built-in power supply voltage detection circuit that monitors whether the power supply voltage is within a voltage range that can guarantee normal operation of the semiconductor integrated circuit. When the power supply voltage falls below a certain voltage, a predetermined detection signal is output from the power supply voltage detection circuit, and an automatic reset operation is performed.

FIG. 3 is a schematic diagram of a conventional general power supply voltage detection circuit 100. The power supply voltage detection circuit 100 includes a band gap type reference voltage generation circuit 101 that outputs a constant reference voltage Vref, and a voltage dividing circuit that divides the power supply voltage Vdd into a divided voltage Vx by voltage dividing resistors Ra and Rb. And a comparator 102 that compares these outputs and outputs the determination result. The power detection signal comparator 102 outputs a voltage detection signal V _1.

  Next, the reference voltage generation circuit 101 will be described with reference to FIG. The bandgap-type reference voltage generation circuit 101 is a circuit using a bandgap voltage (a semiconductor intrinsic voltage, which is about 1.2 V in the case of silicon). (For example, see Patent Document 1)

P-channel MOS transistors (hereinafter referred to as PMOS) Ma and Mb of the same size connected to the power supply voltage Vdd are mirror-connected to form a current mirror circuit. The drain of the PMOSMa on the output side of this current mirror circuit is connected to the collector of an NPN type BIP transistor Q ₁ (bipolar transistor) via resistors Rc and Rd connected in series. The emitter of the NPN BIP transistor Q ₁ is connected to the ground voltage, its base - the scan is connected to the connection point of the resistors Rc, Rd.

On the other hand, the drain of the PMOS Mb of the current mirror circuit is connected to the collector side of _K NPN-type BIP transistors Q _{2 to} Q _{K + 1} whose emitter, base, and collector are commonly connected. The emitter sides of the NPN type BIP transistors Q _{2 to} Q _{K + 1} are connected to the ground voltage, and the base side is connected to the collector of the NPN type BIP transistor Q ₁ . The reference voltage Vref is output from the drain of the NPN BIP transistor Q _1. However, the NPN BIP transistors Q ₁ , Q _{2 to} Q _{K + 1} are all the same size.

In the supply voltage detection circuit 100, equal to or less than the voltage Vdd ₁ is the power supply voltage Vdd as shown in FIG. 5, and when the divided voltage Vx is less than or equal to the reference voltage Vref, the voltage detection signal V ₁ was a high level Become. The power supply voltage detection signal V ₁ of the said high level is supplied to other circuits as a reset signal, the reset operation of the other circuit is made.

  By the way, in a microcomputer, there exists a state called a low power consumption state (henceforth a standby mode) other than a normal operation state (henceforth a normal operation mode). The standby mode is a state in which not all circuits are operating, but some circuits (for example, a CPU and an oscillation circuit) are not operating.

Techniques related to the present invention are described in, for example, the following patent documents.
JP-A-6-75649 Japanese Patent Laid-Open No. 11-119873

  However, the power supply voltage detection circuit as described above has the following two problems. First, while the above-described power supply voltage detection circuit has the advantage of high detection accuracy, it has a problem that it consumes a large amount of current and is not suitable for a standby mode that requires low current consumption.

  Secondly, in the standby mode, even if the power supply voltage is equal to or lower than the operation guarantee voltage in the normal operation mode, there may be no problem in operation as long as it is a certain value or more. For example, it is a case where data is held in a storage element such as a memory or a register. However, in the above-described conventional power supply voltage detection circuit, the detection level (the level of the power supply voltage Vdd that becomes the boundary where the detection signal is inverted) is set within the range of the operation guarantee voltage in the normal operation mode (for example, 3 V to 5 V). . Therefore, for example, when the power supply voltage drops instantaneously and then recovers immediately, a signal for detecting a low voltage is output in spite of the fact that the reset operation is not necessarily required in the standby mode. There was a thing. As a result, there is a problem that the LSI is in a reset state and data held in the memory or register is lost.

  SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a power supply voltage detection circuit that realizes a low current consumption and can prevent an unexpected reset operation in a semiconductor integrated circuit having a standby mode.

  The present invention has been made in view of the above problems, and the main features are as follows. That is, the power supply voltage detection circuit according to the present invention compares the first reference voltage generation circuit of the band gap type with the first reference voltage output from the first reference voltage generation circuit and a voltage corresponding to the power supply voltage. A first power supply voltage detection circuit for outputting a first power supply voltage detection signal from the comparator, and a resistor and a transistor or a diode connected in series to output a second power supply voltage detection signal. A second power supply voltage detection circuit; and a selection circuit that selectively outputs the first power supply voltage detection signal in the normal operation mode and selectively outputs the second power supply voltage detection signal in the standby mode. The second power supply voltage detection circuit is characterized in that the detection level of the power supply voltage is set lower than that of the first power supply voltage detection circuit.

  The power supply voltage detection circuit according to the present invention includes a control circuit that stops supply of power supply voltage to the first reference voltage generation circuit and the comparator in the standby mode.

  In the power supply voltage detection circuit of the present invention, a plurality of power supply voltage detection circuits having different detection levels are arranged, and a detection signal to be output is selected in a normal operation mode and a standby mode using a selection circuit. Therefore, according to the present invention, it is possible to suppress detection of an unexpected low voltage in the standby mode as compared with the conventional case.

  Further, by providing a control circuit for stopping the supply of the power supply voltage to the power supply voltage detection circuit for the normal operation mode in the standby mode, a standby mode with a lower current consumption than in the prior art can be realized. .

  Next, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol is shown about the structure similar to the past, and the description is abbreviate | omitted or simplified.

  As shown in FIG. 1, the power supply voltage detection circuit of this embodiment mainly selects a first power supply voltage detection circuit 10, a second power supply voltage detection circuit 20, and signals output from these circuits. And a selection circuit 30 for outputting.

The first power supply voltage detection circuit 10 will be described. The first power supply voltage detection circuit 10 is a power supply voltage detection circuit corresponding to the normal operation mode of the microcomputer, and is a circuit for detecting whether or not the power supply voltage Vdd is within the range of the operation guarantee voltage in the normal operation mode. It is. The first power supply voltage detection circuit 10 includes a first reference voltage generating circuit 11 of the bandgap for outputting a constant reference voltage Vref, the by the power supply voltage Vdd voltage dividing resistors R ₁ and R ₂ in the divided voltage Vx A voltage dividing circuit 12 that divides and outputs the voltage and a comparator 13 that compares the respective outputs and outputs the determination result are provided. A specific circuit configuration example of the first reference voltage generation circuit 11 is the same as that shown in FIG.

The first reference voltage generating circuit 11, as a control circuit for controlling the supply of the power supply voltage Vdd to the voltage divider circuit 12 and a comparator 13, PMOSM ₁ ~M ₃ the standby signal STB is applied to the gate each Connected to the circuit. If the standby mode, the standby signal STB becomes high level, PMOSM ₁ ~M ₃ the supply of the power supply voltage Vdd to the first power supply voltage detecting circuit 10 is turned off to stop. On the other hand, in the normal operation mode, the standby signal STB becomes low level, the PMOSM _{1 to} M ₃ are turned on, and the power supply voltage Vdd is supplied to the first power supply voltage detection circuit 10.

A detection signal output from the comparator 13 to the first power supply voltage detection signal V _1. In the first power supply voltage detection circuit 10, when the power supply voltage Vdd is smaller than the first voltage Vdd ₁ and the divided voltage Vx is smaller than the first reference voltage Vref, as shown in FIG. first power supply voltage detection signal V ₁ of the level is output. First power supply voltage detection signal V ₁ of the high level is a signal for detecting a voltage drop in the normal operation mode, is supplied as a reset signal to other circuits via the selection circuit 30 to be described later.

Here, the first voltage Vdd ₁ is a voltage value within the range of the operation guarantee voltage in the normal operation mode, and is a voltage value at which the level of the first power supply voltage detection signal V ₁ is inverted. When the power supply voltage Vdd is smaller than the first voltage Vdd ₁ and the divided voltage Vx is smaller than the first reference voltage Vref, a high-level first power supply voltage detection signal V as shown in FIG. ₁ is output.

The second power supply voltage detection circuit 20 will be described. The second power supply voltage detection circuit 20 is a power supply voltage detection circuit corresponding to the standby mode of the microcomputer, and is a circuit for detecting whether or not the power supply voltage Vdd is within the operation guarantee voltage range of the standby mode. . In other words, the second power supply voltage detection circuit 20 is a circuit that uses a voltage value (referred to as the second voltage Vdd ₂ ) lower than that of the first power supply voltage detection circuit 10 as a detection level. Furthermore, the second voltage Vdd ₂ is a voltage value (for example, 1 volt) lower than the lowest voltage value guaranteed for operation in the normal operation mode.

Second power supply voltage detection circuit 20, for example, the power supply voltage Vdd and N-channel type MOS transistor in series-connected resistors R ₃ and the gate and drain are short-circuited between the ground voltage GND (hereinafter referred to as NMOS) M ₄ and _{M 5,} and a resistor _{R 3} and NMOSM ₄ and buffer connected 21. to the connection point of the.

The gate of NMOSM ₄ is connected to a connection point between the power supply voltage Vdd and the resistor _{R 3.} Then, the second power supply voltage detection signal V ₂ is output through the buffer 21 from the connection point between the resistor R ₃ and the NMOS M ₄ . The resistor _{R 3} is as a high resistance compared to NMOSM ₄ and _{M 5.} The threshold values of the NMOSs M ₄ and M ₅ are Vt.

In the second power supply voltage detection circuit 20, the power supply (in this embodiment, _{NMOSM 4} and _{M 5} in the threshold Vt of the added value = 2Vt) second voltage Vdd ₂ voltage Vdd is above is smaller than is, NMOSM ₄ and _{M 5} are turned off, the power supply voltage detection signal _{V 2} of the second as shown in FIG. 2 is a high level. As described above, the relationship of the second voltage Vdd ₂ <the first voltage Vdd ₁ is established. Second power supply voltage detection signal V ₂ of the high level is a signal for detecting a voltage drop in the standby mode, it is supplied as a reset signal to other circuits via the selection circuit 30 to be described later.

On the other hand, when the power supply voltage Vdd is larger than the second voltage Vdd ₂ , the NMOS M ₄ and M ₅ are turned on, so that the second power supply voltage detection signal V ₂ becomes low level as shown in FIG.

Thus, the second power supply voltage detection circuit 20 is a power supply voltage detection circuit dedicated to the standby mode, and thereby detects a voltage level lower than that of the first power supply voltage detection circuit 10. Note that the detection level (second voltage Vdd ₂ ) of the second power supply voltage detection circuit 20 can be arbitrarily set by adjusting the threshold values of the NMOSs M ₄ and M ₅ and the number of transistors to be arranged. it can. In addition, a diode element can be arranged instead of the transistor.

Selection circuit 30 is a so-called multiplexer (Multiplexer), in the case of the normal operation mode selectively outputs the first power supply voltage detection signal V ₁ output from the first power supply voltage detection circuit 10, the standby mode in the case of those for outputting a second power supply voltage detection signal V ₂ output from the second power supply voltage detection circuit 20 selectively. Specifically, for example, as shown in FIG. 1, the first power supply voltage detection signal V1 is input to the _first input terminal, and the standby signal STB is input to the second input terminal via the inverter 32. a circuit 31, the standby signal STB to the first input terminal is input, a second power supply voltage detection signal _V aND circuit _{33 2} is input to the second input terminal, the output of the aND circuit 31 and 33 respectively And an OR circuit 34 inputted to the input terminal. According to the selection circuit 30, in the normal operation mode (standby signal STB is low level) first power supply voltage detection signal V ₁ is output to the, in the case of the standby mode (standby signal STB is high level) the second power supply voltage detection signal V ₂ is output.

Next, the operation of the above circuit will be described. In the normal operation mode of the microcomputer, the standby signal STB is at a low level, the PMOS M _{1 to} M ₃ are turned on, and the power supply voltage Vdd is supplied to the reference voltage generation circuit 11, the voltage dividing circuit 12 and the comparator 13. When the power supply voltage Vdd is higher than the first voltage Vdd ₁ , a low-level first power supply voltage detection signal V ₁ is output from the selection circuit 30 as shown in FIG. When the power supply voltage Vdd is smaller than the first voltage Vdd ₁ , the signal is inverted and the high-level first power supply voltage detection signal V ₁ is output, and the reset operation is performed.

On the other hand, in the standby mode, the standby signal STB is at a high level, the PMOSs M _{1 to} M ₃ are turned off, and the power supply voltage Vdd is not supplied to the first power supply voltage detection circuit 10. When the power supply voltage Vdd is larger than the second voltage Vdd ₂ , a low-level second power supply voltage detection signal V ₂ is output from the selection circuit 30. When the power supply voltage Vdd is lower than the second voltage Vdd ₂ , the signal is inverted and a high-level second power supply voltage detection signal V ₂ is output, and a reset operation is performed.

  Thus, in the present embodiment, the first power supply voltage detection circuit 10 in which the detection level is set within the range of the operation guarantee voltage in the normal operation mode, and the detection level is set lower than the operation guarantee voltage in the normal operation mode. The second power supply voltage detection circuit 20 is arranged, and the selection circuit 30 selectively outputs only one of the detection signals according to the operation mode. Thereby, it is possible to suppress detection of an unexpected low voltage in the standby mode as compared with the conventional case. Then, an unnecessary reset operation can be suppressed, and the reset operation can be performed only when the reset operation is truly necessary.

  In the present embodiment, the power supply voltage is supplied only to the second power supply voltage detection circuit 20 with low current consumption in the standby mode, and the power supply voltage is supplied to the first power supply voltage detection circuit 10 with high current consumption. Is stopped. Therefore, it is possible to realize a standby mode that consumes less current than in the prior art.

It goes without saying that the present invention is not limited to the above-described embodiment, and that design changes can be made without departing from the scope of the invention. For example, the band gap type reference voltage generation circuit 11 may have a circuit configuration using an NPN type BIP transistor as shown in FIG. 4 or a circuit configuration using a PNP type BIP transistor. The second consideration of the supply voltage delay of the detection signal V _2, etc., may not place the buffer 21 described above.

1 is a circuit diagram showing a power supply voltage detection circuit according to an embodiment of the present invention. It is a wave form diagram which shows operation | movement of the power supply voltage detection circuit which concerns on embodiment of this invention. It is a circuit diagram which shows the conventional power supply voltage detection circuit. It is a circuit diagram showing a band gap type reference voltage generating circuit. It is a wave form diagram which shows the operation | movement of the conventional power supply voltage detection circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 1st power supply voltage detection circuit 11 Reference voltage generation circuit 12 Voltage dividing circuit 20 2nd power supply voltage detection circuit 21 Buffer 30 Selection circuit
31 AND circuit 32 Inverter 33 AND circuit 34 OR circuit 100 Power supply voltage detection circuit 101 Reference voltage generation circuit 102 Comparator
M _{1 to} M ₃ , Ma, Mb P-channel MOS transistors M ₄ , M ₅ N-channel MOS transistors
Ra, Rb, Rc, Rd, R ₁ , R ₂ resistance Vx Divided voltage
Vref reference voltage Vref ₁ first reference voltage
STB standby signal V ₁ first power supply voltage detection signal V ₂ second power supply voltage detection signal Vdd power supply voltage Vdd ₁ first voltage Vdd ₂ second voltage
Q1-Q _{K + 1} NPN bipolar transistor

Claims (3)

A band gap type first reference voltage generating circuit;
A first power source that includes a comparator that compares the first reference voltage output from the first reference voltage generation circuit with a voltage corresponding to the power source voltage, and that outputs a first power source voltage detection signal from the comparator; A voltage detection circuit;
A second power supply voltage detection circuit configured by connecting a resistor and a transistor or a diode in series, and outputting a second power supply voltage detection signal;
A selection circuit that selectively outputs the first power supply voltage detection signal in the normal operation mode and selectively outputs the second power supply voltage detection signal in the standby mode;
In the second power supply voltage detection circuit, the power supply voltage detection level is set lower than that in the first power supply voltage detection circuit. The power supply voltage detection circuit according to claim 1, further comprising a control circuit that stops supply of power supply voltage to the first reference voltage generation circuit and the comparator in the standby mode. The power supply voltage according to claim 1 or 2, wherein a detection level of the power supply voltage of the second power supply voltage detection circuit is set in a range lower than an operation guarantee voltage in the normal operation mode. Detection circuit.

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