JP4747281B2 - Method of joining substrate and device using Au-Sn alloy solder paste - Google Patents
Method of joining substrate and device using Au-Sn alloy solder paste Download PDFInfo
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- JP4747281B2 JP4747281B2 JP2006090902A JP2006090902A JP4747281B2 JP 4747281 B2 JP4747281 B2 JP 4747281B2 JP 2006090902 A JP2006090902 A JP 2006090902A JP 2006090902 A JP2006090902 A JP 2006090902A JP 4747281 B2 JP4747281 B2 JP 4747281B2
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- 229910000679 solder Inorganic materials 0.000 title claims abstract description 116
- 229910015363 Au—Sn Inorganic materials 0.000 title claims abstract description 115
- 229910045601 alloy Inorganic materials 0.000 title claims abstract description 114
- 239000000956 alloy Substances 0.000 title claims abstract description 114
- 239000000758 substrate Substances 0.000 title claims abstract description 67
- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000012298 atmosphere Substances 0.000 claims abstract description 5
- 230000001590 oxidative effect Effects 0.000 claims abstract description 5
- 230000004907 flux Effects 0.000 claims description 11
- 239000000843 powder Substances 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 2
- 238000002156 mixing Methods 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 239000007789 gas Substances 0.000 description 15
- 239000010410 layer Substances 0.000 description 13
- 239000000463 material Substances 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 3
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000011888 foil Substances 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 239000012190 activator Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 239000002562 thickening agent Substances 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Die Bonding (AREA)
Abstract
Description
この発明は、Ａｕ−Ｓｎ合金はんだペーストを用いて基板と素子との間の接合部にボイドを発生させることなく接合する方法に関するものであり、特に使用中に発生した熱を放出する必要のある素子、例えば、ＬＥＤ（発光ダイオード）素子を基板に接合する方法に関するものである。 The present invention relates to a method of bonding without generating voids at a bonding portion between a substrate and an element using an Au—Sn alloy solder paste, and it is particularly necessary to release heat generated during use. The present invention relates to a method of bonding an element, for example, an LED (light emitting diode) element to a substrate.
ＬＥＤ（発光ダイオード）素子、ＧａＡｓ光素子、ＧａＡｓ高周波素子、熱伝素子などの半導体素子と基板との接合、特に熱がこもると破損に繋がるようなＬＥＤ（発光ダイオード）素子と基板との接合には、接合部の熱伝導性が非常に重要であるところから、熱伝導性が良くかつ信頼性が高い接合部を形成するＡｕ−Ｓｎ合金はんだ箔材(リボンなど)、Ａｕバンプ、Ａｕ−Ｓｎ合金はんだペーストなどが用いられていた。
For bonding a semiconductor element such as an LED (light-emitting diode) element, a GaAs optical element, a GaAs high-frequency element, or a heat transfer element to the substrate, particularly for bonding an LED (light-emitting diode) element and the substrate that may be damaged when heat is accumulated. Since the thermal conductivity of the joint is very important, an Au—Sn alloy solder foil material (ribbon or the like), Au bump, Au—Sn that forms a joint with good thermal conductivity and high reliability. Alloy solder paste has been used.
しかし、Ａｕ−Ｓｎはんだ合金箔材(リボンなど)は、材料自身の熱伝導性は高いものの接合時の濡れ性が悪いため接合領域を十分に広く取ることができず、また箔材表面には酸化膜が多いため溶融したＡｕ−Ｓｎはんだ合金の流動性が悪い。そのため加熱溶融しながら荷重をかけて接合する工法もあるが、加熱時間が長くまた長時間荷重をかけて接合しなければならないことから、熱を長時間かけることが好ましくないＬＥＤ（発光ダイオード）素子に適用することができない。さらに、Ａｕ−Ｓｎはんだ合金箔材の場合、素子に荷重をかけて接合することから素子側面部にＡｕ−Ｓｎはんだ合金が這い上がりショートを起こすこともあった。
However, Au-Sn solder alloy foil materials (ribbons, etc.) have high thermal conductivity, but the wettability at the time of bonding is poor, so that the bonding area cannot be made sufficiently wide. Since there are many oxide films, the fluidity of the molten Au—Sn solder alloy is poor. For this reason, there is a method of joining by applying a load while heating and melting, but an LED (light emitting diode) element in which it is not preferable to apply heat for a long time because the heating time is long and it is necessary to apply a load for a long time. Cannot be applied to. Further, in the case of the Au—Sn solder alloy foil material, since the load is applied to the element, the Au—Sn solder alloy may creep up on the side surface of the element and cause a short circuit.
また、Ａｕバンプ法による素子の接合は、素子全体にＡｕ−Ｓｎはんだ合金接合層が接合していないため、Ａｕ−Ｓｎはんだ合金接合層と接合していない部分の熱伝導が悪く、また、このＡｕバンプ法では３００℃以上の温度で荷重をかけながら接合を行なうが、３００℃以上高温を長時間保持する必要があり、熱影響を受けて劣化しやすいＬＥＤ（発光ダイオード）素子に適用することができなかった。
そのため、近年、熱影響を受けて劣化しやすいＬＥＤ（発光ダイオード）素子の接合には接合信頼性の一層優れたＡｕ−Ｓｎ合金はんだペーストが多く用いられるようになってきた。このＡｕ−Ｓｎ合金はんだペーストは、Ｓｎ：１５〜２５質量％（好ましくはＳｎ：２０質量％）を含有し、残りがＡｕおよび不可避不純物からなる組成を有するＡｕ−Ｓｎ共晶合金ガスアトマイズ粉末とロジン、活性剤、溶剤および増粘剤からなる市販のフラックスとを混合して作られる。
In addition, since the Au-Sn solder alloy bonding layer is not bonded to the entire element in the bonding of the elements by the Au bump method, the heat conduction of the portion not bonded to the Au-Sn solder alloy bonding layer is poor. In the Au bump method, bonding is performed while applying a load at a temperature of 300 ° C. or higher, but it is necessary to maintain a high temperature of 300 ° C. or higher for a long time, and it is applied to an LED (light emitting diode) element that is easily deteriorated due to thermal influence I could not.
For this reason, in recent years, Au-Sn alloy solder pastes with higher bonding reliability have been frequently used for bonding LED (light-emitting diode) elements that are easily deteriorated under the influence of heat. This Au—Sn alloy solder paste contains Sn: 15 to 25% by mass (preferably Sn: 20% by mass), and the remainder is composed of Au and inevitable impurities. Au—Sn eutectic alloy gas atomized powder and rosin It is made by mixing a commercially available flux consisting of an activator, a solvent and a thickener.
このＡｕ−Ｓｎ合金はんだペーストを使用して素子と基板を接合すると、接合部がＡｕ−Ｓｎ合金はんだで構成されているところから熱伝導性が良く接合信頼性も高いこと、ペーストであるので複数の接合部に一括供給できさらに一括熱処理できること、リフロー時にフラックスがＡｕ−Ｓｎはんだ合金表面を覆っているために酸化膜が少なく、そのため、接合時の溶融Ａｕ−Ｓｎはんだ合金の流動性が大きく、濡れが良くなって接合面積を拡大することができるところから素子全面を接合できること、さらに接合時に過剰な荷重をかける必要がないことなどのメリットがある。
この従来のＡｕ−Ｓｎ合金はんだペーストを用いて基板と素子を接合する方法を図２の側面説明図に基づいて具体的に説明する。Ａｕ−Ｓｎ合金はんだペーストを用いて基板と素子を接合するには図２（ａ）に示されるように、基板１にＡｕ−Ｓｎ合金はんだペースト２を搭載または塗布する。次に、このＡｕ−Ｓｎ合金はんだペースト２の真上に図２（ｂ）に示されるように素子３を搭載し、この状態で加熱してリフロー処理を施したのち冷却すると、図２（ｃ）に示されるように、Ａｕ−Ｓｎ合金はんだ接合層４を介して基板１と素子３が接合する（特許文献１または２など参照）。
When an element and a substrate are joined using this Au—Sn alloy solder paste, since the joint is made of Au—Sn alloy solder, the thermal conductivity is good and the joining reliability is high, and since it is a paste, a plurality of That can be supplied to the joints at the same time and further heat-treated at the same time, and the flux covers the surface of the Au—Sn solder alloy at the time of reflow, so that there is little oxide film. There are advantages such as that the entire surface of the element can be bonded since wetting improves and the bonding area can be expanded, and that it is not necessary to apply an excessive load during bonding.
A method of joining a substrate and an element using this conventional Au—Sn alloy solder paste will be specifically described based on the side view of FIG. In order to join the substrate and the element using the Au—Sn alloy solder paste, the Au—Sn
前述のように、Ａｕ−Ｓｎ合金はんだペーストは最も使いやすい接合材であるが、Ａｕ−Ｓｎ合金はんだペーストには前述のように有機物からなるフラックスを含んでおり、図２（ｂ）に示されるようにＡｕ−Ｓｎ合金はんだペースト２の真上に素子３を搭載し、この状態で加熱してリフロー処理を施すと、Ａｕ−Ｓｎ合金はんだペースト２は溶融する際にフラックスからガスが発生し、この時Ａｕ−Ｓｎ合金はんだペースト２の真上に素子３が被さっているために、溶融中に発生したガスが逃げ場を失って閉じ込められ、Ａｕ−Ｓｎ合金はんだ接合層４の中にボイド５が生成することがある。Ａｕ−Ｓｎ合金はんだ接合層４の中にボイド５が生成すると素子３と基板１との接合面積が少なくなり、接合面積が少なくなると素子３に発生した熱の放熱性が悪くなるので好ましくない。
As described above, the Au-Sn alloy solder paste is the most easy-to-use bonding material, but the Au-Sn alloy solder paste contains the flux made of organic matter as described above, and is shown in FIG. When the
本発明者らは、これら課題を解決すべく研究を行った。その結果、
Ａｕ−Ｓｎ合金はんだペーストを基板に搭載または塗布し、前記基板に搭載または塗布したＡｕ−Ｓｎ合金はんだペーストに素子の一部が接しかつ素子の一端が基板に接するように素子をＡｕ−Ｓｎ合金はんだペースト上に載置し、かかる状態でＡｕ−Ｓｎ合金はんだペーストを搭載または塗布しかつ素子を載置した基板を非酸化性雰囲気中でリフロー処理すると、基板に搭載または塗布したＡｕ−Ｓｎ合金はんだペーストの表面が一部被さることなく不完全に素子が載置されているところから、リフロー処理中に、Ａｕ−Ｓｎ合金はんだペーストが溶融してＡｕ−Ｓｎ合金はんだペーストに含まれるフラックスの分解ガスおよびＡｕ−Ｓｎ合金はんだペーストに含まれるＡｕ−Ｓｎ合金はんだ粉末が溶融してＡｕ−Ｓｎ合金はんだ粉末の表面の酸化膜とフラックスとが反応して生成したガスなどが放出されやすくなり、ガスが抜けた溶融Ａｕ−Ｓｎ合金はんだが生成し、このガスが抜けた溶融Ａｕ−Ｓｎ合金はんだが基板の表面を伝って素子の下に濡れ広がると、溶融Ａｕ−Ｓｎ合金はんだのセルフアライメント効果により素子が溶融Ａｕ−Ｓｎ合金はんだの中央に向かって引き戻され、ガスが十分に抜けた溶融Ａｕ−Ｓｎ合金はんだのほぼ中央に素子が乗った状態となり、かかる状態で冷却すると、基板と素子との間のＡｕ−Ｓｎ合金はんだ接合層の中にボイドが発生することなく接合することができる、という知見が得られたのである。
The present inventors have conducted research to solve these problems. as a result,
An Au—Sn alloy solder paste is mounted on or applied to a substrate, and the device is Au—Sn alloy so that a part of the element is in contact with the Au—Sn alloy solder paste mounted or applied on the substrate and one end of the element is in contact with the substrate. An Au—Sn alloy placed on or applied to the substrate is mounted on or applied to the solder paste, and the Au—Sn alloy solder paste is mounted or applied in such a state and the substrate on which the element is mounted is reflowed in a non-oxidizing atmosphere. Since the element is placed incompletely without partially covering the surface of the solder paste, the Au—Sn alloy solder paste melts during the reflow process, and the flux contained in the Au—Sn alloy solder paste is decomposed. Table of Au-Sn alloy solder powder by melting Au-Sn alloy solder powder contained in gas and Au-Sn alloy solder paste The gas generated by the reaction between the oxide film and the flux is easily released, and a molten Au—Sn alloy solder from which the gas has been released is generated, and the molten Au—Sn alloy solder from which the gas has been released forms the surface of the substrate. Then, when wet and spread under the element, the element is pulled back toward the center of the molten Au—Sn alloy solder by the self-alignment effect of the molten Au—Sn alloy solder, and the molten Au—Sn alloy solder from which the gas has sufficiently escaped is obtained. The element is placed almost in the center, and when it is cooled in such a state, it is possible to obtain the knowledge that the Au-Sn alloy solder joint layer between the substrate and the element can be joined without generating voids. It was.
この発明は、かかる知見に基づいて成されたものであって、 Ａｕ−Ｓｎ合金はんだペーストを基板に搭載または塗布し、前記基板に搭載または塗布したＡｕ−Ｓｎ合金はんだペーストの表面に素子の一部が接しかつ素子の一端が基板に接するように素子をＡｕ−Ｓｎ合金はんだペースト上に載置し、かかる状態でＡｕ−Ｓｎ合金はんだペーストを搭載または塗布しかつ素子を載置した基板を非酸化性雰囲気中でリフロー処理し、溶融Ａｕ−Ｓｎ合金はんだが前記素子の下に濡れ広がって潜り込み、該素子が溶融Ａｕ−Ｓｎ合金はんだの中央に向かって引き戻された後、前記素子の全体が溶融Ａｕ−Ｓｎ合金はんだに乗った状態で冷却するＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法、に特徴を有するものである。 The present invention has been made on the basis of such knowledge. An Au—Sn alloy solder paste is mounted on or applied to a substrate, and an element of the device is formed on the surface of the Au—Sn alloy solder paste mounted or applied on the substrate. The element is placed on the Au-Sn alloy solder paste so that the part is in contact and one end of the element is in contact with the substrate. In this state, the substrate on which the element is placed is mounted or applied with the Au-Sn alloy solder paste. After reflow treatment in an oxidizing atmosphere , the molten Au-Sn alloy solder wets and spreads under the element, and the element is pulled back toward the center of the molten Au-Sn alloy solder. It has a feature in a method of joining a substrate and an element using an Au—Sn alloy solder paste that cools in a state of being put on molten Au—Sn alloy solder .
この発明のＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法を図面に基づいて具体的に説明する。図１はこの発明のＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法を説明するための側面説明図である。
A method for joining a substrate and an element using the Au—Sn alloy solder paste of the present invention will be specifically described with reference to the drawings. FIG. 1 is an explanatory side view for explaining a method of joining a substrate and an element using the Au—Sn alloy solder paste of the present invention.
図１（ａ）に示されるように、Ａｕ−Ｓｎ合金はんだペースト２を基板１に搭載または塗布し、さらに素子３を基板１に搭載または塗布したＡｕ−Ｓｎ合金はんだペースト２の表面の端部に素子３の一部が接しかつ素子３の一端が基板１に接するように素子３をＡｕ−Ｓｎ合金はんだペースト上に載置する。この基板１の表面には最表面層としてＡｕめっき層（図示せず）を形成しておくことが好ましい。 この状態でＡｕ−Ｓｎ合金はんだペースト２および素子３を乗せた基板１を非酸化性雰囲気中でリフロー処理すると、Ａｕ−Ｓｎ合金はんだペースト２の上に素子３が被さらない部分あるためにリフロー処理中に図１（ｂ）に示されるように、Ａｕ−Ｓｎ合金はんだペースト２が溶融してＡｕ−Ｓｎ合金はんだペースト２に含まれるフラックスの分解ガス６が放出され、さらにＡｕ−Ｓｎ合金はんだペーストに含まれるＡｕ−Ｓｎ合金はんだ粉末が溶融してＡｕ−Ｓｎ合金はんだ粉末の表面の酸化膜とフラックスとが反応して生成したガス６が放出されやすくなり、図１（ｃ）に示されるように、ガスが抜けた溶融Ａｕ−Ｓｎ合金はんだ４’が生成し、このガスが抜けた溶融Ａｕ−Ｓｎ合金はんだ４’が基板１の表面を伝って素子３の下に濡れ広がり、このガスが抜けた溶融Ａｕ−Ｓｎ合金はんだ４’が基板１の表面を伝って素子３の下に濡れ広がると、図１（ｃ）に示されるように、溶融Ａｕ−Ｓｎ合金はんだ４’が素子３の下に潜り込み、溶融Ａｕ−Ｓｎ合金はんだ４’が素子３の下に潜り込むと同時に溶融Ａｕ−Ｓｎ合金はんだ４’のセルフアライメント効果により素子３が溶融Ａｕ−Ｓｎ合金はんだ４’の中央に向かって引き戻され（すなわち、図１（ｃ）のＡ方向に引き戻され）てガスが十分に抜けた溶融Ａｕ−Ｓｎ合金はんだ４’のほぼ中央に素子３が乗った状態（素子３の全体が溶融Ａｕ−Ｓｎ合金はんだ４’に乗った状態）となり、かかる状態で冷却すると、図１（ｄ）に示されるように、基板１と素子３との間のＡｕ−Ｓｎ合金はんだ接合層４の中にボイドが発生することなく接合することができる。
As shown in FIG. 1A, an end portion of the surface of the Au—Sn
図１（ａ）に示されるように、基板１の上に搭載または塗布されたＡｕ−Ｓｎ合金はんだペースト２の上に、素子３の一部がかかるようにかつ素子３の一端が基板に接するように素子３を載置すればよい。このときＡｕ−Ｓｎ合金はんだペースト２の表面が可能な限り素子３によって被覆されないように素子３をＡｕ−Ｓｎ合金はんだペースト２の上に載置する。
As shown in FIG. 1A, a part of the
この発明のＡｕ−Ｓｎ合金はんだペーストを用いた接合方法によると、基板１と素子３の間の接合部にボイドの発生が少なくなって接合部の熱伝導性が劣化せず、したがって、使用中に素子に発生した熱が放熱し易くなり、産業上優れた効果をもたらすものである。
According to the bonding method using the Au—Sn alloy solder paste of the present invention, the generation of voids is reduced in the bonding portion between the substrate 1 and the
Ｓｎ：２２質量％を含有し、残部がＡｕからなる成分組成を有しかつ５〜１６μｍの粒径を有する粉末が８０％以上含まれるＡｕ−Ｓｎ合金はんだ粉末を用意し、このＡｕ−Ｓｎ合金はんだ粉末を市販のＲＭＡタイプのロジン系フラックスに、ロジン系フラックス：７質量％を含有し残部がＡｕ−Ｓｎ合金はんだ粉末の配合組成となるように配合し混練してＡｕ−Ｓｎ合金はんだペーストを作製した。このＡｕ−Ｓｎ合金はんだペーストは三菱マテリアル株式会社製金錫合金ペーストとして市販されているものである。
さらに、基板として厚さ：１００μｍのＣｕ板に厚さ：５μｍのＮｉめっきを施し、さらにその上に厚さ：１μｍのＡｕめっきを施した基板を用意した。
さらにＬＥＤ素子の代替として、縦：５００μｍ、横：５００μｍ、厚さ：３００μｍの角銅板を用意し、この角銅板に厚さ：５μｍのＮｉめっきを施し、さらにその上に厚さ：０．５μｍのＡｕめっきを施した代替ＬＥＤ素子を用意した。
An Au—Sn alloy solder powder containing Sn: 22% by mass, with the balance being composed of Au, and containing 80% or more of a powder having a particle size of 5 to 16 μm is prepared. This Au—Sn alloy Solder powder is mixed with a commercially available RMA type rosin-based flux, rosin-based flux: 7% by mass, with the balance being the composition of Au-Sn alloy solder powder, and kneaded to prepare an Au-Sn alloy solder paste. Produced. This Au-Sn alloy solder paste is commercially available as a gold-tin alloy paste manufactured by Mitsubishi Materials Corporation.
Further, a substrate was prepared by applying Ni plating with a thickness of 5 μm to a Cu plate with a thickness of 100 μm as a substrate, and further applying Au plating with a thickness of 1 μm thereon.
Furthermore, as an alternative to the LED element, a square copper plate having a length of 500 μm, a width of 500 μm, and a thickness of 300 μm is prepared, Ni plating of a thickness of 5 μm is applied to the square copper plate, and a thickness of 0.5 μm is further formed thereon. An alternative LED element with Au plating was prepared.
実施例１
先に用意した基板の上に、先に用意したＡｕ−Ｓｎ合金はんだペーストをピン転写法により０．５ｍｇ塗布し、さらに塗布したＡｕ−Ｓｎ合金はんだペーストの上に、Ａｕ−Ｓｎ合金はんだペーストが上から見て半分が代替ＬＥＤ素子によって被さるようにかつ代替ＬＥＤ素子の一端が基板に接するように代替ＬＥＤ素子を載置した。
かかる状態でＡｕ−Ｓｎ合金はんだペーストを塗布しさらに代替ＬＥＤ素子を載置した基板を窒素雰囲気中の熱対流型炉に装入して２００℃に６０秒間保持したのち、さらに３１０℃、３０秒間保持することによりリフロー処理を施し、ついで冷却することにより基板と代替ＬＥＤ素子の間にＡｕ−Ｓｎ合金はんだ接合層を有するはんだ接合試験片を作製した。
このはんだ接合試験片を透過Ｘ線装置（ＴｏｓｈｉｂａＩＴ＆ＣｏｎｔｒｏｌＳｙｓｔｅｍ‘ｓＴＯＳＭＩＣＲＯＮ−６０９０ＦＰ）を用いてＸ線写真を撮り、画像処理(２値化)処理して接合面積％を求め、その結果を表１に示した。
Example 1
On the prepared substrate, 0.5 mg of the previously prepared Au—Sn alloy solder paste is applied by the pin transfer method, and the Au—Sn alloy solder paste is further applied on the applied Au—Sn alloy solder paste. The alternative LED element was placed so that half of the alternative LED element was covered with the alternative LED element when viewed from above and one end of the alternative LED element was in contact with the substrate.
In such a state, the substrate on which the Au—Sn alloy solder paste is applied and the alternative LED element is mounted is placed in a thermal convection furnace in a nitrogen atmosphere and held at 200 ° C. for 60 seconds, and then at 310 ° C. for 30 seconds. A reflow treatment was performed by holding, followed by cooling to prepare a solder joint test piece having an Au—Sn alloy solder joint layer between the substrate and the alternative LED element.
An X-ray photograph of this solder joint test piece was taken using a transmission X-ray apparatus (ToshibaIT & Control System's TOSMICRON-6090FP), image processing (binarization) processing was performed to determine the joint area%, and the results are shown in Table 1. .
従来例１
先に用意した基板の上に、先に用意したＡｕ−Ｓｎ合金はんだペーストをピン転写法により０．５ｍｇ塗布し、この塗布したＡｕ−Ｓｎ合金はんだペーストの真上に代替ＬＥＤ素子がくるように代替ＬＥＤ素子を載置し、かかるＡｕ−Ｓｎ合金はんだペーストの真上に代替ＬＥＤ素子を載置した基板を窒素雰囲気中の熱対流型炉に装入して２００℃に６０秒間保持したのち、さらに３１０℃、３０秒間保持することによりリフロー処理を施し、ついで冷却することにより基板と代替ＬＥＤ素子の間にＡｕ−Ｓｎ合金はんだ接合層を有するはんだ接合試験片を作製した。
このはんだ接合試験片を透過Ｘ線装置（ＴｏｓｈｉｂａＩＴ＆ＣｏｎｔｒｏｌＳｙｓｔｅｍ‘ｓＴＯＳＭＩＣＲＯＮ−６０９０ＦＰ）を用いてＸ線写真を撮り、画像処理(２値化)処理して接合面積％を求め、その結果を表１に示した。
Conventional Example 1
Apply 0.5 mg of the previously prepared Au—Sn alloy solder paste on the previously prepared substrate by the pin transfer method so that the alternative LED element comes directly above the applied Au—Sn alloy solder paste. After placing the substitute LED element, placing the substrate on which the substitute LED element was placed directly above the Au—Sn alloy solder paste in a thermal convection furnace in a nitrogen atmosphere and holding at 200 ° C. for 60 seconds, Furthermore, the reflow process was performed by hold | maintaining at 310 degreeC for 30 second, and it cooled, and the soldering test piece which has an Au-Sn alloy soldering layer between a board | substrate and an alternative LED element was produced.
An X-ray photograph of this solder joint test piece was taken using a transmission X-ray apparatus (ToshibaIT & Control System's TOSMICRON-6090FP), image processing (binarization) processing was performed to determine the joint area%, and the results are shown in Table 1. .
表１に示される結果から、実施例１による接合面積は従来例１による接合面積に比べて格段に大きいことから、実施例１の本発明方法によると、基板と素子との間に形成されているＡｕ−Ｓｎ合金はんだ接合層に発生するボイドは従来例１に比べて格段に少ないことが分かり、Ａｕ−Ｓｎ合金はんだ接合層に発生するボイドが少ないこの発明のＡｕ−Ｓｎ合金はんだペーストを用いた基板と素子の接合方法は特に熱がこもることが好ましくないＬＥＤ素子などの接合に優れた効果を有することが分かる。 From the results shown in Table 1, since the bonding area according to Example 1 is much larger than the bonding area according to Conventional Example 1, it is formed between the substrate and the device according to the method of the present invention in Example 1. It can be seen that the number of voids generated in the Au-Sn alloy solder joint layer is much smaller than that of the conventional example 1, and the number of voids generated in the Au-Sn alloy solder joint layer is small. It can be seen that the bonding method between the substrate and the element has an excellent effect in bonding an LED element or the like, in which heat is not particularly preferred.
１：基板、２：Ａｕ−Ｓｎ合金はんだペースト、３：素子、４：Ａｕ−Ｓｎ合金はんだ接合層、４´：溶融Ａｕ−Ｓｎ合金はんだ、５：ボイド、６：ガス。
1: substrate, 2: Au—Sn alloy solder paste, 3: element, 4: Au—Sn alloy solder bonding layer, 4 ′: molten Au—Sn alloy solder, 5: void, 6: gas.
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