JP4741875B2 - Operation method of power supply device and power supply device - Google Patents

Description

  The present invention relates to an operation of a power supply device that supplies alternating current power to a load by an inverter system formed by connecting a plurality of inverter devices in parallel, and in particular, an operation of a power supply device that can change an equivalent internal impedance by adjusting a control parameter.

  When a large-capacity AC output power is required, a plurality of inverter devices are connected in parallel. In particular, power source decentralization has recently progressed, and redundant operation of inverter devices connected in parallel has been widely performed. In such an inverter system, each inverter device has a power switch such as a circuit breaker, and is used for disconnecting or turning on from the inverter system, or for connection or disconnection with a commercial AC power supply system. The power switch is always turned on and off (see, for example, Patent Document 1). In addition, there is a demand for operating the inverter system in a power efficient range as the load demand increases and decreases. In a conventional power supply, by turning on and off the power switch, operating only certain power supplies connected in parallel within a highly efficient range and halting other inverter devices means that the operation of the power switch is delayed, unbalanced, etc. Therefore, it was difficult to increase the cross current. Furthermore, turning on and off the power switch during normal operation has a problem that a large surge voltage is generated and the load is adversely affected.

  On the other hand, various basic proposals have already been made with respect to the constant sampling type error tracking power supply technology which is an example of the power supply technology to which the present invention is applied (Patent Documents 2 to 4). An outline of the constant sampling type error tracking power supply will be described. First current detection means for detecting an output current of an inverter device including an inverter and an output filter connected to the output side thereof, the inverter and the output 2nd electric current detection means to detect the alternating current which flows between filters, and AC voltage detection means to detect the voltage of the said output filter are provided. And a signal obtained by multiplying the current detection signal from the first current detector by a current feedforward gain β, a voltage detection signal from the AC voltage detector, and a command voltage represented by a sine wave reference voltage signal. A current target function signal J (t) obtained by adding a signal obtained by multiplying the voltage signal indicating the difference by a voltage feedback gain α is formed. Next, it is determined at every constant sampling period whether or not the error signal Δt indicating the difference between the current target function signal J (t) and the current detection signal from the second current detector is within the target tracking range. To do. Then, the error signal Δt is sampled to generate a high frequency PWM signal for controlling the instantaneous value of the current, and the switching mode of the switching element of the inverter is selected according to the error signal Δt.

When the error signal Δt is negative, since the output current of the inverter device is smaller than the current target function signal J (t), the switching mode for increasing the output current of the inverter device is selected, and the error signal When Δt becomes positive, the output current of the inverter device is larger than the current target function signal J (t). Therefore, the first current detection means is selected by selecting a switching mode for reducing the output current of the inverter device. The current detection signal is to be controlled within a predetermined range.
JP 09-331681 A Japanese Patent Application Laid-Open No. 07-7950 JP 2000-125575 A JP 2000-341156 A

  However, in the conventional technique disclosed in the invention of Patent Document 1, the load sharing of the inverter device is changed in accordance with the fluctuation of the load power demand without adversely affecting the load such as a surge voltage. There is a problem that it is difficult to operate the inverter system within a high efficiency range. In addition, the constant sampling type error tracking power supply technology in the inventions of Patent Documents 2 to 4 has various technical advantages. However, the basic technology related to a single inverter device is mainly disclosed. Thus, the technology related to the parallel operation of the inverter device has not yet been disclosed.

  The present invention is applied to a parallel operation of a power source represented by a constant sampling type error tracking power source technology, that is, an inverter device capable of changing an equivalent internal impedance only by adjusting a control parameter. The main purpose is to operate in a region with high power efficiency by appropriately performing load sharing in a power supply device that is made up of parallel inverter devices that can change the equivalent internal impedance simply by adjusting the control parameters. It is said.

In order to solve the above-mentioned problem, the first invention is such that when the output voltage feedback gain is α, the output current feedforward gain is β, and the inverter current gain is G, (1−β · G) / (α · G the inverter device according to the equivalent internal impedance DC resistance value represented by) a method of operating a plurality parallel connection to configure the power supply, the plurality of inverter devices operate at the same frequency, the plurality of the output voltage feedback gain is a control parameter of inverter α and by changing at least one of the output current feed forward gain beta, by changing the equivalent internal impedance of each of the inverter device, the load sharing of the inverter device Provided is a method of operating a power supply device characterized by adjusting.

  According to a second aspect of the present invention, in order to solve the above problem, the equivalent internal impedance is a large value for each inverter device so that some of the inverter devices do not substantially share the load power. A second setting determined for each individual inverter device in which the equivalent internal impedance of the remaining inverter devices is smaller than the first set value capable of supplying load power. When the power supply operation is performed to the load device with the value set or when the equivalent internal impedance of all the inverter devices is set to the second set value and the power supply operation is performed to the load device, the load demand decreases. In this case, the equivalent internal impedance at the second set value is set to the first set value, and a part or all of the inverter device is effectively suspended. It provides a method of operating a power supply device according to the first invention, characterized by the state.

  According to a third aspect of the present invention, the equivalent internal impedance is set to a first set value which is a large value determined for each inverter device so that some of the inverter devices do not substantially share the load power. Load demand when the power supply operation is performed to the load device by setting the equivalent internal impedance of the remaining inverter devices to a second set value determined for each individual inverter device smaller than the first set value. Is increased, the equivalent internal impedance of part or all of the inverter devices having the equivalent internal impedance at the first set value is set to the second set value to supply power to the load device. A method of operating the power supply device according to the first invention is provided.

In the fourth invention, when the output voltage feedback gain is α, the output current feedforward gain is β, and the inverter current gain is G, the DC resistance value represented by (1−β · G) / (α · G) a Ru power supply name and multiple parallel-connected inverters device according to equivalent internal impedance, the plurality of inverter devices operate at the same frequency, the voltage feedback gain is a control parameter of the plurality of inverter by varying one or both either α and the current feed-forward gain beta, to provide a power supply apparatus characterized by said equivalent internal impedance varying to adjust the load sharing of the inverter device.

  According to a fifth aspect of the present invention, the equivalent internal impedance is set to a large first set value so that some of the inverter devices do not substantially share load power, and the rest of the inverter devices are effectively stopped. The equivalent internal impedance is set to an arbitrary second setting value that is smaller than the first setting value capable of supplying load power, or when the power supply operation is performed to the load device, or the equivalent of all the inverter devices. When the load demand decreases when the internal impedance is set to the arbitrary second set value and the load device is reduced, the equivalent internal impedance of a part or all of the inverters in the power supply operation is The power supply apparatus according to the fourth aspect of the present invention is characterized in that the inverter apparatus is effectively put into a dormant state with a first set value.

  According to a sixth aspect of the present invention, the equivalent internal impedance is set to the first set value so that a part of the inverter devices does not substantially share load power, and the rest of the inverter devices are virtually stopped. When the load demand increases when the equivalent internal impedance is set to the arbitrary second set value and the load device is in a power feeding operation, a part or all of the equivalent internal impedance is at the first set value. The power supply device according to the fourth invention is characterized in that the equivalent internal impedance of the inverter device is set to the arbitrary second set value and the power feeding operation is performed to the load device.

In a seventh aspect of the invention, the inverter device detects an AC current flowing between the inverter and the output filter, an inverter that converts a DC input into an AC output, an output filter provided on an output side of the inverter, and the inverter. First current detection means, second current detection means for detecting an alternating current flowing through the output terminal, AC voltage detection means for detecting the voltage of the output filter, and current detection from the second current detection means a signal obtained by multiplying the current feed forward gain β to signal a signal value obtained by multiplying the voltage feedback gain α to the voltage signal value indicating a difference between a voltage detection value and the command voltage value from the AC voltage detecting means The current target function signal value J (t) obtained by adding the current target function signal value J (t), the current target function signal value J (t) and the first current detection means A gate that controls the instantaneous value of the inverter current by sampling the error signal Δ (t) at a constant sampling period so as to reduce an error signal value Δ (t) indicating a difference from the current detection signal value. A power supply apparatus according to any one of the fourth to sixth aspects, further comprising: a gate command / PWM control unit that gives a command to the inverter.

  According to an eighth aspect of the invention, the number of inverter devices connected in parallel is N, the total demand load power is Wt, the rated power of the inverter device is Pr, and the lower limit value of the output power corresponding to the power efficiency allowable limit value Xu is Pu. When an arbitrary power between the rated power Pr and the lower limit value Pu of the output power is Pd, the number m (m ≦ N) satisfying the expression Pd · m> Wt> Pd · (m−1). The power supply device according to any one of the fourth to seventh inventions, wherein the power supply device is operated.

  According to the first invention, the load sharing of each inverter device is automatically set by selectively setting the equivalent internal impedance of the constant-sampling error tracking power supply device in response to a decrease in load power demand. In other words, even if the load power demand decreases drastically and sharply, it is possible to operate in a region of high power efficiency without applying a surge voltage or the like to the load.

  According to the second aspect of the invention, since the power switch is turned off and disconnected in a state where substantially no output power is generated, the operation with less power loss is performed without affecting the load such as a surge voltage. Is possible.

  According to the third aspect of the invention, the load sharing of each inverter device is automatically set by selectively setting the equivalent internal impedance of the constant-sampling error tracking power supply device in response to an increase in load power demand. In other words, even if the load power demand increases significantly and rapidly, it is possible to operate in a region of high power efficiency without applying a surge voltage or the like to the load.

  According to the fourth aspect of the invention, since the power switch is turned on and connected in a state where substantially no output power is generated, the operation with high power efficiency can be performed without affecting the load such as a surge voltage. Can continue.

  According to the fifth and sixth inventions, since the equivalent internal impedance of each inverter device can be automatically set to a desired value by a very simple means, it is possible to easily set the load sharing in a region with high power efficiency. Is possible.

  According to the seventh aspect of the invention, not only can the operation with high power efficiency be performed without affecting the load such as a surge voltage, but also the cross current flowing between the inverter devices can be limited to an allowable value or less.

  According to the eighth aspect of the invention, the operation with high power efficiency can be performed without adversely affecting the load due to the surge voltage or the like.

[Embodiment 1]
A first embodiment for carrying out the present invention will be described with reference to FIGS. FIG. 1 is a diagram for explaining a constant sampling type error-following single-phase AC inverter device 80, which is an embodiment of an inverter device that can vary the equivalent internal impedance only by control parameters employed by the present invention. These are figures which show an example of the power efficiency of this inverter apparatus 80. FIG. FIG. 3 is a diagram for explaining a single-phase AC power supply 100 according to an embodiment of the present invention in which N inverter devices 80 are connected in parallel. First, a constant sampling type error tracking type single-phase AC inverter device 80 using a single-phase inverter will be described with reference to FIG. 1. The inverter 2 is connected to both ends of the DC power supply 1. The DC power source 1 is a general one, and is, for example, a rectifier that rectifies the voltage of a commercial AC power source and converts AC to DC, or a solar cell panel. The inverter 2 is a single-phase inverter composed of four IGBT-like semiconductor elements S1 to S4 formed by full-bridge connection and diodes D1 to D4 connected in parallel to each of the semiconductor elements in reverse polarity. . However, the inverter 2 is not limited to a full-bridge configuration, for example, a half-bridge type single-phase inverter in which two semiconductor elements such as IGBT or MOSFET and two capacitors are connected in a full-bridge configuration, Alternatively, as shown in Patent Document 8, an inverter single-phase voltage doubler type inverter or the like in which two DC power sources 1 are connected in series to form a single-phase voltage doubler configuration may be used. A power switch SW is provided between the DC power source 1 and the inverter 2.

  The AC side line L1 of the inverter 2 is provided with a first current detector 3 such as a current transformer (CT) that detects an inverter current i1, and the AC side line L1 has a current holding inductor Lp. An output filter circuit 4 including a filter resistor Rf, a filter capacitor Cf, and a filter inductor Lf is connected between the load side of the current holding inductor Lp and L2. A filter voltage detector 5 is provided between terminals in which the filter resistor Rf and the filter capacitor Cf are connected in series. The output filter circuit 4 is not limited to the one composed of the filter resistor Rf, the filter capacitor Cf, and the filter inductor Lf. In addition, a second current detector 6 such as a current transformer for detecting the output current i2 of the error tracking type single-phase AC inverter device 80 flowing through the filter inductor Lf is provided. A load 50 is connected to the output terminals 7A and 7B of the error tracking inverter device 80 as an external circuit. As shown in FIG. 3, the output terminals 7A and 7B are connected in parallel to the output terminals of another error-following inverter device having the same configuration. The load 50 is a general AC load that receives power supply, a general DC load that receives power supply from a rectifier circuit, or a general DC load that receives power supply from a transformer, a rectifier circuit, and the like. 80 can supply power to various loads.

  This constant sampling type error tracking type inverter device 80 includes a microcomputer MC for comprehensive control. The microcomputer MC performs a predetermined process (to be described later) on the output current detection signal and the output voltage detection signal to form a current target function signal J (t), and a current target function signal J (t). And the gate command / PWM control unit 9 for selecting the switching mode of the semiconductor elements S1 to S4 of the inverter 2 from the inverter current detection signal and the output power of the constant sampling type error tracking type inverter device 80 to monitor the output power. An output monitoring / gain changing unit 10 for changing the gain and the like is provided. In this drawing, an A / D conversion circuit for analog-digital (A / D) conversion of each detection signal is omitted.

  The current target value forming unit 8 is a voltage command means 8A that gives a command voltage Va represented by a reference sine wave voltage whose polarity changes in positive and negative by 180 degrees, and the current of the output current i2 detected by the second current detector 6. A current gain means 8B that multiplies the detection signal Δi2 by a current feedforward gain β that is one control parameter, and a first subtraction that subtracts the voltage detection value Δv1 of the inverter voltage v1 detected by the inverter voltage detector 5 from the command voltage Va. Means 8C, voltage gain means 8D for multiplying the subtracted voltage by the feedback gain α which is the other control parameter, a current signal corresponding to the voltage value multiplied by the voltage feedback gain α and the current multiplied by the current feedforward gain β A second adding means 8E for adding a signal to generate a current target function signal J (t).

  The voltage command means 8A gives a command voltage Va which is a reference sine wave voltage (Esinωt) that changes in positive and negative at 180 degrees in synchronization with a synchronization signal from the outside of the error tracking type single-phase AC inverter device 80, or is determined in advance. A command voltage Va typified by a reference sine wave voltage (Esinωt) having a different frequency is generated. The reference sine wave voltage (Esinωt) determines the output frequency of the error tracking type single-phase AC inverter device 80. For example, if the output frequency of the error tracking type single-phase AC inverter device 80 is 50 Hz, the reference sine wave voltage (Esinωt) is determined to be 50 Hz. The command voltage Va typified by the reference sine wave voltage is important for parallel operation of the error tracking type single-phase AC inverter device, and a synchronization signal is generated at a period for determining each period of the reference sine wave voltage. Shall. The command voltage Va is given as a digital value corresponding to the instantaneous value of the reference sine wave voltage (Esinωt). When a plurality of inverter devices are operated in parallel, the reference sine wave voltage (Esinωt) may be synchronized with each other by synchronizing with a common synchronization signal from the outside, or each inverter device The voltage command means 8A may have the same frequency and generate a command voltage Va having a reference sine waveform at the same time while following each other. The command voltage Va is not necessarily a sine wave.

  The current gain means 8B multiplies the current detection signal Δi2 of the output current i2 of the error tracking type single-phase AC inverter device 80 detected by the second current detector 6 by the current feedforward gain β that is a control parameter, to obtain Δi2・ Give β. This current feedforward gain β is a current gain for preventing the output voltage from being changed by the output current, and is an important factor of the present invention described later. In the present invention, the current feedforward gain β can be set also by a sequence. In this embodiment, the current detection signal Δi2 of the output current i2 is a digital value corresponding to an instantaneous value sampled every short fixed time. Here, the voltage feedback gain α which is a control parameter is a numerical value larger than zero, and the current feedforward gain β is often a numerical value of 1 or less, but if it is larger than 1, a negative equivalent internal impedance is realized. .

  The subtracting means 8C subtracts a digital value corresponding to an instantaneous value obtained by sampling the voltage detection value Δv1 of the inverter voltage v1 at short regular intervals from the command voltage Va to obtain a difference. The subtraction result is represented by (Va−Δv1). Therefore, the signal on the output side of the voltage gain means 8D becomes (Va−Δv1) · α obtained by multiplying (Va−Δv1) by the voltage feedback gain α. The voltage feedback gain α is also a voltage gain value that can be set to an optimum value according to a sequence in the same manner as the current feedforward gain β. As will be described later, in the present invention, the voltage feedback gain α and the current feedforward that are control parameters are used. The gain β is a very important factor in determining the equivalent internal impedance of the inverter device. The adding means 8E adds Δi2 · β from the current gain means 8B and (Va−Δv1) · α from the voltage gain means 8D to generate a current target function signal J (t). The current target function signal J (t) is given to the gate command / PWM control unit 9.

  The gate command / PWM control unit 9 in the microcomputer MC includes subtracting means 9A for subtracting the current target function signal J (t) from the current detection signal Δi1 of the inverter current i1 detected by the first current detector 3. As described above, the current detection signal Δi1 is also a digital value corresponding to an instantaneous value sampled every short fixed time. Therefore, the subtracting means 9A calculates (Δi1-J (t)) to obtain the error signal Δt. This error signal is input to the gate command / PWM circuit 9B, and the gate command / PWM circuit 9C selects the semiconductor element S1 to S4 of the inverter 2 as described below.

The gate command / PWM circuit 9B issues a gate command according to the polarity of the difference between the current detection signal Δi1 of the inverter current i1 and the current target function signal J (t). The gate command is as follows. When Δt = Δi1−J (t) is negative, the inverter current i1 is smaller than the target value, so the switching mode for increasing the current is selected. When Δt = Δi1−J (t) is positive, since the inverter current i1 is larger than the target value, the switching mode for reducing the current is selected. That is, in error tracking type PWM control, the switching mode is selected as follows according to the polarity of the error signal Δt.
(1) As switching mode 1, when Δt = Δi1-J (t) ≦ 0, the semiconductor elements S3 and S4 are on, and the semiconductor elements S1 and S2 are off.
(2) As switching mode 2, when Δt = Δi1−J (t)> 0, the semiconductor elements S1 and S2 are on, and the semiconductor elements S3 and S4 are off.
(3) As the switching mode 3, there is a recirculation mode in which power supply from the DC power source 1 is not performed. In this case, the semiconductor elements S1 and S4 are on, the semiconductor elements S2 and S3 are off, or the semiconductor elements S2, S3 is on and the semiconductor elements S1 and S4 are off.

  The semiconductor elements S1 to S4 of the inverter 2 are turned on based on the gate command from the gate command / PWM circuit 9C determined based on the polarity of the error signal Δt, or remain off. For example, if the state of Δt = Δi1-J (t) ≦ 0 continues, the semiconductor elements S1 and S2 remain on until Δt = Δi1-J (t)> 0, and the semiconductor element S3 S4 remains off. This point is different from the switching operation of PWM control by a generally used triangular wave (sawtooth wave) comparison method.

  As is well known, in general, an equivalent circuit viewed from the output terminal of a power supply is expressed by a voltage source and an equivalent internal impedance. If the equivalent internal impedance is 0, an ideal power source in which the output terminal voltage does not change no matter how much current flows. Actually, this equivalent internal impedance does not become 0 and cannot be freely controlled. The equivalent internal impedance is obtained by first finding that no current flows when the output terminal is opened (no load), and therefore the voltage drop due to the equivalent internal impedance is zero. Therefore, the no-load voltage Vo becomes the output voltage of the voltage source. Next, since the voltage difference between the output voltage Vc and the no-load voltage Vo when a load having an impedance X is connected is a voltage drop due to the equivalent internal impedance, assuming that the current flowing at that time is I, Vo−Vc = XI relationship. Therefore, the equivalent internal impedance Z is Z = (Vo−Vc) / I = (Vo−Vc) X / Vc.

  The constant-sampling error-following inverter device is characterized by the fact that the characteristics of the inverter as a current amplifier can be expressed by mathematical formulas. High-level control suitable for error-following PWM (control using current target forming means) is used. By adopting it, the equivalent internal impedance can be calculated. The equivalent internal impedance Z of the inverter 2 viewed from the output filter 4 is composed of a resistor and a capacitor. The total resistance value decreases linearly with an increase in the current feedforward gain β that is a control parameter, and is inversely proportional to the voltage feedback gain α that is a control parameter. In most cases, the capacitance in the equivalent circuit is in parallel with a small resistance, and its time constant is negligibly short compared to the frequency component of the main circuit current, so the equivalent internal impedance Z of the inverter 2 can be considered as a resistance component. For this reason, when the current gain of the inverter 2 is G, the equivalent internal impedance Z of the inverter 2 is a DC resistance value represented by the equation (1-β · G) / (α · G) [Ω]. Is almost equal to Here, the current gain G of the inverter 2 is a value determined from the dead time of the inverter 2, a DC voltage, an AC voltage, etc., and is almost 0.99 in most cases, and can be approximated to 1. It is. The current gain G cannot be obtained by calculation or the like, but is a value unique to the inverter device obtained by actual measurement. However, in an inverter device having the same circuit configuration and substantially the same electrical characteristics, the current gain G has substantially the same value.

  The error tracking type single-phase AC inverter device 80 shown in FIG. 1 becomes a master inverter device when a plurality of units are connected in parallel. Therefore, the microcomputer MC has all the error tracking type single-phase AC devices connected in parallel. An output monitoring / gain changing unit 10 that monitors the output power of the inverter device and performs a predetermined gain change is provided. When the output monitoring / gain changing unit 10 is provided with another microcomputer for comprehensively monitoring and controlling the entire power system, the output monitoring / gain changing unit 10 may be incorporated in the microcomputer. The output monitoring / gain changing unit 10 receives the detection voltage Δv1 detected by the inverter voltage detector 5 and the current detection signal Δi2 detected by the second current detector 6 as digital signals, and calculates the output power. To do. Further, the output monitoring / gain changing unit 10 stores efficiency characteristics indicating the power efficiency with respect to the output power as shown in FIG. 2 as data in a storage unit (not shown). This efficiency characteristic is a result calculated by operating and measuring the error tracking type single-phase AC inverter device 80 in advance. However, although not shown in the figure, the input power is calculated by sampling the voltage and current on the input side of the inverter 2, and while calculating the power efficiency during operation from the calculated input power and the calculated output power, Control as described in the example may be performed.

  As described above, the command voltages Va of the error tracking type single-phase AC inverter devices 80 (1),... 80 (N) connected in parallel in the single-phase AC power supply device 100 shown in FIG. Must be synchronized. The synchronization signal generation circuit 11 provides a synchronization signal to each voltage command means 8A of the inverter devices 80 (1),... 80 (N) through the signal line 11A. When a large number of inverter devices are operated in parallel, an optical fiber is used as the signal line 11A, and an optical synchronization signal is given to each voltage command means 8A of each inverter device, so that it is not affected by noise. Accurate control becomes possible. Further, the synchronization signal generation circuit 11 generates a synchronization signal every half cycle or one cycle of a predetermined reference sine wave voltage or every predetermined cycle. That is, it is assumed that the synchronization signal is generated with a period for determining each period of the reference sine wave voltage as the command voltage Va. Each voltage command means 8A operates at the rising edge of each synchronization signal to generate a command voltage Va represented by a reference sine wave voltage (Esinωt). Therefore, the frequency of the output voltage of each inverter device is the same as the frequency of the reference sine wave voltage (Esin ωt), and the phase is also the same, so that the amplitude of the output voltage is not significantly different in a normal state. In the case where the voltage command means 8A of each inverter device generates the reference sine waveform signals having the same frequency and synchronized with each other, and generates the reference sine waveform signals at the same time while following each other, The synchronization signal generation circuit 11 can be omitted.

  In the present invention, the error tracking type single-phase AC inverter devices 80 (1),... 80 (N) are PWM controlled by the constant sampling type error tracking type synchronously. The magnitude of the output voltage of the devices 80 (1),... 80 (N), that is, the amplitude is often different. In this case, a part of the output current tends to flow from the inverter device having a large output voltage amplitude to the inverter device having a small amplitude. However, in the present invention, the error tracking type single-phase AC inverter device 80 (1),... ) Has an equivalent internal impedance Z that is equal to or greater than a value that can suppress the cross current to an allowable value or less, so that the voltage drop of the output filter circuit 4 increases as the output current increases, and the output voltage of the inverter decreases. The error tracking PWM control is performed so that the output voltages of the respective inverter devices are equal to each other.

  In the invention of the first embodiment, an inverter device exhibiting an equivalent internal impedance Z that is substantially equal to the DC resistance value represented by the above-described equation (1-β · G) / (α · G) [Ω], that is, the same circuit A constant sampling type error tracking single-phase AC inverter device 80 (1),... 80 (N) having substantially the same electrical characteristics is connected in parallel as shown in FIG. Set the voltage feedback gain α and the current feedforward gain β, which are control parameters, so that the equivalent internal impedance Z of the error tracking type single-phase AC inverter device is shared at a desired rate, that is, the desired load. It is characterized by doing. Since the equivalent internal impedance Z is an equivalent impedance, no power loss actually occurs. Therefore, even if the equivalent internal impedance Z is increased, the power loss does not increase.

  Now, when N error-following single-phase AC inverter devices 80 (1),... 80 (N) in the single-phase AC power supply device 100 are operating in the vicinity of the rated output power Pr shown in FIG. The follow-up type inverter device 80 (1),... 80 (N) is a voltage feedback that is a control parameter so as to exhibit an impedance value Zs that can limit the cross current to an allowable value or less and can sufficiently flow the rated current. A gain α and a current feedforward gain β are set. In this state, the N constant sampling type error tracking type inverter devices 80 (1),..., 80 (N) share substantially the same load. It is assumed that the load power demand has decreased during such operation. Since the output monitoring / gain changing unit 10 receives output data of N constant sampling type error tracking inverter devices 80 (1),... 80 (N), the output monitoring / gain changing unit 10 First, the total demand load power Wt is calculated from the output data. Next, assuming that the rated output power Pr of N error tracking inverter devices 80 (1),... 80 (N), the number m that can satisfy the total demand load power Wt is calculated. That is, the number m satisfying Pr · m> Wt> Pr · (m−1) is calculated. Here, the reason why the rated output power Pr is used is that the power efficiency is generally the highest in the vicinity of the rated output power, and the rated output power Pr corresponds to the allowable limit value Xu of the power efficiency shown in FIG. Even if it is replaced with the lower limit value Pu of the output power or replaced with an arbitrary power value Pd between the rated output power Pr and the lower limit value Pu of the output power, it is possible to operate within the allowable power efficiency range.

  When the number m is calculated, m error-following inverter devices are operated as they are. On the other hand, (Nm) inverter devices other than m units, that is, (Nm) units determined by the sequence, are set to the maximum set equivalent internal impedance Z in order to substantially stop. Increase to Zm. In order to increase the equivalent internal impedance Z to the set maximum value Zm, the output monitoring / gain changing unit 10 instructs the microcomputers (not shown) of the (N−m) units of the error tracking type inverter device, and their current gains. For the means 8B and the voltage gain means 8D, the current feedforward gain β and the voltage feedback gain α, which are control parameters, are greatly reduced to predetermined values. If the lower limit value Pu of the output power corresponding to the power efficiency allowable limit value Xu shown in FIG. 2 is half or less of the rated power Pr, Pr · m> Wt> Pr even if the number of operating units is small. -If it operates with the number of units which satisfy the formula of (m-1), parallel operation with high efficiency is possible.

As described above, the voltage feedback gain α is a numerical value smaller than zero, the current feedforward gain β is a numerical value of 1 or less, and the current gain G is a numerical value that can be approximated to 1. Therefore, for example, α = β = If it is set to 10 ⁻⁵ , as described above, the equivalent internal impedance Z is equal to the DC resistance value from the equation (1−β · G) / (α · G) [Ω], so that it is approximately 10 ⁵ Ω. Almost 100 kΩ. Here, assuming that the rated output voltage Vr is 200 V and the rated output current Ir is 20 A, since the equivalent internal impedance Z is approximately 100 kΩ, the maximum output current that actually flows is about 2 mA, and the output is 400 mW or less. Since the rated output power is 4 kW, this output is so small that it can be ignored. At this time, the current feedforward gain β and the voltage feedback gain α, which are control parameters, are not changed instantaneously, but are changed over a set time Ts, so that the load is not affected by the surge voltage. A resting state can be realized. The set time Ts is about three times or more of the cycle of the output voltage during the self-sustained operation not linked to the commercial AC power system, and 50 times the cycle of the commercial AC power source when linked to the commercial AC power system. The time length is preferably about twice as long.

  If the demand for load power further decreases during operation, the optimum number m to be operated is calculated as described above, and the equivalent internal impedance Z of the error tracking inverter device of the other number is increased to the set maximum value Zm. To make it substantially dormant. And after putting it into the hibernation state, by turning off the power switch of the inverter device in the hibernation state, it can be disconnected without affecting the load such as a surge, and the power loss of those inverter devices can be made zero. The power efficiency can be further improved. Thus, when operating in a state where there is an inverter device in a dormant state, the total demand load power Wt increases, and the equation Pr · m> Wt> Pr · (m−1) cannot be satisfied. If the number of units is n (N ≧ n> m), the output monitoring / gain changing unit 10 among the inactive inverter devices when the formula Pr · n> Wt> Pr · (n−1) is satisfied A command is issued to the microcomputers (not shown) of the (n−m) inverter devices, and the power switches SW are first turned on, and then the current gain means 8B and the voltage gain means 8D are fed with current. The forward gain β and the voltage feedback gain α are returned to their original values, and the equivalent internal impedance Z is returned to the value Zs. The impedance value Zs is preferably a value that can limit the cross current to an allowable value or less.

  The (n−m) inverter devices are turned on in the order determined by the sequence, and power feeding is started. Therefore, in this state, the N inverter devices perform the operation while sharing the load power almost evenly in the region of the power efficiency higher than the allowable limit value Xu of the power efficiency shown in FIG. Also in this case, it is preferable to change the current feedforward gain β and the voltage feedback gain α, which are control parameters, over a certain set time Ts. It should be noted that the sequence for disconnecting the inverter device may be paused from the one with low power efficiency, and the sequence for input may be one that is input from the inverter device with high power efficiency. Also, if necessary, a correction value is obtained by measuring in advance the power efficiency of the entire constant-sampling error tracking power supply when the number of units to be operated is p (1 ≦ p ≦ N), and the correction value is not shown. In some cases, the necessary number of operations can be obtained more accurately by storing the value in the microcomputer and reflecting the correction value in the power efficiency of the above equation.

  In addition, when supplying power to a load whose total demand load power Wt is quite abrupt and fluctuates frequently, the power switch SW of the inactive inverter device that is not substantially supplied with power is not turned off. If the power is kept on, it can sufficiently cope with a sudden increase in power demand. However, if power efficiency is the first priority, the power switch SW should be turned on and off as described above. Further, unlike the specific examples described above, when it is desired to change the load sharing of the inverter device in the parallel operation state according to a predetermined sequence, the current feedforward gain β and the voltage feedback gain α are changed according to the sequence, In particular, it can be realized by changing the current feedforward gain β. Therefore, by changing the value of the equivalent internal impedance Z as described above, the load sharing can be easily changed or a predetermined load sharing can be realized.

  The configuration of the inverter 2 may be a half-bridge configuration in addition to the above-described full-bridge configuration, or a single-phase voltage doubler inverter in which two DC power supplies 1 are connected in series to form a single-phase voltage doubler configuration. The operation of these single units is not explained because they are described in the above-mentioned patent document, but even in the case of a half-bridge configuration or a single-phase voltage doubler type inverter, a constant sampling type error tracking technique is adopted. The single-phase inverter device exhibits an equivalent internal impedance Z expressed by the equation (1-β · G) / (α · G). Therefore, also in these inverter devices, the load sharing can be easily and arbitrarily changed as described above. In the first embodiment, the voltage limiter or current limiter for limiting the output signal of the subtracting means 8C or the adding means 8E to a predetermined range, the PWM control error correcting means, etc. are directly related to the present invention. However, these means are required for more preferable operation and accurate control. The same applies to later embodiments, and the voltage limiter, current limiter, or PWM control error correction means will be described in a constant sampling type error tracking type three-phase AC inverter device to be described later. In the present invention, by setting the current feedforward gain β to a large negative value, the equivalent internal impedance Z can be easily set to the set maximum value Zm.

[Embodiment 2]
In the above embodiment, the error tracking type inverter device having a single-phase configuration, the error tracking type power supply device connected in parallel, and the turning on and off (pause) of them are described. Since the restriction of the cross current in a constant sampling type error tracking power supply device in which a plurality of devices are connected in parallel can be similarly performed, a plurality of three-phase AC error tracking inverter devices 90 are connected in parallel using FIG. 4 and FIG. The connected three-phase AC power supply device 200 will be described. 4 and 5, the same symbols as those used in FIG. 1 or 3 indicate the same names. The second embodiment also uses the microcomputer MC and does not particularly show an A / D conversion circuit, but each analog detection signal is converted into a digital detection signal, and digital processing is performed for each subsequent process. To do.

  The three-phase AC inverter 2 includes six switch elements U including a semiconductor element S typified by a self-extinguishing voltage driving element such as a MOSFET or IGBT and a diode D connected in parallel to the reverse direction. It is a three-phase inverter formed by connecting V, W, X, Y, and Z in a three-phase full-bridge configuration. The line connected to the connection point a between the switch elements U and X is connected to L1, the line connected to the connection point b between the switch elements V and Y is connected to L2, and the connection point c between the switch elements W and Z is connected. The line is L3. Current detectors 3A, 3B, and 3C that detect inverter currents i1a, i1b, and i1c flowing through the respective lines L1, L2, and L3 are provided. Inductors Lp1, Lp2, Lp3 for holding current are connected in series to the respective lines L1, L2, L3. Further, an output filter circuit 4 in which an output filter circuit including a filter resistor Rf, a filter capacitor Cf, and a filter inductor Lf is connected between the lines L1 and L2, between the lines L2 and L3, and between the lines L1 and L3 is configured. Is done. And filter voltage detector 5A, 5B, 5C which each detects the voltage between the terminals of filter resistance Rf and filter capacitor Cf between each phase is provided. Of course, the output filter circuit 4 for three-phase alternating current may have another circuit configuration that does not include the filter resistor Rf.

  Furthermore, output current detectors 6A, 6B and 6C for detecting output currents i2a, i2b and i2c of each phase are provided, and a load 50A is connected between the output terminals 7A and 7B, and the output terminals 7B and 7C A load 50B is connected between the output terminals 7A and 7C, and a load 50C is connected between the output terminals 7A and 7C. Note that the current detector for one phase and the filter voltage detector for one phase, for example, 3B, 6B, and 5B can be omitted. Since the constant sampling type error tracking type three-phase AC inverter device 90 shown in FIG. 4 also shows a master inverter device when a plurality of units are connected in parallel, the microcomputer MC has a single-phase case. Similarly, a current target value forming unit 8 that generates a current target function signal J (t) by performing predetermined processing described later on the output current detection signal and the output voltage detection signal, and the current target function signal J (t) and the inverter Gate command / PWM controller 9 that performs pulse width modulation (PWM) by selecting the switching mode of the semiconductor elements S1 to S6 of the three-phase AC inverter 2 from the current detection signal, and all three-phase AC error tracking that is connected in parallel Type inverter devices 90 (1), 90 (2)... 90 (N) are monitored and the output monitoring / gain changing unit 10 that performs predetermined control is provided. Further, the error tracking type three-phase AC inverter device 90 includes a dq conversion means 12 having a dq conversion matrix U, a low-pass filter 13, a dq conversion means 14 having a dq conversion matrix U, and the like, which will be described later. In the case where the output monitoring / gain changing unit 10 includes a microcomputer for comprehensively monitoring and controlling the power system, the output monitoring / gain changing unit 10 may be separately provided in the microcomputer.

  Next, the operation of the error tracking type three-phase AC inverter device 90 will be described while describing the current target value forming unit 8 and the like. The current target value forming unit 8 outputs a command voltage value Vf obtained by dq conversion of a command value of a three-phase balanced AC voltage as a target voltage to be output, here a target voltage value of a terminal voltage of the filter capacitor Cf. Means 8a are provided. Here, dq conversion will be briefly described. The dq conversion is often used in handling a three-phase AC inverter, and a dq axis (rotating coordinate system) in which the voltage and current of the three-phase AC are synchronized with the power supply voltage. By converting to the above value and performing dq conversion, three-phase alternating current can be handled in the same way as direct current. The capacitor current command means 8b gives a direct current command value If for correcting the current flowing through the filter capacitor Cf. Assuming that the voltage of the filter capacitor Cf is at the DC command voltage value Vf, the current flowing through the filter capacitor Cf at that time is calculated in advance, and the current command is added and corrected so as to be the current. Yes. In short, it is basically the same as feeding forward the current flowing through the load. Here, since the d-axis current is an active current and the q-axis current is a reactive current, in the case of a capacitor, the command voltage value Vf is only the d-axis component in the dq coordinate, and the current command value If is q Only the axial component. Further, the PWM current error compensation means 8c corrects the deviation to zero because the deviation occurs in the output current with respect to the current command value If in the error tracking type PWM.

  The detection voltages detected by the filter voltage detectors 5A, 5B, and 5C are a matrix UM that performs dq conversion after three-phase to two-phase conversion (the matrix U is a rotation matrix and the matrix M is a three-phase to two-phase conversion matrix). After the high-frequency component is removed through the low-pass filter 13, the signal is input to the subtraction means 8d as a signal Δvf and also input to the output monitoring / gain changing unit 10. The subtraction means 8d subtracts Δvf from the voltage command value Vf of the filter voltage command means 8a and outputs (Vf−Δvf) = UΔv (t). This value UΔv (t) is limited in a predetermined range by the voltage limiter 8e, and is multiplied by the voltage feedback gain α which is one control parameter by the voltage feedback means 8f, and then added to the adding means 8g. On the other hand, the current detection signals of the output currents i2a, i2b, i2c detected by the second current detectors 6A, 6B, 6C are dq transformed as described above by the coordinate transformation means 14 having the matrix UM for performing dq transformation. After that, the current feed forward gain β, which is the other control parameter, is multiplied by the current gain means 8h and added to the adding means 8g. Further, the current detection signals of the output currents i2a, i2b, i2c are also input to the output monitoring / gain changing unit 10.

The current command value If from the capacitor current command means 8b is multiplied by the current feedforward gain γ by the current gain means 8i and then added to the adding means 8g. Here, when the current feedforward gain β is 1 or less, or when the equivalent internal impedance Z is negative, the current feedforward gain β is a value greater than 1, and the voltage feedback gain α and the current feedforward gain γ are values greater than zero. The signal obtained by adding the current signal corresponding to the voltage value by the adding means 8g, the current signal, and the current command signal is limited to a predetermined range by the signal limiter 8j, and then the PWM current error compensating means. The current compensation value Ic from 8c is added by the adding means 8k and processed by the coordinate conversion means 8l having the matrix (UM) ⁻¹ for performing the inverse coordinate conversion, and the gate command / PWM as the current target function signal J (t). This is given to the subtracting means 9A of the control unit 9.

  On the other hand, the inverter currents i1a, i1b, i1c flowing through the lines L1, L2, L3 are detected by the respective current detectors 3A, 3B, 3C, and these current detection signals are input to the gate command / PWM control unit 9. In the gate command / PWM control unit 9, an error signal Δt obtained by subtracting these current detection signals from the current target function signal J (t) is obtained, and the gate is determined according to the polarity of the error signal Δt as in the case of the single-phase inverter device. A command, that is, a switching mode is selected. The basic switching mode in the three-phase AC inverter device, that is, the gate command is the following six types.

The lines L1, L2, and L3 are a-phase, b-phase, and c-phase, and the differences between the current target function signal J (t) and the currents i1a, i1b, and i1c flowing through the phases are Δa ≧, Δb <, and Δc.
(1) Switching mode 1 is when Δa ≧ 0, Δb <0, and Δc <0. At this time, the switch elements U, Y, Z are on, the switch elements V, W, X are off, and the current flowing through the a-phase current holding inductor Lp1 increases.
(2) Switching mode 2 is a case where Δa ≧ 0, Δb ≧ 0, and Δc <0. At this time, the switch elements U, V, Z are on, the switch elements W, X, Y are off, and the current flowing through the a-phase current holding inductor Lp1 and the b-phase current holding inductor Lp2 is To increase.
(3) Switching mode 3 is a case where Δa <0, Δb ≧ 0, and Δc <0. At this time, the switch elements V, X, and Z are on, the switch elements U, W, and Y are off, and the current flowing through the b-phase current holding inductor Lp2 increases.
(4) Switching mode 4 is a case where Δa <0, Δb ≧ 0, and Δc ≧ 0. At this time, the switch elements V, W, and X are on, the switch elements U, Y, and Z are off, and the current flowing through the b-phase current holding inductor Lp2 and the c-phase current holding inductor Lp3 is To increase.
(5) Switching mode 5 is a case where Δa <0, Δb <0, and Δc ≧ 0. At this time, the switch elements W, X, and Y are on, the switch elements U, V, and Z are off, and the current flowing through the c-phase current holding inductor Lp3 increases.
(6) Switching mode 6 is a case where Δa ≧ 0, Δb <0, and Δc ≧ 0. At this time, the switch elements U, W, Y are on, the switch elements V, X, Z are off, and the currents flowing through the a-phase current holding inductor Lp1 and the c-phase current holding inductor Lp3 are To increase.

  Then, a constant sampling type error following three-phase AC inverter device 90 controlled to make the error signals Δa, Δb, Δc zero by a gate command performed according to the polarities of the error signals Δa, Δb, Δc. Then, similar to the inverter device of the above-described embodiment, it exhibits an equivalent internal impedance Z that is substantially equal to the DC resistance value represented by the equation (1-β · G) / (α · G) [Ω]. Therefore, as shown in FIG. 5, the common synchronizing signal of each of the constant sampling type error tracking three-phase AC inverter devices in which two or more such error tracking three-phase AC inverter devices 90 are connected in parallel is coordinate-transformed. Provided to means 8d, 8j, 8p, respectively, to synchronize the inverter devices.

  Therefore, also in the second embodiment, a three-phase AC inverter device exhibiting an equivalent internal impedance Z substantially equal to the DC resistance value represented by the equation (1-β · G) / (α · G) [Ω], that is, a circuit configuration As in the case of the first embodiment shown in FIG. 3, N units of the constant sampling type error tracking type three-phase AC inverter device 90 having the same electrical characteristics and substantially the same electrical characteristics are connected in parallel, and the cross current is allowed. By setting the voltage feedback gain α and the current feedforward gain β, which are control parameters, so that the resistance value can be limited to the following, all the three-phase AC inverters 2 can be operated in synchronization. If the load power demand decreases during such operation, the output monitoring / gain changing unit 10 includes N constant sampling type error following three-phase AC inverter devices 90 (1), 90 (2). ...... Since 90 (N) dq-converted output data is input, the output monitoring / gain changing unit 10 first calculates the total demand load power Wt from the output data. Next, if the rated output power Pr of N constant sampling type error tracking three-phase AC inverter devices 90 (1), 90 (2)... 90 (N) is satisfied, the total number of load powers Wt can be satisfied. m is calculated, that is, the number m satisfying Pr · m> Wt> Pr · (m−1) is calculated. Here, the rated power Pr is used because the power efficiency is generally the highest in the vicinity of the rated power, and the lower limit of the output power corresponding to the power efficiency allowable limit value Xu shown in FIG. Even if it is replaced with the value Pu or replaced with an arbitrary power value Pd between the rated power Pr and the lower limit value Pu of the output power, it is possible to operate within the allowable power efficiency range. Note that load sharing at the time of increasing load power demand and the like is also the same as that of the constant sampling type error tracking type single-phase AC inverter device 80 of the first embodiment described above, and a description thereof will be omitted. The present invention can also be applied to the case where the output voltage of the three-phase inverter is used as a sine wave having a phase difference of 180 °, that is, a single-phase three-wire voltage.

  In the above embodiment, the constant sampling type error tracking type inverter device is mainly described in the case of independent operation regardless of single operation or parallel operation. However, the constant sampling type error tracking inverter device may be operated in conjunction with a commercial AC power supply system. . In this case, it may be necessary to disconnect this error-tracking inverter device from the commercial AC power supply system, that is, to disconnect or turn it on. When connecting to a commercial AC power supply system, the voltage feedback gain α and the current feedforward gain β, which are control parameters, are appropriately set in advance, thereby setting the equivalent internal impedance Z of all inverter devices to the set maximum value Zm. It is preferable to leave it in a dormant state and connect it to a commercial AC power supply system in this state. By doing so, shockless interconnection that does not adversely affect the load such as a surge voltage during interconnection is possible. After the interconnection, the equivalent internal impedance Z of each inverter device is gradually reduced from the set maximum value Zm to the value Zs during operation by increasing the voltage feedback gain α and the current feedforward gain β according to the sequence. However, the phase of the inverter device is adjusted to the phase of the commercial AC power supply system. At this time, it is preferable that the equivalent internal impedance Z of the inverter device is set over a set time in order to achieve a shockless connection that does not adversely affect the commercial AC power supply system such as a surge voltage during the connection. Further, the equivalent internal impedance Z of each inverter device is preferably set to a value that can limit the cross current to an allowable value as described above. In addition, it can be linked to a commercial AC power system without synchronization verification.

  When testing, maintaining, or inspecting the inverter device that is in power supply, the equivalent internal impedance Z of the inverter device to be tested, maintained, or inspected is increased to the maximum set value Zm and then tested, maintained, or inspected. If the equivalent internal impedance Z of the inverter device is increased to the maximum setting value Zm, the power switch is turned off, and then the test or maintenance / inspection is performed. It becomes possible to stop power supply without using a power supply. Conversely, when any inverter device that has stopped supplying power starts supplying output power, the equivalent internal impedance Z of the inverter device set to the maximum set value Zm is set over the set time. If the internal impedance is reduced to an equivalent internal impedance Zs smaller than the maximum set value Zm, shockless power supply can be started with less influence of surge.

The same applies to testing or maintenance / inspection. When the equivalent internal impedance Z of the inverter device is the maximum set value Zm, the power switch is turned on, and then the voltage feedback gain α and the current feedforward gain which are control parameters are turned on. It is only necessary to reduce the equivalent internal impedance Z of the inverter device to a small value during operation by changing β over a set time as described above without changing it abruptly. Also, if the device contains a large-capacitance capacitor such as a filter, or if the load is capacitive, a large inrush current flows when the power switch is turned on. Measures must be taken. In the present invention, the equivalent internal impedance of each inverter device is set to a value that does not cause a large inrush current before the power switch is turned on, and the power switch is turned on in this state without taking any special measures. The inverter device can be started in a normal state. Thereafter, the equivalent internal impedance Z may be reduced to the value Zs during normal operation according to the sequence. In the above embodiment, a microcomputer is used as a control device, but it is needless to say that individual analog circuits may be combined.

It is a figure which shows the constant sampling type | mold error follow-up type single phase inverter apparatus 80 used for Embodiment 1 which concerns on this invention. It is a figure which shows an example of the power efficiency of the constant sampling type | mold error follow-up type single phase inverter apparatus which concerns on this invention. It is a figure which shows the block configuration of the single phase power supply device 100 formed by connecting the error tracking type single phase inverter device 80 according to the first embodiment of the present invention in parallel. It is a figure which shows the constant sampling type | formula error tracking type | formula three-phase inverter apparatus 90 used for Embodiment 2 which concerns on this invention. It is a figure which shows the block structure of the three-phase power supply device 200 formed by connecting the error tracking type single phase inverter apparatus 90 in Embodiment 2 which concerns on this invention in parallel.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... DC power supply 2 ... Inverter 3 ... Inverter current detector 4 ... Output filter circuit 5 ... Filter voltage detector 6 ... Output current detector 7 ... Output terminal 8. ..Current target value forming section 8A... Voltage command means 8B... Current gain means 8C... Subtraction means 8D... Voltage gain means 8E ... Addition means 8a. .. Capacitor current command means 8c... PWM current error compensation means 8d... Subtraction means 8e... Voltage limiter 8f... Voltage feedback means 8g ... Addition means 8h ... Current gain means 8i. Current gain means 8j ... Signal limiter 8k ... Addition means 8l ... Coordinate conversion means 9 ... Gate command / PWM control section 9A ... Subtraction means 9B ... Gate command / PWM circuit 10.・ ・Output monitoring / gain changing unit 11... Synchronization signal generating circuit 12... Coordinate conversion means 13... Low pass filter 14 .. coordinate conversion means 80. ... Constant sampling type error tracking type three-phase inverter device 100 ... Single-phase power supply device 200 ... Three-phase power supply device

Claims (8)

When the output voltage feedback gain is α, the output current feedforward gain is β, and the inverter current gain is G, the DC resistance value represented by (1−β · G) / (α · G) is the equivalent internal impedance. An operation method of a power supply device configured by connecting a plurality of inverter devices in parallel,
The plurality of inverter devices operate at the same frequency,
Wherein said output voltage feedback gain is a control parameter of the plurality of inverter α and by changing at least one of the output current feed forward gain beta, by changing the equivalent internal impedance of each of the inverter device, the inverter device A method for operating a power supply apparatus, comprising adjusting load sharing. The equivalent internal impedance is set to a first set value that is a large value determined for each individual inverter device so that some of the inverter devices do not substantially share the load power, and the remaining rest When the equivalent internal impedance of the inverter device is in a power feeding operation to the load device with a second set value determined for each inverter device that is smaller than the first set value capable of supplying load power, Or, when the equivalent internal impedance of all the inverter devices is set to the second set value and the power feeding operation is performed to the load device,
When the load demand decreases, the equivalent internal impedance at the second set value is set to the first set value so that a part or all of the inverter device is put into a practically dormant state. Item 2. A method for operating the power supply device according to Item 1. The equivalent internal impedance is set to a first set value that is a large value determined for each individual inverter device so that some of the inverter devices do not substantially share the load power, and the remaining rest When the equivalent internal impedance of the inverter device is in a power feeding operation to the load device with a second set value determined for each individual inverter device smaller than the first set value,
When the load demand increases, power is supplied to the load device by setting the equivalent internal impedance of a part or all of the inverter devices having the equivalent internal impedance at the first set value to the second set value. The operation method of the power supply device according to claim 1, wherein When the output voltage feedback gain is α, the output current feedforward gain is β, and the inverter current gain is G, the DC resistance value represented by (1−β · G) / (α · G) is the equivalent internal impedance. the inverter device a plurality parallel Ru power supply name connected,
The plurality of inverter devices operate at the same frequency,
By varying one or both either control parameter is the voltage feedback gain α that the current feed forward gain β of the plurality of inverter to adjust the load sharing of the inverter apparatus by changing the equivalent internal impedance A power supply device characterized by that. In order that some of the inverter devices do not substantially share the load power, the equivalent internal impedance is set to a large first set value so as to be in a practically inactive state, and the equivalent internal impedance of the remaining inverter devices is the load power. When the power supply operation is performed to the load device with an arbitrary second setting value smaller than the first setting value, or the equivalent internal impedance of all the inverter devices is set to the arbitrary When supplying power to the load device with the second set value,
When load demand decreases, the equivalent internal impedance of a part or all of the inverters in power supply operation is set to the first set value to put the inverter device into a virtually dormant state. The power supply device according to claim 4. The equivalent internal impedance is set to the first set value so that some of the inverter devices do not substantially share load power, and the virtual internal state of the rest of the inverter devices is set to the arbitrary value. When the power supply operation to the load device is performed with the second set value of
When the load demand increases, the equivalent internal impedance of the part or all of the inverter devices having the equivalent internal impedance at the first set value is set to the arbitrary second set value to supply power to the load device. The power supply device according to claim 4, wherein The inverter device is
An inverter that converts DC input to AC output;
An output filter provided on the output side of the inverter;
First current detection means for detecting an alternating current flowing between the inverter and the output filter;
Second current detection means for detecting an alternating current flowing through the output terminal;
AC voltage detecting means for detecting the voltage of the output filter;
Wherein the current feed signal obtained by multiplying the forward gain β to the current detection signal from the second current detector, the voltage on the voltage signal value indicating a difference between a voltage detection value and the command voltage value from the AC voltage detecting means A current target value forming unit for generating a current target function signal value J (t) obtained by adding the signal value obtained by multiplying the feedback gain α;
In order to reduce the error signal value Δ (t) indicating the difference between the current target function signal value J (t) and the current detection signal value from the first current detection means, the error is repeated at a constant sampling period. 7. A gate command / PWM control unit that samples the signal Δ (t) and gives a gate command for controlling an instantaneous value of an inverter current to the inverter. Power supply.   The number of inverter devices connected in parallel is N, the total demand load power is Wt, the rated power of the inverter device is Pr, the lower limit value of the output power corresponding to the power efficiency allowable limit value Xu, the rated power Pr and the output power The operation is performed with the number m (m ≦ N) satisfying the expression Pd · m> Wt> Pd · (m−1) where Pd is an arbitrary electric power between the lower limit value Pu of The power supply device according to any one of claims 4 to 7.

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