JP4737378B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and is particularly suitable for application to a field effect transistor formed on an SOI (Silicon On Insulator) substrate.

  Field effect transistors formed on an SOI substrate are attracting attention because of their ease of element isolation, latch-up freeness, and low source / drain junction capacitance. In particular, since a fully depleted SOI transistor can operate at low power consumption and at high speed and can be easily driven at a low voltage, research for operating the SOI transistor in a fully depleted mode has been actively conducted. Here, as the SOI substrate, for example, a SIMOX (Separation by Implanted Oxgen) substrate or a bonded substrate is used.

Further, for example, Non-Patent Document 1 discloses a method of forming a gate electrode on a SON (Silicon On Noting) substrate. That is, in this method, a gate electrode is formed on a semiconductor substrate having a stacked structure of Si / SiGe / Si. Then, the SiGe layers on both sides of the gate electrode are exposed by etching the Si / SiGe / Si layers on both sides of the gate electrode. Then, the cavity is formed under the Si layer where the gate electrode is disposed by selectively removing the SiGe layer by wet etching. Then, after epitaxial growth is selectively performed on both sides of the gate electrode, ion implantation is performed to form source / drain layers on both sides of the gate electrode.
M.M. Jurczak, T .; Scotnicki, M .; Paoli, B.M. Tormen, J-L. Regolini, C.I. Morin, A.M. Schitzz, J. et al. Martins, R.A. Pantel, J. et al. Galvier. “SON (Silicon On Nothing) -A NEW DEVICE ARCHITECTUR FOR THE ULSI ERA.” 1999 Symposium on VLSI Technology of Papers. 29-30

  However, in order to manufacture a SIMOX substrate, high-concentration oxygen ions must be implanted into a silicon wafer. In order to manufacture a bonded substrate, it is necessary to polish the surface of the silicon wafer after bonding two silicon wafers. For this reason, the SOI transistor has a problem that the cost is increased as compared with a field effect transistor formed in a bulk semiconductor.

Also, in ion implantation and polishing, the variation in the thickness of the SOI layer is large, and it is difficult to stabilize the characteristics of the field effect transistor when the SOI layer is thinned in order to produce a fully depleted SOI transistor. There was a problem.
In the method disclosed in Non-Patent Document 1, since the SON structure is formed only under the gate electrode and the SON structure cannot be formed in the source / drain region, the parasitic capacitance of the source / drain region is reduced. There was a problem that could not. Further, since the cavity under the Si layer in which the gate electrode is disposed is an air layer, there is a problem that mechanical strength, thermal conductivity, and the like are inferior to that of a bulk semiconductor and lack reliability. Further, since the selection ratio of SiGe to Si is not sufficient, there is a problem that it is difficult to remove the SiGe layer disposed under the Si layer over a wide range and it is difficult to widen the gate width.

  In view of the above, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can increase the gate width of a transistor formed in a semiconductor layer on an insulator without using an SOI substrate.

  In order to solve the above-described problem, according to a semiconductor device of one embodiment of the present invention, a semiconductor substrate on which an insulating layer is formed, a semiconductor layer that is disposed on the insulating layer and formed by epitaxial growth, A gate electrode formed on the semiconductor layer; a source layer formed on the semiconductor layer and disposed on one side of the gate electrode; and formed on the semiconductor layer and disposed on the other side of the gate electrode. And an opening formed in at least one of the source layer and the drain layer and reaching the insulating layer through the semiconductor layer.

  As a result, in order to form an insulating layer under the semiconductor layer, an opening for removing the lower semiconductor layer is used even when the lower semiconductor layer is removed using the difference in the selectivity between the semiconductor layers having different compositions. Can be disposed in the source layer or the drain layer, the volume of the lower semiconductor layer to be removed can be reduced, and an opening for removing the lower semiconductor layer is formed around the element region. No need to form. For this reason, it is possible to form an SOI transistor on a semiconductor layer without using an SOI substrate, it is possible to reduce the price of the SOI transistor, and relax restrictions on the size and layout of the SOI transistor. However, the integration degree of the SOI transistor can be improved.

The semiconductor device according to one embodiment of the present invention further includes contact regions formed in the source layer and the drain layer so as to avoid the opening.
Thus, even when an opening is formed in the source layer or the drain layer, contact regions can be formed in the source layer and the drain layer, and contact can be made with the source layer and the drain layer.

The semiconductor device according to one embodiment of the present invention further includes an insulating film embedded in the opening.
Accordingly, even when an opening is provided in the source layer or the drain layer, the source layer or the drain layer can be planarized, and the integration degree of the SOI transistor can be improved.

The semiconductor device according to one embodiment of the present invention further includes an element isolation insulating film formed around the semiconductor layer.
This makes it possible to selectively epitaxially grow the semiconductor layer on the semiconductor substrate using the element isolation insulating film, and eliminates the need to form an opening in the element isolation insulating film, thereby reducing the number of processes. As a result, the integration degree of the SOI transistor can be improved.

  In addition, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, the step of forming the first semiconductor layer on a part of the surface of the semiconductor substrate, and the second semiconductor having an etching rate smaller than that of the first semiconductor layer. Forming a layer on the first semiconductor layer; forming a support insulating film on the semiconductor substrate so as to cover the second semiconductor layer; and the support insulating film and the second semiconductor layer Forming an opening through which the first semiconductor layer is exposed and selectively etching the first semiconductor layer through the opening to remove the first semiconductor layer. Forming a hollow portion below the second semiconductor layer, forming a buried insulating layer buried in the hollow portion through the opening, and a gate insulating film on the second semiconductor layer. To form the gate electrode Forming the source layer and the drain layer in the second semiconductor layer so as to sandwich the gate electrode so that the opening is disposed in at least one of the source layer and the drain layer. It is characterized by providing.

  As a result, even when the second semiconductor layer is stacked on the first semiconductor layer, the etching gas or the etchant can be brought into contact with the first semiconductor layer through the opening, leaving the second semiconductor layer. The first semiconductor layer can be removed using the difference in selectivity between the first and second semiconductor layers, and a buried insulating layer embedded in the cavity under the second semiconductor layer is formed. can do. Further, by disposing an opening in the source layer or the drain layer, a part of the first semiconductor layer under the second semiconductor layer where the source layer or the drain layer is formed is removed, and then the first semiconductor layer is etched. This makes it possible to narrow the etching region of the first semiconductor layer, and eliminates the need to form an opening for exposing a part of the first semiconductor layer around the element region. For this reason, since the first semiconductor layer can be removed over a wide range while leaving the second semiconductor layer, a cavity can be formed over a wide range under the second semiconductor layer. Thus, the area of the second semiconductor layer that can be disposed on the buried insulating layer can be increased. Further, by covering the second semiconductor layer with the support insulating film, the second semiconductor layer is supported on the semiconductor substrate by the support insulating film even when the cavity is formed under the second semiconductor layer. It becomes possible. Therefore, the second semiconductor layer can be disposed on the buried insulating layer, and insulation between the second semiconductor layer and the semiconductor substrate can be achieved without deteriorating the quality of the second semiconductor layer. . As a result, it is possible to form an SOI transistor on the second semiconductor layer without using an SOI substrate, and it is possible to reduce the cost of the SOI transistor and to restrict the size and layout of the SOI transistor. The integration degree of the SOI transistor can be improved while relaxing the above.

  According to the method for manufacturing a semiconductor device of one embodiment of the present invention, a step of selectively forming an element isolation insulating film on a semiconductor substrate, and a first step on the semiconductor substrate separated by the element isolation insulating film Forming a semiconductor layer by selective epitaxial growth, forming a second semiconductor layer having a lower etching rate than the first semiconductor layer on the first semiconductor layer by selective epitaxial growth, and the second semiconductor layer comprising: Forming an insulating film on the semiconductor substrate so as to be covered; forming an opening through the insulating film and the second semiconductor layer to expose a part of the first semiconductor layer; Forming a cavity under the second semiconductor layer by selectively etching the first semiconductor layer through the opening and removing the first semiconductor layer through the opening; A step of forming a buried insulating layer embedded in the cavity, a step of forming a gate electrode on the second semiconductor layer via a gate insulating film, and the opening is at least one of a source layer and a drain layer And forming a source layer and a drain layer arranged so as to sandwich the gate electrode in the second semiconductor layer.

  As a result, the first and second semiconductor layers can be selectively epitaxially grown on the semiconductor substrate using the element isolation insulating film, and the first isolation layer can be formed without forming an opening in the element isolation insulating film. The first semiconductor layer under the two semiconductor layers can be removed. For this reason, it is possible to form an SOI transistor on the second semiconductor layer while reducing the number of processes, and it is possible to reduce the price of the SOI transistor and to reduce the size and layout of the SOI transistor. The integration degree of the SOI transistor can be improved while relaxing the restrictions.

  According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the step of forming the first semiconductor layer over the semiconductor substrate, and the second semiconductor layer having an etching rate smaller than that of the first semiconductor layer are provided in the first semiconductor layer. Forming on the first semiconductor layer, forming an opening through the first semiconductor layer and the second semiconductor layer to expose the semiconductor substrate, and filling the opening so that the opening is embedded. (2) forming a support insulating film on the semiconductor layer; patterning the support insulating film; exposing a part of the surface of the second semiconductor layer; and the patterned support insulating film. Etching the second semiconductor layer and the first semiconductor layer using the mask as a mask to expose side surfaces of the first semiconductor layer and the second semiconductor layer, and the first semiconductor A step of selectively etching the first semiconductor layer from the side surface to form a cavity from which the first semiconductor layer has been removed under the second semiconductor layer; and a buried insulation buried in the cavity. A step of forming a layer, a step of exposing the surface of the second semiconductor layer by removing the support insulating film on the second semiconductor layer, and a gate insulating film on the second semiconductor layer Forming the gate electrode, and the source and drain layers disposed so as to sandwich the gate electrode so that the opening is disposed in at least one of the source layer and the drain layer. And a step of forming the semiconductor layer.

  As a result, when the first semiconductor layer is removed, a support for supporting the second semiconductor layer on the semiconductor substrate can be formed on the source layer or the drain layer, and the first removed under the second semiconductor layer. The volume of the semiconductor layer can be reduced, and it is not necessary to form a support for supporting the first semiconductor layer around the element region. For this reason, it is possible to form an SOI transistor on a semiconductor layer without using an SOI substrate, it is possible to reduce the price of the SOI transistor, and relax restrictions on the size and layout of the SOI transistor. However, the integration degree of the SOI transistor can be improved.

According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the step of forming the first semiconductor layer over the semiconductor substrate, and the second semiconductor layer having an etching rate smaller than that of the first semiconductor layer are provided in the first semiconductor layer. Forming a first semiconductor layer; forming a first opening through the first semiconductor layer and the second semiconductor layer to expose the semiconductor substrate; and filling the first opening. Forming a support insulating film on the second semiconductor layer, and forming a second opening through the support insulating film and the second semiconductor layer to expose a part of the first semiconductor layer And a step of selectively etching the first semiconductor layer through the second opening to form a cavity from which the first semiconductor layer has been removed below the second semiconductor layer; Embedded in the cavity Forming a write insulating layer, by removing the support insulating film on the second semiconductor layer, thereby exposing the surface of said second semiconductor layer,
Forming a gate electrode on the second semiconductor layer through a gate insulating film, and arranging the first opening and the second opening in at least one of the source layer and the drain layer. Forming a source layer and a drain layer arranged so as to sandwich the gate electrode in the second semiconductor layer.

  Accordingly, not only can the second opening for removing the first semiconductor layer disposed under the second semiconductor layer be formed in the source layer or the drain layer, but also the first semiconductor layer is removed. In this case, a support for supporting the second semiconductor layer on the semiconductor substrate can be formed on the source layer or the drain layer. Therefore, it is possible to reduce the volume of the first semiconductor layer removed under the second semiconductor layer, and it is not necessary to form a support for supporting the first semiconductor layer around the element region. In addition, there is no need to form a second opening around the element region for removing the first semiconductor layer disposed under the second semiconductor layer. For this reason, it is possible to form an SOI transistor on a semiconductor layer without using an SOI substrate, it is possible to reduce the price of the SOI transistor, and relax restrictions on the size and layout of the SOI transistor. However, the integration degree of the SOI transistor can be improved.

The method for manufacturing a semiconductor device according to one aspect of the present invention further includes a step of forming contacts disposed in the source layer and the drain layer so as to avoid the opening.
Thus, even when an opening is formed in the source layer or the drain layer, contact regions can be formed in the source layer and the drain layer, and contact can be made with the source layer and the drain layer.

Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.
FIGS. 1A to 7A are perspective views showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention, and FIGS. 1B to 7B are FIGS. Sectional views cut along lines A1-A1 ′ to A7-A7 ′ in FIG. 7A, and FIGS. 1C to 7C are B1 in FIGS. 1A to 7A, respectively. It is sectional drawing cut | disconnected by the -B1'-B7-B7 'line | wire, respectively.

  In FIG. 1, for example, an element isolation insulating film 6 is formed in an element isolation region R2 of the semiconductor substrate 1 by a LOCOS (Local Oxidation of Silicon) method, and the element region R1 separated by the element isolation insulating film 6 is formed in the semiconductor substrate. 1 to form. As a method for forming the element isolation insulating film 6 in the element isolation region R2 of the semiconductor substrate 1, a method such as STI (Shallow Trench Isolation) may be used in addition to the LOCOS method.

Next, as shown in FIG. 2, the first semiconductor layer 2 and the second semiconductor layer 3 are selectively formed sequentially on the semiconductor substrate 1 by performing selective epitaxial growth using the element isolation insulating film 6 as a mask.
The first semiconductor layer 2 can be made of a material having an etching rate larger than that of the semiconductor substrate 1 and the second semiconductor layer 3, and the material of the semiconductor substrate 1, the first semiconductor layer 2 and the second semiconductor layer 3 is For example, a combination selected from Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, and the like can be used. In particular, when the semiconductor substrate 1 is Si, it is preferable to use SiGe as the first semiconductor layer 2 and Si as the second semiconductor layer 3. Accordingly, it is possible to secure a selection ratio between the first semiconductor layer 2 and the second semiconductor layer 3 while enabling lattice matching between the first semiconductor layer 2 and the second semiconductor layer 3. it can. In addition, the film thickness of the 1st semiconductor layer 2 and the 2nd semiconductor layer 3 can be about 10-200 nm, for example.

  Here, since the first semiconductor layer 2 and the second semiconductor layer 3 are not epitaxially grown on the element isolation insulating film 6, the first semiconductor layer 2 and the second semiconductor layer 3 are formed after the element isolation insulating film 6 is formed. By performing epitaxial growth, the first semiconductor layer 2 and the second semiconductor layer 3 can be selectively formed in the element region R <b> 1 of the semiconductor substrate 1. Therefore, a mask for selectively forming the first semiconductor layer 2 and the second semiconductor layer 3 in the element region R1 of the semiconductor substrate 1 can be used also as the element isolation insulating film 6, and the first semiconductor layer 2 In addition, since it is not necessary to form a mask for selectively forming the second semiconductor layer 3 in the element region R1 of the semiconductor substrate 1 separately from the element isolation insulating film 6, the number of processes can be reduced.

  Next, as shown in FIG. 3, the support insulating film 5 disposed so as to cover the second semiconductor layer 3 is formed on the second semiconductor layer 3 by a method such as CVD. As the support insulating film 5, for example, a silicon oxide film or a silicon nitride film can be used. Then, the opening 7 exposing at least a part of the first semiconductor layer 2 is formed by patterning the support insulating film 5, the second semiconductor layer 3, and the first semiconductor layer 2 using a photolithography technique and an etching technique. Formed on the support insulating film 5, the second semiconductor layer 3, and the first semiconductor layer 2.

Here, the opening 7 is preferably disposed in the element region R1. As a result, it is not necessary to arrange the opening 7 in the element isolation region R2, the element region R1 can be enlarged, and the integration degree of the SOI transistors formed in the element region R1 can be improved.
In addition, when forming the opening part 7 which exposes at least a part of the first semiconductor layer 2, the etching may be stopped on the surface of the first semiconductor layer 2, or the first semiconductor layer 2 may be over-etched. A recess may be formed in the first semiconductor layer 2. Alternatively, the surface of the semiconductor substrate 1 may be exposed through the first semiconductor layer 2 in the opening 7. Here, by stopping the etching of the first semiconductor layer 2 in the middle, it is possible to prevent the surface of the semiconductor substrate 1 in the opening 7 from being exposed. For this reason, when the first semiconductor layer 2 is removed by etching, it is possible to reduce the time during which the semiconductor substrate 1 in the opening 7 is exposed to the etching solution or the etching gas. Etching can be suppressed.

Next, as shown in FIG. 4, the first semiconductor layer 2 is removed by etching by bringing an etching gas or an etchant into contact with the first semiconductor layer 2 through the opening 7, so that the semiconductor substrate 1 and the second semiconductor A cavity 9 is formed between the layer 3.
Here, the opening 7 exposing a part of the first semiconductor layer 2 is formed in the support insulating film 5, the second semiconductor layer 3, and the first semiconductor layer 2, so that the second semiconductor layer 2 is formed on the first semiconductor layer 2. Even in the case where the semiconductor layer 3 is laminated, it becomes possible to contact an etching gas or an etching solution with the first semiconductor layer 2 under the second semiconductor layer 3, and a cavity is formed between the semiconductor substrate 1 and the second semiconductor layer 3. The part 9 can be formed. Moreover, even when the first semiconductor layer 2 is removed by leaving the second semiconductor layer 3 covered with the support insulating film 5, the second semiconductor layer 3 is made of the semiconductor with the support insulating film 5. It becomes possible to support on the substrate 1, and the second semiconductor layer 3 can be prevented from being depressed.

  In the case where the semiconductor substrate 1 and the second semiconductor layer 3 are Si and the first semiconductor layer 2 is SiGe, it is preferable to use hydrofluoric acid as an etchant for the first semiconductor layer 2. As a result, a Si / SiGe selection ratio of about 1: 100 to 1000 can be obtained, and the first semiconductor layer 2 can be removed while suppressing overetching of the semiconductor substrate 1 and the second semiconductor layer 3. It becomes. Further, as the etchant for the first semiconductor layer 2, hydrofluoric acid / hydrogen peroxide, ammonia / hydrogen peroxide, or hydrofluoric acid / hydrogen peroxide may be used.

  Further, before the first semiconductor layer 2 is removed by etching, the first semiconductor layer 2 may be made porous by a method such as anodic oxidation, or by ion implantation in the first semiconductor layer 2, The first semiconductor layer 2 may be made amorphous. Thereby, the etching rate of the first semiconductor layer 2 can be increased, and the etching area of the first semiconductor layer 2 can be increased.

  Next, as shown in FIG. 5, by performing thermal oxidation of the semiconductor substrate 1 and the second semiconductor layer 3 in the cavity 9 through the opening 7, between the semiconductor substrate 1 and the second semiconductor layer 3. A buried oxide film 10 is formed in the cavity 9. Note that high-temperature annealing may be performed after the buried oxide film 10 is formed. Further, the buried oxide film 10 may be formed so as to fill the entire cavity 9 or may be formed so that a part of the cavity 9 remains.

  In the method of FIG. 5, the buried oxide film 10 is formed in the cavity 9 between the semiconductor substrate 1 and the second semiconductor layer 3 by performing thermal oxidation of the semiconductor substrate 1 and the second semiconductor layer 3. As described above, an insulating film is formed in the cavity 9 between the semiconductor substrate 1 and the second semiconductor layer 3 by chemical vapor deposition, so that the gap between the semiconductor substrate 1 and the second semiconductor layer 3 is obtained. The cavity 9 may be filled with an insulating film. Thereby, it is possible to fill the cavity 9 between the semiconductor substrate 1 and the second semiconductor layer 3 with a material other than the oxide film while preventing the second semiconductor layer 3 from being reduced. Therefore, it is possible to increase the thickness of the insulator disposed on the back surface side of the second semiconductor layer 3 and to reduce the dielectric constant. The capacity can be reduced.

  Next, as shown in FIG. 6, an insulating film is formed on the support insulating film 5 so as to fill the opening 7 by a method such as CVD. Then, after planarizing the insulating film on the support insulating film 5 by a method such as CMP (chemical mechanical polishing), the insulating film on the second semiconductor layer 3 and the support insulating film 5 are removed, The surface of the second semiconductor layer 3 is exposed and a buried insulating film 13 is formed in the opening 7. Here, by forming the buried insulating film 13 in the opening 7, even when the opening 7 is disposed in the source / drain layers 25a and 25b, the source / drain layers 25a and 25b can be planarized. Therefore, the integration degree of the SOI transistor can be improved.

  Next, as shown in FIG. 7, the surface of the second semiconductor layer 3 is thermally oxidized to form a gate insulating film 21 on the surface of the second semiconductor layer 3. Then, a polycrystalline silicon layer is formed on the second semiconductor layer 3 on which the gate insulating film 21 is formed by a method such as CVD. Then, the gate electrode 22 is formed on the second semiconductor layer 3 by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique. Here, the gate electrode 22 is preferably arranged so as to avoid the opening 7 formed in the second semiconductor layer 3.

  Next, by using the gate electrode 22 as a mask, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 3, thereby forming LDDs composed of low-concentration impurity introduction layers respectively disposed on both sides of the gate electrode 22. Layers 23 a and 23 b are formed on the second semiconductor layer 3. Then, an insulating layer is formed on the second semiconductor layer 3 on which the LDD layers 23a and 23b are formed by a method such as CVD, and the insulating layer is etched back using anisotropic etching such as RIE. Side walls 24 a and 24 b are formed on the side walls of the electrode 22. Then, by using the gate electrode 22 and the sidewalls 24a and 24b as masks, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 3, so that the openings 7 are arranged in the source / drain layers 25a and 25b. In this manner, source / drain layers 25 a and 25 b made of a high concentration impurity introduction layer arranged so as to sandwich the gate electrode 22 are formed in the second semiconductor layer 3. Then, source / drain contacts arranged so as to avoid the opening 7 are formed in the source / drain layers 25a and 25b, respectively.

  Here, by disposing the opening 7 in the source / drain layers 25a and 25b, a part of the first semiconductor layer 2 under the second semiconductor layer 3 where the source / drain layers 25a and 25b are formed is removed. Thus, the first semiconductor layer 2 can be etched, the etching region of the first semiconductor layer 2 can be narrowed, and the opening 7 exposing a part of the first semiconductor layer 2 is formed in the element region. It is not necessary to form around R1. For this reason, since it is possible to remove the first semiconductor layer 1 over a wide range while leaving the second semiconductor layer 3, the cavity 9 is formed over the wide range below the second semiconductor layer 3. Thus, the area of the second semiconductor layer 3 that can be disposed on the buried oxide film 10 can be increased. For this reason, it is possible to dispose the second semiconductor layer 3 on the buried oxide film 10 while reducing the occurrence of defects in the second semiconductor layer 3, and the second semiconductor layer 3 can be disposed without degrading the quality of the second semiconductor layer 3. Insulation between the semiconductor layer 3 and the semiconductor substrate 1 can be achieved. As a result, an SOI transistor can be formed on the second semiconductor layer 3 without using an SOI substrate, so that the SOI transistor can be reduced in price and the size and layout of the SOI transistor can be reduced. It is possible to improve the integration degree of the SOI transistor while relaxing the restriction.

  FIGS. 8A to 15A are perspective views showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention, and FIGS. 8B to 15B are FIGS. -Sectional drawing cut | disconnected by A11-A11'-A18-A18 'line of Fig.15 (a), respectively, Fig.8 (c)-FIG.15 (c) are B11 of Fig.8 (a)-FIG.15 (a). It is sectional drawing cut | disconnected by the -B11'-B18-B18 'line | wire, respectively.

  In FIG. 8, the first semiconductor layer 32 and the second semiconductor layer 33 are selectively formed sequentially on the semiconductor substrate 31 by performing epitaxial growth. The first semiconductor layer 32 can be made of a material having a higher etching rate than the semiconductor substrate 31 and the second semiconductor layer 33. When the semiconductor substrate 31 and the second semiconductor layer 33 are Si, the first semiconductor layer 32 is used. It is preferable to use SiGe.

  Next, as shown in FIG. 9, by patterning the first semiconductor layer 32 and the second semiconductor layer 33 using a photolithography technique and an etching technique, the first semiconductor layer 32 and the second semiconductor layer 33 are penetrated. Then, an opening 34 for exposing the semiconductor substrate 31 is formed. Here, the opening 34 is preferably disposed in the element region. Thereby, it is not necessary to arrange the opening 34 in the element isolation region, the element region can be enlarged, and the integration degree of SOI transistors formed in the element region can be improved.

Next, as shown in FIG. 10, a support insulating film 35 is formed on the entire surface of the second semiconductor layer 33 so as to fill the opening 34 by a method such as CVD. As the material of the support insulating film 35, for example, a silicon oxide film or a silicon nitride film can be used.
Next, as shown in FIG. 11, a part of the surface of the second semiconductor layer 33 is exposed by patterning the support insulating film 35 using a photolithography technique and an etching technique. Then, by etching the second semiconductor layer 33 and the first semiconductor layer 32 using the patterned support insulating film 35 as a mask, a part of the surface of the semiconductor substrate 31 is exposed, and the first semiconductor layer 32 and the first semiconductor layer 32 are exposed. 2 The side surface of the semiconductor layer 33 is exposed. When exposing the side surfaces of the first semiconductor layer 32 and the second semiconductor layer 33, it is not always necessary to expose a part of the surface of the semiconductor substrate 31, and etching is stopped on the surface of the first semiconductor layer 32. Alternatively, the first semiconductor layer 32 may be over-etched to form a recess in the first semiconductor layer 32.

  Next, as shown in FIG. 12, the first semiconductor layer 32 is removed by etching by bringing an etching gas or an etchant into contact with the first semiconductor layer 32 through the side surface of the first semiconductor layer 32. A cavity 39 is formed between the first semiconductor layer 33 and the second semiconductor layer 33. Here, even when the first semiconductor layer 32 is removed by embedding the support insulating film 35 in the opening 34, the second semiconductor layer 33 is supported on the semiconductor substrate 31 by the support insulating film 35. It is possible to prevent the second semiconductor layer 33 from being depressed. Further, by patterning the antioxidant film 35, the second semiconductor layer 33, and the first semiconductor layer 32 so that the side surfaces of the first semiconductor layer 32 are exposed, the second semiconductor layer 33 and the oxidation layer are formed on the first semiconductor layer 32. Even when the prevention film 35 is laminated, the etching gas or the etching liquid can be brought into contact with the first semiconductor layer 32 under the second semiconductor layer 33, and the cavity is formed between the semiconductor substrate 31 and the second semiconductor layer 33. The part 39 can be formed.

  Next, as shown in FIG. 13, the buried oxide film 40 is formed in the cavity 39 between the semiconductor substrate 31 and the second semiconductor layer 33 by performing thermal oxidation of the semiconductor substrate 31 and the second semiconductor layer 33. To do. Note that high-temperature annealing may be performed after the buried oxide film 40 is formed. Further, the buried oxide film 40 may be formed so as to fill the entire cavity 39, or may be formed so that a part of the cavity 39 remains.

  In the method of FIG. 13, the buried oxide film 40 is formed in the cavity 39 between the semiconductor substrate 31 and the second semiconductor layer 33 by performing thermal oxidation of the semiconductor substrate 31 and the second semiconductor layer 33. As described above, an insulating film is formed in the cavity 39 between the semiconductor substrate 31 and the second semiconductor layer 33 by chemical vapor deposition, so that the gap between the semiconductor substrate 31 and the second semiconductor layer 33 is obtained. The cavity 39 may be filled with an insulating film.

  Next, as shown in FIG. 14, the support insulating film 35 is thinned by a method such as etch back or CMP (Chemical Mechanical Polishing), so that the inside of the opening 34 is filled with the support insulating film 35. Thus, the surface of the second semiconductor layer 33 is exposed. Here, by embedding the support insulating film 35 in the opening 34, the source / drain layers 35a and 35b can be flattened even when the opening 34 is disposed in the source / drain layers 55a and 55b. Therefore, the integration degree of the SOI transistor can be improved.

  Next, as shown in FIG. 15, a gate insulating film 51 is formed on the surface of the second semiconductor layer 33 by performing thermal oxidation of the surface of the second semiconductor layer 33. Then, a polycrystalline silicon layer is formed on the second semiconductor layer 33 on which the gate insulating film 51 is formed by a method such as CVD. Then, the gate electrode 52 is formed on the second semiconductor layer 33 by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique. Here, the gate electrode 52 is preferably arranged so as to avoid the opening 34 formed in the second semiconductor layer 33.

  Next, by using the gate electrode 52 as a mask, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 33, whereby LDDs composed of low-concentration impurity introduction layers respectively disposed on both sides of the gate electrode 52. Layers 53 a and 53 b are formed on the second semiconductor layer 33. Then, an insulating layer is formed on the second semiconductor layer 33 on which the LDD layers 53a and 53b are formed by a method such as CVD, and the insulating layer is etched back using anisotropic etching such as RIE. Side walls 54 a and 54 b are formed on the side walls of the electrode 52. Then, using the gate electrode 52 and the side walls 54a and 54b as masks, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 33, whereby the opening 34 is disposed in the source / drain layers 55a and 55b. In this manner, source / drain layers 55 a and 55 b made of high-concentration impurity introduction layers disposed so as to sandwich the gate electrode 52 are formed in the second semiconductor layer 33. Then, source / drain contacts arranged so as to avoid the opening 34 are formed in the source / drain layers 55a and 55b, respectively.

  Thereby, when the first semiconductor layer 32 is removed, the support insulating film 35 that supports the second semiconductor layer 33 on the semiconductor substrate 31 can be formed on the source / drain layers 55a and 55b. The volume of the first semiconductor layer 32 removed under the layer 33 can be reduced, and the support insulating film 35 for supporting the first semiconductor layer 32 need not be formed around the element region. Therefore, it is possible to form an SOI transistor on the second semiconductor layer 33 without using an SOI substrate, it is possible to reduce the price of the SOI transistor, and to the size and layout of the SOI transistor. The integration degree of the SOI transistor can be improved while relaxing the restrictions.

  FIGS. 16A to 23A are perspective views showing a method of manufacturing a semiconductor device according to the third embodiment of the present invention, and FIGS. 16B to 23B are FIGS. Cross-sectional views cut along lines A21-A21 ′ to A28-A28 ′ in FIG. 23 (a), and FIGS. 16 (c) to 23 (c) are B21 in FIGS. 16 (a) to 23 (a). It is sectional drawing cut | disconnected by the -B21'-B28-B28 'line | wire, respectively.

  In FIG. 16, the first semiconductor layer 62 and the second semiconductor layer 63 are selectively formed sequentially on the semiconductor substrate 61 by performing epitaxial growth. The first semiconductor layer 62 can be made of a material having a higher etching rate than the semiconductor substrate 61 and the second semiconductor layer 63. When the semiconductor substrate 61 and the second semiconductor layer 63 are Si, the first semiconductor layer 62 is used. It is preferable to use SiGe.

  Next, as shown in FIG. 17, the first semiconductor layer 62 and the second semiconductor layer 63 are penetrated by patterning the first semiconductor layer 62 and the second semiconductor layer 63 using a photolithography technique and an etching technique. Thus, an opening 67a exposing the semiconductor substrate 61 is formed. Here, the opening 67a is preferably disposed in the element region. Accordingly, it is not necessary to arrange the opening 67a in the element isolation region, the element region can be enlarged, and the integration degree of SOI transistors formed in the element region can be improved.

Next, as shown in FIG. 18, a support insulating film 65 is formed on the entire surface of the second semiconductor layer 63 so as to fill the opening 67 a by a method such as CVD. As a material of the support insulating film 65, for example, a silicon oxide film or a silicon nitride film can be used.
Next, as shown in FIG. 19, at least one of the first semiconductor layers 62 is patterned by patterning the support insulating film 65, the second semiconductor layer 63, and the first semiconductor layer 62 using a photolithography technique and an etching technique. An opening 67b exposing the portion is formed in the support insulating film 65, the second semiconductor layer 63, and the first semiconductor layer 62.

Here, the opening 67b is preferably disposed in the element region. Thereby, it is not necessary to arrange the opening 67b in the element isolation region, the element region can be enlarged, and the integration degree of SOI transistors formed in the element region can be improved.
When forming the opening 67b exposing at least a part of the first semiconductor layer 62, the etching may be stopped on the surface of the first semiconductor layer 62, or the first semiconductor layer 62 may be over-etched. A recess may be formed in the first semiconductor layer 62. Alternatively, the surface of the semiconductor substrate 61 may be exposed through the first semiconductor layer 62 in the opening 67b.

  Next, as shown in FIG. 20, the first semiconductor layer 62 is removed by etching by bringing an etching gas or an etchant into contact with the first semiconductor layer 62 through the opening 67 b, and the semiconductor substrate 61 and the second semiconductor are removed. A cavity 69 is formed between the layer 63. Here, even when the first semiconductor layer 62 is removed by embedding the support insulating film 65 in the opening 67a, the second semiconductor layer 63 is supported on the semiconductor substrate 61 by the support insulating film 65. It is possible to prevent the second semiconductor layer 63 from being depressed. Even when the second semiconductor layer 63 and the support insulating film 65 are stacked on the first semiconductor layer 62 by forming the opening 67b separately from the opening 67a in which the support insulating film 65 is embedded. The etching gas or the etchant can be brought into contact with the first semiconductor layer 62 under the second semiconductor layer 63, and the cavity 69 can be formed between the semiconductor substrate 61 and the second semiconductor layer 63.

  Next, as shown in FIG. 21, the buried oxide film 70 is formed in the cavity 69 between the semiconductor substrate 61 and the second semiconductor layer 63 by performing thermal oxidation of the semiconductor substrate 61 and the second semiconductor layer 63. To do. Note that high-temperature annealing may be performed after the buried oxide film 70 is formed. Further, the buried oxide film 70 may be formed so as to fill the entire cavity 69 or may be formed so that a part of the cavity 69 remains.

  In the method of FIG. 21, the buried oxide film 70 is formed in the cavity 69 between the semiconductor substrate 61 and the second semiconductor layer 63 by performing thermal oxidation of the semiconductor substrate 61 and the second semiconductor layer 63. However, the insulating film is formed in the cavity 69 between the semiconductor substrate 61 and the second semiconductor layer 63 by chemical vapor deposition, so that the gap between the semiconductor substrate 61 and the second semiconductor layer 63 is increased. The cavity 69 may be filled with an insulating film.

  Next, as shown in FIG. 22, an insulating film is formed on the support insulating film 65 so as to fill the opening 67b by a method such as CVD. Then, after planarizing the insulating film on the support insulating film 65 by a method such as CMP (Chemical Mechanical Polishing), the support insulating film 65 on the second semiconductor layer 3 is thinned, thereby opening the opening portion. The surface of the second semiconductor layer 63 is exposed so that the inside of the support 67a is filled with the support insulating film 65, and a buried insulating film 73 is formed in the opening 67b. Here, in the case where the openings 67a and 67b are arranged in the source / drain layers 85a and 85b by embedding the support insulating film 65 in the opening 67a and forming the buried insulating film 73 in the opening 67b. However, the source / drain layers 85a and 85b can be planarized, and the integration degree of the SOI transistor can be improved.

  Next, as shown in FIG. 23, the surface of the second semiconductor layer 63 is thermally oxidized to form a gate insulating film 81 on the surface of the second semiconductor layer 63. Then, a polycrystalline silicon layer is formed on the second semiconductor layer 63 on which the gate insulating film 81 is formed by a method such as CVD. Then, the gate electrode 82 is formed on the second semiconductor layer 63 by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique. Here, the gate electrode 82 is preferably arranged so as to avoid the openings 67 a and 67 b formed in the second semiconductor layer 63.

  Next, by using the gate electrode 82 as a mask, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 63, whereby LDDs composed of low-concentration impurity introduction layers respectively disposed on both sides of the gate electrode 82. Layers 83 a and 83 b are formed in the second semiconductor layer 63. Then, an insulating layer is formed on the second semiconductor layer 63 on which the LDD layers 83a and 83b are formed by a method such as CVD, and the insulating layer is etched back using anisotropic etching such as RIE. Side walls 84 a and 84 b are formed on the side walls of the electrode 82. Then, by using the gate electrode 82 and the sidewalls 84a and 84b as masks, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 63, whereby the openings 67a and 67b are formed in the source / drain layers 85a and 85b. Thus, source / drain layers 85 a and 85 b made of high-concentration impurity introduction layers arranged so as to sandwich the gate electrode 82 are formed in the second semiconductor layer 63. Then, source / drain contacts arranged so as to avoid the openings 67a and 67b are formed in the source / drain layers 85a and 85b, respectively.

  Thereby, not only the opening 67b for removing the first semiconductor layer 62 disposed under the second semiconductor layer 63 can be formed in the source / drain layers 85a and 85b, but also the first semiconductor layer. When 62 is removed, the support insulating film 65 that supports the second semiconductor layer 63 on the semiconductor substrate 61 can be disposed on the source / drain layers 85a and 85b. Therefore, the volume of the first semiconductor layer 62 removed under the second semiconductor layer 63 can be reduced, and the support insulating film 65 for supporting the first semiconductor layer 62 is provided around the element region. And an opening 67b for removing the first semiconductor layer 62 disposed under the second semiconductor layer 63 need not be formed around the element region. For this reason, it is possible to form an SOI transistor on the second semiconductor layer 63 without using an SOI substrate, it is possible to reduce the price of the SOI transistor, and to the size and layout of the SOI transistor. The integration degree of the SOI transistor can be improved while relaxing the restrictions.

The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention.

Explanation of symbols

  R1 element region, R2 element isolation region, 1, 31, 61 semiconductor substrate, 2, 32, 62 first semiconductor layer, 3, 33, 63 second semiconductor layer, 5, 35, 65 support insulating film, 6 element isolation Insulating film, 7, 34, 67a, 67b Opening, 9, 39, 69 Cavity, 10, 70 Embedded oxide film, 13, 40, 73 Embedded insulating film, 21, 51, 81 Gate insulating film, 22, 52, 82 Gate electrode, 23a, 23b, 53a, 53b, 83a, 83b LDD layer, 24a, 24b, 54a, 54b, 84a, 84b Side wall spacer, 25a, 25b, 55a, 55b, 85a, 85b Source / drain layer

Claims (5)

Forming a first semiconductor layer on a part of the surface of the semiconductor substrate;
Forming a second semiconductor layer having a lower etching rate than the first semiconductor layer on the first semiconductor layer;
Forming a support insulating film on the semiconductor substrate so as to cover the second semiconductor layer;
Forming an opening that penetrates the support insulating film and the second semiconductor layer and exposes a portion of the first semiconductor layer;
Forming a cavity from which the first semiconductor layer has been removed by selectively etching the first semiconductor layer through the opening, under the second semiconductor layer;
Forming a buried insulating layer buried in the cavity through the opening;
Forming a gate electrode on the second semiconductor layer through a gate insulating film;
Forming the source layer and the drain layer in the second semiconductor layer so as to sandwich the gate electrode so that the opening is disposed in at least one of the source layer and the drain layer. A method for manufacturing a semiconductor device. Selectively forming an element isolation insulating film on a semiconductor substrate;
Forming a first semiconductor layer on the semiconductor substrate separated by the element isolation insulating film by selective epitaxial growth;
Forming a second semiconductor layer having an etching rate smaller than that of the first semiconductor layer on the first semiconductor layer by selective epitaxial growth;
Forming an insulating film on the semiconductor substrate so as to cover the second semiconductor layer;
Forming an opening through the insulating film and the second semiconductor layer to expose a portion of the first semiconductor layer;
Forming a cavity from which the first semiconductor layer has been removed by selectively etching the first semiconductor layer through the opening, under the second semiconductor layer;
Forming a buried insulating layer buried in the cavity through the opening;
Forming a gate electrode on the second semiconductor layer through a gate insulating film;
Forming the source layer and the drain layer in the second semiconductor layer so as to sandwich the gate electrode so that the opening is disposed in at least one of the source layer and the drain layer. A method for manufacturing a semiconductor device. Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer having a lower etching rate than the first semiconductor layer on the first semiconductor layer;
Forming an opening through the first semiconductor layer and the second semiconductor layer to expose the semiconductor substrate;
Forming a support insulating film on the second semiconductor layer so that the opening is embedded;
Exposing a part of the surface of the second semiconductor layer by patterning the support insulating film;
Exposing the side surfaces of the first semiconductor layer and the second semiconductor layer by etching the second semiconductor layer and the first semiconductor layer using the patterned support insulating film as a mask;
Forming a cavity from which the first semiconductor layer has been removed by selectively etching the first semiconductor layer from a side surface of the first semiconductor layer under the second semiconductor layer;
Forming a buried insulating layer buried in the cavity;
Exposing the surface of the second semiconductor layer by removing the support insulating film on the second semiconductor layer;
Forming a gate electrode on the second semiconductor layer through a gate insulating film;
Forming the source layer and the drain layer in the second semiconductor layer so as to sandwich the gate electrode so that the opening is disposed in at least one of the source layer and the drain layer. A method for manufacturing a semiconductor device. Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer having a lower etching rate than the first semiconductor layer on the first semiconductor layer;
Forming a first opening through the first semiconductor layer and the second semiconductor layer to expose the semiconductor substrate;
Forming a support insulating film on the second semiconductor layer so that the first opening is embedded;
Forming a second opening that penetrates the support insulating film and the second semiconductor layer and exposes a portion of the first semiconductor layer;
Forming a cavity under the second semiconductor layer by selectively etching the first semiconductor layer through the second opening, and removing the first semiconductor layer;
Forming a buried insulating layer buried in the cavity;
Exposing the surface of the second semiconductor layer by removing the support insulating film on the second semiconductor layer;
Forming a gate electrode on the second semiconductor layer through a gate insulating film;
The source and drain layers arranged so as to sandwich the gate electrode so that the first opening and the second opening are arranged in at least one of the source layer and the drain layer. Forming a layer. A method for manufacturing a semiconductor device, comprising: 5. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming contacts disposed in the source layer and the drain layer so as to avoid the opening .

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