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JP4727138B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP4727138B2
JP4727138B2 JP2003370255A JP2003370255A JP4727138B2 JP 4727138 B2 JP4727138 B2 JP 4727138B2 JP 2003370255 A JP2003370255 A JP 2003370255A JP 2003370255 A JP2003370255 A JP 2003370255A JP 4727138 B2 JP4727138 B2 JP 4727138B2
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wafer
semiconductor device
manufacturing
hydrogen
hole
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JP2005136149A (en
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克哉 国吉
克行 高橋
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Seiko NPC Corp
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Seiko NPC Corp
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Description

本発明は、半導体素子の製造方法に関し、特に、ウェハの界面準位を回復して、少なくすることができる半導体素子の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that can recover and reduce the interface state of a wafer.

一般に、ＭＯＳ型の半導体素子においては、シリコン基板等のシリコンと酸化シリコンとの界面に存在する準位、すなわち界面準位が、しきい値電圧の不安定化要因となったり、暗電流の発生原因になる。また、アモルファスシリコンで半導体素子を形成したものにおいては、シリコングレインの表面の界面準位が移動度を低下させる原因となる。このような事態を生じるのは、界面準位は各シリコンの持つ手のうちの少なくとも一つが空きとなり、そこにエレクトロンが入ってクーロン力によりキャリアのパスに影響を及ぼす可能性があるからである。この界面準位は一般に、１〜２×１０１０／ｃｍ２程度までは許容されるが、それより多くなると許容されないものである。 In general, in a MOS type semiconductor device, a level existing at the interface between silicon and silicon oxide, such as a silicon substrate, that is, an interface level causes destabilization of the threshold voltage or generates dark current. Cause. Moreover, in the case where the semiconductor element is formed of amorphous silicon, the interface state on the surface of the silicon grain causes the mobility to be lowered. This occurs because at least one of the hands of each silicon has an empty interface state, and electrons may enter there and affect the carrier path by Coulomb force. . In general, this interface state is allowed up to about 1 to 2 × 10 10 / cm 2 , but not higher than that.

したがって、電気的特性に優れた半導体素子をウェハに形成するには、素子を形成する前に、ウェハ表面（半導体素子を形成する面）の界面準位を十分に回復し、少なくしておくことが必要である。そのために、界面準位、すなわち界面の活性なシリコンの手に、水素を結合することにより、水素とシリコンとを共有結合させ、キャリアのパスに影響を及ぼすクーロン力の発生をなくす技術として、水素雰囲気中でウェハに高温の熱処理を行う水素アニール法が知られている。
特開平８−７８４２７号公報 Therefore, in order to form a semiconductor element having excellent electrical characteristics on a wafer, the interface state on the wafer surface (surface on which the semiconductor element is formed) must be sufficiently recovered and reduced before the element is formed. is required. For this purpose, hydrogen is bonded to the interface state, that is, the active silicon in the interface, to covalently bond hydrogen and silicon, thereby eliminating the generation of Coulomb force that affects the carrier path. A hydrogen annealing method is known in which high-temperature heat treatment is performed on a wafer in an atmosphere.
JP-A-8-78427

しかしながら、従来一般に行われている水素アニール法では、ウェハの表裏面が窒化シリコン膜や金属膜で覆われているような場合には、被膜によって水素の侵入が妨げられ、十分に界面準位を回復して、少なくすることができなかった。本発明は、このような従来の不都合を解消し、ウェハ表面の界面準位を十分に回復して、少なくすることができる半導体素子の製造方法を提供することを目的とする。   However, in the conventional hydrogen annealing method, when the front and back surfaces of the wafer are covered with a silicon nitride film or a metal film, the coating prevents hydrogen from entering, and the interface state is sufficiently increased. He was unable to recover and reduce. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can eliminate such conventional disadvantages and sufficiently recover and reduce the interface state on the wafer surface.

この目的を達成するため、本発明の請求項１に係る半導体素子の製造方法は、表裏面に水素の侵入を妨げる被膜が形成されてなるウェハの裏面側に、各チップ形成予定部分の一つずつに対応するよう、穴や溝などの凹部を形成する第１の工程と、水素アニールを施す第２の工程とからなるものである。前記凹部の深さは、ウェハの強度を損なわない厚さを残すように設定する。 In order to achieve this object, a method for manufacturing a semiconductor device according to claim 1 of the present invention is characterized in that one of the chip formation scheduled portions is formed on the back surface side of a wafer formed with a coating that prevents hydrogen from entering on the front and back surfaces. In order to correspond to each, it consists of a first step of forming recesses such as holes and grooves and a second step of applying hydrogen annealing. The depth of the recess is set so as to leave a thickness that does not impair the strength of the wafer.

同じく上記目的を達成するために、本発明の請求項２に係る半導体素子の製造方法は、表裏面に水素の侵入を妨げる被膜が形成されてなるウェハの裏面側に、各チップ形成予定部分の中央部に対応するよう穴を形成する第１の工程と、水素アニールを施す第２の工程とからなるものである。 Similarly, in order to achieve the above object, a method for manufacturing a semiconductor device according to claim 2 of the present invention provides a method for forming each chip formation portion on the back surface side of a wafer in which a coating that prevents hydrogen from entering on the front and back surfaces is formed . This comprises a first step of forming a hole so as to correspond to the central portion, and a second step of performing hydrogen annealing.

本発明の請求項１に係る半導体素子の製造方法によれば、ウェハ裏面側に、各チップ形成予定部分の一つずつに対応するように設けた凹部から、水素が侵入することにより、半導体素子形成領域に生じている界面準位を十分に回復して、少なくすることができるという効果を奏する。   According to the method for manufacturing a semiconductor device according to claim 1 of the present invention, the hydrogen enters from the concave portion provided to correspond to each of the chip formation scheduled portions on the back surface side of the wafer. There is an effect that the interface states generated in the formation region can be sufficiently recovered and reduced.

本発明の請求項２に係る半導体素子の製造方法によれば、ウェハ裏面側に、各チップ形成予定部分の中央部に対応するよう設けた穴から、水素が侵入することにより、半導体素子形成領域に生じている界面準位を、より一層十分に回復して、少なくすることができるという効果を奏する。   According to the method for manufacturing a semiconductor device according to claim 2 of the present invention, the hydrogen enters from the hole provided on the back side of the wafer so as to correspond to the central portion of each chip formation scheduled portion. The interface state generated in the step can be further sufficiently recovered and reduced.

以下、本発明の好適な実施形態を添付図面に基づいて説明する。はじめに、第１の工程として、図１及び図２に示すように、ウェハ１の裏面側に、各チップ形成予定部分２の中央部に対応するよう穴３を形成する。この穴３の形成は、通常のフォトリソグラフィーとエッチングとによって行うもので、穴３の断面形状は特に限定されない。   DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the accompanying drawings. First, as a first step, as shown in FIGS. 1 and 2, a hole 3 is formed on the back side of the wafer 1 so as to correspond to the central portion of each chip formation scheduled portion 2. The formation of the hole 3 is performed by ordinary photolithography and etching, and the cross-sectional shape of the hole 3 is not particularly limited.

各穴３の深さと断面の大きさは、ウェハ１の厚み及び各チップ形成予定部分２の大きさに応じて設定する。例えば、厚さ６２５μｍのウェハ１から、縦横
１×１ｍｍのチップを得る場合に、断面円形の穴３を形成するのであれば、各穴３の深さは４００〜６００μｍ程度、断面の最大径は３００〜６００μｍ程度が好適である。 The depth of each hole 3 and the size of the cross section are set according to the thickness of the wafer 1 and the size of each chip formation scheduled portion 2. For example, in the case of obtaining a chip of 1 × 1 mm in length and width from a wafer 1 having a thickness of 625 μm, if the holes 3 having a circular cross section are formed, the depth of each hole 3 is about 400 to 600 μm, and the maximum diameter of the cross section is About 300-600 micrometers is suitable.

次に、第２の工程として、通常の水素アニールを施す。この水素アニールは４００〜４５０℃で０．５〜１時間行う。この際、穴３の底部が半導体形成領域を形成するウェハ１の表面側に近づくので、ウェハ１の各チップ形成予定部分２に対して、水素が裏面側から十分に侵入し、半導体素子形成領域に生じている界面準位を回復して、少なくすることができる。   Next, as a second step, normal hydrogen annealing is performed. This hydrogen annealing is performed at 400 to 450 ° C. for 0.5 to 1 hour. At this time, since the bottom of the hole 3 approaches the front surface side of the wafer 1 forming the semiconductor formation region, hydrogen sufficiently enters the chip formation scheduled portions 2 of the wafer 1 from the back surface side, and the semiconductor element formation region It is possible to recover and reduce the interface states generated in the layer.

なお、本発明は上述の実施形態に限定されるものではなく、例えば、穴３の断面形状は、円形のほか、多角形や楕円形などでもよい。また、穴３に換えて、溝を形成してもよい。   In addition, this invention is not limited to the above-mentioned embodiment, For example, the cross-sectional shape of the hole 3 may be a polygon, an ellipse, etc. other than circular. Further, a groove may be formed instead of the hole 3.

ウェハの裏面側を示す平面図。The top view which shows the back surface side of a wafer. 図１のＡ−Ａ線断面図。AA sectional view taken on the line AA of FIG.

１ ウェハ
２ チップ形成予定部分
３ 穴 1 Wafer 2 Chip formation planned part 3 Hole

Claims (2)

表裏面に水素の侵入を妨げる被膜が形成されてなるウェハの裏面側に、各チップ形成予定部分に対応するよう凹部を形成する第１の工程と、水素アニールを施す第２の工程とからなることを特徴とする半導体素子の製造方法。 It consists of a first step of forming recesses on the back side of the wafer formed with a film that prevents hydrogen intrusion on the front and back surfaces, corresponding to each chip formation scheduled portion, and a second step of performing hydrogen annealing. A method for manufacturing a semiconductor device, comprising: 表裏面に水素の侵入を妨げる被膜が形成されてなるウェハの裏面側に、各チップ形成予定部分の中央部に対応するよう穴を形成する第１の工程と、水素アニールを施す第２の工程とからなることを特徴とする半導体素子の製造方法。 A first step of forming a hole on the back side of the wafer on which a film that prevents hydrogen from entering on the front and back sides is formed so as to correspond to the central portion of each chip formation scheduled portion, and a second step of performing hydrogen annealing A method for manufacturing a semiconductor device, comprising:
JP2003370255A 2003-10-30 2003-10-30 Manufacturing method of semiconductor device Expired - Fee Related JP4727138B2 (en)

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JP2613074B2 (en) * 1988-03-04 1997-05-21 富士通株式会社 Method for manufacturing semiconductor device
JP3419792B2 (en) * 1991-03-15 2003-06-23 ソニー株式会社 Method for manufacturing semiconductor device
JPH0878427A (en) * 1994-09-08 1996-03-22 Toshiba Corp Semiconductor substrate and its manufacture
JP2000223674A (en) * 1998-11-27 2000-08-11 Nec Corp Fabrication of semiconductor integrated circuit device
US6521977B1 (en) * 2000-01-21 2003-02-18 International Business Machines Corporation Deuterium reservoirs and ingress paths
JP2003303966A (en) * 2002-04-11 2003-10-24 Matsushita Electric Ind Co Ltd Semiconductor device and method of manufacturing the same

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