JP4724220B2 - ELECTRO-OPTICAL ELEMENT AND METHOD FOR PRODUCING THE ELECTRO-OPTICAL ELEMENT - Google Patents

Description

  The present invention relates to a method of manufacturing an active matrix liquid crystal display device (TFT-LCD) using a thin film transistor (TFT) as a switching element. More specifically, when a highly corrosive metal material is applied to the auxiliary capacitance wiring group or the collective lead wiring, the auxiliary capacitance wiring group is prevented from corroding in the subsequent transparent conductive layer etching step.

  Electro-optical elements using liquid crystals have been actively applied to displays. In general, an electro-optic element using liquid crystal has a configuration in which a liquid crystal is sandwiched between two substrates having electrodes on the upper and lower sides, and a configuration in which polarizing plates are further installed on the upper and lower sides. Backlight will be installed. The surfaces of the upper and lower electrode substrates are subjected to a so-called alignment process, and the director which is the average direction of the liquid crystal molecules is controlled to a desired initial state. The liquid crystal has birefringence, and light incident through the polarizing plate from the backlight is changed into elliptically polarized light by birefringence and is incident on the polarizing plate on the opposite side. In this state, when a voltage is applied between the upper and lower electrodes, the alignment state of the director changes, the birefringence of the liquid crystal layer changes, and the elliptical polarization state incident on the opposite polarizing plate changes. Accordingly, the intensity and spectrum of light transmitted through the electro-optic element changes. This electro-optic effect varies depending on the type of liquid crystal phase to be used, the initial alignment state, the direction of the polarization axis of the polarizing plate, the thickness of the liquid crystal layer, or the color filter and various interference films installed in the middle of light transmission. It is reported in detail by known literatures. Generally, a structure called TN or STN using a nematic liquid crystal layer is used.

  There are two types of electro-optic elements for display using liquid crystals: a simple matrix type and a TFT-LCD using TFTs as switching elements. TFT-LCDs having characteristics superior to those of CRTs and simple matrix liquid crystal display devices in terms of portability and display quality have been widely used in notebook personal computers and the like. In a TFT-LCD, polarizing plates are generally installed above and below a structure in which liquid crystal is sandwiched between a TFT array substrate in which TFTs are formed in an array and a counter substrate with a color filter on which a common electrode is formed, and further behind Take a configuration with a backlight. With such a configuration, a good color display can be obtained.

  In the TFT-LCD, since a voltage is applied to the liquid crystal, the TFT is turned on within the selection time of the gate line, charge flows from the source wiring to the pixel electrode, and the pixel potential is set to the same potential as the source wiring. After that, when the gate is in a non-selected state, the TFT is turned off and the pixel charge is held, but the pixel charge amount actually decreases due to the leakage current in the TFT and the liquid crystal, resulting in the pixel potential. Decrease. In order to prevent these fluctuations in the pixel potential, an auxiliary capacitor is usually provided so that the amount of change in the pixel potential with respect to the change in the unit charge amount is reduced. The auxiliary capacitance can be broadly divided into a case where it is formed with a previous gate and a pixel electrode (additional capacitance type) and a case where it is formed with a dedicated wiring and a pixel electrode (auxiliary capacitance wiring type). The additional capacitance type does not require a dedicated wiring as in the auxiliary capacitance wiring type, so that the aperture ratio can be increased. However, since the gate wiring also serves as the auxiliary capacitance wiring, the current load increases. For this reason, in a large panel, the sum of the wiring resistance and the auxiliary capacitance becomes large, so that the auxiliary capacitance wiring is generally used to reduce the gate wiring load. FIG. 10 shows a conceptual diagram of a TFT array substrate using auxiliary capacitance wiring. Here, 1 is a gate line, 8 is a source line, 3 is an auxiliary capacity line, 10a and 10b are collective lead lines for applying a voltage to the auxiliary capacity line. On the other hand, attempts have been made to apply low-resistance wiring materials in order to reduce wiring resistance. When Al or Al alloy such as AlSiCu, AlCu is applied to the gate wiring and auxiliary capacitance wiring of the reverse stagger type TFT, when an insulating film is formed on the wiring pattern, a hillock is generated or the pixel pattern is formed in the subsequent process. Problems such as corrosion by strong acids used during etching occur. In order to avoid these problems, in the prior art, Al or the above Al alloy wiring is covered with a refractory metal pattern such as Cr or Mo to prevent hillock, or Al or Al alloy is anodized to prevent corrosion due to hillock and strong acid. Attempts have been made to prevent it. In this case, the number of photoengraving steps and the anodizing step increase, resulting in a decrease in productivity. On the other hand, attempts have been made to use Al alloys such as AlZr and AlTa in order to prevent hillocks. In these cases, however, the specific resistance increases, resulting in a resistance comparable to that of refractory metals such as Cr. End up. Recently, as shown in Japanese Patent No. 2733006, a wiring material capable of preventing hillocks without increasing specific resistance has been developed for AlNd as in the case of AlZr. A manufacturing method of a TFT array substrate produced by a conventional method using AlNd for the gate wiring and the auxiliary capacitance wiring shown in FIGS. 8 and 9 will be described below.

  After a 200 nm film of AlNd is formed on the glass substrate by sputtering, wet etching is performed with a mixed solution of phosphoric acid / acetic acid / nitric acid to form the gate wiring 1, the auxiliary capacitance electrode 2, and the auxiliary capacitance wiring 3. At this time, the auxiliary capacitance line is connected to the collective lead line 3a on the gate opposite terminal side. Next, 400 nm of SiN, a semiconductor layer a-Si of 150 nm, and a P-doped a-Si impurity layer of 30 nm are continuously formed by plasma CVD as the gate insulating film 4, and the impurity layer and the semiconductor layer are patterned to form a semiconductor on the gate wiring. Pattern 5 is formed. Thereafter, a pixel electrode film 100 nm is formed and patterned with a mixed acid such as hydrochloric acid and nitric acid to form the pixel electrode 6. Next, a contact hole 7a is formed in the gate insulating film at the gate terminal side auxiliary capacitance wiring end. Thereafter, Cr 400 nm is continuously formed for the source wiring 8 and the drain electrode 9 and then patterned. Thereafter, the impurity layer in the channel portion is removed by dry etching. Finally, SiN 400 nm is formed as a protective film 11 and SiN in the terminal portion is removed.

  If the gate insulating film 4 has a film defect, it is broken by corrosion due to strong acid when the pixel electrode is etched. Recently, there has been a reduction in dust due to improvements in film formation equipment, and as a result, there are almost no large film defects in the gate insulating film. In the case of covering, if the coverage of the gate insulating film at the gate step portion is bad, the wiring may corrode due to these. In this way, a wiring material that has low resistance and does not generate hillocks has been developed. When the wiring material is used for the common auxiliary capacitance wiring, wiring disconnection due to corrosion as described above has become a problem.

  In particular, with regard to disconnection of the common auxiliary capacitance wiring, since the auxiliary capacitance wiring signal is input from both ends of the wiring, the disconnection is not detected electrically, and the pixel of the corresponding gate line becomes a bright line defect when the panel is lit. Need to be reduced. Regarding the auxiliary capacity wiring and the collective lead wiring pattern, Japanese Patent Laid-Open No. 3-72321 discloses that the auxiliary capacity wiring is provided at both ends of the panel as shown in FIG. 10 in order to improve the signal delay of the auxiliary capacity wiring. However, there is no mention of corrosion of auxiliary capacitance wiring during wet etching of the transparent conductive layer, which is a problem when an easily eroded metal such as Al is used for auxiliary capacitance wiring. Japanese Patent Application Laid-Open No. 7-36061 discloses a pattern example of auxiliary capacitance wiring and collective lead wiring including patterning of a transparent conductive layer. However, a corrosive metal such as Al is used for the auxiliary capacitance wiring. There is no mention of auxiliary capacitor wiring corrosion during the wet etching of the transparent conductive film, which is a problem when there is a problem.

  As described above, the object of the present invention is to prevent the corrosion disconnection of the auxiliary capacitance wiring that occurs during the wet etching of the transparent conductive layer when a metal such as Al is used for the auxiliary capacitance wiring. It is.

In the electro-optical element according to claim 1, an electro-optical material is sandwiched between a pair of substrates arranged to face each other, and a gate wiring formed on one substrate is formed in the same layer as the gate wiring, and covering a plurality of storage capacitor lines formed by the first metal thin film separated, the plurality of storage capacitor lines and the set drawing wiring that are separated from one another, the plurality of storage capacitor lines and the set drawing wiring and insulation layer formed on the substrate, wherein a plurality of auxiliary capacitance thin film transistor formed in an upper layer than the wiring, the thin film transistor is electrically connected, a transparent conductive film provided on the insulating layer a pixel electrode formed of the plurality of capacitor lines and the set drawer via a contact hole provided in the insulating layer on the wiring of the plurality storage capacitor lines the set drawer A electrooptical element comprising a conductive pattern for electrically connecting the line, the conductive pattern, said auxiliary capacitance lines and the assembly wiring has been formed separately from the first The metal thin film is formed of Al, an Al alloy, or a multilayer metal using at least one of them, or Mo.

As described in detail above, according to the invention described in claims 1 to 5 , a material that is easily corroded, such as Al, is applied to the auxiliary capacitance wiring group, and the insulating film formed on the auxiliary capacitance wiring group is covered. Even if film defects such as defects exist, it is possible to manufacture a TFT array substrate without corroding the wiring during pixel electrode etching. A natural oxide film is formed on the surface of the Al wiring or the like. However, if a potential difference of a certain level or more with the etching solution is generated during etching of the pixel electrode, the natural oxide film is dissolved and eventually the metal itself is corroded. When the auxiliary capacitance wiring group is formed separately from each other, the amount of wiring metal is small, so that the potential of the wiring is dragged by the etching solution, and as a result, the potential difference between the etching solution and the wiring metal is small and corrosion does not occur. Conceivable. On the other hand, in the state where the storage capacitor wiring group is connected to the collective lead wiring, when the pixel electrode is etched, the amount of the entire wiring is several hundred times to thousand times that when the pixel electrode is separated. It is presumed that a potential difference occurs between them, and natural oxidation and wiring are corroded.

Embodiment 1
Set drawing wiring of the first embodiment, a plan view of the storage capacitance wiring group and the pixel area in FIG. 1, FIG. 2 is a sectional view in the FIG. 1 A-A. First, a glass substrate having a thickness of 0.7 mm is cleaned as an insulating substrate to clean the surface. In the case where the electro-optic element is configured as a transmissive type, a transparent insulating substrate such as a glass substrate is used as the insulating substrate. Further, when the electro-optic element is configured as a reflection type, an insulating substrate having an insulating property comparable to that of a glass substrate can be used. The thickness of the insulating substrate may be arbitrary, but in order to reduce the thickness of the electro-optic element, a thickness of about 0.7 mm or 1.1 mm is preferable. If the insulating substrate is too thin, the substrate may be distorted by various film formation and thermal history of the process, resulting in problems such as poor patterning accuracy. Therefore, the thickness of the insulating substrate depends on the process used. It is necessary to consider and select. Further, when the insulating substrate is made of a brittle fracture material such as glass, it is preferable to chamfer the end surface of the substrate in order to prevent foreign matter from being mixed due to chipping from the end surface. In addition, it is more preferable to provide a notch in a part of the insulating substrate so that the orientation of the substrate can be specified, because the direction of substrate processing in each process can be specified, thereby facilitating process management.

  Next, a first metal thin film is formed by a method such as sputtering. As the first metal thin film, for example, a thin film having a thickness of about 100 nm to 300 nm made of an Al alloy such as Mo, AlZr, or AlNd can be used. For example, in the case of AlNd, the concentration of Nd is preferably about 1 to 3% by weight in order to reduce the wiring resistance and prevent the occurrence of hillocks. Further, as the first metal thin film, a metal thin film in which different metal thin films such as Cr / Al or Cr / AlSiCu are laminated, or a metal thin film having a different composition in the film thickness direction can be used.

Next, the gate electrode and the wiring 1, the auxiliary capacitance electrode 2, and the auxiliary capacitance wiring group 3 are patterned with the first metal thin film in the first photolithography and patterning process. At this time, the storage capacitor wiring groups are formed in a state of being separated from each other. In the photoengraving process, after the TFT array substrate is washed, a photosensitive resist is applied and dried, and then exposed through a mask pattern in which a predetermined pattern is formed and developed to form a mask pattern on the TFT array substrate in a photoengraving manner. The transferred resist is formed, and after the photosensitive resist is heated and cured, etching is performed and the photosensitive resist is peeled off. For example, in the case of Mo, AlNd, and AlZr, the first metal film is etched by wet etching using an aqueous solution of phosphoric acid, acetic acid, and nitric acid. In the case of Mo, dry etching using CF ₄ and oxygen gas is performed. In the case of AlNd and AlZr, dry etching using chlorine gas and oxygen gas is also applicable.

Next, the first insulating film 4, the semiconductor active film, and the ohmic contact film are successively formed by plasma CVD. As the first insulating film 4 serving as the gate insulating film, a SiNx film, a SiOx film, a SiOxNy film, or a laminated film thereof is used. The thickness of the first insulating film is about 300 nm to 600 nm. When the film thickness is small, a short circuit is likely to occur at the intersection of the gate wiring and the source wiring, and it is preferable that the thickness be about the thickness of the first metal thin film. When the film thickness is large, the ON current of the TFT becomes small and the display characteristics are deteriorated. As the semiconductor active film, an amorphous silicon (a-Si) film or a polysilicon (p-Si) film is used. The film thickness of the semiconductor active film is about 100 nm to 300 nm. When the film thickness is small, the film thickness is selected based on the controllability of the depth during dry etching of the ohmic contact film, which will be described later, and the required ON current of the TFT. When an a-Si film is used as the semiconductor active film, the interface between the gate insulating film and the aSi film is preferably a SiNx film or a SiOxNy film in terms of controllability and reliability of the Vth of the TFT. When a p-Si film is used as the semiconductor active film, the interface between the gate insulating film and the p-Si film is preferably a SiOx film or a SiOxNy film from the viewpoint of controllability and reliability of the Vth of the TFT. Further, when an a-Si film is used as the semiconductor active film, it is short to form a film near the interface with the gate insulating film under a condition with a low film formation rate and to form an upper layer part under a condition with a high film formation rate. It is more preferable that TFT characteristics with high mobility can be obtained in the film formation time and that the leakage current when the TFT is off can be reduced. As the ohmic contact film, an n ⁺ a-Si film or an n ⁺ p-Si film obtained by doping a-Si or p-Si with a small amount of phosphorus is used. The thickness of the ohmic contact film can be about 20 nm to 70 nm. These SiNx film, SiOx film, SiOxNy film, a-Si film, p-Si film, n ⁺ a-Si film, and n ⁺ p-Si film can be formed using a known gas.

Next, the semiconductor active film and the ohmic contact film are patterned in a second photolithography and etching process to form a semiconductor pattern 5 of the TFT portion. Etching of the semiconductor active film and the ohmic contact film is performed by dry etching with, for example, SF ₆ and oxygen gas. Next, a conductive thin film is formed by a method such as sputtering. As the conductive thin film, ITO, SnO ₂ or the like which is a transparent conductive film can be used when the electro-optic element is configured as a transmission type, and ITO is particularly preferable from the viewpoint of chemical stability. The thickness of the conductive thin film is about 50 nm to 200 nm. Next, the transparent conductive film is patterned in a third photolithography / etching process to form the pixel electrode 6. Etching of the transparent conductive film usually uses a mixed acid of hydrochloric acid and nitric acid, but an aqueous ferric chloride solution or the like can also be used. Next, the gate insulating film 4 is etched by the fourth photoengraving / etching step, and the gate terminal side collective lead wire connection portion 7a, the anti-gate terminal side collective lead wire connection portion 7b, and the gate wiring terminal connection of the auxiliary capacitance wiring group. And contact hole are formed in the source wiring terminal connection portion. The contact hole is formed by dry etching using a mixed gas of CF ₄ and oxygen or a mixed gas of SF ₆ and oxygen. Next, Cr is formed to a thickness of 400 nm, and the source wiring 8, the drain electrode 9, the gate terminal side collective lead line 10a and the anti-gate terminal side collective lead line 10b are patterned in a fifth photoengraving / etching step. Etching uses a mixed acid of perchloric acid and ceric ammonium nitrate. After these are patterned, the n ⁺ a-Si film or n ⁺ p-Si film in the TFT channel portion is removed. Next, a passivation film 11 is formed, and in the sixth photoengraving / etching step, the drive IC connection portions of the gate terminal and the source terminal are exposed by dry etching using CF ₄ and oxygen gas. In the above process, when the auxiliary capacitance wiring group is connected to the collective wiring as in the prior art, if the gate insulating film has a local defect during the pixel electrode etching, the etching solution is removed from the auxiliary capacitance wiring group. Corrosion of the auxiliary capacitance wiring group is generated. If the storage capacitor wiring group and the assembly wiring are formed separately from each other as described in claim 1, corrosion can be prevented even if there is a minute defect in the gate insulating film.

  In particular, when the auxiliary capacitance wiring group is formed of Al, an Al alloy, or at least a multilayer metal using them, this manufacturing method is particularly effective because it is easily corroded when the pixel electrode is etched.

Embodiment 2
FIG. 3 is a plan view of the collective lead wiring, the auxiliary capacitance wiring group, and the pixel region of the second embodiment, and FIG. 4 is a cross-sectional view taken along line BB in FIG. The manufacturing method of the embodiment of claim 1 will be described in detail below. In addition, what overlaps with Embodiment 1 by each film-forming, photoengraving, and an etching is abbreviate | omitted and described. A first metal thin film is formed by a method such as sputtering. As the first metal thin film, for example, a thin film having a thickness of about 100 nm to 300 nm made of an Al alloy such as Mo, AlZr, or AlNd can be used. For example, in the case of AlNd, the concentration of Nd is preferably about 1 to 3% by weight in order to reduce the wiring resistance and prevent the occurrence of hillocks. Further, as the first metal thin film, a metal thin film in which different metal thin films such as Cr / Al or Cr / AlSiCu are laminated, or a metal thin film having a different composition in the film thickness direction can be used. In the first photoengraving / etching process, the first metal thin film is patterned into the gate electrode and wiring 1, the auxiliary capacitance electrode 2, the auxiliary capacitance wiring group 3, and the gate wiring non-terminal side collective lead wiring 10b. At this time, each auxiliary capacitance line group 3 and the gate opposite terminal side collective lead line 10b are separated from each other. The film formation, photoengraving and etching processes at this time are the same as those in the first embodiment . Next, the first insulating film 4, the semiconductor active film, and the ohmic contact film are continuously formed by plasma CVD, and the semiconductor active film and the ohmic contact film are patterned into display pixels in the second photoengraving / etching process, and the TFT A part of the semiconductor pattern 5 is formed.

Next, a conductive thin film is formed by a method such as sputtering, and the transparent conductive film is patterned by a third photoengraving / etching process to form the pixel electrode 6. The film formation, photoengraving and etching processes at this time are the same as those in the first embodiment . Next, the gate insulating film 4 is etched by a fourth photoengraving / etching step, the gate terminal side collective lead wire connection portion 7a of the auxiliary capacitance wiring group, the anti-gate terminal side end portion 7b of the auxiliary capacitance wiring group, and the anti-gate. Contact holes are formed on the terminal-side collective lead wiring 7c, the gate wiring terminal connection portion, and the source wiring terminal connection portion. The photoengraving / etching process at this time is the same as in the first embodiment . Next, Cr is deposited to a thickness of 400 nm, and in the fifth photolithography / etching process, the source wiring 8, the drain electrode 9, the gate terminal side collective wiring 10a, the collective wiring 10b on the gate non-terminal side, and the auxiliary capacitance wiring group 3 The pattern 10c for connecting is patterned. The film formation, photoengraving and etching processes at this time are the same as those in the first embodiment . Next, a passivation film 11 is formed, and the driving IC connection portions of the gate terminal and the source terminal are exposed in the sixth photolithography and etching process. The film formation, photoengraving and etching processes at this time are the same as those in the first embodiment. In the above process, when the auxiliary capacitance wiring group is connected to the collective wiring as in the prior art, if the gate insulating film has a local defect during the pixel electrode etching, the etching solution is removed from the auxiliary capacitance wiring group. Corrosion of the auxiliary capacitance wiring group is generated. If the storage capacitor wiring group and the assembly wiring are formed separately from each other, corrosion can be prevented even if the gate insulating film has a minute defect. In the second embodiment, since the collective lead wiring is simultaneously formed on the side opposite to the gate terminal when the auxiliary capacitance wiring group is formed, the collective lead wiring 10b serves as an electrostatic shield against static electricity generated during the manufacture of the electro-optic element. Therefore, element destruction due to electrostatic breakdown during the manufacturing process can be prevented.

Embodiment 3
FIG. 5 shows a plan view of the collective lead-out wiring, the auxiliary capacitance wiring, and the pixel region according to the third embodiment. The manufacturing method of the third embodiment will be described in detail below.

  A first metal thin film is formed on the glass substrate by a method such as sputtering. As the first metal thin film, for example, a thin film having a thickness of about 100 nm to 500 nm made of an Al alloy such as Mo, AlZr, or AlNd can be used. For example, in the case of AlNd, the concentration of Nd is preferably about 1 to 3% by weight in order to reduce the wiring resistance and prevent the occurrence of hillocks. Further, as the first metal thin film, a metal thin film in which different metal thin films such as Cr / Al or Cr / AlSiCu are laminated, or a metal thin film having a different composition in the film thickness direction can be used.

Next, in the first photoengraving / etching step, the first metal thin film is applied to the gate electrode and wiring 1, the auxiliary capacitance electrode 2 and the auxiliary capacitance wiring group 3, the anti-gate terminal side collective lead line 10b, and the auxiliary capacitance wiring group 3 The protruding pattern 14 is patterned on the opposite portion of the anti-gate terminal side collective lead wire 10b. At this time, the storage capacitor wiring groups and the anti-gate terminal side collective lead wires 10b are separated from each other, and the protruding patterns 14 are arranged as close to each other as possible so that the patterns can be separated by photolithography. In mass production, the interval is preferably 3 μm to 4 μm. Next, the first insulating film 4, the semiconductor active film, and the ohmic contact film are continuously formed by plasma CVD, and the semiconductor active film and the ohmic contact film are patterned into display pixels in the second photoengraving / etching process, and the TFT A part of the semiconductor pattern 5 is formed. The film formation, photoengraving and etching processes at this time are the same as those in the first embodiment . Next, a conductive thin film is formed by a method such as sputtering, and the transparent conductive film is patterned by a third photoengraving / etching process to form the pixel electrode 6. The film formation, photoengraving and etching processes at this time are the same as those in the first embodiment. Next, the gate insulating film 4 is etched by a fourth photoengraving / etching step, and the gate terminal side collective lead wire connection part 7a, the auxiliary capacity line group anti-gate terminal side end part 7b, the anti-gate terminal of the auxiliary capacity line group Contact holes are formed on the side collective lead wiring 7c and the gate wiring terminal connection portion and the source wiring terminal connection portion. The photoengraving / etching process at this time is the same as in the first embodiment . Next, Cr is deposited to a thickness of 400 nm, and in the fifth photoengraving / etching step, the source wiring 8, the drain electrode 9, the gate terminal side collective wiring 10a, the anti-gate terminal side collective wiring 10b, and the auxiliary capacitance wiring group 3 The pattern 10c for connecting is patterned. The film formation, photoengraving and etching processes at this time are the same as those in the first embodiment . Next, a passivation film 11 is formed, and the driving IC connection portions of the gate terminal and the source terminal are exposed in the sixth photolithography and etching process. The film formation, photoengraving and etching processes at this time are the same as those in the first embodiment .

  In the above process, when the auxiliary capacitance wiring group is connected to the collective wiring as in the prior art, if the gate insulating film has a local defect during the pixel electrode etching, the etching solution is removed from the auxiliary capacitance wiring group. Corrosion of the auxiliary capacitance wiring group is generated. If the storage capacitor wiring group and the assembly wiring are formed separately from each other, corrosion can be prevented even if the gate insulating film has a minute defect. In the second embodiment, since the collective lead wiring is simultaneously formed on the gate opposite terminal side when the auxiliary capacitance wiring group is formed, the collective lead wiring 10b functions as an electrostatic shield against static electricity generated during the manufacture of the electro-optic element. Therefore, element destruction due to electrostatic breakdown during the manufacturing process can be prevented.

  In particular, in the third embodiment, even when static electricity enters the gate opposite terminal side collecting lead wiring from the outside, the electrostatic energy can be consumed by discharging between the protruding patterns 14, so that the anti gate terminal side collecting lead wiring 10b is discharged. Further, it is possible to prevent the auxiliary capacitance wiring group 3 from being damaged.

Embodiment 4
FIG. 6 is a plan view of the collective lead-out wiring, auxiliary capacitance wiring group, and pixel region of the fourth embodiment, and FIG. 7 is a cross-sectional view taken along the line CC in FIG. A first metal thin film is formed on the glass substrate by a method such as sputtering. As the first metal thin film, for example, a thin film having a thickness of about 100 nm to 500 nm made of an Al alloy such as Mo, AlZr, or AlNd can be used. For example, in the case of AlNd, the concentration of Nd is preferably about 1 to 3% by weight in order to lower the wiring resistance and prevent the occurrence of hillocks. Further, as the first metal thin film, a metal thin film in which different metal thin films such as Cr / Al or Cr / AlSiCu are laminated, or a metal thin film having a different composition in the film thickness direction can be used. Next, the gate electrode and wiring 1, the auxiliary capacitance electrode 2, and the auxiliary capacitance wiring group 3 are patterned with the first metal thin film in the first photoengraving / etching step. The film formation, photoengraving and etching processes at this time are the same as those in the first embodiment . Next, the first insulating film 4, the semiconductor active film, and the ohmic contact film are continuously formed by plasma CVD, and the semiconductor active film and the ohmic contact film are patterned into display pixels in the second photoengraving / etching process, and the TFT A part of the semiconductor pattern 5 is formed. The film formation, photoengraving and etching processes at this time are the same as those in the first embodiment .

Next, a conductive thin film is formed by a method such as sputtering, and the transparent conductive film is patterned by a third photoengraving / etching process to form the pixel electrode 6. The film formation, photoengraving and etching processes at this time are the same as those in the first embodiment . Next, the gate insulating film 4 is etched by a fourth photoengraving / etching step to form contact holes on the gate wiring connection portion and the source wiring terminal connection portion. The photoengraving / etching process at this time is the same as in the first embodiment . Next, Cr is deposited to a thickness of 400 nm, and the source wiring 8 and the drain electrode 9 are patterned in the fifth photolithography and etching process. The film formation, photoengraving and etching processes at this time are the same as those in the first embodiment . Next, a passivation film 11 is formed, and contact holes are formed in the gate terminal side auxiliary capacitance line group 12a and the anti-gate terminal side auxiliary capacitance line group 12b in the sixth photoengraving / etching step. The drive IC connection is exposed. The film formation, photoengraving and etching processes at this time are the same as those in the first embodiment . Thereafter, after transferring to the TFT array substrate and the counter substrate, a transfer material for supplying the counter substrate potential is applied on the TFT substrate to form transfer electrodes, and at the same time, contact holes 12a and 12b formed on the auxiliary capacitance wiring group are formed. A transfer material is formed so as to cover the gate terminal side collective lead wiring 13a and the anti-gate terminal side collective lead wiring 13b. The transfer material is usually a mixture of silver particles in an epoxy adhesive. Thereafter, a sealing material is formed on the counter substrate, the TFT substrate and the counter substrate are overlapped, and the both substrates are bonded together by thermosetting the sealing material. As a result, corrosion of the auxiliary capacitance line group during pixel electrode etching can be prevented, and at the same time, since the auxiliary capacitance line groups are separated from each other when the TFT array is completed, the auxiliary capacitance that cannot be detected by the conventional electrical defect inspection. Since the wiring groups are separated from each other, it is possible to detect the position of the short circuit between the auxiliary capacitance wiring group and the gate line and the short circuit between the auxiliary capacitance wiring group and the source line, which could not be detected by the conventional electrical defect inspection. It is also possible to repair the short by cutting the part with a laser.

It is a connection part top view of auxiliary capacity wiring and collective extraction wiring of Embodiment 1 of the present invention. It is the sectional view on the AA line in FIG. 1 of Embodiment 1 of this invention. It is a connection part top view of auxiliary capacity wiring and collective extraction wiring of Embodiment 2 of the present invention. It is BB sectional drawing in FIG. 3 of Embodiment 2 of this invention. It is a connection part top view of auxiliary capacity wiring and collective extraction wiring of Embodiment 3 of the present invention. It is a connection part top view of auxiliary capacity wiring and collective extraction wiring of Embodiment 4 of the present invention. It is CC sectional view taken on the line in FIG. 6 of Embodiment 4 of this invention. It is a connection part top view of auxiliary capacity wiring and collective extraction wiring in the prior art. It is the DD sectional view taken on the line in FIG. 8 in a prior art. It is a conceptual diagram of the TFT substrate provided with auxiliary capacity wiring.

Explanation of symbols

1 Gate wiring
2 Auxiliary capacitance electrodes
3 Auxiliary capacitance wiring group 3a, 10a, 10b,
13a, 13b Collective lead wiring
4 Gate insulation film
5 Semiconductor pattern
6 Pixel electrodes 7a, 7b, 7c,
12a, 12b Contact hole
8 Source wiring
9 Drain electrode
11 Protective insulating film
10c, 14 patterns
15 Opposite substrate conductive film
16 Counter substrate

Claims (5)

An electro-optic material is sandwiched between a pair of opposed substrates, a gate wiring formed on one substrate, and a first metal thin film formed in the same layer as the gate wiring and separated from each other. A plurality of auxiliary capacitance lines formed;
A plurality of auxiliary capacitor lines and a collective lead line separated from each other;
An insulating layer formed on the substrate so as to cover the plurality of auxiliary capacitance wires and the collective lead wires ;
A thin film transistor formed in an upper layer than the plurality of auxiliary capacitance lines ;
A pixel electrode made of a transparent conductive film electrically connected to the thin film transistor and provided on the insulating layer;
Electricity and a conductive pattern for electrically connecting the plurality in the capacitor wiring and the on set drawing wiring through a contact hole provided in the insulating layer and the plurality of storage capacitor lines and the set drawing wiring An optical element,
The conductive pattern is formed separately from the auxiliary capacitance wiring and the collective wiring,
The electro-optic element, wherein the first metal thin film is formed of Al, an Al alloy, a multilayer metal using at least one of them, or Mo. In the contact hole, the conductive pattern is stacked on the upper layer of the plurality of auxiliary capacitor wires and the upper layer of the collective lead wire to electrically connect the plurality of auxiliary capacitor wires and the collective lead wire. The electro-optic element according to claim 1, wherein the electro-optic element is connected. The Al alloy, an electro-optical device according to claim 1 or claim 2, characterized in that a AlNd or AlZr. The set drawing wiring The electro-optical device according to any one of claims 1 to 3, characterized in that it is formed in the counter-gate terminal side. Before formation of the contact hole provided in the front Kize' edge layer, an electro-optical device according to any one of claims 1 to 4, characterized in that wet etching is performed.

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