JP4715645B2 - Buffer memory - Google Patents

Description

  The present invention relates to a buffer memory in which variable length frame data is written and read.

There is a time division highway (HW) on the exchange system, and data is transmitted and received by being divided into a plurality of time slots on the HW.
First, transmission / reception of frame data will be described.
When the frame data of each channel is transmitted in the exchange system, the transmission is performed by using the time slot on the time division HW for each channel and dividing it according to the data size of the time slot. For example, 0 channel is used for time slot 0 and 1 channel is used for time slot 1.
On the receiving side, the data of the time slot corresponding to each channel can be received, written in the memory in order, and frame data can be assembled. For example, 0 channel data uses the 0 channel buffer receiving area, and 1 channel data uses the 1 channel buffer receiving area.
When the reception of the frame data is completed, it is read for the next processing.

When a plurality of channels are accommodated on the HW, the above reception processing needs to be performed in parallel for each channel.
At this time, the memory necessary for assembling the received frame data is the size Abyte of 1 frame data, assuming that the maximum size of the frame data to be handled is Abyte.
Further, since it is necessary to be able to receive the next frame data even during the reading process, at least one buffer for writing data is required during reading, and two or more buffer memories are required in total. .
In order to continuously receive frames for a plurality of channels, the total number of channels × Abyte × 2 or more is required.

For example, when receiving 0 channel and 1 channel, the configuration is as shown in FIG. The buffer memory includes a reception memory 301, a reception data write control unit 302, a reception data read control unit 303, a write pointer 304, and a read pointer 305. The reception memory 301 includes a 0-channel reception area and a 1-channel reception area. The 0-channel reception area includes a buffer 01 and a buffer 02, and the 1-channel reception area includes a buffer 11 and a buffer 12. Buffer 01, buffer 02, buffer 11 and buffer 12 each have an Abyte area.
The write pointer 304 has a 0-channel write pointer and a 1-channel write pointer, and the read pointer 305 has a 0-channel read pointer and a 1-channel read pointer.

The operation for the 0 channel will be described as an example, but the same operation is performed for the 1 channel. First, the write operation will be described. When data is received from the HW, the received data write control unit 302 writes data to the buffer 01 according to the 0 channel write pointer value, and increments the write pointer by one.
Similarly, until the last data of the frame is received, and the last data is received, the received data write control unit 302 writes data to the buffer 01 according to the write pointer value of the 0 channel, and sets the write pointer to the head of the buffer 02. Since reception of one frame is complete, reception data write control unit 302 notifies reception data read control unit 303 of completion of frame data writing.

When data is newly received from the HW, the received data write control unit 302 writes data to the buffer 02 in accordance with the 0 channel write pointer value, and increments the write pointer by one.
Similarly, when the final data is received until the final data of the frame is received, the received data write control unit 302 writes data to the buffer 02 in accordance with the write pointer value of the 0 channel, and sets the write pointer to the head of the buffer 01. Since reception of one frame is complete, the reception data write control unit 302 notifies the reception data read control unit 303 that frame data has been written.
The same is repeated thereafter.

Next, the reading operation will be described. When it is detected that the 0-channel frame data has been written, the received data read control unit 303 determines that there is a readable frame.
The received data read control unit 303 reads data from the buffer 01 in accordance with the read pointer value of the read channel, and increments the read pointer by one.
The reception data read control unit 303 repeats the operation of reading data and incrementing the read pointer by 1 until reading of one frame is completed.
When the data reading for one frame is completed, the reception data read control unit 303 notifies the reception data write control unit 302 of the completion of frame data reading.
Thereafter, the reception data read control unit 303 performs the same read processing as the buffer 02 and buffer 01 each time a frame data write completion notification is received.
The above operation is performed every time data of a channel for processing is received.

If the frame data in the buffer 01 is not read when the frame data has been written to the buffer 02, it is necessary to prepare the buffer 03 in order to receive the next frame.
For example, when the frame data in the buffer 01 is long and the reading process takes time, and the subsequent frame data is short and one frame is received in a short time, the frame data is no longer stored in the buffer 02. Can not be received, so it is possible to write the next data.
If the same condition can occur even if the buffer 03 is prepared, it is necessary to further increase the number of buffers such as 04 and 05.

Further, as in Patent Document 1 below, a patent has been filed relating to a data transmission apparatus that can prevent packet overrun and reliably transmit packet data even if the memory capacity of the reception buffer is minimized.
JP 2002-271424 A

However, in the conventional buffer memory configuration, assuming that the maximum size of the frame data to be handled is A bytes, the buffer memory size per side requires A bytes, and the smaller the minimum size that the frame data can take, the smaller the per-time time. Since the number of received frames increases, a large number of memory planes are required to receive all.
From the above, there is a problem that the number of buffer memories for each channel increases in order not to miss the received frame.

In order to solve such a problem, a first buffer memory according to the present invention is a buffer memory in which variable length frame data is written and read, and has a size larger than the maximum size of received frame data for each channel. A write control unit that controls writing of received frame data, a read control unit that controls reading of written frame data, and a memory that stores the number of frame data written for each channel A memory that stores the number of frame data read for each channel, a write pointer that stores the write position of the buffer memory for each channel, a read pointer that stores the read position of the buffer memory for each channel, and a channel The number of frame data written to the Offering a comparator for comparing the data number, when written data number read frame data number is different, and wherein the reading the frame data.

In addition, the second buffer memory according to the present invention has a configuration in which, in the first buffer memory, when there are a plurality of channels in which the number of written frame data is larger than the number of read frame data as a result of comparison by the comparison unit, Reading is performed from a channel having a large difference in results .

Furthermore, a third buffer memory according to the present invention is characterized in that, in the first or second buffer memory, the comparison unit is provided in the read control unit .

As an effect of the invention, according to the buffer memory of the present invention, while having a buffer memory of a plurality of channels in one memory, the number of buffer planes according to the number of received frames is not required, and the buffer size according to the total size of the received frames is not required. Because it can be managed, the memory usage efficiency increases even when the frame data size is small. As a result, the total buffer memory capacity can be reduced.
The number of frames accumulated in the buffer can be known from the number of write frames and the number of read frames.
Further, the number of frames accumulated in the buffer can be compared for each channel, and priority can be given to reading from the buffer.

In a buffer memory where variable length frame data is written and read, each channel has one surface with a size larger than the maximum size of the received frame data, and the size larger than the maximum size of the frame data is The total size of the maximum size of frame data and the size at which new frame data can be received while reading out received frame data, and a write control unit that controls writing of received frame data Read control unit for controlling reading of frame data, memory for storing the number of frame data written for each channel, memory for storing the number of frame data read for each channel, and writing to buffer memory for each channel Write pointer to save position and back for each channel A read pointer that stores the read position of the memory, and a comparison unit that compares the number of frame data written for each channel with the number of read frame data, and the number of written data If it is different from the above, the frame data is read out.

Hereinafter, a buffer memory according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a diagram showing a configuration of a buffer memory according to the present invention. FIG. 2 is a diagram showing the operation of the buffer memory of the present invention.

First, the configuration of the buffer memory will be described with reference to FIG.
The buffer memory includes a reception memory 101, a reception data write control unit 102, a reception data read control unit 103, a write pointer 104, a read pointer 105, a write frame number storage unit 106, a read frame number storage unit 107, and a comparison unit 108. Composed.

Assuming that the maximum size of the frame data to be handled is A bytes, the reception memory 101 is provided with A + α bytes of buffer memory for each channel. As shown in FIG. 1, the reception memory 101 has a buffer for each channel such as an A + αbyte 0 channel reception area and a 1 channel reception area. α is a size at which the data from the HW can be sufficiently received while the received frame data is read for the next processing, and the size is determined by the reading and writing processing speed. Since the processing on the reading side is faster than the processing on the normal writing side, α is smaller than A. This is because if the processing on the reading side is slower than the processing on the writing side, data overflows from the buffer memory.

The reception data write control unit 102 performs write control of reception data in the reception memory 101 by the write pointer 104 according to the write pointer value of the write channel.
The reception data read control unit 103 performs data read control from the reception memory 101 according to the read pointer value of the read channel by the read pointer 105.

The write pointer 104 stores the write position of the buffer memory for each channel, and is configured for each channel such as a 0-channel write pointer and a 1-channel write pointer.
The read pointer 105 stores the read position of the buffer memory for each channel, and is configured for each channel such as a 0-channel read pointer and a 1-channel read pointer.

The write frame number storage unit 106 is a memory for storing the number of write frames of received data for each channel. The number of write frames for each channel such as the number of write frames for 0 channel and the number of write frames for 1 channel. The number is saved.
The read frame number storage unit 107 is a memory that stores the number of read frames of received data for each channel, and stores the number of read frames for each channel such as the number of read frames for 0 channel and the number of read frames for 1 channel. .

  The comparison unit 108 receives information of the number of frame data written for each channel and the number of read frame data from the write frame number storage unit 106 and the read frame number storage unit 107, compares them, and writes them. When the number of received frame data is larger than the number of read frame data, the received data read control unit 103 is caused to read the frame data. Further, since there is an upper limit on the counter value of the number of frames, simply subtracting the number of read frame data from the number of written frame data may result in a negative value. Therefore, the comparison unit 108 may read frame data when the number of written frame data is different from the number of read frame data.

Next, the operation of the buffer memory of the present invention will be described with reference to FIG. The following operation is performed every time data of a channel to be processed is received. First, the operation on the writing side will be described.
When data is received from the HW, the reception data write control unit 102 writes the reception data in the reception area of the corresponding buffer of the reception memory 101 according to the write pointer value of each corresponding channel, and increments the write pointer by 1 (S201). ).
Similarly, until the final data of the frame is received, and the final data is received, the received data write control unit 102 writes data to the buffer memory according to the write pointer value of each corresponding channel, and increments the write pointer by one. Since reception of reception frame 1 is completed, the write frame number storage unit 106 increments the number of write frames of the corresponding channel by 1 (S202).

When new data is received from the HW, the received data write control unit 102 writes the data after the received frame 1 in the receiving area of the corresponding buffer of the receiving memory 101 in accordance with the write pointer value of each corresponding channel. The pointer is incremented by 1 (S203).
Similarly, until the final data of the frame is received, when the final data is received, the received data is written to the buffer memory according to the write pointer value of each corresponding channel, and the write pointer is incremented by one. Further, since reception of the reception frame 2 is completed, the number of write frames is incremented by 1 (S204).

Thereafter, the same processing is performed, and new reception data is written into the reception area of the corresponding buffer of the reception memory 101 after the reception frame 2 (S205). When the final data is received, the received data is written to the buffer memory according to the write pointer value of each corresponding channel, the write pointer is incremented by 1, the write of the received frame 3 is completed, and the number of write frames is incremented by 1 (S206). ). However, when the write pointer value reaches the end of the reception area of each channel in the reception memory 101, the write pointer value is set to zero.

Next, the operation on the reading side will be described. The comparison unit 108 compares the number of write frames and the number of read frames of each channel, and determines that there is a readable frame in the buffer of the corresponding channel if there is a channel where “the number of write frames> the number of read frames”. The received data read control unit 103 reads data from the buffer memory 101 according to the read pointer value of the corresponding read channel, and increments the read pointer by 1 (S207).
The reception data read control unit 103 repeats the operation of reading data and incrementing the read pointer by one until the reading of one frame of the reception frame 1 is completed.

  When the data reading for one frame of the received frame 1 is completed, the read frame number storage unit 107 increments the read frame number of the corresponding channel by 1 (S208). Next, the received frame reading control unit 103 reads the data of the received frame 2 from the buffer (S209). When the data reading for one frame of the received frame 2 is completed, the read frame number storage unit 107 increments the number of read frames by 1 (S210).

Further, the comparison unit 108 compares the number of frames stored in the buffer for each channel when reading the received frame from the buffer as “number of write frames−number of read frames”, and as a result of comparison, “number of write frames−read frame” Reading may be performed preferentially from channels having a large difference in “number”.

In this embodiment, the number of channels is two. However, the reception memory 101, the write pointer 104, the write frame number storage unit 106, the read pointer 105, and the read frame number storage unit 107 are matched to the required number of channels. It is possible to cope with multiple channels by preparing the memory.
In the embodiment, frame data reception by time division HW has been described. However, reception by other interfaces, for example, frame data reception by Ethernet (registered trademark) can be handled in the same manner.

The figure which shows the structure of the buffer memory of this invention The figure which shows operation | movement of the buffer memory of this invention The figure which shows the structure of the conventional buffer memory

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Reception memory, 102 ... Reception data write control part, 103 ... Reception data read control part, 104 ... Write pointer, 105 ... Read pointer, 106 ... Write frame number storage part, 107 ... Read frame number storage part, 108 ... Comparison part

Claims (3)

In buffer memory where variable length frame data is written and read,
Each channel is provided with one surface having a size larger than the maximum size of the received frame data.
A write control unit that controls writing of received frame data;
A read control unit for controlling reading of the written frame data;
A memory for storing the number of frame data written for each channel;
A memory for storing the number of frame data read for each channel;
A write pointer that stores the buffer memory write position for each channel,
A read pointer for storing the read position of the buffer memory for each channel;
A comparison unit for comparing the number of frame data written for each channel and the number of read frame data is provided.
A buffer memory , wherein frame data is read when the number of written data is different from the number of read frame data . 2. As a result of comparison by the comparison unit, when there are a plurality of channels in which the number of written frame data is larger than the number of read frame data, reading is performed from a channel having a large difference as a result. The buffer memory according to 1. The buffer memory according to claim 1, wherein the comparison unit is provided in the read control unit .

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