JP4710660B2 - Solid-state imaging device and electronic camera using the same - Google Patents

Description

  The present invention relates to a solid-state imaging device that outputs a focus detection signal and an electronic camera using the same.

In recent years, video cameras and electronic still cameras have been widely used. For these cameras, CCD type or amplification type solid-state imaging devices are used. In the solid-state imaging device, a plurality of pixels are arranged two-dimensionally, and a charge corresponding to incident light is generated and accumulated in a photoelectric conversion unit arranged in each pixel.
The amplification type solid-state imaging device guides signal charges generated and accumulated in the photoelectric conversion unit of the pixel to a pixel amplifier unit provided in the pixel, and outputs an electrical signal corresponding to the signal charge from the pixel. As the amplification type solid-state imaging device, a solid-state imaging device using a junction field effect transistor in the pixel amplifier unit (Patent Document 1), a CMOS type solid-state imaging device using a MOS transistor in the pixel amplifier unit, etc. are proposed. Has been.

  In the conventional solid-state imaging device disclosed in Patent Document 1-2, a photoelectric conversion unit and a pixel amplifier unit are provided for each pixel, and a charge storage unit that temporarily accumulates charges between them. Yes. In such a conventional solid-state imaging device, after all the pixels are exposed at the same time, the generated signal charges are transferred from the photoelectric conversion unit to the charge storage unit and accumulated all at the same time. Then, the floating diffusion region or the control electrode is reset for each row, a correlated double sampling process is performed, and a signal is output. As described above, the solid-state imaging device disclosed in Patent Document 1-2 enables simultaneous exposure of all pixels subjected to correlated double sampling.

On the other hand, a pupil division phase difference method is known as one of focus detection techniques. The pupil division phase difference method detects the defocus amount of the photographing lens by forming a pair of divided images by dividing the light beam passing through the photographing lens into pupils and detecting the pattern shift.
And the proposal which applied the pupil division | segmentation phase difference system to the solid-state image sensor is made | formed. For example, Patent Document 3 proposes a solid-state imaging device having pixels that generate image signals and pixels that generate signals for focus detection. The focus detection pixel has two photoelectric conversion units. Further, the focus detection pixels are provided so as not to be adjacently arranged. When obtaining a focus detection signal, the signal of one of the two photoelectric conversion units is output from the output unit of the pixel, and the signal of the other photoelectric conversion unit is transmitted to the adjacent image signal pixel. Read simultaneously from the output section. Thus, the solid-state imaging device described in Patent Document 3 can make the exposure time and timing in the two photoelectric conversion units of the focus detection pixel the same.
JP-A-11-177076 JP 2004-111590 A JP 2003-244712 A

  However, in the solid-state imaging device proposed in Patent Document 3, although the exposure timing is the same in the same row, the exposure timing of the focus detection signal is different between different rows. That is, there was no synchronism of exposure timing in focus detection of effective pixels.

  For this reason, there has been a problem that the position of the focus varies in one frame. In particular, a significant problem has arisen when shooting a fast-moving subject or when shooting a still image. Therefore, in a solid-state imaging device that adopts the pupil division phase difference method, an in-focus image may be obtained even when the all-pixel simultaneous electronic shutter is operated as described in Patent Document 1-2. .

  The present invention has been made in view of such a problem, and provides a solid-state imaging device in which simultaneity of exposure timing in focus detection in one frame is ensured.

Since the solid-state image sensor of Patent Document 3 can simultaneously output signals from two photoelectric conversion units arranged in each pixel, the exposure time and the timing thereof can be made the same between pixels connected to the same row. it can. However, the exposure timing is shifted between different lines because of the so-called rolling shutter. For this reason, the focus detection timing is shifted between different rows.

  Therefore, the solid-state imaging device according to the first aspect of the present invention includes a plurality of pixels arranged two-dimensionally, and a peripheral circuit for driving the pixels and outputting signals from the pixels to the outside, At least some of the pixels are arranged corresponding to (1) a plurality of photoelectric conversion units that generate and store charges according to incident light, and (2) each of the photoelectric conversion units. A plurality of charge storage units that receive and accumulate from the photoelectric conversion units; (3) a floating diffusion region that receives and accumulates the charges from the plurality of charge storage units; and (4) corresponding to each of the plurality of photoelectric conversion units. A first transfer unit that transfers the charge to the charge storage unit; (5) a second transfer unit that transfers the charge from the plurality of charge storage units to the floating diffusion region; and (6) the plurality of the transfer units. The incident light is guided to the photoelectric conversion unit of And a microlens.

  Incident light is converted into signal charges by a plurality of photoelectric conversion units arranged in the pixel. Those signal charges are independently transferred and accumulated in the charge storage units corresponding to the respective photoelectric conversion units. With this configuration, it is possible to perform simultaneous exposure of all pixels while performing correlated double sampling processing for each row. Furthermore, this signal charge can be used as a focus detection signal. Therefore, the synchronism at the exposure timing of the focus detection signal of one frame is ensured. Therefore, it is possible to correctly focus even when shooting a fast-moving subject or when shooting a still image.

  The solid-state imaging device according to a second aspect of the present invention is the solid-state imaging device according to the first aspect, wherein the at least part of the pixels further includes (7) a signal corresponding to the amount of the charge accumulated in the floating diffusion region. A pixel amplifier unit that outputs, (8) a first reset unit that resets charges accumulated in the floating diffusion region, and (9) a pixel that reads a signal and selects the pixel amplifier unit of the selected pixel And a selection switch for outputting a signal from.

  In the solid-state imaging device according to the third aspect of the present invention, in the second aspect, one of the pixel amplifier unit, the first reset unit, and the selection switch is arranged for a plurality of pixels. It is characterized by that. With this configuration, the pixel amplifier unit, the first reset unit, and the selection switch can be shared by a plurality of pixels and can be further miniaturized.

  In the solid-state imaging device according to the fourth aspect of the present invention, in any one of the first to third aspects, the first transfer units arranged in the same pixel are simultaneously driven by the peripheral circuit and are the same. The second transfer unit disposed in each pixel is individually driven by the peripheral circuit.

The solid-state imaging device according to the fifth aspect of the present invention is characterized in that, in any of the first to fourth aspects, the at least some of the pixels include two photoelectric conversion units.
The solid-state imaging device according to a sixth aspect of the present invention is characterized in that, in any of the first to fourth aspects, the at least some of the pixels include three photoelectric conversion units.

  The solid-state imaging device according to a seventh aspect of the present invention is the solid-state imaging device according to any one of the first to sixth aspects, wherein the at least some pixels are two-dimensionally arranged and output a focus detection signal, and the focus An image signal is output at a timing different from that of the detection signal. With this configuration, at least some pixels output not only a focus detection signal for detecting the focus but also an image signal for obtaining an image at a different timing, so that correction such as interpolation is performed when the image signal is generated. There is no need to do.

  According to an eighth aspect of the present invention, in the first to seventh aspects, the solid-state imaging device includes a second reset unit that resets the charge accumulated in the photoelectric conversion unit. It is characterized by that. With this configuration, the photoelectric conversion unit can be easily reset.

  According to a ninth aspect of the present invention, in the first to seventh aspects, the solid-state imaging device is configured such that the charge storage unit is disposed between the photoelectric conversion unit and the floating diffusion region, and the first transfer unit is A gate electrode disposed between the photoelectric conversion unit and the charge storage unit; and the second transfer unit includes a gate electrode disposed between the charge storage unit and the floating diffusion region; The direction in which the photoelectric conversion unit and the charge storage unit are arranged is the same as the direction in which the charge storage unit and the floating diffusion region are arranged. With this configuration, the photoelectric conversion unit, the charge storage unit, and the floating diffusion region are arranged in the same direction, which facilitates manufacturing.

  Furthermore, an electronic camera according to a tenth aspect of the present invention acquires the focus detection signal from the solid-state image sensor according to any one of the first to ninth aspects and the solid-state image sensor, and A focus calculation unit that detects a pattern shift of the pupil-divided image extracted from this signal and performs focus detection, and an imaging control unit that reads out the image signal from the solid-state imaging device.

  According to the present invention, the synchronism of exposure timing in focus detection in one frame is ensured. Thereby, a fast subject can be reliably imaged.

Hereinafter, a solid-state imaging device and an electronic camera according to the present invention will be described with reference to the drawings.
[First Embodiment]
(Configuration of electronic camera)
FIG. 1 is a block diagram showing an electronic camera 1 according to the first embodiment of the present invention. A photographing lens 2 is attached to the electronic camera 1. The photographing lens 2 is driven at its focal point and stop by the lens control unit 2a. In the image space of the photographic lens 2, the imaging surface of the solid-state imaging device 3 is arranged.
The solid-state imaging device 3 is driven by a command from the imaging control unit 4 and outputs a signal. The signal output from the solid-state imaging device 3 is either an image signal or a focus detection signal. In any case, the signal is processed through the signal processing unit 5 and the A / D conversion unit 6 and then temporarily stored in the memory 7. The memory 7 is connected to the bus 8. The bus 8 is also connected with a lens control unit 2a, an imaging control unit 4, a microprocessor 9, a focus calculation unit 10, a recording unit 11, an image compression unit 12, an image processing unit 13, and the like. The microprocessor 9 is connected to an operation unit 9a such as a release button. A recording medium 11a is detachably attached to the recording unit 11 described above.

The microprocessor 9 in the electronic camera 1 drives the imaging control unit 4 in synchronization with the half-press operation of the release button. The imaging control unit 4 reads out a focus detection signal from the pixels arranged in the solid-state imaging device 3 and accumulates it in the memory 7.
Here, as described later, all the effective pixels generate a focus detection signal. Further, all the effective pixels generate an image signal at a timing different from that of the focus detection signal. However, the present invention is not limited to this, and the pixels that generate the focus detection signal may be at least some of the pixels arranged in the solid-state imaging device 3. In this case, the other pixels output image signals.

When a focus detection signal is output from the solid-state imaging device 3 according to a command from the imaging control unit 4 and accumulated in the memory 7, the focus calculation unit 10 performs a focus detection calculation process using this signal, and the defocus amount Is calculated.
By the way, as will be described later, the solid-state imaging device 3 of this embodiment has two photoelectric conversion units in a pixel that outputs a focus detection signal. A common microlens is disposed on the two photoelectric conversion units. The focus detection signals output from the two photoelectric conversion units form a pair (one set), and the defocus amount is calculated as follows by using this set of focus detection signals.

  The light beam emitted from one point of the focused subject passes through different positions of the exit pupil of the photographic lens 2 and then converges again to form a point image on the imaging surface. For this reason, in the in-focus state, the two photoelectric conversion units receive the pupil-divided light beam emitted from the same point on the subject. Therefore, a set of pupil divided images obtained by each photoelectric conversion has substantially the same image pattern, and the phase difference is substantially zero.

  On the other hand, the luminous flux emitted from the subject in the front pin state passes through different portions of the exit pupil of the photographic lens 2 and then intersects in front of the imaging surface to deviate from the in-focus position and reach the pixel position. In this case, the pair of pupil division images shows a phase difference shifted in the pupil division direction. On the other hand, the light beam emitted from the subject image in the rear pin state passes through different portions of the exit pupil of the photographing lens 2 and then defocuss and reaches the pixel position with insufficient focusing. In this case, a set of pupil-divided images shows a phase difference shifted in the opposite direction to the front pin state.

  As described above, the phase difference of the pupil-divided image changes according to the focusing state of the taking lens 2. Therefore, the focus calculation unit 10 distributes the focus detection signal in the memory 7 to obtain an image pattern of a set of pupil division images. The focus calculation unit 10 performs a pattern matching process on these image patterns to detect a phase difference (image shift). Then, the focus calculation unit 10 detects the defocus amount of the photographing lens 2 based on this phase difference.

  The defocus amount detected by the focus calculation unit 10 is transmitted to the lens control unit 2a. The lens control unit 2a drives the photographing lens 2 based on the defocus amount to focus the photographing lens 2 on the subject. Thereafter, the microprocessor 9 in the electronic camera 1 starts an image signal reading operation using the imaging control unit 4 in synchronism with the full pressing operation of the release button.

  The imaging control unit 4 reads out image signals from the pixels and stores them in the memory 7. Thereafter, the microprocessor 9 performs a desired process in the image processing unit 13 or the image compression unit 12 as necessary based on a command from the operation unit 9a, and outputs a processed signal to the recording unit to the recording medium 11a. Record.

(Overall configuration of solid-state image sensor)
FIG. 2 is a circuit diagram illustrating a schematic configuration of the solid-state imaging device 3 according to the present embodiment. The solid-state imaging device 3 includes a plurality of pixels 20 arranged in a matrix and a peripheral circuit for outputting a signal from the pixels 20. In the figure, the number of pixels indicates 16 pixels of 4 rows horizontally and 4 rows vertically. However, it is not limited to this. In addition, although the code | symbol 20 of a broken line part shows the schematic part of a pixel, the specific circuit structure and structure are mentioned later.
In the present embodiment, the pixels 20 have the same circuit configuration and planar structure except for pixels that do not perform photoelectric conversion for an image such as dummy or optical black (that is, in a so-called effective pixel region). . These pixels 20 output either an image signal or a focus detection signal in accordance with a peripheral circuit drive signal. In all the pixels 20, the photoelectric conversion unit is reset at the same time so that the exposure time and timing can be made the same.

The peripheral circuit includes a vertical scanning circuit 21, a horizontal scanning circuit 22, driving signal lines 23 and 24 connected thereto, a vertical signal line 25 for receiving a signal from a pixel, and a constant current source 26 connected to the vertical signal line 25. And a correlated double sampling circuit (CDS) 27, a horizontal signal line 28 for receiving a signal output from the correlated double sampling circuit 27, an output amplifier 29, and the like.
The vertical scanning circuit 21 and the horizontal scanning circuit 22 output drive signals based on a command from the imaging control unit 4 of the electronic camera 1. Each pixel 20 is driven by receiving a drive signal output from the vertical scanning circuit 21 from a predetermined drive signal line 23, and outputs an image signal or a focus detection signal to the vertical signal line 25. There are a plurality of drive signals output from the vertical scanning circuit 21, and accordingly, a plurality of drive wirings 23. These will be described later.
The signal output from the pixel is subjected to predetermined noise removal by the correlated double sampling circuit 27. Then, a signal is output to the outside through the horizontal signal line 28 and the output amplifier 29 by the drive signal of the horizontal scanning circuit 22.

(Pixel configuration)
FIG. 3 is a pixel circuit diagram of the solid-state imaging device 3 according to the present embodiment. The pixel 20 includes two embedded photodiodes 51 and 52 as photoelectric conversion units that generate and store charges according to incident light, and two charges that independently store charges transferred from the embedded photodiodes 51 and 52, respectively. The charge storage units 61 and 62, the first transfer units 63 and 64 that transfer charges from the embedded photodiodes 51 and 52 to the corresponding charge storage units 61 and 62, and the charge storage units 61 and 62, respectively. Floating diffusion region (FD) 67 that accumulates charges individually or simultaneously, second transfer units 65 and 66 that transfer charges individually or simultaneously from charge storage units 61 and 62 to FD 67, and FD 67 An amplification transistor 48 as a pixel amplifier unit that outputs a signal corresponding to the amount of charge, and an F as a first reset unit that discharges the charge of the FD 67 A reset unit 49, a selection switch 50 that outputs the signal of the amplification transistor 48 from the pixel, and a second reset that discharges unnecessary charges that are generated by the embedded photodiodes 51 and 52 from the embedded photodiodes 51 and 52. It has a PD reset unit 68 as a unit.

As shown in FIG. 3, two embedded photodiodes 51 and 52 are arranged in each pixel 20. One microlens is disposed on the upper surface of the embedded photodiodes 51 and 52. Thereby, the pupil-divided incident light is guided to the embedded photodiodes 51 and 52. Accordingly, each of the embedded photodiodes 51 and 52 can generate a focus detection signal. On the other hand, if the signal is output by adding the photoelectric charges of the two embedded photodiodes 51 and 52, the solid-state imaging device 3 can obtain an image signal.
In addition, charge storage portions 61 and 62 are arranged corresponding to the respective embedded photodiodes 51 and 52. The charge storage units 61 and 62 temporarily store charges by transferring charges from the corresponding embedded photodiodes 51 and 52. This makes it possible to make the exposure time and the timing of all the pixels the same while performing the correlated double sampling process.

  If the photoelectric charges generated by the embedded photodiodes 51 and 52 are used as a focus detection signal, the focus detection exposure time and timing are made the same for all pixels while performing correlated double sampling processing. Is possible. Therefore, it is possible to correctly focus even when shooting a fast-moving subject or when shooting a still image. Further, when the photocharge generated by the embedded photodiodes 51 and 52 is used as an image signal, the exposure time and timing of the image signals of all the pixels can be made the same while performing correlated double sampling processing. It becomes possible.

One first transfer unit 63 transfers the charge stored in one embedded photodiode 51 to one charge storage unit 61. The other first transfer unit 64 transfers the charge stored in the other embedded photodiode 52 to the other charge storage unit 62.
The first transfer units 63 and 64 are configured as gate portions of MOS transistors as described later. The gate electrodes of the two first transfer units in the pixel are connected in common, and the drive signal φTGA is supplied from the vertical scanning circuit 21 via the drive wiring 23. The two first transfer units 63 and 64 are simultaneously turned on at a predetermined timing in accordance with the drive signal φTGA, and charges are transferred from the two embedded photodiodes 51 and 52 to the respective charge storage units 61 and 62 at the same time. . However, each gate electrode may be individually supplied with the drive signal φTGA as long as it is turned on at the same time.

  Similarly to the first transfer unit, the second transfer units 65 and 66 are gate portions of MOS transistors. However, individual drive signals are supplied to the gate electrodes of the two second transfer units 65 and 66, respectively. That is, the gate signal of one second transfer unit 65 is supplied with the drive signal φTGB from the vertical scanning circuit 21 via the drive wiring 23, and the gate electrode of the other second transfer unit 66 is driven from the vertical scanning circuit 21. A drive signal φTGC is supplied through the wiring 23. The two second transfer units 65 and 66 are individually turned on at a predetermined timing according to these drive signals, and the charges from the two charge storage units 61 and 62 are individually timingd or at the same timing. Transfer to FD67.

The selection switch 50 is configured as a gate portion of a MOS transistor. The gate electrode is supplied with a drive signal φS from the vertical scanning circuit 21 via the drive wiring 23. The FD reset unit 49 is configured as a gate unit of a MOS transistor. The gate electrode is supplied with a drive signal φFDR from the vertical scanning circuit 21 via the drive wiring 23. The PD reset unit 68 is also configured as a gate unit of a MOS transistor, and the gate electrode is supplied with a drive signal φPDR from the vertical scanning circuit 21 through the drive wiring 23.
In the present embodiment, the effective pixels are all pixels having the same structure, and these pixels can output a focus detection signal and an image signal at different timings. However, the present invention is not limited to this, and the solid-state imaging device 3 is provided with a focus detection area in a predetermined portion, and pixels having the circuit of FIG. 2 are arranged in this area to generate a focus detection signal, and in other areas. A pixel having one photoelectric conversion unit may be arranged to generate an image signal.
In FIG. 3, one terminal of the embedded photodiodes 51 and 52, one terminal of the charge storage units 61 and 62, and one terminal of the FD 67 are grounded. However, the present invention is not limited to this, and a predetermined voltage is applied (in reality, these potentials become the potential of the P-type well 32 as understood from FIGS. 5 and 6 below).

  FIG. 4 is a pixel plan view of the solid-state imaging device according to the present embodiment. FIG. 5 is a cross-sectional view taken along the line A-A ′ in FIG. 4. However, the microlens is omitted in FIG. 6 is a cross-sectional view taken along the line B-B ′ in FIG. 4. 4 to 6, the drive wiring is omitted, and only the electrical connection relationship in the pixel is shown.

  As shown in FIGS. 5 and 6, a P-type well 32 is provided on an N-type silicon substrate 31. Then, an N-type charge accumulation layer 55 is formed in the P-type well 32, and a P-type depletion prevention layer 56 is provided on the substrate surface side of the charge accumulation layer 55, thereby forming embedded photodiodes 51 and 52. ing. Here, although the structure of the embedded photodiode is used, the present invention is not limited to this, and a photodiode in which the depletion prevention layer 56 is omitted may be used.

  Each pixel 20 has two embedded photodiodes 51 and 52. One microlens 57 that guides incident light to the embedded photodiodes 51 and 52 is disposed. The two embedded photodiodes 51 and 52 are arranged so as to be line-symmetric with respect to the center line XX ′ (line having a diameter) of the microlens 57 when viewed from the incident light side. Therefore, the incident light guided from the microlens 57 is divided into pupils and is incident on the embedded photodiodes 51 and 52.

  Between the charge storage units 61 and 62 and the embedded photodiodes 51 and 52, the gate electrodes 35 of the first transfer units 63 and 64 are arranged via a thin silicon oxide film 33. A MOS transistor is configured with the gate electrode 35 as a gate and the charge storage portions 61 and 62 and the charge storage layer 55 of the embedded photodiodes 51 and 52 as a source or drain.

  The gate electrode of one first transfer unit 63 and the gate electrode of the other first transfer transistor 64 are integrally formed and are electrically connected to each other. For this reason, the two first transfer units 63 and 64 are simultaneously turned on and off in accordance with the drive signal φTGA. Therefore, the respective charges accumulated in the two embedded photodiodes 51 and 52 are simultaneously transferred to the corresponding charge storage units 61 and 62 when the drive signal φTGA becomes high.

The charge storage portions 61 and 62 have N-type diffusion layers 75 and 76 formed in the P-type well 32. The gate electrodes 35 of the first transfer units 63 and 64 are disposed so as to cover the upper portions of the two N-type diffusion layers 75 and 76. The charge storage portions 61 and 62 are configured as MOS capacitors including the gate electrode 35 and the N-type diffusion layers 75 and 76 as described above.
With this configuration, when a low voltage is applied to the gate electrode 35, it is pinned to the potential of the P-type well 32, and the interface states on the surfaces of the charge storage portions 61 and 62 are filled with holes. The magnitude of the dark current is greatly influenced by the electron occupation probability of the interface state. Therefore, the dark current in the charge storage portions 61 and 62 can be significantly reduced by applying the voltage as described above to the gate electrode 35 to fill the interface state with holes. Further, since the N-type diffusion layers 75 and 76 are shielded by the gate electrode 35, noise due to unnecessary light is reduced. However, the present invention is not limited to this, and the gate electrode 35 may be disposed only between the embedded photodiodes 51 and 52 and the N-type diffusion layers 75 and 76.

  The FD 67 has two N-type diffusion layers 36 and 41 formed in the P-type well 32 so as to be separated from each other, and the N-type diffusion layers 36 and 41 are electrically connected by the wiring 40 to substantially form the FD 67. Are configured as one floating diffusion. The FD 67 transfers charges from either of the two charge storage units 61 and 62.

  A gate electrode 37 of the second transfer unit 65 is formed between the one charge storage unit 61 and the N-type diffusion layer 36 of the FD 67 through a thin silicon oxide film 33. A gate electrode 38 of the second transfer unit 66 is formed between the other charge storage unit 62 and the N-type diffusion layer 36 of the FD 67 with a thin silicon oxide film 33 interposed therebetween. A MOS transistor is configured with the gate electrodes 37 and 38 as gates and the charge storage portions 61 and 62 and the N-type diffusion layer 36 as sources or drains.

  The gate electrode 37 of one second transfer unit 65 and the gate electrode 38 of the other second transfer unit 66 are individually formed, and individual drive signals φTGB and φTGC are supplied from the vertical scanning circuit 21, respectively. Therefore, each of the second transfer units 65 and 66 is individually driven according to the respective drive signals φTGB and φTGC. Therefore, the two second transfer units 65 and 66 can be turned on at different timings or can be turned on at the same time. If they are turned on at different timings, the photocharges accumulated in the two charge storage units 61 and 62 are individually transferred to the FD 67 at different timings. Further, if these are simultaneously turned on, the photocharges accumulated in the two charge storage units 61 and 62 are added together in the FD 67.

  In the P-type well 32, N-type diffusion layers 41, 42, 43, 44, 71 are formed. The N-type diffusion layers 42 and 71 are connected to the power supply VDD by wiring not shown. A gate electrode 46 is disposed between the N-type diffusion layer 42 and the N-type diffusion layer 43 through a thin silicon oxide film 33 to form an amplification transistor 48. The amplification transistor 48 is configured as a MOS transistor having the gate electrode 46 as a gate and the N-type diffusion layers 42 and 43 as sources or drains. Note that the gate electrode 46 is electrically connected to the N-type diffusion layers 36 and 41 of the FD 67 by the wiring 40.

  Between the N-type diffusion layer 43 and the N-type diffusion layer 44, the gate electrode 47 of the selection switch 50 is disposed through a thin silicon oxide film 33. A MOS transistor is configured with the gate electrode 47 as a gate and the N-type diffusion layers 43 and 44 as sources or drains.

  A gate electrode 45 of the FD reset unit 49 is disposed between the N-type diffusion layer 41 and the N-type diffusion layer 42 via a thin silicon oxide film 33. A MOS transistor is configured with the gate electrode 45 as a gate and the N-type diffusion layers 41 and 42 as sources or drains.

  Two gate electrodes 72 and 73 of the PD reset unit 68 are disposed between the N-type diffusion layer 71 and the embedded photodiodes 51 and 52 via a thin silicon oxide film 33. A MOS transistor is configured in which the gate electrodes 72 and 73 are used as gates and the N-type diffusion layer 71 and the charge storage layers 55 and 56 of the embedded photodiodes 51 and 52 are used as sources or drains. The gate electrodes 72 and 73 are electrically connected by a wiring 74. The drive signal φPDR is supplied in common. Therefore, although the gate electrodes 72 and 73 are individually arranged in the respective embedded photodiodes 51 and 52, the circuit configuration is equivalent to one MOS transistor as shown in FIG. Here, the two gate electrodes are connected by the wiring 74, but the present invention is not limited to this, and the two gate electrodes 72 and 73 may be integrally formed.

  Further, the gate electrodes 72 and 73 of the PD reset transistor 68 are connected to the common drive wiring 23 in all effective pixels. That is, the PD reset transistors 68 of all effective pixels are driven simultaneously.

The PD reset transistor 68 discharges unnecessary charges generated by the embedded photodiodes 51 and 52. The unnecessary charges include charges due to overflow when strong light is incident and charges due to other noise.
Unnecessary charges may be transferred to the FD 67 and discharged by the FD reset unit 49. In this case, the PD reset unit 68 may not be arranged. Alternatively, it may be arranged at least in part (for example, focus detection pixels).

Further, a thick silicon oxide film 34 is formed by LOCOS around the buried photodiodes 51 and 52 and each N-type diffusion layer, and the respective portions are separated from each other.
(Driving procedure)
FIGS. 7A and 7B are timing charts for explaining an operation of reading a signal from the solid-state imaging device according to the present embodiment. FIG. 7A shows a drive signal for reading an image signal, and FIG. 7B shows a drive signal for reading a focus detection signal. Show.

The transistors constituting the first transfer units 63 and 64, the second transfer units 65 and 66, the amplification transistor 48, the FD reset unit 49, the selection switch 50, and the PD reset unit 68 are clearly shown in FIGS. As shown in the figure, both are configured by NMOS transistors. Therefore, they are turned on by a high drive signal and turned off by a low drive signal.
First, an operation for reading an image signal will be described with reference to FIG. Note that the period T1 is a period in which all effective pixels are driven simultaneously. In other words, the same drive signal is output from the vertical scanning circuit 21 in all rows for the drive pulse during the period T1. Further, T2 is a period during which the first row is read out, and T3 is a period during which the second row is read out. Only the selected row outputs the drive signal shown in FIG.
First, during the period of T11, φPDR is set high and the PD reset unit 68 is turned on. By this operation, unnecessary electric charges accumulated in the embedded photodiodes 51 and 52 of all effective pixels are discharged to the power supply VDD. That is, the embedded photodiodes 51 and 52 are reset. The embedded photodiodes 51 and 52 of all effective pixels simultaneously start exposure from the end of T11.

  In the period of T12, φFDR is set high and the FD reset unit 49 is turned on. In the period T13, simultaneously with the rise of φFDR, φTGB and φTGC are set high, and the two second transfer units 65 and 66 are simultaneously turned on. With this operation, the charges accumulated in the FD 67 and the charge storage units 61 and 62 are discharged to the power supply VDD. That is, the FD 67 and the charge storage units 61 and 62 of all effective pixels are reset.

  In the period of T14, φTGA is set high and the first transfer units 63 and 64 are turned on. By this operation, the charges accumulated in the two embedded photodiodes 51 and 52 of all effective pixels are transferred to the corresponding charge storage units 61 and 62, respectively. Here, the period of T15 shown in the figure (period in which φTGA is set high after φPDR is set to low) is the exposure period. The period of T15 is the same period for all effective pixels and has the same timing. For this reason, all effective pixels can acquire image information without a timing shift.

  Next, in the period of T16, φS in the first row is set high, and the selection switch 50 is turned on. Thereby, the pixels in the first row are selected, and during this period, signals are output from the pixels in the first row to the vertical signal line 25.

  In the period of T17, φFDR in the first row is high, and the FD reset unit 49 is turned on. By this operation, the FD 67 is reset to a dark level potential. Then, during the period from when φFDR becomes low to when φTGB becomes high (period T18), the amplification transistor 48 in the first row outputs a signal corresponding to the dark level of the FD67. The output signal is stored in the CDS circuit 27 via the vertical signal line 25.

In the period T19, φTGB and φTGC are set to high, and the two second transfer units 65 and 66 are simultaneously turned on. As a result, the charges accumulated in the charge storage units 61 and 62 are transferred to the FD 67 and added together. Note that the potential of the FD 67 is a potential obtained by superimposing these charges and the dark level. This potential is sent to the CDS circuit 27 through the vertical signal line 25.
The CDS circuit 27 outputs the difference between the signal sent during this period and the signal corresponding to the dark level stored earlier as the pixel signal of the pixel in the first row. The pixel signals of the pixels in the first row are output to the outside through the horizontal signal line 28 and the output amplifier 29 by the drive signal of the horizontal scanning circuit 22. The signal output to the outside is sent to the memory 7 via the signal processing unit 5 (see FIG. 1) and is temporarily accumulated.

  Similarly, reading of the second row is performed in the period T3. The drive signal is the same as T2. After image signals are output from all rows, the image processing unit 13 receives signals from the memory 7 and generates an image of one frame.

As can be understood from the above description, each pixel 20 has two embedded photodiodes 51 and 52, but can output an image signal as usual. In addition, an electronic shutter with the same exposure timing for all effective pixels is possible. Of course, it is also possible to perform a rolling shutter operation that is reset for each row. In this case, the driving during the period T1 may be performed for each row.
Next, an operation for reading a focus detection signal will be described with reference to FIG. Note that the period T1 is a period in which all effective pixels are driven simultaneously. In other words, the same drive signal is output from the vertical scanning circuit 21 in all rows for the drive pulse during the period T1. Further, T2 is a period during which the first row is read out, and T3 is a period during which the second row is read out. Only the selected row outputs the drive signal shown in FIG.
First, during the period of T21, φPDR is set high, and the PD reset unit 68 is turned on. By this operation, unnecessary electric charges accumulated in the embedded photodiodes 51 and 52 of all effective pixels are discharged to the power supply VDD. That is, the embedded photodiodes 51 and 52 are reset. Then, the embedded photodiodes 51 and 52 of all effective pixels simultaneously start exposure.

  In the period of T22, φFDR is set high and the FD reset unit 49 is turned on. Further, during the period T23, φTGB and φTGC are made high simultaneously with the rise of φFDR, and the two second transfer units 65 and 66 are simultaneously turned on. By this operation, the charges stored in the FD 67 and the charge storage units 61 and 62 are discharged to the power supply VDD. That is, the FD 67 and the charge storage units 61 and 62 of all effective pixels are reset.

  In the period T24, φTGA is set high, and the first transfer units 63 and 64 are turned on. The charges accumulated in the two embedded photodiodes 51 and 52 of all effective pixels are transferred to the corresponding charge storage units 61 and 62, respectively. Here, the period of T25 shown in the figure (the period in which φPGA is set low and then φTGA is set high) is the exposure period. The period of T25 is the same period for all effective pixels and has the same timing. For this reason, it becomes possible for all the effective pixels to acquire the focus detection information without a timing shift. Note that the operation in the period up to this point (period T1) is the same as the driving operation for obtaining the image signal.

  In the period T26, φS in the first row is set high and the selection switch 50 is turned on. As a result, the pixels in the first row are selected, and a signal is output from the pixels in the first row to the vertical signal line 25.

  In the period T27, φFDR in the first row is set high, and the FD reset unit 49 is turned on. By this operation, the FD 67 is reset to a dark level potential. Then, during the period from when φFDR becomes low until φTGB becomes high (period T28), the amplification transistor 48 in the first row outputs a signal corresponding to the dark level of the FD67. The output signal is stored in the CDS circuit 27 via the vertical signal line 25.

In the period T29, φTGB is set high, and one second transfer unit 65 is turned on. As a result, the charge accumulated in one charge storage unit 61 is transferred to the FD 67. Note that the potential of the FD 67 is a potential obtained by superimposing the charge and the dark level. Then, the amplification transistor 48 outputs a signal corresponding to this potential. The output signal is sent to the CDS circuit 27 through the vertical signal line 25.
The CDS circuit 27 outputs the difference between the signal sent during this period and the signal corresponding to the dark level stored earlier as one pupil division focus detection signal for the pixels in the first row. One pupil division focus detection signal in the pixels in the first row is output to the outside through the horizontal signal line 28 and the output amplifier 29 by the drive signal of the horizontal scanning circuit 22. The output signal is sent to the memory 7 via the signal processing unit 5 (see FIG. 1) and temporarily accumulated.

  Next, in the period T30, φFDR in the first row is set to high again, and the FD reset unit 49 is turned on. By this operation, the FD 67 is reset again, and becomes a dark level potential different from the previous time. Then, during the period from when φFDR becomes low until φTGC becomes high (period T31), the amplification transistor 48 in the first row outputs a signal corresponding to the dark level of the FD67. The output signal is stored in the CDS circuit 27 via the vertical signal line 25.

In the period of T32, φTGC is set high, and the other second transfer unit 66 is turned on. As a result, the charge accumulated in the other charge storage unit 62 is transferred to the FD 67. Note that the potential of the FD 67 is a potential obtained by superimposing the charge and the dark level. Then, the amplification transistor 48 outputs a signal corresponding to this potential. The output signal is sent to the CDS circuit 27 through the vertical signal line 25.
The CDS circuit 27 outputs the difference between the signal sent during this period and the signal corresponding to the dark level stored earlier as the other pupil division focus detection signal for the pixels in the first row. Then, the other pupil division focus detection signal in the pixels in the first row is output to the outside through the horizontal signal line 28 and the output amplifier 29 by the drive signal of the horizontal scanning circuit 22. The signal output to the outside is sent to the memory 7 via the signal processing unit 5 (see FIG. 1) and is temporarily accumulated.

  Similarly, reading of the second row is performed in the period T3. The drive signal is the same as T2. After image signals are output from all rows, the focus calculation unit 10 receives signals from the memory 7 and calculates a focus position based on a known pupil division phase difference.

  As can be understood from the above description, the solid-state imaging device 3 can make the exposure timings of all effective pixels the same when obtaining an image signal and obtaining a focus detection signal. Become. For this reason, even when a fast-moving subject is imaged, the timing for focusing in one frame is not shifted, and the focus can be detected and imaged well.

  Further, the pixel 20 can be used for all effective pixel regions of the solid-state imaging device 3. In this way, since pixels dedicated to focus detection are not used, the image signal does not need to be corrected such as interpolation. In addition, since any pixel can output a focus detection signal, it is possible to freely set the focus detection area within the effective pixel area.

[Modification of First Embodiment]
FIG. 8 is a cross-sectional view of a pixel of a solid-state imaging device according to a modification of the first embodiment of the present invention, and corresponds to FIG. This modification is different from the first embodiment in that the gate electrode 35 of the first transfer units 63 and 64 covers the N-type diffusion layers 75 and 76 of the charge storage units 61 and 62 in the first embodiment. In contrast, in this modification, the gate electrode 101 of the first transfer units 63 and 64 is only between the buried photodiodes 51 and 52 and the N-type diffusion layers 75 and 76 of the charge storage units 61 and 62. The N-type diffusion layers 75 and 76 of the charge storage portions 61 and 62 are not covered.
An electrode 102 for a MOS capacitor is disposed on the upper surfaces of the N-type diffusion layers 75 and 76 of the charge storage portions 61 and 62 via the silicon oxide film 33 (for ease of understanding, FIG. , The ratio of dimensions is partially changed from FIG. The electrode 102 disposed on the upper surface of the N-type diffusion layer 75 and the electrode 102 disposed on the upper surface of the N-type diffusion layer 76 are integrally formed and electrically connected.

  The electrode 102 is electrically connected to the gate electrode 101 of the first transfer units 63 and 64. Therefore, the drive signal applied to the electrode 102 and the drive procedure thereof are the same as those in the first embodiment. However, the present invention is not limited to this, and the electrodes 102 may be driven with a potential and timing that are individually pinned and more pinned.

The direction in which the embedded photodiodes 51 and 52 and the charge storage units 61 and 62 are arranged is the same as the direction in which the charge storage units 61 and 62 and the floating diffusion region 36 are arranged. If each is arranged in this manner, the structure in which the charge storage layer 55 of the embedded photodiodes 51 and 52 and the N-type diffusion layers 75 and 76 of the charge storage portions 61 and 62 enter under the transfer electrodes 101 and 102 is easy. Formed.
The structure in which the buried photodiodes 51 and 52 and the N-type diffusion layers of the charge storage portions 61 and 62 enter under the transfer electrodes 101 and 102 is preferable for complete transfer. Therefore, there is an effect that an afterimage is hardly generated.
Hereinafter, the point that the structure in which the N-type diffusion layer enters under the electrode is easily formed will be described in more detail.

FIG. 9 is a pixel cross-sectional view illustrating a part of the manufacturing process of the solid-state imaging device according to the present modification. This sectional view also shows a portion corresponding to FIG. Although only the configuration related to FIG. 8 will be described here, the peripheral circuit is also formed according to a predetermined process.
According to a known silicon process, a P-type well 32, a thick silicon oxide film 34 (isolation region) made of LOCOS, and gate electrodes 72, 101, 103 made of polysilicon of the first layer are formed on an N-type silicon substrate 31. The A silicon oxide film is formed on the surface of the gate electrodes 72, 101, 103 made of polysilicon of the first layer by thermal oxidation.

Next, a resist is patterned in the gate electrodes 72, 101, 103, the thick silicon oxide film 34 in the isolation region, and a predetermined region (not shown) if necessary, and phosphorus ions are implanted using these as a mask. This state is shown in FIG. As shown in the figure, phosphorus ions are implanted from an oblique direction 108 so as to enter under the gate electrodes 72, 101, and 103. Here, the direction in which the embedded photodiodes 51 and 52 and the charge storage units 61 and 62 are arranged is the same as the direction in which the charge storage units 61 and 62 and the floating diffusion region 36 are arranged.
Therefore, if ion implantation from an oblique direction is performed once, ions enter under the gate electrodes 72, 101, and 103, and a diffusion region is formed. If the directions are different, the diffusion region under the gate electrode is formed by performing ion implantation from an oblique direction to each gate electrode. Therefore, in this step, ion implantation from an oblique direction is performed a plurality of times.

In the solid-state imaging device of the present embodiment, since the above directions are the same, ion implantation from one oblique direction is sufficient. For this reason, manufacture becomes easy. The acceleration voltage may be relatively low, and the formed diffusion layers 104, 105, 106, and 107 may be relatively shallow.
Next, the resist 110 is patterned so that the regions where the N-type diffusion layers 75 and 76 of the charge storage portions 61 and 62 are formed are opened, and phosphorus ions are implanted, and the N-type diffusion layers 75 and 75 of the charge storage portions 61 and 62 are formed. 76 is formed. In this step, ions are implanted from the normal direction 111. By this step, the N-type diffusion layers 75 and 76 of the load storage units 61 and 62 can be set to a concentration and depth suitable as a charge storage unit. FIG. 9B shows this state.
Similarly, patterning of resist is sequentially performed in the same manner on the charge storage portion 55 of the embedded photodiodes 51 and 52, the N-type diffusion layer 36 of the floating diffusion region 67, and the N-type diffusion layer 71 of the PD reset portion 68, and phosphorus ions are implanted. These are formed sequentially.

An electrode 102 for the MOS capacitor is formed so as to cover the surfaces of the N-type diffusion layers 75 and 76 of the charge storage portions 61 and 62. The electrode 102 is electrically connected to the gate electrode 101 of the first transfer unit.
Thus, the charge storage layer 55 of the embedded photodiodes 51 and 52, the N-type diffusion layer 36 of the floating diffusion region 67, and the N-type diffusion layer 71 of the PD reset unit 68 are set to suitable concentrations and depths, respectively. Is possible.

Here, the N-type diffusion layers 104, 105, 106, and 107 are simultaneously ion-implanted so that the diffusion layer enters under each gate electrode, and then each region has a suitable impurity concentration and depth. Ions are individually implanted in each. However, the present invention is not limited to this, and if the concentration and depth of the N-type diffusion layers 71, 55, 75, and 36 that are finally formed are substantially the same, these ions can be obtained by performing ion implantation once from an oblique direction. Regions may be formed simultaneously.
The PD reset unit 68 is disposed to reset the charge storage layer 55 of the embedded photodiodes 51 and 52 to a constant potential. For this reason, the N-type diffusion layer 71 does not require a structure that enters under the gate electrode 72. Therefore, the N-type diffusion layer 104 may not be formed in the step of implanting ions from an oblique direction.

[Another Modification of First Embodiment]
FIG. 10 is a pixel plan view of a solid-state imaging device according to another modification of the first embodiment. For simplicity, FIG. 10 omits portions of the gate electrodes 35 of the first transfer units 63 and 64 that are disposed on the charge storage units 81 and 82. Each gate electrode 35 is drawn so as to be connected by an internal wiring 83.

  The pixel 80 of this modification is different from the pixel 20 of the first embodiment only in the following points. That is, in the first embodiment, the embedded photodiode 51, the charge storage unit 61, and the N-type diffusion layer 36 of the FD 67 are arranged in the same direction (the embedded photodiode 52, the charge storage unit 62, and the FD 67). The same applies to the N-type diffusion layer 36 of the N-type diffusion layer 36), but in this modification, the direction in which the embedded photodiode 51 and the charge storage unit 81 are arranged, the charge storage unit 81, and the N-type diffusion layer 86 of the FD 67 are arranged. The direction to be done is different. The N-type diffusion layer 86 of the FD 67 is disposed between the two charge storage portions 81 and 82.

If the N-type diffusion layer 86 of the FD 67 is arranged in this way, not only the timing of exposure of all the pixels is ensured, but also the area of the FD 67 can be reduced and miniaturized.
Since other points are the same as those in the first embodiment, description thereof will be omitted.

[Second Embodiment]
(Pixel configuration)
FIG. 11 is a pixel circuit diagram of a solid-state imaging device according to the second embodiment of the present invention. FIG. 12 is a pixel plan view of the solid-state imaging device according to the second embodiment. In FIG. 12, the portions of the gate electrodes 35 of the first transfer portions 87, 88, 89 disposed on the charge storage portion are omitted, and each gate electrode 35 is depicted as being connected by an internal wiring 83. Yes. Note that the overall configuration of the solid-state imaging device corresponding to FIG. 2 is the same as that of the first embodiment, and thus description thereof is omitted here.

The solid-state image sensor of this embodiment is different from the solid-state image sensor according to the first embodiment in that three embedded photodiodes 91, 92, and 93 that are photoelectric conversion units are arranged in each pixel 90. The corresponding charge storage portions 94, 95, and 96 are also arranged. As will be described later, the drive wiring and the drive signal are also changed accordingly. Other points (amplification transistor 48, FD reset unit 49, selection switch 50, PD reset unit 68, etc.) are the same as those in the first embodiment, and the description thereof is omitted here.
The pixel 90 has three embedded photodiodes 91, 92, and 93 as a photoelectric conversion unit that generates and accumulates charges according to incident light. Then, three charge storage portions 94, 95, and 96 that store charges independently corresponding to the embedded photodiodes 91, 92, and 93 are disposed.
First transfer units 87, 88, and 89 are disposed between the embedded photodiodes 91, 92, and 93 and the charge storage units 94, 95, and 96. Charges generated and accumulated by the embedded photodiodes 91, 92, 93 are transferred to the charge storage units 94, 95, 96 corresponding to the first transfer units 87, 88, 89, respectively, when the first transfer units 87, 88, 89 are turned on. Is done.

Note that the gate electrodes 35 of the three first transfer units 87, 88, and 89 are connected in common. These gate electrodes 35 are supplied with a drive signal φTGA from the vertical scanning circuit 21 via the drive wiring 23. Accordingly, the three first transfer units 87, 88, and 89 receive the drive signal φTGA and are simultaneously turned on and off. When the drive signal φTGA becomes high, the charges accumulated in the embedded photodiodes 91, 92, and 93 are simultaneously transferred to the corresponding charge storage portions 94, 95, and 96, respectively.
In addition, a floating diffusion region (FD) 67 is disposed in the pixel 90, and charges transferred from the charge storage units 94, 95, and 96 are stored individually or simultaneously. Second transfer units 97, 98, and 99 are disposed between the charge storage units 94, 95, and 96 and the FD 67. The gate electrodes of the three second transfer portions 97, 98, and 99 are electrically separated from each other, and individual drive signals φTGB, φTGC, and φTGD are supplied from the vertical scanning circuit 21. For this reason, each of the second transfer units 97, 98, 99 is individually driven according to the respective drive signals φTGB, φTGC, φTGD.

  Therefore, the three second transfer units 97, 98, and 99 can be turned on at different timings or can be turned on at the same time. If they are turned on at different timings, the photocharges accumulated in the three charge storage units 94, 95, 96 are individually transferred to the FD 67 at different timings. If these are simultaneously turned on, the photocharges accumulated in the three charge storage portions 94, 95, 96 are added together in the FD 67.

  As described above, each pixel 90 includes three embedded photodiodes 91, 92, and 93. One microlens 57 that guides incident light to the embedded photodiodes 91, 92, and 93 is disposed. The three embedded photodiodes 91, 92, 93 are arranged so as to be line-symmetric with respect to the center line XX ′ (line having a diameter) of the microlens 57 when viewed from the incident light side.

One of the embedded photodiodes is disposed at the center of the microlens 57 when viewed from the incident light side. This position is the position where the light is most efficiently collected, and the photoelectric conversion unit arranged at this position increases the generation of photoelectric charges, and thus the output increases. The central embedded photodiode 92 is used to obtain an image signal because light that is not divided into pupils is received.
Further, the embedded photodiodes 91 and 93 at both ends are arranged at positions symmetrical with respect to the center line XX ′. Therefore, the incident light guided from the microlens 57 is divided into pupils and is incident on the embedded photodiodes 91 and 93. Therefore, the focus can be detected by using signals output from these two embedded photodiodes 91 and 93.

  As described above, the solid-state imaging device of the present embodiment can use the signal output from the central embedded photodiode 92 as an image signal. In addition, the solid-state imaging device of the present embodiment can use signals output from the embedded photodiodes 91 and 93 at both ends as focus detection signals of the pupil division phase difference method. In this case, the image signal and the focus detection signal may be generated at different timings. However, if the exposure timings of the three photodiodes 91, 92, and 93 are made the same, it is possible to match the same timing of the image signal and the focus detection signal. For this reason, this solid-state image sensor is further preferable for imaging a moving body that operates quickly. In addition, since the image signal and the focus detection signal can be obtained by one exposure, the imaging speed is improved.

  The solid-state imaging device can also add up the charges of the three embedded photodiodes. If the output signal is used as an image signal, the output of the image signal is further increased.

(Driving procedure)
As described above, the solid-state imaging device according to the present embodiment has many signal readout drive systems. Here, the driving method will be described for each case.
First, a driving procedure for reading an image signal from the central embedded photodiode 92 will be described. The timing chart is the same as FIG. 7A except for φTGB and φTGD. Note that φTGB and φTGD are always low. Alternatively, in order to prevent blooming, φTGB and φTGD may be set to high only during the period T13.
Next, a driving procedure for reading out focus detection signals from the embedded photodiodes 91 and 93 at both ends will be described. The timing chart is the same as FIG. 7B except for φTGC and φTGD. Then, φTGD is the same as that replaced with φTGC in this figure, and φTGC is always low. Alternatively, φTGC may be set high only during the period T13 in order to prevent blooming.

Next, a driving procedure for reading out image signals from all the embedded photodiodes 91, 92, 93 will be described. The timing chart is the same as FIG. 7A except for φTGD. Note that φTGD is the same as φTGB and φTGC in this figure.
Further, a driving procedure for simultaneously exposing and reading out the image signal and the focus detection signal at the same timing will be described. FIG. 13 is a timing chart for explaining this read operation. Note that the period T1 is a period in which all effective pixels are driven simultaneously. In other words, the same drive signal is output from the vertical scanning circuit 21 in all rows for the drive pulse during the period T1. Further, T2 is a period during which the first row is read out, and T3 is a period during which the second row is read out. Only the selected row outputs the drive signal shown in FIG.

  First, during the period of T41, φPDR is set high and the PD reset unit 68 is turned on. By this operation, unnecessary charges accumulated in the embedded photodiodes 91, 92, and 93 of all effective pixels are discharged to the power supply VDD. That is, the embedded photodiodes 91, 92, and 93 are reset. Then, the embedded photodiodes 91, 92, and 93 of all effective pixels start exposure at the same time.

  In the period of T42, φFDR is set high and the FD reset unit 49 is turned on. Further, during the period of T43, simultaneously with the rise of φFDR, φTGB, φTGC, and φTGD are made high, and the three second transfer units 97, 98, and 99 are simultaneously turned on. With this operation, the charges accumulated in the FD 67 and the charge storage units 94, 95, and 96 are discharged to the power supply VDD. That is, the FD 67 and the charge storage units 94, 95, and 96 of all effective pixels are reset.

  In the period of T44, φTGA is set high, and the first transfer units 87, 88, 89 are turned on. The charges accumulated in the three embedded photodiodes 91, 92, 93 of all effective pixels are transferred to the corresponding charge storage units 94, 95, 96, respectively. Here, the period of T45 (period in which φPDR is set low and then φTGA is set high) shown in the drawing is the exposure period. The period of T45 is the same period for all effective pixels and has the same timing. For this reason, all the embedded photodiodes 91, 92, and 93 of all effective pixels can acquire the image signal and the focus detection signal in the same period without any timing shift.

  In the period T46, φS in the first row is set high, and the selection switch 50 is turned on. As a result, the pixels in the first row are selected, and a signal is output from the pixels in the first row to the vertical signal line 25.

  In the period of T47, φFDR in the first row is set high, and the FD reset unit 49 is turned on. By this operation, the FD 67 is reset to a dark level potential. Then, during the period from when φFDR becomes low until φTGB becomes high (period T48), the amplification transistor 48 in the first row outputs a signal corresponding to the dark level of the FD67. The output signal is stored in the CDS circuit 27 via the vertical signal line 25.

In the period of T49, φTGB is set high, and the corresponding second transfer unit 97 is turned on. As a result, the charges accumulated in the charge storage unit 94 are transferred to the FD 67. Note that the potential of the FD 67 is a potential obtained by superimposing the charge and the dark level. Then, the amplification transistor 48 outputs a signal corresponding to this potential. The output signal is sent to the CDS circuit 27 through the vertical signal line 25.
The CDS circuit 27 outputs the difference between the signal output during this period and the signal corresponding to the dark level stored earlier as one pupil division focus detection signal for the pixels in the first row. One pupil division focus detection signal in the pixels in the first row is output to the outside through the horizontal signal line 28 and the output amplifier 29 by the drive signal of the horizontal scanning circuit 22. The output signal is sent to the memory 7 via the signal processing unit 5 (see FIG. 1) and temporarily accumulated.

  Next, in the period of T50, φFDR in the first row is set high again, and the FD reset unit 49 is turned on. By this operation, the FD 67 is reset again, and becomes a dark level potential different from the previous time. Then, during the period from when φFDR becomes low until φTGC becomes high (period T51), the amplification transistor 48 in the first row outputs a signal corresponding to the dark level of the FD67. The output signal is stored in the CDS circuit 27 via the vertical signal line 25.

In the period of T52, φTGC is set high, and the second transfer unit 98 is turned on. As a result, the charge accumulated in the charge storage unit 95 is transferred to the FD 67. Note that the potential of the FD 67 is a potential obtained by superimposing the charge and the dark level. Then, the amplification transistor 48 outputs a signal corresponding to this potential. The output signal is sent to the CDS circuit 27 through the vertical signal line 25.
The CDS circuit 27 outputs the difference between the signal output during this period and the signal corresponding to the dark level stored earlier as an image signal in the pixels in the first row. The image signals in the pixels in the first row are output to the outside via the horizontal signal line 28 and the output amplifier 29 by the drive signal of the horizontal scanning circuit 22. The signal output to the outside is sent to the memory 7 via the signal processing unit 5 or the like and temporarily stored.

  Next, in the period of T53, φFDR in the first row is set high again, and the FD reset unit 49 is turned on. By this operation, the FD 67 is reset again, and becomes a dark level potential different from the previous time. Then, during the period from when φFDR becomes low until φTGC becomes high (period T54), the amplification transistor 48 in the first row outputs a signal corresponding to the dark level of the FD67. The output signal is stored in the CDS circuit 27 via the vertical signal line 25.

In the period of T55, φTGC is set high, and the second transfer unit 66 is turned on. As a result, the charge accumulated in the charge storage unit 96 is transferred to the FD 67. Note that the potential of the FD 67 is a potential obtained by superimposing the charge and the dark level. Then, the amplification transistor 48 outputs a signal corresponding to this potential. The output signal is sent to the CDS circuit 27 through the vertical signal line 25.
The CDS circuit 27 outputs the difference between the signal output during this period and the signal corresponding to the dark level stored earlier as the other pupil division focus detection signal for the pixels in the first row. Then, the other pupil division focus detection signal in the pixels in the first row is output to the outside through the horizontal signal line 28 and the output amplifier 29 by the drive signal of the horizontal scanning circuit 22. The signal output to the outside is sent to the memory 7 via the signal processing unit 5 or the like and temporarily stored. Similarly, reading of the second row is performed in the period T3. The drive signal is the same as T2.
After the image signals are output from all the rows, the image processing unit 13 receives the signals from the memory 7 and generates an image of one frame. The focus calculation unit 10 receives a signal from the memory 7, calculates a focus position based on a known pupil division phase difference, and transmits the focus detection information to the microprocessor 9.
The microprocessor 9 transmits information for moving the lens to the lens control unit 2a based on the information. Alternatively, if the microprocessor 9 determines that the image is in focus, the image processing unit 13, the image compression unit 12, and the image processing unit 13 are configured to transmit the image information generated by the image processing unit 13. This is transmitted to the recording unit 11.

  As can be understood from the above description, this solid-state imaging device has an image signal in which the exposure timings of all the effective pixels are the same and the exposure timings of the three embedded photodiodes 91, 92, and 93 are the same. A focus detection signal can be obtained. For this reason, even when a fast-moving subject is imaged, it is possible to detect the focus even better.

[Third Embodiment]
FIG. 14 is a plan view of two pixels of a solid-state imaging device according to the third embodiment of the present invention. The difference from the solid-state imaging device according to the first embodiment is that an amplification transistor 48, an FD reset unit 49, and a selection switch 50 are arranged for every two pixels. In this way, the amplification transistor 48, the FD reset unit 49, and the selection switch 50 can be shared by two pixels, and the pixel can be miniaturized or the aperture ratio can be improved. Become.

Here, as shown in the figure, two pixels adjacent in the vertical direction in the odd and even rows form one set, and the amplification transistor 48, the FD reset unit 49, and the selection switch 50 are shared. . Therefore, the driving procedure may be the same as in the first embodiment.
Here, one amplification transistor 48, one FD reset unit 49, and one selection switch 50 are arranged for two pixels. However, the present invention is not limited to this, and the amplification transistor 48, the FD reset unit 49, and the selection switch 50 may be arranged in a plurality of pixels.

1 is a block diagram illustrating an electronic camera 1 according to a first embodiment of the present invention. It is a circuit diagram which shows schematic structure of the solid-state image sensor 3 which concerns on 1st Embodiment. 1 is a pixel circuit diagram of a solid-state image sensor 3 according to a first embodiment. It is a pixel top view of the solid-state image sensor 3 concerning 1st Embodiment. It is sectional drawing of the A-A 'part in FIG. It is sectional drawing of the B-B 'part in FIG. It is a timing chart explaining the operation | movement which reads a signal from the solid-state image sensor which concerns on 1st Embodiment. It is a pixel top view of the solid-state image sensing device concerning the modification of a 1st embodiment. It is a pixel sectional view showing a part of manufacturing process of a solid-state image sensing device concerning a modification of a 1st embodiment. It is a pixel top view of the solid-state image sensing device concerning another modification of a 1st embodiment. It is a pixel circuit diagram of the solid-state image sensor concerning a 2nd embodiment. It is a pixel top view of the solid-state image sensing device concerning a 2nd embodiment of the present invention. It is a timing chart explaining the operation | movement which reads and reads an image signal and a focus detection signal simultaneously from the solid-state image sensor which concerns on 2nd Embodiment at the same timing. It is a top view for 2 pixels of the solid-state image sensing device concerning a 3rd embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Electronic camera 3 Solid-state image sensor 20 Pixel 23, 24 Drive wiring 25 Vertical signal line 28 Horizontal signal line 31 N type silicon substrate 32 P type well 36,41,42,43,44,71,86,104,105,106 107 N-type diffusion layers 40, 83, 74 Internal wiring 48 Amplifying transistor 49 FD reset unit 50 Select switch 51, 52 Embedded photodiode 55 Charge storage layer 56 Depletion prevention layer 57 Microlens 61, 62, 81, 82, 94 , 95, 96 Charge storage unit 63, 64, 87, 88, 89 First transfer unit 65, 66, 97, 98, 99 Second transfer unit 67 Floating diffusion region 68 PD reset unit 102 MOS capacitor electrode 110 Resist

Claims (10)

A plurality of pixels arranged two-dimensionally, and a peripheral circuit for driving the pixels and outputting signals from the pixels to the outside, at least some of the pixels being
A plurality of photoelectric conversion units that generate and store charges according to incident light; and
A plurality of charge storage units arranged corresponding to each of the photoelectric conversion units and receiving and storing the charges from the corresponding photoelectric conversion units;
A floating diffusion region that receives and accumulates the charge from the plurality of charge storage units;
A first transfer unit that transfers the charge from the plurality of photoelectric conversion units to the corresponding charge storage unit;
A second transfer unit that transfers the charge from the plurality of charge storage units to the floating diffusion region;
A solid-state imaging device comprising: a microlens that guides the incident light to the plurality of photoelectric conversion units. The at least some pixels further include:
A pixel amplifier unit that outputs a signal corresponding to the amount of charge accumulated in the floating diffusion region;
A first reset unit for resetting the charge accumulated in the floating diffusion region;
The solid-state imaging device according to claim 1, further comprising: a selection switch that selects a pixel from which a signal is read and outputs a signal from the pixel amplifier unit of the selected pixel. The solid-state imaging device according to claim 2, wherein one of the pixel amplifier unit, the first reset unit, and the selection switch is arranged for a plurality of pixels. The first transfer units arranged in the same pixel are simultaneously driven by the peripheral circuit,
4. The solid-state imaging device according to claim 1, wherein the second transfer units arranged in the same pixel are individually driven by the peripheral circuit. 5.   5. The solid-state imaging device according to claim 1, wherein two of the photoelectric conversion units are arranged in the at least some of the pixels.   5. The solid-state imaging device according to claim 1, wherein three of the photoelectric conversion units are arranged in the at least some of the pixels. The at least some pixels are two-dimensionally arranged, output a focus detection signal, and output an image signal at a timing different from the focus detection signal. The solid-state image sensor in any one.   8. The solid-state imaging device according to claim 1, wherein the at least some of the pixels include a second reset unit that resets charges accumulated in the photoelectric conversion unit. 9. The charge storage unit is disposed between the photoelectric conversion unit and the floating diffusion region,
The first transfer unit includes a gate electrode disposed between the photoelectric conversion unit and the charge storage unit,
The second transfer unit includes a gate electrode disposed between the charge storage unit and the floating diffusion region,
The direction in which the photoelectric conversion unit and the charge storage unit are disposed and the direction in which the charge storage unit and the floating diffusion region are disposed are the same direction. A solid-state imaging device according to claim 1. A solid-state imaging device according to any one of claims 1 to 9,
A focus calculation unit that acquires a focus detection signal from the solid-state imaging device, detects a pattern shift of a pupil-divided image extracted from the focus detection signal, and performs focus detection;
An electronic camera comprising: an imaging control unit that reads out an image signal from the solid-state imaging device.

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