JP4708099B2 - Mask for manufacturing a transistor and method for manufacturing a transistor using the same - Google Patents

Description

  The present invention relates to a transistor manufacturing mask for exposing a resist formed on a semiconductor layer. The present invention also relates to a method of manufacturing a transistor by implanting impurities after patterning a resist using the transistor manufacturing mask of the present invention.

  Among thin and low power consumption liquid crystal display devices that use TFTs (thin film transistors) as liquid crystal drive elements have high performance such as high contrast and high response speed, so they are used for mobile phone displays and televisions. Has been. Some of the TFT channel region semiconductors use CGS ((continuous grain boundary crystal silicon) film. The CGS film is a regular arrangement of silicon crystals, and the arrangement of the crystal interface is regular. As a result, the CGS film has a higher electron transfer rate than an amorphous silicon film or a low-temperature polysilicon film, and is comparable to a single crystal silicon film. Since it can be used not only as a driving element but also as a driver IC (integrated circuit), a liquid crystal driving element and a driver IC can be formed on a substrate having a CGS film, that is, a narrow frame and a manufacturing cost. Can be reduced.

  Patent Document 1 discloses a method for producing a CGS film. Specifically, it is disclosed that a heat treatment is performed after adding a metal catalyst such as nickel to an amorphous silicon film. However, the CGS film obtained by this method contains a metal catalyst. When a TFT is manufactured using a CGS film containing a metal catalyst, the metal catalyst acts as an impurity in the silicon crystal forming the channel region of the TFT to form an order, so that the threshold value of the TFT changes with time and the OFF current increases. There is a risk of serious adverse effects such as.

Patent Document 2 discloses a method for removing the metal catalyst. Specifically, after a portion of the CGS film is doped with phosphorus at a high concentration, heat treatment is performed to getter the metal catalyst in the phosphorus-doped region and remove the metal catalyst from the channel region of the TFT. ing.
JP-A-6-244103 JP-A-10-223533

When a TFT is formed on a silicon film doped with phosphorus, the threshold value of the TFT shifts to minus. Therefore, it is necessary to implant boron into the channel region of the TFT to make the channel region intrinsic. Typically, a structure is employed in which a layer containing a small amount of impurities (for example, an n ⁻ layer in an n-type transistor) is formed in a channel region overlapping with the gate electrode to ensure the reliability of the transistor. However, in order to manufacture a TFT having such a structure, it is necessary to perform patterning twice using two masks.

  An object of the present invention is to reduce the number of masks and shorten the manufacturing process in the process of manufacturing a transistor.

The transistor manufacturing mask of the present invention includes a light shielding region, a transmission region, and a gray tone region having a light transmittance higher than that of the light shielding region and lower than that of the transmission region. By using the transistor manufacturing mask of the present invention to expose the resist formed on the semiconductor layer, a stepwise resist pattern having a step can be formed. After injecting n-type impurities into the semiconductor layer through this resist pattern, the resist having the smaller film thickness is removed. Thereby, the opening pattern of the resist can be changed. Further, a p-type impurity is implanted into the semiconductor layer to manufacture a transistor.

According to the present invention, the resist pattern used in the n-type impurity implantation step and the p-type impurity implantation step can be formed by a single mask. That is, in the process of manufacturing a transistor, the number of masks can be reduced and the manufacturing process can be shortened.

  Embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a case where an n-type TFT is manufactured will be described, but the present invention is not limited to this. A p-type TFT can be manufactured by changing the conductivity type of the impurity to be implanted.

(Embodiment 1)
FIG. 1 is a plan view schematically showing a mask used in this embodiment, and FIG. 2 is a cross-sectional view schematically showing a TFT manufacturing process according to this embodiment. Note that FIG. 1 shows a pattern for forming one TFT for simplification, but a typical mask has a plurality of patterns for forming a plurality of TFTs.

  First, the TFT manufactured according to this embodiment will be described with reference to FIG. The TFT shown in FIG. 2D is formed on the insulating substrate 10. The TFT has an intrinsic layer 20a, an intrinsic layer 20a sandwiched in the plane direction, a first conductivity type layer 20b containing impurities at a higher concentration than the intrinsic layer 20a, a first conductivity type layer 20b sandwiched in the plane direction, and And second conductive type layers 20s and 20d containing impurities at a higher concentration than the first conductive type layer 20b. The intrinsic layer 20 a and the first conductivity type layer 20 b are overlapped with the gate electrode 70 through the gate insulating film 60. One second conductivity type layer 20s serves as a source electrode, and the other second conductivity type layer 20d serves as a drain electrode.

  The mask 1 shown in FIG. 1 has three regions corresponding to the TFT shown in FIG. Specifically, it corresponds to the light shielding region 11 formed in the region corresponding to the second conductivity type layers 20s and 20d, the transmission region 12 formed in the region corresponding to the first conductivity type layer 20b, and the intrinsic layer 20a. And a gray tone region 13 formed in the region to be processed. The gray tone region 13 is a region having a light transmittance higher than that of the light shielding region 11 and lower than that of the transmission region 12.

  The mask 1 has a transparent substrate and two types of films 14 and 15 formed on the transparent substrate. One film 14 is a light shielding film 14 formed in the light shielding region 11, and the other film 15 is a gray tone film 15 formed in the gray tone region 13.

  The light shielding film 14 and the gray tone film 15 can be formed using a chromium film, a chromium oxide film, a molybdenum oxide silicide film, a polysilicon film, a silicon nitride film, a tungsten film, or an aluminum film. The gray tone film 15 is formed to have a higher transmittance than the light shielding film 14. The transmittance of the gray tone film 15 can be adjusted by changing the type and film thickness of the film material. Alternatively, the transmittance can be adjusted by forming openings in the gray tone film 15 and adjusting the density and diameter of the openings. Note that the size of the opening is preferably smaller than the resolution limit of the stepper optical system. A specific pattern of the gray tone film is disclosed in, for example, Japanese Patent Laid-Open No. 8-250446.

  Next, a process of manufacturing the TFT of this embodiment using the mask 1 will be described with reference to FIG. First, the CGS film 20 is formed on the insulating substrate 10. The CGS film 20 contains a small amount of n-type impurities. In other words, the CGS film 20 has extra electrons. A positive resist 30 is formed on the CGS film 20. The positive resist 30 is exposed through the mask 1 and then developed to form a resist 31 having a pattern shown in FIG. The resist 30 corresponding to the transmission region 12 of the mask 1 is removed, and the CGS film 20 is exposed. On the other hand, the resist 30 corresponding to the light shielding region 11 and the gray tone region 13 of the mask 1 remains even after development. However, the developed resist 31 corresponding to the gray tone region 13 has a film thickness approximately half that of the developed resist 31 corresponding to the light shielding region 11.

As shown in FIG. 2B, phosphorus ions 40 as n-type impurities are implanted into the exposed CGS film 20. The implantation concentration of phosphorus ions 40 is, for example, about 5 × 10 ¹³ atoms / cm ³ . Thereby, the first conductivity type layer 20b doped with the n-type impurity at a low concentration is formed.

As shown in FIG. 2C, ashing of the resist 31 is performed. Ashing can be performed by plasma etching, for example. Specifically, the insulating substrate 10 is held in a vacuum, oxygen gas is introduced into the vacuum, oxygen gas is turned into plasma by high frequency, and the resist 31 is etched with the oxygen plasma. As a result, the resist 31 corresponding to the light shielding region 11 of the mask 1 has a film thickness of about half, and the resist 31 corresponding to the gray tone region 13 of the mask 1 is removed. Boron ions 50 are implanted into the exposed CGS film 20. The implantation concentration of boron ions 50 is, for example, about 1 × 10 ¹³ atoms / cm ³ . Since boron is a p-type impurity with respect to silicon, the CGS film 20 containing a small amount of n-type impurity becomes the intrinsic layer 20a. On the other hand, since the implantation concentration of boron ions 50 is lower than the implantation concentration of phosphorus ions 40, the layer 20b is a first conductivity type layer doped with an n-type impurity at a low concentration.

As shown in FIG. 2D, after removing the resist 32, a gate insulating film 60 and a gate electrode 70 are formed by a photolithography method or the like. High concentration (about 5 × 10 ¹⁵ atoms / cm ³ ) phosphorus ions are implanted using the gate electrode 70 as a mask. Thereby, the source electrode 20s and the drain electrode 20d as the second conductivity type layer are formed.

  According to the present embodiment, since the TFT can be manufactured using one mask 1, the manufacturing cost can be reduced. Further, since the resist patterning process can be performed only once, the manufacturing process is shortened.

  The manufacturing process of the top gate type TFT has been described above with reference to FIG. 2, but the bottom gate type TFT can also be manufactured using the mask 1. FIG. 3 is a cross-sectional view schematically showing the manufacturing process of the bottom gate type TFT. In FIG. 3, only the TFT is different from that in FIG. 2 and the other configurations are the same as those in FIG. 2. Therefore, components having substantially the same functions as those shown in FIG. Is omitted.

  Since the TFT shown in FIG. 3 is a bottom gate type, high concentration phosphorus ions cannot be implanted using the gate electrode 70 as a mask. Therefore, it is necessary to separately form a resist that covers the intrinsic layer 20a and the first conductivity type layer 20b and to implant high-concentration phosphorus ions. However, since the intrinsic layer 20a and the first conductive type layer 20b are formed by a resist pattern formed using a single mask, the number of masks and the manufacturing process can be reduced by manufacturing the bottom gate TFT. Is also achieved.

  Although the case where the positive resist 30 is used has been described in the present embodiment, a negative resist may be used instead of the positive resist 30. In this case, the mask used is different from that shown in FIG. FIG. 4 is a plan view schematically showing a negative resist mask. The mask 2 shown in FIG. 4 has a pattern in which the light shielding region 11 and the transmission region 12 of the mask 1 shown in FIG. 1 are interchanged. Specifically, in the mask 2, the light shielding film 14 is formed in a region corresponding to the first conductive type layer 20b of the TFT, and the transmissive region 12 is formed in a region corresponding to the second conductive type layers 20s and 20d. . By exposing the negative resist using the mask 2 shown in FIG. 4 and developing it, a resist 31 having a pattern shown in FIG. 2B can be formed.

(Embodiment 2)
In the first embodiment, the case where a TFT is manufactured using the CGS film 20 containing impurities has been described. In this embodiment, a case where a TFT is manufactured using an intrinsic semiconductor film will be described.

  FIG. 5 is a plan view schematically showing a mask used in this embodiment, and FIG. 6 is a sectional view schematically showing a TFT manufacturing process according to this embodiment. Note that the TFT manufactured according to this embodiment is the same as that according to Embodiment 1 shown in FIG. 2D, and therefore the description of the TFT manufactured according to this embodiment is omitted.

  The mask 3 shown in FIG. 5 includes a light shielding region 11 formed in a region corresponding to the intrinsic layer 21a, a transmissive region 12 formed in regions corresponding to the second conductivity type layers 21s and 21d, and a first conductivity type layer. And a gray tone region 13 formed in a region corresponding to 21b. As in the first embodiment, a light shielding film 14 is formed in the light shielding region 11, and a gray tone film 15 is formed in the gray tone region 13.

  With reference to FIG. 6, a process of manufacturing the TFT of the present embodiment using the mask 3 will be described. First, an intrinsic semiconductor film (for example, an amorphous silicon film or a low-temperature polysilicon film) 21 is formed on the insulating substrate 10. A positive resist 30 is formed on the semiconductor film 21. The positive resist 30 is exposed through the mask 3 and then developed to form a resist 31 having a pattern shown in FIG. The resist 30 corresponding to the transmission region 12 of the mask 3 is removed, and the semiconductor film 21 is exposed. On the other hand, the resist 30 corresponding to the light shielding region 11 and the gray tone region 13 of the mask 3 remains even after development. However, the developed resist 31 corresponding to the gray tone region 13 has a film thickness approximately half that of the developed resist 31 corresponding to the light shielding region 11.

As shown in FIG. 6B, phosphorus ions 40 as n-type impurities are implanted into the exposed semiconductor film 21 at a high concentration. The implantation concentration of phosphorus ions 40 is, for example, about 5 × 10 ¹⁵ atoms / cm ³ . Thereby, the source electrode 21s and the drain electrode 21d are formed as the second conductivity type layer doped with the n-type impurity at a high concentration.

As shown in FIG. 6C, ashing of the resist 31 is performed. Ashing can be performed by plasma etching, for example, as in the first embodiment. As a result, the resist 31 corresponding to the light shielding region 11 of the mask 3 has a film thickness of about half, and the resist 31 corresponding to the gray tone region 13 of the mask 3 is removed. Phosphorus ions 41 as n-type impurities are implanted into the exposed semiconductor film 21 at a low concentration. The implantation concentration of phosphorus ions 41 is, for example, about 5 × 10 ¹³ atoms / cm ³ . As a result, a first conductivity type layer 21b doped with n-type impurities at a low concentration is formed.

  After removing the resist 32 on the intrinsic layer 21a, the gate insulating film 60 and the gate electrode 70 are formed by photolithography or the like, whereby the TFT of this embodiment is manufactured.

  According to the present embodiment, as in the first embodiment, the manufacturing cost can be reduced and the manufacturing process can be shortened. Although the manufacturing process of the top gate type TFT has been described with reference to FIG. 6, the bottom gate type TFT can also be manufactured in the same manner. In the present embodiment, since the source electrode 21s and the drain electrode 21d are formed before the first conductivity type layer 21b is formed, the intrinsic layer 21a and the first conductivity type layer 21b are covered in the manufacturing process of the bottom gate TFT. There is no need to form a resist. Therefore, a mask and a process for forming a resist are not necessary.

  Although the case where the positive resist 30 is used has been described in the present embodiment, a negative resist may be used instead of the positive resist 30. In this case, the mask used is different from that shown in FIG. FIG. 7 is a plan view schematically showing a negative resist mask. The mask 4 shown in FIG. 7 has a pattern in which the light shielding region 11 and the transmission region 12 of the mask 3 shown in FIG. 5 are interchanged. Specifically, in the mask 4, the light shielding region 14 is formed in a region corresponding to the second conductive type layers 21 s and 21 d of the TFT, and the transmission region 12 is formed in a region corresponding to the intrinsic layer 21 a. By exposing and developing the negative resist using the mask 4 shown in FIG. 7, the resist 31 having the pattern shown in FIG. 6B can be formed.

  As mentioned above, although this invention was demonstrated based on embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Those skilled in the art will understand that the above-described embodiments are exemplifications, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. By the way.

  The transistor manufactured according to the present invention can be used as a drive element in a display device such as a liquid crystal display device or as a driver IC that controls the drive element.

2 is a plan view schematically showing a mask 1 used in Embodiment 1. FIG. 5 is a cross-sectional view schematically showing a TFT manufacturing process according to Embodiment 1. FIG. It is sectional drawing which shows the manufacturing process of bottom gate type TFT typically. It is a top view which shows typically the mask 2 for negative resists. It is a top view which shows typically the mask 3 used for Embodiment 2. FIG. 6 is a cross-sectional view schematically showing a TFT manufacturing process according to Embodiment 2. FIG. It is a top view which shows typically the mask 4 for negative resists.

1, 2, 3, 4 Mask 10 Insulating substrate 11 Light shielding region 12 Transmission region 13 Gray tone region 14 Light shielding film 15 Gray tone film 20 CGS film 20a Intrinsic layer 20b First conductivity type layer 20d Second conductivity type layer (drain electrode) )
20s Second conductivity type layer (source electrode)
21 Semiconductor film 21a Intrinsic layer 21b First conductivity type layer 21d Second conductivity type layer (drain electrode)
21s Second conductivity type layer (source electrode)
30, 31, 32 Positive resist 40, 41 Phosphorus ion 50 Boron ion 60 Gate insulating film 70 Gate electrode

Claims (5)

A mask for manufacturing a transistor for exposing a positive resist formed on a semiconductor layer containing an n-type impurity,
The transistor includes an intrinsic layer, a first conductivity type layer sandwiching the intrinsic layer in the plane direction and including an n-type impurity, a first conductivity type layer sandwiched in the plane direction, and the first conductivity type layer. And a second conductivity type layer containing a high concentration of n-type impurities,
A light-shielding region formed in a region corresponding to the second conductivity type layer, a transmission region formed in a region corresponding to the first conductivity type layer, and a region corresponding to the intrinsic layer; And a gray tone region that is higher than the light shielding region and lower than the transmission region. A mask for manufacturing a transistor for exposing a negative resist formed on a semiconductor layer containing an n-type impurity,
The transistor includes an intrinsic layer, a first conductivity type layer sandwiching the intrinsic layer in the plane direction and including an n-type impurity, a first conductivity type layer sandwiched in the plane direction, and the first conductivity type layer. And a second conductivity type layer containing a high concentration of n-type impurities,
A light shielding region formed in a region corresponding to the first conductivity type layer; a transmission region formed in a region corresponding to the second conductivity type layer; and a region corresponding to the intrinsic layer; And a gray tone region that is higher than the light shielding region and lower than the transmission region. A transistor manufacturing mask for exposing a negative resist formed on an intrinsic semiconductor layer,
The transistor includes an intrinsic layer, a first conductivity type layer sandwiching the intrinsic layer in the plane direction and including an n-type impurity, a first conductivity type layer sandwiched in the plane direction, and the first conductivity type layer. And a second conductivity type layer containing a high concentration of n-type impurities,
A light-shielding region formed in a region corresponding to the second conductivity type layer, a transmission region formed in a region corresponding to the intrinsic layer, and a region corresponding to the first conductivity type layer; And a gray tone region that is higher than the light shielding region and lower than the transmission region. A method of manufacturing a transistor using the mask according to claim 1, comprising:
Forming the resist on the semiconductor layer;
Forming the resist having a pattern in which a portion corresponding to the transmissive region is removed by developing after exposing the resist through the mask ; and
Implanting n-type impurities into the semiconductor layer corresponding to the transmissive region;
Removing the resist corresponding to the gray tone region after implanting the n-type impurity;
Implanting a p-type impurity into the semiconductor layer corresponding to the gray tone region. A method of manufacturing a transistor using the mask according to claim 3 , comprising:
Forming the resist on the semiconductor layer;
Forming the resist having a pattern in which a portion corresponding to the transmissive region is removed by developing after exposing the resist through the mask ; and
Implanting n-type impurities into the semiconductor layer corresponding to the transmissive region;
Removing the resist corresponding to the gray tone region after implanting the n-type impurity;
Injecting an n-type impurity at a lower concentration into the semiconductor layer corresponding to the gray tone region.

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