JP4703585B2 - Semiconductor integrated circuit and driving method of electrostatic actuator - Google Patents

Description

  The present invention relates to a micromachine or MEMS (Micro-Electro-Mechanical Systems) technology using an actuator. For example, the present invention relates to a semiconductor integrated circuit including a switch or a variable capacitance element using an electrostatic actuator, a MEMS, and an electrostatic The present invention relates to a method for driving a mold actuator.

  A structure of a MEMS switch using an electrostatic actuator is disclosed in Patent Document 1, for example. In order to close the MEMS switch, a potential difference is applied between the upper electrode and the lower electrode of the electrostatic actuator so that the electrostatic attractive force between these electrodes exceeds the spring force of the beam to which the upper electrode is fixed. To. Usually, in order to make a closed state, it is necessary to apply a potential difference of 20 V or more between the upper electrode and the lower electrode. Hereinafter, the absolute value of this potential difference is referred to as voltage Vs.

  In the MEMS switch in the closed state, the upper electrode and the lower electrode of the electrostatic actuator are in contact with each other through an insulating film. At this time, since there is a potential difference of 20 V or more between the upper electrode and the lower electrode, charges are injected into the insulating film and trapped by the FN tunnel or Pool-Frenkel mechanism. This phenomenon is called die-electric charging of an electrostatic actuator.

  When the amount of charge accumulated in the insulating film due to die electric charging becomes sufficiently large, even if the potential difference between the upper electrode and the lower electrode is set to 0 V, the upper electrode is attracted to the charge in the insulating film, and the switch is closed. It cannot be opened. This phenomenon is called stiction by dielectric charging.

  In order to suppress stiction, a method for biasing the voltage between the upper electrode and the lower electrode is described in Non-Patent Document 1 below. The points of this bias method are the following three points.

(1) The hold voltage Vh is made lower than the voltage Vs.

(2) The driving voltage applied to the upper and lower electrodes is reversed every time (bipolar actuation).

(3) Continue to apply positive and negative pulses of amplitude Vh in the switch hold state.

Here, the hold voltage Vh is a potential difference between the upper electrode and the lower electrode necessary to keep the closed state (hold state) after the open switch is closed. Since the electrostatic attractive force between the upper electrode and the lower electrode is proportional to the square of the reciprocal of the distance between both electrodes, the hold voltage Vh can be made lower than the voltage Vs.

Although it is possible to reduce the amount of charge trapped in the insulating film by the bias method consisting of the three points (1) to (3), it cannot be completely eliminated. This is because the amount of charge injected is different between periods in which a positive pulse and a negative pulse are applied. This is because the charge injection mechanism is not symmetrical. Therefore, if the switching of the positive voltage pulse and the negative voltage pulse is repeated for a sufficiently long time in the hold state, the amount of charge in the insulating film gradually increases, and finally stiction occurs.
US Pat. No. 5,578,976 GMRebeiz, "RF MEMS Theory, Design, and Technology", Wiley-Interscience, 2003, pp.190-191.

  The present invention has been made in view of such a situation. A semiconductor integrated circuit, a MEMS, and a static circuit that can drive an electrostatic actuator so as not to cause a malfunction even when a sufficiently long time has passed in a hold state. It is an object of the present invention to provide a method for driving an electric actuator.

  According to a first aspect of the present invention, there is provided a semiconductor integrated circuit including an upper electrode, a lower electrode, an electrostatic actuator having an insulating film disposed between the upper electrode and the lower electrode, and the electrostatic actuator Based on a detection circuit for detecting the amount of charge accumulated in the insulating film, a storage circuit for storing the detection result of the charge amount detected by the detection circuit, and the detection result stored in the storage circuit And a bias circuit for changing a driving voltage for driving the electrostatic actuator.

A semiconductor integrated circuit according to a second embodiment of the present invention includes an upper electrode, a lower electrode, an electrostatic actuator having an insulating film disposed between the upper electrode and the lower electrode, and the electrostatic actuator A detection circuit for detecting whether or not the amount of charge accumulated in the insulating film is within a predetermined range; and detecting that the amount of charge accumulated in the insulating film is not within the predetermined range When this is done, a drive voltage is applied between the upper electrode and the lower electrode so that the charge amount falls within a predetermined range, and either injection or extraction of charges is performed on the insulating film. And a bias circuit to be performed.

A micro-electro-mechanical system (MEMS) according to a third embodiment of the present invention includes a lower electrode formed on a substrate, an upper electrode disposed so that a cavity exists between the lower electrode, and the upper electrode. An electrostatic actuator having a first insulating film disposed between an electrode and the lower electrode, a first electrode formed on the substrate and spaced apart from the lower electrode, and the upper electrode A second electrode formed through an insulator between the second electrode disposed to face the first electrode and the lower electrode while a driving voltage is applied to the upper electrode of the electrostatic actuator. A bias circuit having the electrode as a ground voltage and the upper electrode as the ground voltage while the drive voltage is applied to the lower electrode, and the bias circuit supplies the drive voltage and the ground voltage as the upper electrode. And above By applying the electrodes, the electrostatic actuator is characterized by varying the distance between the second electrode and the first electrode.

An electrostatic actuator driving method according to a fourth embodiment of the present invention is an electrostatic actuator driving method having an upper electrode, a lower electrode, and an insulating film disposed between the upper electrode and the lower electrode. Detecting the power-on and command input, and detecting either the power-on or command input, the amount of charge accumulated in the insulating film falls within a predetermined range. Detecting whether or not the charge amount accumulated in the insulating film is not within a predetermined range, so that the charge amount is within a predetermined range, And a step of either injecting or extracting charge from the insulating film.

  According to the present invention, there is provided a semiconductor integrated circuit, a MEMS, and an electrostatic actuator driving method capable of driving an electrostatic actuator so as not to cause a problem even if a sufficiently long time has passed in a hold state. Can be provided.

  Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

  Usually, there are the following two methods for driving the electrostatic actuator to lower the upper electrode, that is, moving the upper electrode to the lower electrode side and bringing the upper electrode into contact with the insulating film on the lower electrode.

(A) The voltage Vs is applied to the upper electrode, and the lower electrode is set to the ground voltage.

(B) The voltage Vs is applied to the lower electrode, and the upper electrode is set to the ground voltage.

As described above, in a state where the upper electrode is lowered, a high electric field is applied to the insulating film disposed on the lower electrode, so that dielectric charging occurs. However, since the directions of the electric field applied to the insulating film are different between (a) and (b), the sign of the charge injected into the insulating film is different. For example, when a laminated film of a silicon nitride film (SiN) and a silicon oxide film (SiO ₂ ) is employed as the insulating film, electrons are injected into the insulating film in the case of (a), and the upper electrode is separated from the insulating film. The pull-out voltage of FIG. 1A shows how the CV characteristics change at this time. Here, the voltage “Vtop−Vbtm” is a potential difference between the upper electrode and the lower electrode, and the capacitor Ces is a capacitor of the insulating film disposed between the upper electrode and the lower electrode. In the case of (b), the CV characteristic changes as shown in FIG. 1B. Therefore, when Vs> 0, in any case, the pull-out voltage Vpo moves in the direction of decreasing with respect to the absolute value of the voltage “Vtop−Vbtm”. Therefore, if the operation is continued without changing the sign of the voltage “Vtop−Vbtm”, stiction eventually occurs. The point of the embodiment of the present invention is to prevent defects due to stiction by using the bias methods (a) and (b) properly according to the amount of charge injected into the insulating film. In other words, by changing the direction of the electric field between the upper electrode and the lower electrode in accordance with the amount of charge injected into the insulating film, the amount of charge injected into the insulating film is maintained within a certain range.

  The direction of the electric field applied to the insulating film and the sign of the electric charge injected into the insulating film may vary depending on the type of the insulating film and the location of the trap, but in the following, mainly as shown in FIGS. 1A and 1B. In the following description, it is assumed that the CV characteristics change. The case where the pull-out voltage Vpo moves in the direction in which the pull-out voltage Vpo decreases with respect to the absolute value of the voltage “Vtop−Vbtm” is referred to as a first type of charge injection. Obviously, however, when the CV characteristic changes as shown in FIGS. 1C and 1D, that is, when the pull-out voltage Vpo moves in an increasing direction with respect to the absolute value of the voltage “Vtop−Vbtm” (the second type of charge injection and The embodiment of the present invention can also be applied. When the CV characteristic changes as shown in FIGS. 1C and 1D, the drive voltage rises and pull-in does not occur, that is, the upper electrode does not contact the insulating film.

  FIG. 1E is a diagram showing a configuration of a semiconductor integrated circuit that realizes the first to sixth embodiments of the present invention described below. The semiconductor integrated circuit includes a MEMS unit 10 and a circuit unit 20. The MEMS unit 10 and the circuit unit 20 may be formed in the same semiconductor chip, or may be separated into different chips. The circuit unit 20 includes a charge accumulation amount detection circuit 21, a storage circuit 22, a bias circuit 23, and a controller 24. The node Ntop is a node that connects the bias circuit 23 and the upper electrode 17, and the node Nbot is a node that connects the bias circuit 23 and the lower electrode 15. The node N1 is a node that connects between the charge accumulation amount detection circuit 21 and the bias circuit 23. The charge accumulation amount detection circuit 21 is a circuit that detects the amount of charge accumulation trapped in the insulating film 16 on the lower electrode 15 in the electrostatic actuator. The detection result of the charge accumulation amount by the charge accumulation amount detection circuit 21 is stored in a storage circuit 22 such as a register. The bias circuit 23 supplies a drive voltage (bias voltage) for driving the electrostatic actuator to the lower electrode 15 and the upper electrode 17 based on the detection result (charge accumulation amount) stored in the storage circuit 22.

  Hereinafter, the MEMS unit 10 in FIG. 1E will be described in detail.

  The MEMS unit 10 includes an electrostatic actuator 11. The MEMS unit 10 has a structure in which one end of an elastic member 14 is fixed to an anchor 13 on a semiconductor substrate 12, and a cavity 30 is provided between the semiconductor substrate 12 and the elastic member 14. A lower electrode 15 is formed on the semiconductor substrate 12, and an insulating film 16 is formed on the lower electrode 15 so as to cover the lower electrode 15. An upper electrode 17 is formed on one surface of the elastic member 14 so as to face the lower electrode 15. In the MEMS part 10 having such a structure, when the electrostatic actuator 11 is driven, the central part of the elastic member 14 is deformed so as to approach the semiconductor substrate 12, and the upper electrode 17 moves to the lower electrode 15 side. Thus, the upper electrode 17 contacts the insulating film 16 on the lower electrode 15. Thus, a mechanism in which the distance between the elastic member 14 and the semiconductor substrate 12 changes is used for the switch and the variable capacitance element.

  In FIG. 1E, only the electrostatic actuator 11 is schematically shown as the MEMS unit 10, but the present invention can be applied to various devices including the electrostatic actuator, such as switches and variable capacitance elements.

  FIG. 2 is a cross-sectional view of the MEMS portion when the electrostatic actuator is applied to a contact switch. The first electrode 18 and the second electrode 19 constitute a contact type switch. A first electrode 18 is formed on the semiconductor substrate 12 adjacent to the lower electrode 15, and a second electrode adjacent to the upper electrode 17 is formed on one surface of the elastic member 14 facing the first electrode 18. An electrode 19 is formed. In the MEMS portion having such a structure, when the electrostatic actuator 11 is driven, the upper electrode 17 moves to the lower electrode 15 side, and the upper electrode 17 contacts the insulating film 16 on the lower electrode 15. Thereby, the 1st electrode 18 and the 2nd electrode 19 contact and are electrically connected, and a contact type switch will be in a closed state. On the other hand, when the electrostatic actuator 11 is not driven, a cavity is formed between the lower electrode 15 and the upper electrode 17. Thereby, the 1st electrode 18 and the 2nd electrode 19 become non-contact, and a contact type switch will be in an open state.

  FIG. 3 is a cross-sectional view of the MEMS portion when the electrostatic actuator is applied to a variable capacitance element. The first electrode 18, the second electrode 19, and the insulating film 16 disposed between the first electrode and the second electrode constitute a variable capacitance element. On the semiconductor substrate 12, a first electrode 18 is formed adjacent to the lower electrode 15, and an insulating film 16 is disposed so as to cover the first electrode 18. A second electrode 19 is formed adjacent to the upper electrode 17 on one surface of the elastic member 14 facing the first electrode 18. In the MEMS portion having such a structure, when the electrostatic actuator 11 is driven, the upper electrode 17 moves to the lower electrode 15 side, and the upper electrode 17 contacts the insulating film 16 on the lower electrode 15. As a result, the insulating film 16 on the first electrode 18 and the second electrode 19 come into contact with each other, and the variable capacitance element has a first capacitance. On the other hand, when the electrostatic actuator 11 is not driven, a cavity is formed between the lower electrode 15 and the upper electrode 17. As a result, the insulating film 16 on the first electrode 18 and the second electrode 19 are not in contact with each other, and the variable capacitance element has a second capacitance smaller than the first capacitance.

  As shown in FIG. 4, the present invention can also be applied to a hybrid actuator in which an electrostatic actuator and an actuator 31 other than an electrostatic actuator are combined. As actuators other than the electrostatic type, there are a piezoelectric type, a thermal type, an electromagnetic type, and the like. When the hybrid type actuator is employed, the upper electrode 17 can be moved to the lower electrode 15 side by the actuator 31 other than the electrostatic type, so that the driving voltage of the electrostatic type actuator 11 can be lowered.

[First Embodiment]
A semiconductor integrated circuit according to a first embodiment of the present invention will be described.

  FIG. 5 is a diagram illustrating a configuration of the semiconductor integrated circuit according to the first embodiment. As described above, the semiconductor integrated circuit includes the MEMS unit 10 and the circuit unit 20. The MEMS unit 10 includes an electrostatic actuator 11 having a capacitance Ces. The circuit unit 20 includes a charge accumulation amount detection circuit 21, a storage circuit 22, a bias circuit 23, and a controller 24.

  The bias circuit 23 includes a voltage generation circuit 25 and switch elements SW1, SW2, SW3, SW4. By switching these switch elements SW1, SW2, SW3, SW4, the output voltage of the voltage generation circuit 25 is switched to the upper electrode 17 (node Ntop) or the lower electrode 15 (node Nbot) of the electrostatic actuator 11 and output. . At this time, the ground voltage GND is supplied to the upper electrode 17 or the lower electrode 15 to which the voltage generating circuit 25 is not connected. That is, when the switch elements SW1 and SW4 are closed, the switch elements SW2 and SW3 are opened, and conversely when the switch elements SW1 and SW4 are open, the switch elements SW2 and SW3 are closed. Which switch element is opened or closed is determined based on data stored in the memory circuit 22. The data indicates the charge accumulation amount in the insulating film 16 detected by the charge accumulation amount detection circuit 21.

  FIG. 6A is a circuit diagram of the charge accumulation amount detection circuit 21 in the circuit unit 20. The capacitance Ces is a capacitance between the upper electrode 17 and the lower electrode 15 of the electrostatic actuator 11. The value of the capacitance Ces when the upper electrode 17 of the electrostatic actuator 11 is lowered is assumed to be a capacitance Cdown, and the value of the capacitance Ces when the upper electrode 17 is raised is assumed to be a capacitance Cup. The capacity Cdown is larger than the capacity Cup. The value of the fixed capacitor Cref is generally set to an intermediate value between the capacitor Cup and the capacitor Cdown (Cref≈ (Cup + Cdown) / 2).

  The connection relationship of the charge accumulation amount detection circuit 21 is as follows. The output voltage Ves of the voltage generation circuit 25 is supplied to the upper electrode 17 via the switch element S5, and the ground voltage GND is supplied to the lower electrode 15. The output voltage Ves is supplied to one electrode of the capacitor having the fixed capacitor Cref via the switch element S6, and the ground voltage is supplied to the other electrode. A constant voltage V1 is supplied to one electrode of the first capacitor having a constant capacitance C1 via the switch element S1, and a ground voltage is supplied to the other electrode. Similarly, a constant voltage V1 is supplied to one electrode of the second capacitor having a constant capacitance C1 via the switch element S2, and a ground voltage is supplied to the other electrode.

  One end (node N11) of the switch element S3 is connected to the connection point between the upper electrode 17 and the switch element S5, the other end of the switch element S3 is connected to the positive input terminal of the comparator CP, and the first capacitor C1. Is connected to the connection point of the switch element S1. One end of the switch element S4 (node N12) is connected to the connection point between one electrode of the capacitor having the fixed capacitance Cref and the switch element S6, and the other end of the switch element S4 is connected to the negative input terminal of the comparator CP. And connected to the connection point between one electrode of the second capacitor C1 and the switch element S2. Then, an output voltage Vout corresponding to the comparison result of the voltages input to the positive input terminal and the negative input terminal of the comparator CP is output from the output terminal of the comparator CP. 6A, a circuit in which a sense amplifier SA is arranged instead of the comparator CP may be used as shown in FIG. 6B.

  In addition, when the MEMS unit 10 and the circuit unit 20 are configured by separate semiconductor chips, it is desirable that the fixed capacitor Cref is formed on the same chip as the MEMS unit 10. If they are not formed on the same chip, the values of the parasitic capacitance and the parasitic resistance are different, and the accuracy of the charge accumulation amount detection operation is lost. The constant voltage V1 is higher than the voltage VmonH and the voltage VmonL described later.

  Further, a period during which the output voltage Ves of the voltage generation circuit 25 is supplied to the upper electrode 17 is referred to as mode 1, and a period during which the output voltage Ves is supplied to the lower electrode 15 is referred to as mode 2. It is assumed that the pull-out voltage drops in mode 1 and rises in mode 2 due to dielectric charging. In the present embodiment, the pull-out voltage is monitored every time the voltage application sequence is completed, and the mode 1 and the mode 2 are switched so that the pull-out voltage is within a predetermined range. This means that the amount of charge trapped in the insulating film of the electrostatic actuator 11 falls within an appropriate range. Specifically, it is carried out as follows.

  FIG. 7 is a voltage waveform of the output voltage Ves of the voltage generation circuit 25 in mode 1, and FIG. 8 is a voltage waveform during the charge accumulation amount detection operation in mode 1. FIG. 9 is a voltage waveform of the output voltage Ves of the voltage generation circuit 25 in mode 2. FIG. 10 is a voltage waveform during the charge accumulation amount detection operation in mode 2. FIG. 11A is a flowchart illustrating the operation of the semiconductor integrated circuit according to the first embodiment.

  Periods T1 and T2 in FIGS. 7 and 9 are periods in which the electrostatic actuator 11 is driven. More specifically, the period T1 is a period during which the upper electrode 17 is moved to the lower electrode 15 side, and the period T2 is a period during which the upper electrode 17 is held in contact with the insulating film 16 (hold period). . The length of the period T2 varies depending on the usage status of the application and device. When there is not much dielectric charging in the period T1, the hold voltage Vh in the period T2 may be set to the voltage Vs1 or the voltage Vs2. The period T3 is assigned to the operation of detecting the charge accumulation amount in the insulating film 16. The period T3 can be about 100 nsec, and is sufficiently shorter than the periods T1 (about 20 μs) and the period T2 (about 1 ms to 1H). Therefore, there is almost no performance degradation due to the addition of the period T3. During the period T3, the output voltage Ves of the voltage generation circuit 25 is set to the voltage VmonL in the mode 1 and set to the voltage VmonH in the mode 2. 8 and 10, the switches S1, S2,..., S6 are closed when the voltage waveform is at “H” level.

  When the voltage waveform of mode 1 shown in FIG. 7 is continuously applied, the pull-out voltage Vpo gradually decreases as shown in FIG. 12A. As a result of the charge accumulation amount detection operation by the charge accumulation amount detection circuit 21, if the pullout voltage Vpo is higher than the voltage VmonL, the mode 1 is continued thereafter. On the other hand, when the pull-out voltage Vpo becomes lower than the voltage VmonL, the mode 2 is shifted thereafter. Information for determining which mode to execute is stored in the storage circuit 22. That is, if the pull-out voltage Vpo is higher than the voltage VmonL, the charge accumulation amount detection circuit 21 stores the first data in the storage circuit 22, and if the pull-out voltage Vpo is lower than the voltage VmonL, the charge storage amount detection circuit 21 stores the second data in the storage circuit 22. Store the data. The controller 24 executes mode 1 when the first data is stored in the storage circuit 22, and executes mode 2 when the second data is stored.

The level relationship between the pullout voltage Vpo and the voltage VmonL can be detected by the charge accumulation amount detection circuit 21 shown in FIG. 6A. The potential difference ΔV between the node N11 and the node N12 is expressed by the following equation (1).

  Therefore, by monitoring the output voltage Vout of the comparator CP in FIG. 6A, the magnitude of the capacitance Ces and the capacitance Cref can be known, and from this, the level of the pullout voltage Vpo and the voltage VmonL can be seen.

  Similarly, when the voltage waveform of mode 2 is continuously applied, the pullout voltage Vpo gradually increases as shown in FIG. 12B. When the pull-out voltage Vpo exceeds the voltage VmonH, the mode 1 is shifted thereafter. That is, if the pull-out voltage Vpo is higher than the voltage VmonH (if the absolute value is small), the charge accumulation amount detection circuit 21 stores the first data in the memory circuit 22, and when the pull-out voltage Vpo is lower than the voltage VmonH. When the absolute value is large, the second data is stored in the storage circuit 22. The controller 24 executes mode 1 when the first data is stored in the storage circuit 22, and executes mode 2 when the second data is stored.

  In the following, the operation in mode 1 and mode 2 will be described using the flowchart shown in FIG. 11A. In mode 1, the following operation is performed. First, the output destination of the voltage generation circuit 25 is set to the upper electrode 17 by the switch elements SW1 to SW4, the voltage Vs is applied to the upper electrode 17 by the bias circuit 23 (period T1), and the electrostatic actuator 11 is driven. (Step S1). Subsequently, a hold voltage Vh is applied to the upper electrode 17 by the bias circuit 23 (period T2), and the electrostatic actuator 11 is put into a hold state (step S2).

  Further, the voltage VmonL is applied to the upper electrode 17 by the bias circuit 23 (period T3), and the charge accumulation amount accumulated in the insulating film 16 of the electrostatic actuator is detected by the charge accumulation amount detection circuit 21 shown in FIG. 6A. (Step S3). It is detected whether or not the charge accumulation amount in the insulating film 16 is larger than a predetermined charge amount, that is, whether or not the capacitance Ces between the upper electrode 17 and the lower electrode 15 is larger than the fixed capacitance Cref (step S4). When the capacity Ces is not larger than the fixed capacity Cref, the process proceeds to step S1, the electrostatic actuator 11 is driven, and the processes after step S2 are repeated. On the other hand, when the capacitor Ces is larger than the fixed capacitor Cref, the second data is stored in the storage circuit 22, and the switch elements SW1 to SW4 are set so that the output destination of the voltage generation circuit 25 is switched to the lower electrode 15 (step). S5).

  Thereafter, the mode is shifted to mode 2, and in mode 2, the following operation is performed. A voltage Vs is applied to the lower electrode 15 by the bias circuit 23 (period T1), and the electrostatic actuator 11 is driven (step S6). Subsequently, the hold circuit Vh is applied to the lower electrode 15 by the bias circuit 23 (period T2), and the electrostatic actuator 11 is placed in the hold state (step S7).

  Further, the voltage VmonH is applied to the lower electrode 15 by the bias circuit 23 (period T3), and the charge accumulation amount accumulated in the insulating film 16 of the electrostatic actuator is detected by the charge accumulation amount detection circuit 21 shown in FIG. 6A. (Step S8). It is detected whether or not the charge accumulation amount of the insulating film 16 is larger than a predetermined charge amount, that is, whether or not the capacitance Ces between the upper electrode 17 and the lower electrode 15 is larger than the fixed capacitance Cref (step S9). When the capacity Ces is not larger than the fixed capacity Cref, the process proceeds to step S6, the electrostatic actuator 11 is driven, and the processes after step S7 are repeated. On the other hand, when the capacitance Ces is larger than the fixed capacitance Cref, the first data is stored in the storage circuit 22, and the switch elements SW1 to SW4 are set so that the output destination of the voltage generation circuit 25 is switched to the upper electrode 17 (step). S10). Thereafter, the mode is shifted to mode 1.

  FIG. 13 shows a potential difference between the upper electrode voltage (Vtop) and the lower electrode voltage (Vbtm) during continuous operation of the semiconductor integrated circuit. In FIG. 13, the voltages Vs1 and Vs2 which are the magnitudes of the voltage amplitudes are not necessarily the same. Similarly, the hold voltages Vh1 and Vh2 may be changed between modes 1 and 2.

  As described above, by operating according to the flowchart shown in FIG. 11A, when the voltage “Vtop−Vbtm” is positive or negative, the absolute value of the pullout voltage Vpo is set higher than the absolute value of the voltage VmonL or the voltage VmonH, respectively. Can be bigger. This corresponds to measuring the amount of charge in the insulating film 16 in the electrostatic actuator 11 and controlling the amount of charge in the insulating film 16 within a range that does not cause defects such as stiction. Accordingly, it is possible to provide a semiconductor integrated circuit including the electrostatic actuator 11 that does not cause stiction even when the electrostatic actuator 11 is held in a hold state for a sufficiently long time. The reason why the voltages VmonL and VmonH are set to different values is that a case is assumed in which the margin of the pullout voltage Vpo for preventing stiction varies depending on the direction of the electric field. However, depending on the type of the insulating film 16, the margin may be considered not to depend on the direction of the electric field. In that case, the voltage VmonL and the voltage VmonH may be the same value. That is, VmonL = VmonH = Vmon. FIG. 11B shows a flowchart in this case, and FIG. 11C shows a state when the operation is continuously performed. The embodiment of the present invention is characterized in that the direction of the electric field between the upper electrode 17 and the lower electrode 15 is determined according to the value of the pull-out voltage Vpo as described above. The pull-out voltage Vpo is determined from the capacitance value at a certain monitor voltage.

  Note that when the second type of charge injection described above is applied to the embodiment of the present invention, the flowchart shown in FIG. 11D may be adopted. The values of the voltage VmonL and the voltage VmonH at this time are determined in consideration of a margin so that a defect that does not cause pull-in does not occur. In the case of the second type of charge injection, VmonL = VmonH = Vmon may be used if the margin can be regarded as independent of the direction of the electric field. A flowchart in this case is shown in FIG. 11E.

  Next, a semiconductor integrated circuit according to a modification of the first embodiment will be described.

  FIG. 14 is a diagram illustrating a configuration of a semiconductor integrated circuit according to a modification of the first embodiment. In the first embodiment, the output destination of the output voltage of the voltage generation circuit 25 is switched to the upper electrode 17 or the lower electrode 15 by the switch elements SW1 to SW4 shown in FIG. On the other hand, in the modified example of the first embodiment, as shown in FIG. 14, the switch element for switching the output destination of the output voltage of the voltage generation circuit 25 is eliminated, and the voltage generation circuit 25 has a positive or negative output voltage. Is output to the upper voltage 17, and the ground voltage GND is supplied to the lower electrode 15. At this time, the waveform of the applied voltage applied between the upper electrode 17 and the lower electrode 15 is shown in FIG. Other configurations and effects are the same as those in the first embodiment. In this modification, the output voltage of the voltage generation circuit 25 is always supplied to the upper electrode 17. Conversely, the output voltage of the voltage generation circuit 25 is always supplied to the lower electrode 15. It may be.

  In the first embodiment described above and its modification, a constant hold voltage Vh is applied in the period T2 in mode 1 as shown in FIG. 7, but a bipolar voltage is applied as shown in FIG. 16A. A waveform may be applied. The bipolar voltage waveform refers to a waveform in which a positive hold voltage (Vh) and a negative hold voltage (−Vh) are alternately switched every certain period (pulse width).

  Although such a bipolar voltage waveform cannot completely eliminate dielectric charging, it is possible to reduce the amount of charge accumulated in the insulating film 16. When the holding period of the electrostatic actuator 11 is long and dielectric charging during the holding period cannot be ignored, it is effective to apply such a bias waveform, that is, a bipolar voltage waveform. Here, as the bipolar voltage waveform, a waveform in which positive or negative hold voltages having the same pulse width and amplitude are alternately switched is shown. However, the present invention is not limited to this, and the amplitude gradually increases with the same pulse width. A waveform in which positive or negative voltage changing alternately (see mode 2 in FIG. 20B), or a waveform in which positive or negative voltage with gradually changing pulse width with the same amplitude is switched alternately (mode 2 in FIG. 20C). For example, a waveform (see mode 2 in FIG. 20D) in which a positive voltage or a negative voltage in which both the amplitude and the pulse width are gradually changed may be used. Further, in the first embodiment and its modification, the pull-out voltage is monitored and the actuator is driven so that the pull-out voltage falls within a predetermined range. However, the pull-in voltage is monitored instead of the pull-out voltage. The actuator may be driven so that the voltage falls within a predetermined range. FIG. 16B is a voltage waveform of the output voltage of the voltage generation circuit 25 at this time. As shown in FIG. 16B, the pull-in voltage is monitored in the period T0 of the start of the voltage application sequence. That is, it is possible to detect the amount of charge accumulated in the insulating film 16 by determining whether or not the actuator pull-in occurs based on the output voltage Vmon applied during this period T0.

[Second Embodiment]
Next, a semiconductor integrated circuit according to a second embodiment of the present invention will be described. The same parts as those in the first embodiment are denoted by the same reference numerals.

  In the first embodiment, the charge accumulation amount in the insulating film 16 is monitored by detecting the capacitance value at a predetermined voltage by the charge accumulation amount detection circuit 21 shown in FIG. 6A. However, the circuit configuration of the charge accumulation amount detection circuit 21 may be other than this. In the second embodiment, another circuit configuration example of the charge accumulation amount detection circuit 21 used in the first embodiment will be described.

  FIG. 17 is a circuit diagram of a charge accumulation amount detection circuit according to the second embodiment. FIG. 18 is a waveform at the time of detection operation in the charge accumulation amount detection circuit, and FIG. 19 is a flowchart showing the operation of the semiconductor integrated circuit of the second embodiment.

  The bias circuit 23 applies a voltage Vs to the upper electrode 17 to drive the electrostatic actuator 11 (step S21). Subsequently, the bias circuit 23 applies the hold voltage Vh to the upper electrode 17 to place the electrostatic actuator 11 in the hold state (step S22). Then, the charge accumulation amount accumulated in the insulating film 16 of the electrostatic actuator is detected by the charge accumulation amount detection circuit 21 shown in FIG. 17 (step S23). It is detected whether or not the voltage VN23 is higher than the voltage VrefL and lower than the voltage VrefH from the charge accumulation amount accumulated in the insulating film 16 (step S24). When VrefL <VN23 <VrefH is established, the process proceeds to step S21, and the processes after step S21 are repeated. On the other hand, when VrefL <VN23 <VrefH does not hold, the switch elements SW1 to SW4 are set so that the second data is stored in the storage circuit 22 and the output destination of the voltage generation circuit 25 is switched to the lower electrode 15 ( Step S25). Then, it transfers to step S21 and repeats the process after step S21.

  In the second embodiment, in the charge accumulation amount detection mode, the voltage applied to the electrostatic actuator 11 is gradually lowered from the hold voltage Vh. If a circuit using the current source I as shown in FIG. 17 is employed, a linear voltage drop of the hold voltage Vh can be realized. When the voltage at the node N21 falls and reaches the pull-out voltage, the upper electrode 17 rises and the capacitance Ces falls. When the capacitance Ces decreases while the charge amount of the node N21 is kept constant, the voltage of the node N21 increases. The comparator CP1 detects the voltage increase at the node N21. Actually, there is a voltage drop from the node N21 due to the current source circuit, but the effect is sufficiently small and does not suppress the voltage rise at the node N21.

  If the value of the capacitor Cref1 is set to the same level as the capacitor Cdown and the start of discharge from the node N21 is made earlier than the start of discharge from the node N22, the comparator when the value of the capacitor Ces changes as shown in FIG. The output voltage Vout1 of CP1 can be inverted. In response to the inversion of the output voltage Vout1, the switch S16 is opened to stop the discharge from the node N23. The voltage VN23 at the node N23 at this time reflects the pull-out voltage of the electrostatic actuator. That is, the level of the voltage VN23 corresponds to the level of the pullout voltage. Therefore, the charge accumulation amount in the insulating film 16 can be obtained from the voltage VN23. If the lower limit and the upper limit of the voltage VN23 corresponding to the charge accumulation amount in the insulating film 16 that does not cause a defect are the voltage VrefL and the voltage VrefH, respectively, the circuit and the flowchart shown in FIGS. Can be maintained at an appropriate value. About another structure and effect, it is the same as that of 1st Embodiment mentioned above.

[Third Embodiment]
Next, a semiconductor integrated circuit according to a third embodiment of the present invention will be described. The same parts as those in the first embodiment are denoted by the same reference numerals.

  In the first embodiment, the charge accumulation amount detection operation is performed at the end of mode 1 and mode 2, and when the determination criterion is exceeded, the voltage applied between the upper electrode and the lower electrode is inverted. On the other hand, in the third embodiment, when the criterion is exceeded, the operation of extracting the charge in the insulating film 16 is concentrated.

  FIG. 20A shows a voltage waveform of the output voltage Ves of the voltage generation circuit 25 in the third embodiment. In the third embodiment, mode 2 is assigned to a dedicated operation for extracting charges from the insulating film 16. That is, in mode 2, the hold voltage Vh is not applied, and only the charge accumulation amount detection operation by applying the voltage Vs2 and the voltage VmonH is performed. The application of the voltage Vs2 and the voltage VmonH is repeated until the pullout voltage reaches the voltage VmonH. FIG. 21 is a flowchart showing the operation of the semiconductor integrated circuit according to the third embodiment.

  In mode 1, the following operation is performed. First, the output destination of the voltage generation circuit 25 is set to the upper electrode 17 by the switch elements SW1 to SW4, the voltage Vs is applied to the upper electrode 17 by the bias circuit 23 (period T1), and the electrostatic actuator 11 is driven. (Step S31). Subsequently, the hold circuit Vh is applied to the upper electrode 17 by the bias circuit 23 (period T2), and the electrostatic actuator 11 is placed in the hold state (step S32).

  Further, the voltage VmonL is applied to the upper electrode 17 by the bias circuit 23 (period T3), and the charge accumulation amount accumulated in the insulating film 16 of the electrostatic actuator is detected by the charge accumulation amount detection circuit 21 shown in FIG. 6A. (Step S33). It is detected whether or not the charge accumulation amount of the insulating film 16 is larger than a predetermined charge amount, that is, whether or not the capacitance Ces between the upper electrode 17 and the lower electrode 15 is larger than the fixed capacitance Cref (step S34). When the capacity Ces is larger than the fixed capacity Cref, the process proceeds to step S31, and the processes after step S31 are repeated. On the other hand, when the capacitance Ces is not larger than the fixed capacitance Cref, the second data is stored in the storage circuit 22, and the switch elements SW1 to SW4 are set so that the output destination of the voltage generation circuit 25 is switched to the lower electrode 15 ( Step S35).

  Thereafter, the mode is shifted to mode 2 and the following operation is performed. The bias circuit 23 applies the voltage Vs to the lower electrode 15 (period T1), and drives the electrostatic actuator 11 (step S36). Subsequently, a voltage VmonH is applied to the lower electrode 15 by the bias circuit 23 (period T3), and the charge accumulation amount accumulated in the insulating film 16 of the electrostatic actuator is detected by the charge accumulation amount detection circuit 21 shown in FIG. 6A. Detection is performed (step S37). It is detected whether or not the charge accumulation amount of the insulating film 16 is larger than a predetermined charge amount, that is, whether or not the capacitance Ces between the upper electrode 17 and the lower electrode 15 is larger than the fixed capacitance Cref (step S38). When the capacity Ces is larger than the fixed capacity Cref, the process proceeds to step S36, and the processes after step S36 are repeated. On the other hand, when the capacitance Ces is not larger than the fixed capacitance Cref, the first data is stored in the storage circuit 22 and the switch elements SW1 to SW4 are set so that the output destination of the voltage generation circuit 25 is switched to the upper electrode 17 ( Step S39). Thereafter, the mode is shifted to mode 1. Note that VmonL = VmonH = Vmon may be used for the same reason as in the first embodiment.

  In order to clarify the difference from the first embodiment, FIG. 22A shows a schematic diagram of the transition of the charge accumulation amount in the insulating film 16 of the third embodiment, and FIG. 22B shows the transition in the insulating film 16 of the first embodiment. The schematic diagram of transition of the charge accumulation amount is shown. The charge amount Qmax and the charge amount Qmin are the maximum value and the minimum value of the charge accumulation amount that do not cause defects. That is, the maximum and minimum values of the charge accumulation amount in the insulating film 16 that the electrostatic actuator 11 can pull in with the hold voltage without causing stiction. In the third embodiment, the charge accumulation amount in the insulating film 16 decreases rapidly, but in the first embodiment, the charge accumulation amount in the insulating film 16 gradually decreases.

  FIGS. 20A and 21 correspond to the case where the circuit shown in FIG. 6A or 6B is adopted as the charge accumulation amount detection circuit. This third embodiment is the same as that of FIG. 17 described in the second embodiment. It can also be realized by a charge accumulation amount detection circuit. Further, the roles of mode 1 and mode 2 in FIG. 20A may be exchanged. That is, the period during which the hold voltage Vh is applied is eliminated from the mode 1, and the mode 1 is set as a dedicated operation mode for returning the charge amount in the insulating film 16 to the initial value of the mode 2, and the hold voltage Vh is set in the mode 2. You may make it apply. Further, as shown in FIG. 20B, the voltage amplitude of the voltage Vs2 in the mode 2 may be changed, and as shown in FIG. 20C, the pulse width of the voltage Vs2 in the mode 2 may be changed. Furthermore, as shown in FIG. 20D, both the voltage amplitude and the pulse width of the voltage Vs2 in mode 2 may be changed. As a result, the amount of charge extracted from the insulating film 16 can be easily controlled, and defects due to excessive charge extraction can be suppressed. Note that the method of changing the voltage amplitude and / or pulse width of the voltage Vs2 shown in FIGS. 20B, 20C, and 20D can be applied to embodiments other than the third embodiment.

[Fourth Embodiment]
Next, a semiconductor integrated circuit according to a fourth embodiment of the present invention will be described. The same parts as those in the first embodiment are denoted by the same reference numerals.

  In the first to third embodiments described above, it is assumed that the dielectric charging during the hold period is sufficiently small. However, when the hold period is sufficiently long, or when an insulating film in which charges are easily trapped is employed, dielectric charging during the hold period cannot be ignored. In such a case, stiction may occur after the end of the hold period. On the other hand, there may be a phenomenon in which pull-in cannot be performed with the hold voltage, that is, the hold state cannot be maintained with the hold voltage. In the fourth embodiment, a biasing method between the upper electrode and the lower electrode that can cope with such a case will be described.

  FIG. 23 is a flowchart showing the operation of the semiconductor integrated circuit according to the fourth embodiment. 24 and 25 are output waveforms of the voltage generation circuit 25 in the fourth embodiment.

  First, the voltage Vs is applied to the upper electrode 17 by the bias circuit 23 (period T1), and the electrostatic actuator 11 is driven. Subsequently, a hold voltage Vh is applied to the upper electrode 17 by the bias circuit 23 (period T2), and the electrostatic actuator 11 is brought into a hold state. Further, the voltage VmonL is applied to the upper electrode 17 by the bias circuit 23 (period T3) (step S41). Then, it is detected whether or not the pull-out voltage Vpo is higher than the voltage VmonL (step S42). When the pull-out voltage Vpo is higher than the voltage VmonL, the process proceeds to step S41, and the processes after step S41 are repeated.

  On the other hand, when the pullout voltage Vpo is not higher than the voltage VmonL in step S42, it is further detected whether or not the pullout voltage Vpo is higher than 0V (step S43). When the pull-out voltage Vpo is not higher than 0V, after the mode 3 is executed (step S44), the process proceeds to step S41, and the processes after step S41 are repeated.

  In step S43, when the pull-out voltage Vpo is higher than 0 V, the output destination of the voltage generation circuit 25 is switched to the lower electrode 15 (step S45). Subsequently, the bias circuit 23 applies a voltage Vs to the lower electrode 15 (period T1), and drives the electrostatic actuator 11 (step S46). Further, the hold circuit Vh is applied to the lower electrode 15 by the bias circuit 23 (period T5), and it is detected whether or not the pull-out voltage Vpo is lower than the hold voltage Vh (step S47). When the pull-out voltage Vpo is not lower than the hold voltage Vh, after the mode 4 is executed (step S48), the process proceeds to step S46, and the processes after step S46 are repeated.

  In step S47, when the pull-out voltage Vpo is lower than the hold voltage Vh, the bias circuit 23 applies the hold voltage Vh to the lower electrode 15 as it is (period T2). 15 is applied with a voltage VmonH (period T3) (step S49). Then, it is detected whether or not the pullout voltage Vpo is lower than the voltage VmonH (step S50). When the pull-out voltage Vpo is lower than the voltage VmonH, the process proceeds to step S46, and the processes after step S46 are repeated. On the other hand, when the pull-out voltage Vpo is not lower than the voltage VmonH, the output destination of the voltage generation circuit 25 is switched to the upper electrode 17 (step S51), the process proceeds to step S41, and the processes after step S41 are repeated.

  26A and 26B show a voltage waveform and a flowchart of mode 3 in FIG.

  In mode 3, the following operation is performed. First, the voltage Vs is applied to the lower electrode 15 by the bias circuit 23. Subsequently, a voltage VmonH is applied to the lower electrode 15 by the bias circuit 23 (step S61). Then, it is detected whether or not the pull-out voltage Vpo is higher than the voltage VmonH (step S62). When the pull-out voltage Vpo is not higher than the voltage VmonH, the process proceeds to step S61, and the processes after step S61 are repeated. On the other hand, when the pull-out voltage Vpo is higher than the voltage VmonH, the mode 3 process is terminated.

  27A and 27B show a voltage waveform and a flowchart of mode 4 in FIG.

  In mode 4, the following operation is performed. First, the voltage Vs is applied to the upper electrode 17 by the bias circuit 23. Subsequently, the voltage VmonL is applied to the upper electrode 17 by the bias circuit 23 (step S71). Then, it is detected whether or not the pull-out voltage Vpo is lower than the voltage VmonL (step S72). When the pull-out voltage Vpo is not lower than the voltage VmonL, the process proceeds to step S71, and the processes after step S71 are repeated. On the other hand, when the pull-out voltage Vpo is lower than the voltage VmonL, the mode 4 process is terminated.

  In the fourth embodiment, as in the above-described embodiment, if it is determined that Vpo ≦ VmonL after comparing the levels of the pullout voltage Vpo and the voltage VmonL, the pullout voltage Vpo and 0 V Compare high and low. This comparison is performed to determine whether or not stiction has occurred in the electrostatic actuator 11. When the pull-out voltage Vpo is 0 V or less, it is determined that stiction has occurred, and mode 3 is executed. In mode 3, the voltage waveform as shown in FIG. 26A is applied and the operation shown in FIG. 26B is performed. As a result, the pull-out voltage Vpo is made higher than the voltage VmonH to eliminate stiction. The comparison operation shown in steps S42 and S43 can be realized by the charge accumulation amount detection circuit 21 of the above-described embodiment. The comparison operation in step S42 is performed in the period T3 in FIG. 24, and the comparison operation in step S43 is performed. It implements in period T4 in FIG.

  On the other hand, when a failure that cannot hold the hold state with the hold voltage Vh occurs, a voltage waveform as shown in FIG. 27A is applied between the upper electrode 17 and the lower electrode 15 to perform the operation shown in FIG. 27B. Thereby, the pull-out voltage Vpo is made lower than the voltage VmonL. Whether or not the electrostatic actuator 11 is holding at the hold voltage Vh is detected in a period T5 in FIG. Note that a flowchart may be employed in which the electric field applied between the upper electrode 17 and the lower electrode 15 is reversed after the pull-out voltage Vpo is raised to the voltage level of the voltage VmonL in mode 3. Note that VmonL = VmonH = Vmon may be used for the same reason as in the first embodiment.

[Fifth Embodiment]
Next, a driving method of the electrostatic actuator provided in the semiconductor integrated circuit according to the fifth embodiment of the present invention will be described. The same parts as those in the first embodiment are denoted by the same reference numerals.

  Immediately after turning on the power to the semiconductor integrated circuit, it is unknown how much charge is accumulated in the insulating film 16. In such a case, it is convenient to have a test mode for testing whether the pull-out voltage is within an appropriate range. In the fifth embodiment, this test mode will be described.

  FIG. 28 is a flowchart showing an operation in a test mode provided in the semiconductor integrated circuit according to the fifth embodiment. When the pull-out voltage is monitored by the charge accumulation amount detection circuit shown in FIG. 6A or 17 and is not within the proper range, the above-described mode 3 or mode 4 is executed to keep the pull-out voltage within the proper range. . The operation in the test mode will be described in detail below.

  When the power is turned on or a command is input (step S81), the charge accumulation amount detection circuit 21 detects whether or not the pullout voltage Vpo is lower than the hold voltage Vh (step S82). When the pullout voltage Vpo is not lower than the hold voltage Vh, the mode is shifted to mode 4 (step S83). On the other hand, when the pullout voltage Vpo is lower than the hold voltage Vh, the charge accumulation amount detection circuit 21 further detects whether or not the pullout voltage Vpo is higher than 0V (step S84). When the pull-out voltage Vpo is not higher than 0V, the mode is shifted to mode 3 (step S85). On the other hand, when the pull-out voltage Vpo is higher than 0V, the test mode is terminated assuming that the pull-out voltage Vpo is within an appropriate range.

  Here, the pull-out voltage is monitored and adjusted so that the pull-out voltage falls within the proper range. However, the pull-in voltage may be monitored instead of the pull-out voltage and adjusted so that the pull-in voltage falls within the proper range. . The test mode may be automatically executed after receiving the power-on detection signal and after the power is turned on, or the test mode may be executed in response to a command from the controller.

[Sixth Embodiment]
In a semiconductor integrated circuit (system) that does not include a non-volatile memory, when the power is turned off, the data in the memory circuit 22 that stores the direction of the applied electric field between the upper electrode and the lower electrode, such as register data, is lost. Therefore, it is necessary to determine the data of the register that stores the direction of the applied electric field when the power is turned on. The sixth embodiment relates to the data determination method.

  FIG. 29 is a flowchart showing an operation in a test mode provided in the semiconductor integrated circuit according to the sixth embodiment.

  After power-on (step S91), the output signal of the power-on reset circuit is received, and the register data is set to a predetermined data value, for example, first data (step S92). Thereafter, the electrostatic actuator 11 is driven (step S93), and the hold state is set (step S94). Thereafter, the charge accumulation amount accumulated in the insulating film 16 of the electrostatic actuator 11 is detected by the charge accumulation amount detection circuit 21 (step S95). During normal operation, the user determines the period of the hold operation. In this case, the user holds for a predetermined period Tph. Since the period Tph does not need to be a long period, for example, it is 1 msec here. As a result of the charge accumulation amount detection operation, a data value corresponding to the accumulated charge amount in the insulating film 16 is stored in the register, so that the occurrence of defects in the subsequent operations in steps S96 and S97 can be suppressed.

[Seventh Embodiment]
In the seventh embodiment, a specific application example to a variable capacitance element (MEMS variable capacitance element) will be described as a device using an electrostatic actuator.

  FIG. 30A is a diagram illustrating a configuration of a semiconductor integrated circuit including the MEMS variable capacitor 40 according to the seventh embodiment, and FIG. 30B is a plan view of the MEMS variable capacitor 40. The structure of the MEMS variable capacitance element 40 is as follows. A driving upper electrode 17 is fixed to the anchor 13 disposed on the semiconductor substrate 12. A driving lower electrode 15 and RF lower electrodes 18 A and 18 B are formed on the semiconductor substrate 12, and the RF lower electrodes 18 A and 18 B are disposed between the driving lower electrodes 15. An insulating film 16 is formed on the lower driving electrode 15 so as to cover the lower driving electrode 15, and an insulating film 42 is formed on the lower RF electrodes 18 A and 18 B so as to cover the lower RF electrodes 18 A and 18 B. Is formed. These RF lower electrodes 18A and 18B, the RF upper electrode 19 and the insulating film 42 constitute a variable capacitance element. Further, an insulator 41 is inserted between the RF upper electrode 19 and the driving upper electrode 17, and the RF upper electrode 19 and the driving upper electrode 17 are electrically isolated.

  The RF lower electrode is disposed so as to face the RF upper electrode 19, and is cut below the RF upper electrode 19 to form the RF lower electrodes 18A and 18B as shown in FIG. 30B. ing. The RF lower electrode 18A is connected to the port 1, and the RF lower electrode 18B is connected to the port 2. Therefore, by changing the distance between the RF upper electrode 19 and the RF lower electrodes 18A and 18B by the electrostatic actuator composed of the driving upper electrode 17 and the lower electrode 15, the capacitance value between the ports 1 and 2 is changed. Can be made variable.

  This embodiment is characterized in that the sign of the voltage “Vtop−Vbtm” is changed in accordance with the amount of charge in the insulating film 16. One example of realizing this is a system in which the voltage Vtop applied to the driving upper electrode 17 is always set to 0 V, and a positive or negative voltage is applied to the voltage Vbtm applied to the driving lower electrode 15. In this case, however, a circuit for generating a positive and negative high voltage is required. Making such a circuit involves process costs. Therefore, the voltage Vbtm is set to 0 V when a positive high voltage is applied to the voltage Vtop, and the voltage Vtop is set to 0 V when a positive high voltage is applied to the voltage Vbtm. It is desirable to change the direction of the electric field between the driving lower electrodes 15.

  However, in this case, the RF upper electrode 19 and the driving upper electrode 17 of the MEMS variable capacitance element 40 cannot be electrically shared. This is because it is not desirable that the voltage of the RF upper electrode 19 changes according to the direction of the electric field of the drive electrode portion (the drive upper electrode 17 and the drive lower electrode 15). Therefore, as shown in FIG. 30A, an insulator 41 is inserted between the RF upper electrode 19 and the driving upper electrode 17 to electrically isolate the RF upper electrode 19 and the driving upper electrode 17 from each other. To rate. With such a structure, there is an effect that noise of the drive electrode portion can be prevented from being transmitted to the RF electrode portion.

[Eighth Embodiment]
In the eighth embodiment, a specific application example to a switch (MEMS switch) will be described as a device using an electrostatic actuator.

  FIG. 31A is a diagram illustrating a configuration of a semiconductor integrated circuit including the MEMS switch 50 according to the eighth embodiment, and FIG. 31B is a plan view of the MEMS switch 50. In the MEMS variable capacitance element 40 described above, the insulating film 42 is formed on the RF lower electrodes 18A and 18B. However, in the MEMS switch 50, since an insulating film is not formed on the RF lower electrode 18, the RF film is used. When the upper electrode 19 is lowered, the RF upper electrode 19 is in electrical contact with the RF lower electrode 18. For this reason, by driving the RF upper electrode 19 by the electrostatic actuator composed of the driving upper electrode 17 and the lower electrode 15, the ports 1 and 2 can be electrically short-circuited or opened. Also in this embodiment, since the RF upper electrode 19 and the driving upper electrode 17 are electrically isolated, the driving and driving method of these electrodes has the same operations and effects as those of the seventh embodiment.

  As described above, in the first to eighth embodiments described above, the case where the charge amount in the insulating film 16 is estimated from the pull-out voltage Vpo has been mainly described. However, the charge amount in the insulating film 16 is estimated by monitoring the pull-in voltage. You may make it do. For this purpose, the voltage Vs may be changed to monitor whether the pull-in is performed. This operation can be realized by a circuit similar to the charge accumulation amount detection circuit shown in FIG. 6A or 6B.

  In addition, each of the above-described embodiments can be implemented not only independently but also in an appropriate combination. For example, the charge accumulation amount detection in the insulating film in the flowchart shown in FIG. 23 may be performed by using the charge accumulation amount detection circuit shown in FIG. 6B or FIG. 17, and there are various other combinations. Is possible. Furthermore, the above-described embodiments include inventions at various stages, and the inventions at various stages can be extracted by appropriately combining a plurality of constituent elements disclosed in the embodiments.

  According to the embodiments of the present invention, a semiconductor integrated circuit and a driving method of an electrostatic actuator that can drive an electrostatic actuator so as not to cause a malfunction even when a sufficiently long time has passed in a hold state are provided. Is possible.

It is a figure which shows the CV characteristic when voltage Vs is applied to an upper electrode in an electrostatic actuator, and a lower electrode is made into a ground voltage (in the case of the 1st type charge injection). It is a figure which shows the CV characteristic when voltage Vs is applied to a lower electrode in an electrostatic actuator, and an upper electrode is made into a ground voltage (in the case of the 1st type charge injection). It is a figure which shows the CV characteristic when the voltage Vs is applied to an upper electrode in an electrostatic actuator, and a lower electrode is made into a ground voltage (in the case of the second type charge injection). It is a figure which shows the CV characteristic when the voltage Vs is applied to a lower electrode in an electrostatic actuator, and an upper electrode is made into a ground voltage (in the case of 2nd type charge injection). It is the schematic which shows the structure of the semiconductor integrated circuit which implement | achieves embodiment of this invention. It is sectional drawing of the MEMS part at the time of applying the electrostatic actuator in embodiment to a contact type switch. It is sectional drawing of the MEMS part at the time of applying the said electrostatic type actuator in embodiment to a variable capacitance element. It is sectional drawing of the MEMS part using the hybrid type actuator which combined the said electrostatic type actuator and actuator other than an electrostatic type in embodiment. 1 is a schematic diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. FIG. 3 is a circuit diagram of a charge accumulation amount detection circuit in the semiconductor integrated circuit according to the first embodiment. FIG. 6B is a circuit diagram of a modification of the charge accumulation amount detection circuit shown in FIG. 6A. It is a voltage waveform diagram of the output voltage of the voltage generation circuit in the semiconductor integrated circuit of the first embodiment (mode 1). FIG. 6 is a voltage waveform diagram during the charge accumulation amount detection operation in the semiconductor integrated circuit according to the first embodiment (mode 1). It is a voltage waveform diagram of the output voltage of the voltage generation circuit in the semiconductor integrated circuit of the first embodiment (mode 2). FIG. 6 is a voltage waveform diagram during the charge accumulation amount detection operation in the semiconductor integrated circuit according to the first embodiment (mode 2). 3 is a flowchart showing the operation of the semiconductor integrated circuit according to the first embodiment (in the case of the first type of charge injection). 3 is a flowchart showing the operation of the semiconductor integrated circuit according to the first embodiment (in the case of VmonL = VmonH = Vmon in the first type of charge injection). FIG. 11B is a voltage waveform diagram applied to the upper electrode and the lower electrode during continuous operation in the semiconductor integrated circuit shown in FIG. 11B. 3 is a flowchart showing the operation of the semiconductor integrated circuit of the first embodiment (in the case of the second type of charge injection). 3 is a flowchart showing the operation of the semiconductor integrated circuit according to the first embodiment (in the case of VmonL = VmonH = Vmon in the second type of charge injection). It is a figure which shows the CV characteristic in the electrostatic actuator of the semiconductor integrated circuit of 1st Embodiment (mode 1). It is a figure which shows the CV characteristic in the electrostatic actuator of the semiconductor integrated circuit of 1st Embodiment (mode 2). It is a voltage waveform diagram applied to the upper electrode and the lower electrode during continuous operation in the semiconductor integrated circuit of the first embodiment. It is the schematic which shows the structure of the semiconductor integrated circuit of the modification of 1st Embodiment. It is a voltage waveform diagram applied to the upper electrode and the lower electrode during continuous operation in the semiconductor integrated circuit of the modification of the first embodiment. FIG. 3 is a bipolar voltage waveform diagram as a hold voltage applied to an upper electrode and a lower electrode in the semiconductor integrated circuit of the first embodiment. It is a voltage waveform diagram which shows the other modification of the output voltage of the voltage generation circuit in the semiconductor integrated circuit of 1st Embodiment. FIG. 6 is a circuit diagram of a charge accumulation amount detection circuit in a semiconductor integrated circuit according to a second embodiment of the present invention. It is a wave form diagram at the time of detection operation of the electric charge accumulation amount detection circuit in the semiconductor integrated circuit of a 2nd embodiment. It is a flowchart which shows operation | movement of the semiconductor integrated circuit of 2nd Embodiment. It is a voltage waveform diagram of the output voltage of the voltage generation circuit in the third embodiment of the present invention. It is a voltage waveform diagram of the output voltage as a 1st modification of the voltage generation circuit in 3rd Embodiment. It is a voltage waveform diagram of the output voltage as a 2nd modification of the voltage generation circuit in 3rd Embodiment. It is a voltage waveform diagram of the output voltage as a 3rd modification of the voltage generation circuit in 3rd Embodiment. 10 is a flowchart showing the operation of the semiconductor integrated circuit of the third embodiment. It is a schematic diagram which shows transition of the charge accumulation amount in the insulating film in the semiconductor integrated circuit of 3rd Embodiment. It is a schematic diagram showing a transition of the charge accumulation amount in the insulating film in the semiconductor integrated circuit of the first embodiment. It is a flowchart which shows operation | movement of the semiconductor integrated circuit of 4th Embodiment of this invention. It is a 1st output waveform diagram of the voltage generation circuit in the semiconductor integrated circuit of 4th Embodiment. It is a 2nd output waveform diagram of the voltage generation circuit in the semiconductor integrated circuit of 4th Embodiment. FIG. 24 is a voltage waveform diagram in mode 3 in FIG. 23. It is a flowchart in the mode 3 in FIG. FIG. 24 is a voltage waveform diagram in mode 4 in FIG. 23. It is a flowchart in the mode 4 in FIG. It is a flowchart which shows operation | movement of the test mode with which the semiconductor integrated circuit of 5th Embodiment of this invention was equipped. It is a flowchart which shows operation | movement of the test mode with which the semiconductor integrated circuit of 6th Embodiment of this invention was provided. It is the schematic which shows the structure of the semiconductor integrated circuit containing the MEMS variable capacitance element of 7th Embodiment of this invention. It is a top view of the said MEMS variable capacitance element in 7th Embodiment. It is the schematic which shows the structure of the semiconductor integrated circuit containing the MEMS switch of 8th Embodiment of this invention. It is a top view of the MEMS switch in an 8th embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... MEMS part, 11 ... Electrostatic actuator, 12 ... Semiconductor substrate, 13 ... Anchor, 14 ... Elastic member, 15 ... Lower electrode, 16 ... Insulating film, 17 ... Upper electrode, 18 ... First electrode, 19 ... First 2 electrodes, 20 ... circuit section, 21 ... charge accumulation amount detection circuit, 22 ... memory circuit, 23 ... bias circuit, 24 ... controller, 25 ... voltage generation circuit, 30 ... cavity, 31 ... actuator other than electrostatic type, 40 ... MEMS variable capacitance element, 41 ... insulator, 42 ... insulating film, 50 ... MEMS switch.

Claims (4)

An electrostatic actuator having an upper electrode, a lower electrode, and an insulating film disposed between the upper electrode and the lower electrode;
A detection circuit for detecting a charge amount accumulated in the insulating film of the electrostatic actuator;
A storage circuit for storing a detection result of the charge amount detected by the detection circuit;
A bias circuit that changes a drive voltage for driving the electrostatic actuator based on the detection result stored in the storage circuit;
A semiconductor integrated circuit comprising: The detection of the charge amount by the detection circuit is performed by monitoring a pull-out voltage for separating the upper electrode from the connection state to the lower electrode side through the insulating film in the electrostatic actuator. ,
The bias circuit determines a direction of an electric field applied to the insulating film by the upper electrode and the lower electrode when the electrostatic actuator is driven based on the pullout voltage monitored by the detection circuit. The semiconductor integrated circuit according to claim 1 . An electrostatic actuator having an upper electrode, a lower electrode, and an insulating film disposed between the upper electrode and the lower electrode;
A detection circuit for detecting whether or not the amount of charge accumulated in the insulating film of the electrostatic actuator is within a predetermined range;
When it is detected that the amount of charge accumulated in the insulating film does not fall within a predetermined range, the charge amount falls between the upper electrode and the lower electrode so as to fall within a predetermined range. A bias circuit that applies a driving voltage to inject and extract charges from the insulating film;
A semiconductor integrated circuit comprising: In the driving method of the electrostatic actuator having the upper electrode, the lower electrode, and the insulating film disposed between the upper electrode and the lower electrode,
Detecting either power-on or command input;
Detecting whether the amount of electric charge accumulated in the insulating film is within a predetermined range when detecting either the power-on or the command input;
When it is detected that the amount of charge accumulated in the insulating film does not fall within a predetermined range, injection of charges into the insulating film and A step of either pulling,
A driving method of an electrostatic actuator, comprising:

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