JP4703207B2 - 配線基板 - Google Patents
配線基板 Download PDFInfo
- Publication number
- JP4703207B2 JP4703207B2 JP2005035003A JP2005035003A JP4703207B2 JP 4703207 B2 JP4703207 B2 JP 4703207B2 JP 2005035003 A JP2005035003 A JP 2005035003A JP 2005035003 A JP2005035003 A JP 2005035003A JP 4703207 B2 JP4703207 B2 JP 4703207B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- insulating
- layer
- glass
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
2・・・配線層
3・・・ビアホール導体
4・・・接続用電極
5・・・電子部品
6・・・封止樹脂
7・・・ワイヤボンディング
8・・・半田
9・・・半田
10・・接着剤
A・・・配線基板
B・・・プリント基板
Claims (6)
- 複数の絶縁層を積層してなる絶縁基板と、該絶縁基板の少なくとも表面および前記複数の絶縁層間に設けられた配線層とを具備する配線基板であって、
前記絶縁基板の表層をなす前記絶縁層は、少なくともSiO 2 およびY 2 O 3 を含有するガラス、及び結晶相を含み、厚みが100μm以下のガラスセラミック焼結体からなり、
前記ガラスセラミック焼結体の断面におけるボイドの面積占有率が1.8%以下であり、該ボイドのうち、孤立して存在するボイドの占有面積が全体の81%以上であることを特徴とする配線基板。 - 前記ボイドのうち、略球状のボイドの占有面積が全体の83%以上であることを特徴とする請求項1記載の配線基板。
- 前記ガラスセラミック焼結体が、実質的にアルカリ金属酸化物を含有しないことを特徴とする請求項1又は請求項2記載の配線基板。
- 前記絶縁基板の表層をなす前記絶縁層の厚み方向の電気抵抗が、10 11 Ω/mm2以上であることを特徴とする請求項1〜3のいずれかに記載の配線基板。
- 前記配線層が、金、銀及び銅の少なくとも1種を主成分とすることを特徴とする請求項1〜4のいずれかに記載の配線基板。
- 前記絶縁基板の表面に配設された配線層の表面に、めっき層が被着形成されていることを特徴とする請求項1〜5のいずれかに記載の配線基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005035003A JP4703207B2 (ja) | 2005-02-10 | 2005-02-10 | 配線基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005035003A JP4703207B2 (ja) | 2005-02-10 | 2005-02-10 | 配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006222307A JP2006222307A (ja) | 2006-08-24 |
JP4703207B2 true JP4703207B2 (ja) | 2011-06-15 |
Family
ID=36984394
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005035003A Expired - Lifetime JP4703207B2 (ja) | 2005-02-10 | 2005-02-10 | 配線基板 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4703207B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4869005B2 (ja) * | 2006-09-27 | 2012-02-01 | 京セラ株式会社 | 多層基板の製造方法 |
JP2010055157A (ja) * | 2008-08-26 | 2010-03-11 | Panasonic Corp | 交差点状況認識システム |
KR101051583B1 (ko) * | 2009-06-03 | 2011-07-29 | 삼성전기주식회사 | 다층 세라믹 기판 및 그 제조방법 |
EP2790215B1 (en) * | 2011-12-08 | 2018-05-23 | NGK Insulators, Ltd. | Substrate for large-capacity module, and manufacturing method for said substrate |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63175496A (ja) * | 1987-01-16 | 1988-07-19 | 旭硝子株式会社 | 厚膜回路基板 |
JPH03193656A (ja) * | 1989-12-21 | 1991-08-23 | Hitachi Chem Co Ltd | セラミツク基板の製造法 |
JPH04206988A (ja) * | 1990-11-30 | 1992-07-28 | Kyocera Corp | 高絶縁性セラミック基板およびその製造方法 |
JP2003342060A (ja) * | 2002-05-23 | 2003-12-03 | Kyocera Corp | ガラスセラミック焼結体および配線基板 |
JP2004235347A (ja) * | 2003-01-29 | 2004-08-19 | Kyocera Corp | 絶縁性セラミックスおよびそれを用いた多層セラミック基板 |
-
2005
- 2005-02-10 JP JP2005035003A patent/JP4703207B2/ja not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63175496A (ja) * | 1987-01-16 | 1988-07-19 | 旭硝子株式会社 | 厚膜回路基板 |
JPH03193656A (ja) * | 1989-12-21 | 1991-08-23 | Hitachi Chem Co Ltd | セラミツク基板の製造法 |
JPH04206988A (ja) * | 1990-11-30 | 1992-07-28 | Kyocera Corp | 高絶縁性セラミック基板およびその製造方法 |
JP2003342060A (ja) * | 2002-05-23 | 2003-12-03 | Kyocera Corp | ガラスセラミック焼結体および配線基板 |
JP2004235347A (ja) * | 2003-01-29 | 2004-08-19 | Kyocera Corp | 絶縁性セラミックスおよびそれを用いた多層セラミック基板 |
Also Published As
Publication number | Publication date |
---|---|
JP2006222307A (ja) | 2006-08-24 |
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