JP4696672B2 - Phase synchronization apparatus and method, data reproduction apparatus and method, and program - Google Patents

Description

  The present invention relates to a phase synchronization apparatus and method, a data reproduction apparatus and method, and a program. In particular, in a data reproduction apparatus including a phase synchronization apparatus, the error rate of reproduction data is improved, and thus the entire data reproduction apparatus is stabilized. The present invention relates to a phase synchronization apparatus and method, a data reproduction apparatus and method, and a program.

In recent years, a digital PLL (Phase Locked Loop) that has appeared as one of phase synchronization devices (see, for example, Patent Documents 1 to 6 and Non-Patent Document 1) is input with asynchronous sampling data corresponding to an RLL code. Thus, feedback control can be performed based on the phase error (phase_error) so as to output synchronous sampling data shaped into the partial response system equalization.
JP 2001-358882 A Japanese Patent No. 3071142 Japanese Patent Laid-Open No. 10-69727 Japanese National Patent Publication No. 10-508135 JP 2000-76805 A JP 2002-42428 A Interpolated Timing Recovery For Hard Disk Drive Read Channels Mark Spurbeck and Richard T. Behrens / Cirrus Logic 1997 IEEE p1618-1624

  However, in a data reproduction device (system) that reproduces original data (RLL-encoded original data) from the synchronous sampling data output from such a PLL, the error rate of the reproduced data is improved, and thus the entire system In recent years, many requests have been made to make the system stable.

  The present invention has been made in view of such a situation, and in a data reproducing apparatus (system) including a phase synchronization apparatus, the error rate of reproduced data can be improved, and as a result, the entire system can be kept stable. It is.

When the data recorded on a predetermined recording medium as an RLL recording code of d> 0 is read asynchronously at a predetermined frequency, the phase synchronization apparatus of the present invention converts the data from the asynchronous data to the predetermined frequency. A phase synchronization apparatus for generating synchronized synchronization data, comprising phase error information detection means for detecting phase error information indicating a phase error of the synchronization data, wherein the phase error information detection means includes each sampling constituting the synchronization data Among the values, the predetermined information regarding the sampling value to be processed is a specific pattern by a specific pattern determination unit that determines whether or not the predetermined pattern is a predetermined specific pattern, and by the specific pattern determination unit. A phase error information calculating unit that calculates phase error information by distinguishing between the case where it is determined and the case where it is determined otherwise The specific pattern, out of the sampling values which constitute the synchronous data is a pattern that can not exist in the state is the ideal state within a predetermined range including the sampling value of the processing target, the specific pattern determination means, certain When it is determined that the pattern is a pattern, it is further determined which type of the specific pattern classified into a plurality of types, and the phase error information calculation means further determines each of the plurality of types of the specific pattern. The phase error information is calculated separately from each other.

  When the specific pattern determining unit determines that the specific pattern is the specific pattern, the specific pattern determining unit further determines which type of the specific pattern is classified into a plurality of types, and the phase error information calculating unit further determines the specific pattern. The phase error information can be calculated by distinguishing each of the plurality of types.

  As the plurality of types of the specific pattern, the first type generated due to the phase position of the sampling data within the predetermined range including the sampling data to be processed deviating from the ideal state position, and the range within the predetermined range There can be at least the second type that does not exist in the ideal state without depending on the phase position of the sampling data.

  The phase error information calculation unit calculates phase error information according to the first calculation method as a reference when the specific pattern determination unit determines that the specific pattern is not a specific pattern, and is the first type of the specific pattern. When it is determined, the phase error information is calculated according to the second calculation method, and when it is determined that it is the second type of the specific pattern, the phase error information is calculated according to the third calculation method. be able to.

  At least one of the second calculation method and the third calculation method may be a method that outputs a fixed 0 as phase error information.

  At least one of the second calculation method and the third calculation method is a method of calculating a value of a different code as phase error information with respect to a value calculated as phase error information according to the first calculation method. Can be.

  The first calculation method is a method for outputting a calculation value based on a predetermined calculation formula as phase error information, and at least one of the second calculation method and the third calculation method is based on a predetermined calculation formula. A method in which a value obtained by inverting the sign of the operation value is output as phase error information can be employed.

In the phase synchronization method of the present invention, when data recorded on a predetermined recording medium as an RLL recording code of d> 0 is read asynchronously to a predetermined frequency, the asynchronous data is changed to the predetermined frequency. A phase synchronization method of a phase synchronization apparatus for generating synchronized synchronization data, including a phase error information detection step of detecting phase error information indicating a phase error of the synchronization data, wherein the phase error information detection step A specific pattern determination step for determining whether or not the predetermined information related to the sampling value to be processed among the sampling values to be configured is a predetermined specific pattern based on information based on the run restriction, and a specific pattern determination step Distinguish between the case where it is determined to be a specific pattern by processing and the case where it is not, and phase error information And a specific pattern cannot exist when the state within a predetermined range including the sampling value to be processed among the sampling values constituting the synchronization data is an ideal state. If it is a pattern and is determined to be a specific pattern by the processing of the specific pattern determination step, it is further determined which type of the specific pattern is classified into a plurality of types, and a phase error information calculation step Further, the process is characterized in that the phase error information is calculated by distinguishing each of a plurality of types of the specific pattern .

  The first program of the present invention is a program corresponding to the above-described phase synchronization method of the present invention.

In the phase synchronization apparatus and method and the first program of the present invention, when data recorded on a predetermined recording medium as an RLL recording code of d> 0 is read asynchronously at a predetermined frequency, the asynchronous From this data, synchronized data synchronized with a predetermined frequency is generated. At this time, phase error information indicating the phase error of the synchronization data is detected, and synchronization data (next sampling value) is generated based on the phase error information. Specifically, whether or not the predetermined information related to the sampling value to be processed among the sampling values constituting the synchronization data is a predetermined specific pattern is determined based on the information based on the run restriction. Then, the case where it is determined that the pattern is a specific pattern is distinguished from the case where it is determined that it is not, and the phase error information is calculated. The specific pattern is a pattern that cannot exist when a state within a predetermined range including the sampling value to be processed is an ideal state among the sampling values constituting the synchronization data. Further, when it is determined that the pattern is a specific pattern, it is further determined which type of the specific pattern is classified into a plurality of types, and in the process of the phase error information calculation step, the specific pattern is further determined. Phase error information is calculated by distinguishing each of a plurality of types.

In the data reproducing apparatus for reproducing data recorded on a predetermined recording medium as an RLL recording code of d> 0, when the data is read from the predetermined recording medium as an analog signal, the data reproducing apparatus of the present invention, A differential means for generating a differential response signal of the analog signal, a sampling means for generating asynchronous data by asynchronously sampling the analog differential response signal generated by the differential means at a predetermined frequency, and a sampling means Phase synchronization means for generating synchronization data synchronized with a predetermined frequency from the generated asynchronous data, and the phase synchronization means is a phase indicating the phase error of the synchronization data according to the PR (1, -1) equalization algorithm. Phase error information detecting means for detecting error information, and the phase error information detecting means includes each sampling value constituting the synchronization data. The specific pattern determination means for determining whether or not the predetermined information related to the sampling value to be processed is a predetermined specific pattern based on information based on the run restriction, and the specific pattern determination means determines that the specific pattern is the specific pattern The phase error information calculating means for calculating each of the phase error information is distinguished from the case where it is determined to be different from the case where it is determined, and each of the sampling values constituting the synchronization sample is compared with a predetermined threshold value. Slicing means for calculating a slice value based on the result of the comparison is provided, and the specific pattern is ideal if the state within a predetermined range including the sampling value to be processed among the sampling values constituting the synchronization data a pattern that can not exist in the state, out of the sampling values which constitute the synchronous data, the processed sub The pulling data is the first value, the value immediately before the first value is the second value, and the specific pattern determining means is the first of the slice values calculated by the slicing means. Determining whether or not the pattern is a specific pattern based on a combination of the second slice value corresponding to the value of 2 and the first slice value corresponding to the first value; If it is determined that the pattern is not a specific pattern, the first value is data_now, the second value is data_D, the first slice value is slice_now, the second slice value is slice_D, and the phase error information is phase_err , Phase_err = (data_now * slice_D)-phase error information is calculated according to the first calculation method using the calculation formula represented by (data_D * slice_now), Specific patterns classified into types Determines whether the in the range of any type, to distinguish each of the plurality of types of specific patterns, according to different calculation method from the first calculation method, and calculates the phase error information, respectively.

  As a plurality of types of the specific pattern, at least a first type and a second type can exist.

  The phase error information calculating unit calculates the phase error information according to the first calculation method when it is determined by the specific pattern determining unit that the phase pattern is not the specific pattern, and is determined to be the first type of the specific pattern. In the case, the phase error information is calculated according to the second calculation method different from the first calculation method, and when it is determined that the second type of the specific pattern is determined, the third calculation method is different from the first calculation method. The phase error information can be calculated according to the above calculation method.

  At least one of the second calculation method and the third calculation method may be a calculation method that uses a calculation expression represented by rev_phase_err = −phase_err, with phase error information as rev_phase_err.

  At least one of the second calculation method and the third calculation method is set to be negative when the sign of phase_err is + and positive when the sign of phase_err is-(the output of the phase_err output). (Inverted code), a predetermined constant is RLEV, phase error information is rev_phase_err, and rev_phase_err = (inverted code of phase_err output) x RLEV is used. .

  At least one of the second calculation method and the third calculation method may be a method of outputting a predetermined value as phase information.

  D = 1 of the RLL recording code recorded on the recording medium, and the phase error information detecting means detects the phase error information according to the PR (1,0, -1) equalization algorithm. Can do.

  Of the sampling values constituting the synchronization data, the sampling data to be processed is the first value, the value immediately before the first value is the second value, and the second value The specific value determining means is the third value, and the specific pattern determining means includes the third slice value corresponding to the third value of the slice values calculated by the slicing means, and the second value. The phase error information calculating means determines whether the pattern is a specific pattern based on a combination of the second slice value corresponding to the value of the first slice value and the first slice value corresponding to the first value. If it is determined that the pattern is not a pattern, the first value is data_now, the second value is data_D, the first slice value is slice_now, the second slice value is slice_D, the phase error information is phase_err, When both slice_now and slice_D are not 0, phase_err = (data_n ow * slice_D)-If the phase error information is calculated according to the first calculation method using the calculation formula shown by (data_D * slice_now) and determined to be a specific pattern, it is different from the first calculation method The phase error information can be calculated according to the calculation method.

  The calculation method different from the first calculation method can be a method of outputting a predetermined value as phase error information.

  When the specific pattern determining unit determines that the specific pattern is the specific pattern, the specific pattern determining unit further determines which type of the specific pattern is classified into a plurality of types, and the phase error information calculating unit further determines the specific pattern. The phase error information can be calculated by distinguishing each of the plurality of types.

  As a plurality of types of the specific pattern, at least a first type and a second type can exist.

  The phase error information calculating unit calculates phase error information according to the first calculation method when the specific pattern determining unit determines that the specific pattern is not a specific pattern, and determines that the phase error information is a first type of the specific pattern. If the phase error information is calculated according to a second calculation method different from the first calculation method and is determined to be the second type of the specific pattern, the second calculation method is different from the first calculation method. The phase error information can be calculated in accordance with the third calculation method.

  At least one of the second calculation method and the third calculation method may be a calculation method that uses a calculation expression represented by rev_phase_err = −phase_err, with phase error information as rev_phase_err.

  At least one of the second calculation method and the third calculation method indicates that if the sign of phase_err is +, it is-when the sign of phase_err is-(inverted phase_err output). Code), a predetermined constant is RLEV, phase error information is rev_phase_err, and an arithmetic method using an arithmetic expression represented by rev_phase_err = (inverted code of phase_err output) × RLEV can be used.

  At least one of the second calculation method and the third calculation method may be a method of outputting a predetermined value as phase information.

  In the second calculation method, the third value is data_2D, the third slice value is slice_2D, phase_err_2D = (data_now × slice_D) − (data_2D × slice_D), the phase error information is rev_phase_err_2D, and rev_phase_err_2D = − This is an arithmetic technique that uses the arithmetic expression indicated by phase_err_2D, and the third arithmetic technique can be a technique that outputs a predetermined value as phase error information.

  In the second calculation method, the third value is data_2D, the third slice value is slice_2D, phase_err_2D = (data_now × slice_D) − (data_2D × slice_D), and − when the sign of phase_err_2D is + And when phase_err_2D has a minus sign, it is described as + (inverted sign of phase_err_2D output), a predetermined constant is RLEV, phase error information is rev_phase_err_2D, and rev_phase_err_2D = (inverted sign of phase_err_2D output) × An arithmetic technique using an arithmetic expression represented by RLEV, and the third arithmetic technique can be a technique for outputting a predetermined value as phase error information.

The data reproduction method of the present invention is a data reproduction method of a data reproduction apparatus for reproducing data recorded on a predetermined recording medium as an RLL recording code of d> 0, in which data is read out from the predetermined recording medium as an analog signal. In this case, the differential step that generates the differential response signal of the analog signal, and the analog differential response signal generated by the processing of the differential step are sampled asynchronously at a predetermined frequency to generate asynchronous data. And a phase synchronization step for generating synchronization data synchronized with a predetermined frequency from the asynchronous data generated by the processing of the sampling step, and the phase synchronization step is performed according to a PR (1, -1) equalization algorithm. A phase error information detection step for detecting phase error information indicating a phase error of the synchronization data, The difference information detection step is a specific pattern for determining whether or not the predetermined information related to the sampling value to be processed among the sampling values constituting the synchronization data is a predetermined specific pattern based on information based on the run restriction. A phase error information calculation step for calculating phase error information by distinguishing between a determination step and a case where it is determined that the specific pattern is determined by the processing of the specific pattern determination step and a case where it is not, and a synchronous sample Each of the sampling values that constitutes a predetermined threshold value and a slice step that calculates a slice value based on the result of the comparison, and the specific pattern is the sampling value that constitutes the synchronization data Exists when the state within the predetermined range including the sampling value to be processed is the ideal state. A not patterned, out of the sampling values which constitute the synchronous data, the sampling data to be processed is the first value, the value before one of the first value, is the second value In the processing of the specific pattern determination step, the second slice value corresponding to the second value and the first slice corresponding to the first value among the slice values calculated by the processing of the slice step Based on the combination with the value, it is determined whether or not it is a specific pattern, and in the process of the phase error information calculation step, if it is determined that the pattern is not a specific pattern, the first value is data_now and the second value Is set to data_D, the first slice value is set to slice_now, the second slice value is set to slice_D, the phase error information is set to phase_err, and an arithmetic expression represented by phase_err = (data_now * slice_D)-(data_D * slice_now) is used First performance When phase error information is calculated according to the method and determined to be a specific pattern, it is further determined which type of the specific pattern is classified into a plurality of types, and a plurality of types of the specific pattern The phase error information is calculated according to a calculation method different from the first calculation method .

  The second program of the present invention is a program corresponding to the above-described data reproduction method of the present invention.

In the data reproducing apparatus and method and the second program of the present invention, data recorded on a predetermined recording medium as an RLL recording code of d> 0 is reproduced. Specifically, when data is read out from a predetermined recording medium as an analog signal, a differential response signal of the analog signal is generated, and the analog differential response signal is asynchronously sampled at a predetermined frequency, thereby asynchronous data. And synchronous data synchronized with a predetermined frequency is generated from the generated asynchronous data. The synchronization data is generated based on phase error information indicating the phase error of the synchronization data. This phase error information is calculated as follows. That is, whether or not the predetermined information related to the sampling value to be processed among the sampling values constituting the synchronization data is a predetermined specific pattern is determined based on the information based on the run restriction. Then, the case where it is determined to be a specific pattern is distinguished from the case where it is determined that it is not, phase error information is calculated, and each sampling value constituting a synchronous sample and a predetermined threshold value are determined. The slice value is calculated based on the result of the comparison. The specific pattern is a pattern that cannot exist when the state within a predetermined range including the sampling value to be processed is an ideal state among the sampling values constituting the synchronization data, and constitutes the synchronization data. Of each sampling value, the sampling data to be processed is the first value, the value immediately before the first value is the second value, and among the calculated slice values, Based on the combination of the second slice value corresponding to the second value and the first slice value corresponding to the first value, it is determined whether or not it is a specific pattern, and it is determined not to be a specific pattern In this case, the first value is data_now, the second value is data_D, the first slice value is slice_now, the second slice value is slice_D, the phase error information is phase_err, and phase_err = (data_now * slice_D)-(data_D * slice_now)
When the phase error information is calculated and determined to be a specific pattern according to the first calculation method using the calculation formula shown by the following, any type of specific patterns classified into a plurality of types is selected. The phase error information is calculated according to a calculation method different from the first calculation method by determining whether or not there is a plurality of types of specific patterns .

  According to the present invention, it is possible to provide a phase synchronization apparatus or a data reproducing apparatus including the same. In particular, in a data reproduction apparatus (system) including a phase synchronization apparatus, it is possible to improve the error rate of reproduction data and thus keep the entire system stable.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a configuration example of an embodiment of a data reproducing apparatus to which the present invention is applied or a data reproducing apparatus including a phase synchronization apparatus to which the present invention is applied.

  The data reproducing apparatus can reproduce data recorded on a recording medium such as a magnetic disk, an optical disk, and a magneto-optical disk.

  Therefore, before describing the data reproducing apparatus of FIG. 1, data recorded on the recording medium will be described.

  That is, when data is recorded on a recording medium as in this embodiment or transmitted to a predetermined transmission path, the data is modulated so as to be suitable for the recording medium and transmission path.

  A block code is known as one of such modulation methods. In this block code, a data string is blocked into units of m × i bits (hereinafter referred to as data words), and the data words are converted into code words of n × i bits according to an appropriate coding rule. . This code becomes a fixed length code when i = 1, and when a plurality of i can be selected, that is, when a predetermined i in the range of 1 to imax (maximum i) is selected and converted, Become. The block-coded code is represented as a variable length code (d, k; m, n; r). Hereinafter, the variable length code (d, k; m, n; r) is appropriately referred to as an RLL code (Run Length Limited Code).

  Here, i is referred to as a constraint length, and imax is r (maximum constraint length). D indicates the minimum continuous number of “0”, for example, “0” minimum run, which falls between consecutive “1” s, and k indicates the maximum continuous of “0”, which falls between consecutive “1” s. The number, for example, the maximum run of “0” is shown.

  More specifically, in order to perform recording with high density in the linear velocity direction, where Tmin is the minimum inversion interval of the recording waveform sequence (the RLL code is NRZI-modulated as will be described later) and Tmax is the maximum inversion interval. In this case, it is preferable that the minimum inversion interval Tmin is longer, that is, d is larger, and that the maximum inversion interval Tmax is shorter, that is, the maximum run k is smaller in terms of clock reproduction. In order to satisfy the above, various modulation methods have been proposed.

  More specifically, for example, RLL (1-7) ((1, 7; m, n), which is a variable-length code, is used as a modulation method proposed or actually used in an optical disk, a magnetic disk, a magneto-optical disk, or the like. ; Also expressed as r)) and RLL (2-7) (also expressed as (2, 7; m, n; r)), and fixed length RLL (1-7) used in ISO standard MO (Also expressed as (1, 7; m, n; 1)).

  In disk devices such as optical disks and magneto-optical disks with high recording density that are currently being researched and developed, d = 1 RLL codes are often used, for example, variable-length RLL (1-7) codes.

  The parameter of the variable length RLL (1-7) is (1, 7; 2, 3; 2), and the minimum inversion interval Tmin represented by (d + 1) T is 2 where T is the bit interval of the recording waveform sequence. (= 1 + 1) T. Assuming that the bit interval of the data string is Tdata, the minimum inversion interval Tmin represented by (m / n) × 2 is 1.33 (= (2/3) × 2) Tdata. The maximum inversion interval Tmax represented by (k + 1) T is 8 (= 7 + 1) T ((= (m / n) × 8Tdata = (2/3) × 8Tdata = 5.33Tdata) Further, the detection window width. Tw is represented by (m / n) × Tdata, and its value is 0.67 (= 2/3) Tdata.

  When the occurrence frequency of T in the channel bit string modulated by RLL (1-7) is examined, 2T, which is Tmin, is the largest, followed by 3T, 4T, and 5T. The occurrence of a large amount of edge information such as 2T or 3T at an early cycle is often advantageous for clock recovery.

  The 17PP code adopted in the Blu-ray Disc ReWritable Format is based on the RLL (1-7) code, and the minimum run, the maximum run, and the basic conversion rate are the same. Furthermore, the continuation of the minimum run 2T is limited to a finite number of times, and the relationship between the data string and the conversion code string is regular in the number of “1” s in the table, and at the time of DSV (Digital Sum Value) control It is a format that can be done efficiently.

  DSV control refers to the following control.

  That is, when data is recorded on a recording medium or when data is transmitted, encoding modulation suitable for the recording medium or transmission path is performed. These modulation codes include a direct current component and a low frequency component. For example, various error detection signals such as tracking errors in the servo control of the disk device are likely to fluctuate or jitter is likely to occur. Therefore, it is better to avoid the DC component and the low frequency component as much as possible in the modulation code.

  Therefore, it has been proposed to control the DSV. In this DSV, the RLL code is level-coded (for example, NRZI modulation described later), and the code is added with “1” being “+1” and “0” being “−1” in the bit string (data symbol). This is called DSV control. Decreasing the absolute value of the DSV transition that is a measure of the DC component and low-frequency component of the code string, that is, performing DSV control, suppresses the DC component and low-frequency component of the code string.

  Note that DSV control is not performed on the modulation code based on the variable length RLL (1-7). Since conversion efficiency is good, DSV control cannot be performed at the time of modulation like, for example, 8-16 code of DVD (Digital Versatile Disk). In such a case, DSV control is performed by, for example, performing DSV calculation at a predetermined interval in a modulated encoded string (channel bit string), and as a DSV control bit at a predetermined position in the encoded string (channel bit string). This is realized by inserting.

  However, the DSV control bit is basically a redundant bit. Therefore, from the viewpoint of code conversion efficiency, it is better to have as few DSV control bits as possible.

  As described above, in the present embodiment, such an RLL code is recorded on a recording medium.

  More precisely, when such an RLL code is recorded on a recording medium such as an optical disk or a magneto-optical disk, for example, in a compact disk or a mini-disc, “1” is inverted and “0” is omitted in the RLL code. NRZI (Non Return to Zero Inverted) modulation, which is inverted, is performed, and recording based on a variable-length code (hereinafter also referred to as a recording waveform sequence) that has been subjected to NRZI modulation is often performed. However, in addition to this, in the early ISO (International Organization for Standardization) magneto-optical disk where the recording density was not so high, the recording-modulated bit string was recorded as it was without being subjected to NRZI modulation.

  In the present embodiment, the RLL code (hereinafter referred to as RLL recording code) recorded on a recording medium such as an optical disk or a magneto-optical disk in this way is reproduced by the data reproducing apparatus of FIG. Furthermore, in the present embodiment, an RLL recording code with d> 0 is reproduced by the data reproducing apparatus of FIG.

  That is, for example, an RLL recording code recorded on a recording medium is read as an RF (Radio Frequency) signal (hereinafter referred to as a reproduction RF signal) by a head (not shown) or the like and input to the data reproduction apparatus of FIG. .

  Therefore, the data reproducing apparatus in FIG. 1 restores the original data from the reproduced RF signal and outputs it. For this reason, in the example of FIG. 1, the data reproducing apparatus is configured from the differential filter unit 1 to the decoding unit 7.

  An example of the data reproduction process of the data reproduction apparatus having such a configuration is shown in the flowchart of FIG. An example of the data reproduction process of the data reproduction apparatus in FIG. 1 will be described below with reference to the flowchart in FIG. In addition, when the processing of each step in the flowchart of FIG. 2 is described, the block that executes the processing of the step to be described in the differential filter unit 1 to the decoding unit 7 will also be described.

  In step S <b> 1, the differential filter unit 1 generates a differential response signal of the reproduction RF signal and supplies it to the A / D conversion unit 2. That is, the differential filter unit 1 is constituted by, for example, a differential filter as the name suggests.

  In step S2, the A / D (Analog / Digital) converter 2 performs digital sampling by asynchronously sampling the analog differential response signal at a predetermined sampling frequency asynchronous with the target channel clock (write frequency) fch. Asynchronous sampling data is generated and supplied to the EQ unit 3.

  Note that the sampling frequency used in the process of step S2 may be set to a frequency that is smaller than twice the channel clock fch and slightly higher than the same size, for example. For example, in this embodiment, the sampling frequency is n / m times the channel clock fch. Specifically, for example, m = 7 and n = 8, and fch * 8/7, that is, the channel clock. It is 8/7 times that of fch.

  In step S3, the EQ unit 3 shapes the asynchronous sampling data supplied from the A / D conversion unit 2 into a predetermined waveform. For example, in the present embodiment, the EQ unit 3 is configured as an equalizer to which a fixed coefficient is given at 5 taps, and asynchronous sampling data is shaped into a predetermined waveform by each of the fixed coefficients for 5 taps. Is done.

  When the asynchronous sampling data shaped into a predetermined waveform is provided from the EQ unit 3 to the AGC / DCC unit 4, the process proceeds to step S4. In step S4, the AGC / DCC unit 4 performs non-sampling data gain control (AGC: Auto Gain Control) and DC (Direct Current) offset cancellation (DCC: DC Cancel).

  The AGC / DCC unit 4 may obtain information from other blocks and perform predetermined calculations as necessary.

  When asynchronous sampling data subjected to gain control and DC offset cancellation is provided from the AGC / DCC unit 4 to the PLL unit 5, the process proceeds to step S5. In step S5, the PLL (Phase Locked Loop) unit 5 converts the asynchronous sampling data into synchronous sampling data synchronized with the channel clock fch.

  Although details will be described later, an algorithm corresponding to PR (1, -1) equalization or PR (1,0, -1) equalization is given to the PLL unit 5, and as a result, the PLL unit 5 The synchronous sampling data output from is a digital signal shaped to PR (1, -1) equalization or PR (1,0, -1) equalization.

  When the synchronous sampling data is provided from the PLL unit 5 to the PRML unit 6, the process proceeds to step S6. In step S6, the PRML unit 6 uses the Partial Response Maximum Likelihood (PRML) method that combines the Partial Response (PR) method and the Maximum Likelihood Sequence Detection (ML) method, and performs synchronous sampling. The RLL code (0 or 1 channel bit) is detected from the data.

  Note that Viterbi detection (Viterbi decoding) is mainly used as the maximum likelihood decoding. However, the data detection method of the PRML unit 6 is not particularly limited to Viterbi decoding. For example, a method using an NPML code may be used, or a simple slice detection method may be used.

  When the RLL code is supplied from the PRML unit 6 to the decoding unit 7, the process proceeds to step S7. In step S7, the decoding unit 7 decodes the RLL code (channel decoding = encoding decoding), and outputs the original data string obtained as a result.

  The data reproduction process executed by the data reproduction apparatus having the configuration shown in FIG. 1 has been described above.

  Now, for example, instead of the PLL unit 5 (see FIG. 10 for the detailed configuration) to which the present invention is applied to the data reproducing apparatus having the configuration of FIG. Consider a playback device with a PLL section. That is, FIG. 3 shows a configuration example of a conventional PLL unit.

  In the example of FIG. 3, the conventional PLL unit is configured as a Digital ITR type PLL circuit. For this reason, in the example of FIG. 3, the interpolation filter unit 11 to the remainder accumulation unit 14 are provided in the conventional PLL unit.

  The interpolation filter unit 11 is configured as an interpolation filter having a filter coefficient for converting the asynchronous sampling data input from the AGC / DCC unit 4 of FIG. 1 into synchronous sampling data. That is, the interpolation filter unit 11 selects a predetermined one from a plurality of filter coefficients based on the information supplied from the remainder accumulating unit 14, and determines the phase of the asynchronous sampling data corresponding to the selected filter coefficient. Just shift. As a result, the sampling data output from the interpolation filter unit 11 is close to the synchronous sampling data.

  In other words, in a transition period or the like, the sampling data output from the interpolation filter unit 11 is not yet accurately synchronized with the channel frequency fch. That is, there is a phase error in the sampling data output from the interpolation filter unit 11. For this reason, the PLL unit performs feedback control to make the phase error as close to 0 as possible, and as a result, outputs the sampling data substantially synchronized with the channel frequency fch. In order to perform such feedback control, in addition to the interpolation filter unit 11, a phase error information detection unit 12, a loop filter unit 13, and a residue accumulation unit 14 are provided. That is, the interpolation filter unit 11 to the remainder accumulation unit 14 constitute a feedback loop.

  However, in the following description, the sampling data output from the interpolation filter unit 11 are collectively referred to as synchronous sampling data. That is, even sampling data that includes some phase error is referred to as synchronous sampling data.

  The phase error information detection unit 12 is provided with an algorithm corresponding to, for example, PR (1, -1) equalization, detects information indicating the phase error of synchronous sampling data (hereinafter referred to as phase error information), Provided to the loop filter unit 13.

  Specifically, the phase error information detection unit 12 includes a slice unit 21 and a phase error detection unit 22.

  Hereinafter, the synchronous sampling data for which the phase error is detected by the phase error information detection unit 12, that is, the sampling value of the current processing target is referred to as data_now. On the other hand, the synchronous sampling data immediately before data_now is referred to as data_D.

  In this case, the slicing unit 21 tentatively determines a value that data_now can originally take by comparing the actual value of data_now with a predetermined threshold th, and uses the tentative determination value (hereinafter referred to as a slice value) as a phase. The error detection unit 22 is provided.

  Specifically, for example, since the synchronous sampling data is a digital signal shaped by PR (1, -1) equalization here, 1, 0, -1 is a value that data_now can originally take. That is, for example, in the present embodiment, the slicing unit 21 determines which of the following inequalities (1) to (3) the data_now satisfies.

data_now ≧ th (1)
th>data_now> -th (2)
-th ≧ data_now (3)

  When the inequality (1) is satisfied, the slice unit 21 is 1. When the inequality (2) is satisfied, the slice value is 0. When the inequality (3) is satisfied, the slice unit 21 satisfies the inequality (3). Each slice value is determined to be −1, and the determined slice value is provided to the phase error detector 22.

  The phase error detection unit 22 calculates the phase_err as phase error information by calculating the right side of the next Mueller & Mueller equation (4), and provides it to the loop filter unit 13. In Expression (4), slice_now indicates a slice value corresponding to data_now, and slice_D indicates a slice value corresponding to data_D.

  phase_err = (data_now * slice_D)-(data_D * slice_now) (4)

  The loop filter unit 13 performs a loop filter operation using a predetermined loop filter coefficient and a predetermined initial value as required in addition to the phase error information supplied from the phase error detection unit 22, and the calculation The result is provided to the remainder accumulation unit 14.

  The remainder accumulation unit 14 performs a predetermined accumulation process on the loop filter calculation result of the loop filter unit 13, generates information necessary for the interpolation filter unit 11 based on the processing result, and stores the information in the interpolation filter unit 11. Provide necessary enable information for other blocks.

  In the conventional PLL section having such a configuration, there is a problem that the accuracy of the phase error information is poor. Therefore, the present inventor has invented a technique capable of ascertaining the cause of this problem and removing the cause.

  Hereinafter, the cause of this problem will be described.

  That is, the conventional phase error information detection unit 12 calculates the phase error information (phase_err) using the above-described Mueller & Mueller equation (4).

  As can be seen from this equation (4), phase error information (phase_err) is calculated using slice_D and slice_now.

  However, depending on data_D and data_now output from the interpolation filter unit 11, the combination of slice_D and slice calculated from them (slice_D, slice_now), that is, the transition from slice_D to slice_now is usually in an ideal time (the error is There is a case that the pattern is completely different from the pattern that can occur when no occurrence has occurred.

  If (slice_D, slice_now) in such a case is substituted into the equation (4), the phase error information (phase_err) obtained as a result of course has an inaccurate (inaccurate) value. That is, the above-described problem occurs.

  As described above, the conventional PLL unit calculates the phase error information using the same calculation method even when the (slice_D, slice_now) pattern is different from the normal ideal pattern. That is, conventionally, a pattern different from the normal ideal pattern (hereinafter referred to as a specific pattern) is not considered at all as the (slice_D, slice_now) pattern. Furthermore, considering the slice value two times before slice_now (hereinafter referred to as slice_2D), the pattern that would normally occur at the ideal time by looking at (slice_D, slice_now) is (slice_2D, slice_D, slice_now) ), There is a specific pattern. Conventionally, such a specific pattern has not been taken into account. This is considered to be the cause of the problem described above.

  Therefore, the present inventor has invented the following method in order to solve such problems.

  That is, when the transition pattern of the slice value is determined, for example, (slice_2D, slice_D, slice_now), (slice_D, slice_now), etc. are determined, and the determined transition pattern is a normal ideal pattern (a pattern that is not a specific pattern) In this method, the calculation result of the above-described formula (4) is used as phase error information, and when the determined transition pattern is a specific pattern, the method of using phase error information corresponding to the specific pattern is used. Invented by the inventor. Note that the phase error information corresponding to the specific pattern naturally includes a value different from the calculation result of Expression (4), and also includes the calculation result of Expression (4) as a result (see FIG. 8 described later). There is also.

  FIG. 4 shows a configuration example of the phase synchronization apparatus to which the method of the present invention is applied, that is, a configuration example of the PLL unit 5 of FIG. In the PLL unit 5 of FIG. 4, the same reference numerals are given to the parts corresponding to those of the conventional PLL unit of FIG. 3, and the description thereof is omitted as appropriate.

  In the example of FIG. 4, the PLL unit 5 is configured as a Digital ITR type PLL circuit. For this reason, in the example of FIG. 4, the PLL unit 5 includes an interpolation filter unit 11, a phase error information detection unit 31, a loop filter unit 13, and a remainder accumulation unit 14. That is, the PLL unit 5 in the example of FIG. 4 employs a phase error information detection unit 31 instead of the phase error information detection unit 12 with respect to the conventional PLL unit of FIG.

  Therefore, only the phase error information detection unit 31 will be described below.

  In the example of FIG. 4, the phase error information detection unit 31 includes a slice unit 41 and a phase error detection unit 42.

  The slicing unit 41 has basically the same configuration and function as the slicing unit 21 of FIG. That is, when the synchronous sampling data output from the PLL unit 5 is a digital signal shaped into PR (1, -1) equalization, the slice unit 41 determines that the data_now is the inequality (1) to (1) to It is determined which of (3) is satisfied. When the inequality (1) is satisfied, the slice unit 41 indicates that the slice value is 1. When the inequality (2) is satisfied, the slice value is 0. When the inequality (3) is satisfied, Each slice value is determined to be −1, and the determined slice value is provided to the phase error detector 42 as slice_now.

  In the example of FIG. 4, the phase error detector 42 includes a specific pattern detector 51 and a phase error information calculator 52.

  Whether the transition pattern of the past several slice values (slice values that have been sequentially provided as slice_now) provided from the slice unit 41 is a specific pattern or not (Whether it is a normal ideal pattern).

  Note that specific examples of normal ideal patterns and specific patterns will be described later with reference to FIGS.

  The determination result of the specific pattern detection unit 51 is supplied to the phase error information calculation unit 52. For example, when a determination result indicating that the pattern is not a specific pattern (usually a pattern at an ideal time) is supplied from the specific pattern detection unit 51, the phase error information calculation unit 52 calculates the calculation method represented by the above equation (4). Phase error information is calculated according to (hereinafter referred to as a reference calculation method), that is, phase_err is calculated as phase error information and provided to the loop filter unit 13. On the other hand, for example, when the determination result that the pattern is a specific pattern is supplied from the specific pattern detection unit 51, the phase error information calculation unit 52 calculates the phase error information according to the calculation method corresponding to the specific pattern, and the loop Provided to the filter unit 13. The calculation method corresponding to the specific pattern naturally includes a method different from the reference calculation method, and may include the reference calculation method itself (see FIG. 8 described later). A specific example of the calculation method corresponding to the specific pattern will be described later with reference to FIGS.

  An example of the processing of the phase error information detection unit 31 having such a configuration (hereinafter referred to as phase error information detection processing) is shown in the flowchart of FIG. Therefore, an example of the phase error information detection process will be described below with reference to the flowchart of FIG.

  In step S21, the phase error information detection unit 31 acquires one sampling value of the synchronous sampling data output immediately before from the interpolation filter unit 11 as data_now. When this data_now is supplied to the slice unit 41 and the phase error information calculation unit 52, the process proceeds to step S22.

  In step S22, the slice unit 41 acquires slice_now from data_now as described above. When this slice_now is supplied from the slice unit 41 to the specific pattern detection unit 51 and the phase error information calculation unit 52, the process proceeds to step S23.

  In step S23, the specific pattern detection unit 51 determines the transition pattern of the slice value as described above. When the determination result is supplied from the specific pattern detection unit 51 to the phase error information calculation unit 52, the process proceeds to step S24.

  In step S24, the phase error information calculation unit 52 determines whether or not the determination result of step S23 by the specific pattern detection unit 51 is a specific pattern.

  If it is determined in step S24 that the pattern is not a specific pattern, that is, if it is determined that the pattern is a normal ideal pattern, in step S25, the phase error information calculation unit 52 follows the reference calculation method as described above. Compute phase error information.

  On the other hand, if it is determined in step S24 that the pattern is a specific pattern, in step S26, the phase error information calculation unit 52 calculates phase error information according to the calculation method corresponding to the specific pattern as described above.

  When the phase error information is calculated by the phase error information calculation unit 52 and provided to the loop filter unit 13 in the process of step S25 or S26, the process proceeds to step S27.

  In step S27, the phase error information detection unit 31 sets data_now so far to data_D, and sets slice_now so far to slice_D. In some cases, the data_D so far is set to data_2D and the previous slice_D is set to slice_2D in the process of step S27. However, data_2D and slice_2D will be described later.

  In step S <b> 28, the phase error information detection unit 31 determines whether the output of the synchronous sampling data from the interpolation filter unit 11 has been completed.

  That is, as long as the output of the synchronous sampling data from the interpolation filter unit 11 continues, it is determined as NO in step S28, the process returns to step S21, and the loop process of steps S21 to S28 described above is repeatedly executed. Is done.

  When the output of the synchronous sampling data from the interpolation filter unit 11 is completed, it is determined as YES in Step S28, and the phase error information detection process is completed.

  Next, specific examples of the specific pattern and the calculation method corresponding to the specific pattern in step S26 will be described with reference to FIGS.

  FIG. 6 is an operation (algorithm) of the phase error information detection unit 12 of the conventional PLL unit of FIG. 3 described above, and is a diagram for explaining an algorithm in d = 1 and PR (1, -1) equalization. It is.

  As a precondition in FIG. 6, whether to appear or not is an item indicating whether or not a pattern (slice_D, slice_now) shown on the left side is present at the normal time (normal ideal time) with no error. . That is, in the item of whether to appear, the pattern of (slice_D, slice_now) shown on the left side with ◎ (double circle) is the above-described normal ideal pattern. On the other hand, the pattern of (slice_D, slice_now) shown on the left side with a cross (x) in the presence / absence of appearance is a pattern (one of the specific patterns) that cannot occur at normal time without error. .

  In addition, as a prerequisite of FIG. 6, whether or not correction is possible is an item indicating whether or not phase correction by phase_err (described below) can be performed when there is no error. That is, in the correction availability item, in the pattern (slice_D, slice_now) shown on the left side with ◎ (double circle), phase correction by phase_err can be performed when there is no error. On the other hand, when correction is possible, in the pattern (slice_D, slice_now) shown on the left side with-(bar mark), phase correction by phase_err cannot be performed when there is no error.

  Furthermore, as a prerequisite of FIG. 6, phase_err is an item indicating phase error information (a calculation method thereof). The forward direction phase_err indicates the above-described formula (4) (the formula shown in the lower part of FIG. 6) itself. That is, when there is no error and normal, the phase error information is calculated according to the calculation method (reference calculation method) represented by the above-described equation (4).

  These assumptions in FIG. 6 are similarly assumed in FIGS. 7 to 14 described later.

  Thus, in the past, as (slice_D, slice_now), (0, -1), (0, 1), (1, 0), and (-1, 0) are all normal ideal time patterns. It was handled. However, as described above, when considering even slice_2D, some of these patterns are classified into specific patterns. Conventionally, however, these specific patterns have not been considered at all.

  Therefore, the phase error information detection unit 31 of the PLL unit 5 of FIG. 4 to which the present invention is applied can determine the phase error information in accordance with, for example, the algorithm of FIG. That is, FIG. 7 is a diagram for explaining an example of the operation (algorithm) of the phase error information detection unit 31 of the PLL unit 5 of FIG. 4 to which the present invention is applied, where d = 1 and PR (1, -1) It is a figure explaining an example of the algorithm in equalization.

  The above-described conventional algorithm in FIG. 6 is an algorithm based on (slice_D, slice_now), which is a set of slice_D and slice_now delayed by one section of slice_now.

  On the other hand, the algorithm of the example of FIG. 7 to which the present invention is applied is an algorithm based on a set of slice_2D, slice_D, and slice_now (slice_2D, slice_D, slice_now) delayed by two sections of slice_now.

  That is, for example, even if (slice_D, slice_now) = (0, 1), (0,0,1) and (− 1,0,1) can occur (appear), but (1,0,1) does not occur. That is, (slice_2D, slice_D, slice_now) = (1,0,1) is an example of the specific pattern.

  In addition, as the specific pattern, as shown in FIG. 7, (slice_2D, slice_D, slice_now) = (− 1,0, −1), (1,1,0), (−1,1,0), There are (1, -1,0) and (-1, -1,0).

  Of the specific patterns, the specific pattern in which (Pha) is described as the possibility of appearance is a pattern that occurs when the phase position of data_now exists in the back phase (hereinafter referred to as the back phase state). It shows that there is. The back phase refers to a phase position when the phase position of data_D and data_now has a value of only one of data_D and data_now exceeding a predetermined threshold value.

  That is, there are two types of specific patterns. The first type is a first specific pattern that occurs in a reverse phase state in which only the phase position of the synchronous sampling data has shifted, although the transition of the synchronous sampling data is normally an ideal transition. In the second type, due to factors such as errors, regardless of the phase position of the synchronous sampling data (whether it is shifted or not shifted), the transition usually becomes a pattern that cannot exist in ideal time. This is the second specific pattern that results. For this reason, in FIGS. 7 to 14 including FIG. 7, p is described on the left of at least a part of the column (row) of the former first specific pattern, and the latter second specific pattern is included. E is described on the left side of at least a part of the pattern column (row). Note that the * (US symbol) to the left of e or p indicates that phase_err has been newly defined.

  Thus, in the example algorithm of FIG. 7, (slice_2D, slice_D, slice_now) is (1,0,1), (-1,0, -1), (1,1,0), (-1, 1,0), (1, -1,0), or (-1, -1,0), the specific pattern detection unit 51 in FIG. The error information calculation unit 52 outputs 0 as phase error information (does not output phase error information).

  The position error information calculation unit 52 may output a predetermined constant instead of 0 as the phase error information.

  By adopting such an algorithm of FIG. 7, a system in which PR (1, -1) equalization is performed using an RLL code of d = 1 (for example, in this embodiment, the data of FIG. 1 is used). Even when the input signal deteriorates due to disturbance or the like in the entire playback device), it is possible to provide a higher quality phase error output, and as a result, the error rate can be improved, and the system is stabilized. be able to.

  By the way, it is desirable that the phase error information is output in a wrong direction and for each sample as much as possible as a phase error output with higher quality.

  For example, when (slice_2D, slice_D, slice_now) is (-1,1,0) or (1, -1,0), the output direction of the phase error information at the time of error is highly likely to be forward It is a pattern. Therefore, for such a specific pattern, the position error information calculation unit 52 may output the forward phase_err instead of 0 as the phase error information. That is, the position error information calculation unit 52 may calculate the phase error information according to a reference calculation method (the above-described equation (4)).

  The algorithm in this case is as shown in FIG. That is, FIG. 8 shows another example of the algorithm of the phase error information detection unit 31 when d = 1 and PR (1, −1) equalization.

  As in the algorithm of FIG. 8, the specific pattern is further classified and the phase error output is given individually, that is, the phase error information is calculated according to a different calculation method for each classified type. Therefore, it becomes possible to provide a phase error output with higher quality.

  Furthermore, the phase error information detection unit 31 can also determine the phase error information according to the algorithm of FIG. That is, FIG. 9 shows another example of the algorithm of the phase error information detection unit 31 when d = 1 and PR (1, −1) equalization.

  The algorithm of the example of FIG. 9 is the following algorithm for the purpose of outputting phase error information more suitable than the examples of FIGS. 7 and 8 described above.

  That is, in the example of FIG. 9, (slice_2D, slice_D, slice_now) = (0,1,1), (-1,1,1), (-1, -1,1) is further added to the example of FIG. ), (1,1, -1), (0, -1, -1), (1, -1, -1), etc., the phase error information calculation unit 52 reverses the phase error information. An algorithm that outputs the direction rev_phase_err is added.

  The reverse direction rev_phase_err corresponds to a value obtained by inverting the sign of phase_err, and is calculated by, for example, the following equation (5) (= the same equation as the lowest equation in FIG. 9).

  rev_phase_err = -phase_err (5)

  In addition, rev_phase_err may be calculated from the following equation (6) instead of the above equation (5). In Expression (6), (inverted sign of phase_err output) means − (minus) when the calculation result phase_err of Expression (4) is a positive value (when the sign is +), and Expression (4) ) Is + (plus) when the calculation result phase_err is negative (when the sign is −). RLEV represents a predetermined constant (for example, a threshold value).

  rev_phase_err = (inverted sign of phase_err output) × RLEV (6)

  As described above, in the example of FIG. 9, among the specific patterns that occur in the back phase state (patterns that are described as (pha) as to whether to appear or not), a pattern in which both slice_now and sline_D are not 0 The reverse direction rev_phase_err is output as the phase error information. This is to realize the above-described “outputting the phase error information for each sample as much as possible without outputting it in the wrong direction”.

  Furthermore, the phase error information detector 31 can also determine the phase error information according to the algorithm of FIG. That is, FIG. 10 shows another example of the algorithm of the phase error information detection unit 31 when d = 1 and PR (1, −1) equalization.

  The algorithm of the example of FIG. 10 is the following algorithm for the purpose of outputting phase error information more suitable than the examples of FIGS. 7 to 9 described above.

  That is, in the example of FIG. 10, in the case of a specific pattern such as (slice_2D, slice_D, slice_now) = (0, -1,1), (0,1, -1) in addition to the example of FIG. The phase error information calculation unit 52 is added with an algorithm that outputs not the zero phase error information but the reverse direction rev_phase_err.

  That is, (slice_2D, slice_D, slice_now) = (0, -1,1), (0,1, -1), as described above, the transition is usually ideal regardless of the phase position of the synchronous sampling data. It is a specific pattern that results from a pattern that cannot exist at times. However, (slice_2D, slice_D, slice_now) = (0, -1,1), (0,1, -1) is a pattern in which the phase error output direction at the time of error is likely to be in the reverse direction It is. Therefore, in order to realize the above-described “outputting the phase error information in each sample as much as possible without outputting in the wrong direction”, in the example of FIG. 10, (slice_2D, slice_D, slice_now) = ( In the case of specific patterns such as 0, -1,1) and (0,1, -1), the reverse direction rev_phase_err is output.

  By the way, in the above-described example, an algorithm corresponding to PR (1, -1) equalization is given to the PLL unit 5 in FIG. 4, and therefore, the synchronous sampling data that is output is PR (1 , -1) It was supposed to be a digital signal shaped for equalization.

  However, the algorithm given to the PLL unit 5 is not particularly limited to an algorithm corresponding to PR (1, -1) equalization. For example, an algorithm corresponding to PR (1,0, −1) equalization may be given to the PLL unit 5. That is, the PLL unit 5 may output a digital signal shaped to PR (1,0, -1) equalization as synchronous sampling data.

  However, in this case, the slicing unit 41 determines a slice value according to an algorithm corresponding to PR (1,0, −1) equalization.

  In this case, as shown in FIG. 11, (slice_D, slice_now) patterns at normal time (normally ideal time) without error include (0, -1), (0, 1), (1, 0). And (-1, 0), and (1, -1), (1, 1), (-1, 1), (-1, 1), and (0, 0) exist (appear) Get). On the other hand, the pattern of (slice_D, slice_now) at the back phase is (0, -1), (0, 1), (1, 0), (-1, 0), and (0, 0). Exists.

  FIG. 11 shows the operation (algorithm) of the phase error information detection unit 12 of the conventional PLL unit shown in FIG. 3 described above, and shows an algorithm in d = 1 and PR (1,0, -1) equalization. It is a figure explaining.

  As shown in FIG. 11, in the conventional PLL section of FIG. 3, (slice_D, slice_now) is (1, 1), (-1, -1), (1, -1), (-1,- In any case of 1), it was recognized that the pattern was normally an ideal time, and the forward phase_err was output as phase error information. However, as described above, when considering even slice_2D, some of these patterns are classified into specific patterns. Conventionally, however, these specific patterns have not been considered at all.

  Therefore, the phase error information detection unit 31 in FIG. 4 according to the present embodiment uses the phase error information as the algorithm in d = 1 and PR (1,0, −1) equalization, for example, according to the algorithm in FIG. It can also be determined. That is, FIG. 12 shows an example of the algorithm of the phase error information detection unit 31 when d = 1 and PR (1,0, −1) equalization.

  Specifically, in the example algorithm of FIG. 12, (slice_2D, slice_D, slice_now) is (1,1,1), (0, -1,1), (1, -1,1), (0, 1, -1), (-1,1, -1), or (-1, -1, -1), the specific pattern detection unit 51 in FIG. 4 detects that it is a specific pattern. The position error information calculation unit 52 outputs 0 as phase error information (does not output phase error information).

  The position error information calculation unit 52 may output a predetermined constant instead of 0 as the phase error information.

  In this way, a system in which PR (1,0, −1) equalization is performed using an RLL code of d = 1 (for example, in this embodiment, the entire data reproduction apparatus in FIG. 1). However, even when the input signal is deteriorated due to disturbance or the like, it is possible to provide a phase error output with higher quality, and as a result, the error rate can be improved and the system can be stabilized.

  Furthermore, the phase error information detector 31 can also determine the phase error information according to the algorithm of FIG. That is, FIG. 13 shows another example of the algorithm of the phase error information detection unit 31 when d = 1 and PR (1,0, -1) equalization.

  The algorithm of the example of FIG. 13 is the following algorithm for the purpose of outputting phase error information that is more suitable than the example of FIG. 12 described above.

  That is, in the example of FIG. 13, in the case of a specific pattern such as (slice_2D, slice_D, slice_now) = (0, -1,1), (0,1, -1) in addition to the example of FIG. The phase error information calculation unit 52 outputs not phase 0 but forward phase_err as phase error information, and also specifies (slice_2D, slice_D, slice_now) = (-1,1,0), (1, -1,0) In the case of a pattern, an algorithm is added such that the phase error information calculation unit 52 outputs the reverse direction rev_phase_err as the phase error information. This is to realize the above-described “outputting the phase error information for each sample as much as possible without outputting it in the wrong direction”.

  Furthermore, the phase error information detection unit 31 can also determine the phase error information according to the algorithm of FIG. That is, FIG. 14 shows another example of the algorithm of the phase error information detection unit 31 when d = 1 and PR (1,0, -1) equalization.

  The example of FIG. 14 is the following algorithm for the purpose of outputting phase error information that is more suitable than the examples of FIGS. 12 and 13 described above.

  That is, in the example of FIG. 14, in addition to the example of FIG. 13, in the case of a specific pattern such as (slice_2D, slice_D, slice_now) = (0,1,0), (0, −1,0), The error information calculation unit 52 is added with an algorithm that outputs backward (2D) rev_phase_err_2D as phase error information. This is to realize the above-described “outputting the phase error information for each sample as much as possible without outputting it in the wrong direction”.

  The reverse direction (2D) rev_phase_err_2D corresponds to a value obtained by inverting the sign of phase_err_2D on the left side of the following equation (7) (the second underlined equation from the top in FIG. 14).

phase_err_2D = (data_now x slice_D)-(data_2D x slice_D)
... (7)

  Accordingly, the reverse direction (2D) rev_phase_err_2D refers to the following equation (8) (the lowest equation in FIG. 14) or the value on the left side of equation (9).

  rev_phase_err_2D = -phase_err_2D (8)

rev_phase_err_2D = (inverted sign of phase_err_2D output) × RLEV (9)
In Expression (9), (inverted sign of phase_err_2D output) indicates that it is-when the sign of phase_err_2D is + and + when the sign of phase_err_2D is-. Or, RLEV indicates a predetermined constant.

  As shown in the examples of FIG. 13 and FIG. 14 described above, the specific pattern is further classified and the phase error output is given individually, that is, the phase error information is obtained in accordance with a different calculation method for each classified type. By calculating each, it becomes possible to give a phase error output with better quality.

  By the way, since the specific pattern can be classified into two or more types as described above, the PLL unit 5 shown in FIG. 1 has a configuration shown in FIG. 15, for example, instead of the PLL unit shown in FIG. A PLL section can also be adopted. That is, FIG. 15 shows a detailed configuration example (configuration example different from FIG. 4) of the PLL unit 5 of FIG. 1 when the specific patterns are classified into two types.

  In the PLL unit 5 of FIG. 15, the same reference numerals are given to the portions corresponding to those of the example of FIG. 4, and the description thereof will be omitted as appropriate.

  In the example of FIG. 15 as well, the PLL unit 5 is configured as a Digital ITR type PLL circuit. For this reason, in the example of FIG. 15, the PLL unit 5 includes an interpolation filter unit 11, a phase error information detection unit 61, a loop filter unit 13, and a remainder accumulation unit 14. That is, in the example of FIG. 15, the PLL unit 5 is configured to include a phase error information detection unit 61 instead of the phase error information detection unit 31 with respect to that of the example of FIG. 4.

  Therefore, only the phase error information detection unit 61 will be described below.

  In the example of FIG. 15, the phase error information detection unit 61 includes a slice unit 41 and a phase error detection unit 72.

  The slicing unit 41 has basically the same configuration and function as that of FIG.

  In the example of FIG. 15, the phase error detection unit 72 includes a first specific pattern detection unit 81, a second specific pattern detection unit 82, and a phase error information calculation unit 52.

  Whether the first specific pattern detection unit 81 has a transition pattern of several past slice values provided from the slice unit 41 is a predetermined one type (first type) of two types of specific patterns, Or, determine whether this is not the case.

  The second specific pattern detection unit 82 is a type (second type) in which the transition patterns of several past slice values provided from the slice unit 41 are different from the first type of the two types of specific patterns. It is determined whether or not.

  Each of the determination result of the first specific pattern detection unit 81 and the determination result of the second specific pattern detection unit 82 is supplied to the phase error information calculation unit 52. This phase error information calculation unit 52 has basically the same configuration and function as that of FIG.

  As described above, when the specific patterns are classified into two types, the first specific pattern detection unit 81 that detects the first type of specific pattern and the second type that detects the second type of specific pattern. What is necessary is just to employ | adopt the phase error information detection part 61 which has the specific pattern detection part 82. FIG.

  Therefore, when the specific patterns are classified into N types (N is an integer value of 2 or more), the first specific pattern detection unit to the Nth type specific patterns for detecting the first type specific patterns are used. What is necessary is just to employ | adopt the phase error information detection part which has the Nth specific pattern detection part to detect.

  By the way, the method of the present invention, that is, the method of calculating phase error information corresponding to a specific pattern when the transition of the slice value that does not normally exist at the ideal time is a specific pattern, is d = 1 and PR (1, − 1) It is not limited to equalization or PR (1,0, -1) equalization.

  Specifically, for example, in the case of d = 2 and PR (1, -1) equalization, the transition of the slice value is a pattern in which + 1 → -1 or a pattern in which -1 → + 1, that is, (slice_D , Slice_now) is (1, -1) and (-1,1) is the second type of specific pattern. Furthermore, a pattern in which the transition of the slice value is +1 → +1 or a pattern in which −1 → −1, ie, (slice_D, slice_now) is (1,1) or (-1, -1) is the first. It is a specific type of pattern. Therefore, for such specific patterns, the phase error information corresponding to each specific pattern may be calculated.

  Further, for example, in the case of d = 2 and PR (1,0, -1) equalization, a pattern in which the transition of the slice value is + 1 → -1 or a pattern in which -1 → + 1 is satisfied, that is, (slice_D, (slice_now) is (1, -1) and (-1,1) is the second type of specific pattern. A pattern in which the transition of the slice value is 0 → +1 → 0 or a pattern that is 0 → −1 → 0, that is, (slice_2D, slice_D, slice_now) is (0, 1, 0) or (0, -1, 0 ) Is the first type of specific pattern. Therefore, for such specific patterns, the phase error information corresponding to each specific pattern may be calculated.

  That is, after all, the specific pattern differs depending on the combination of d and the PR equalization method, but any combination corresponds to the specific pattern when the specific pattern is generated by the combination. What is necessary is just to calculate phase error information.

  Further, for example, the method of the present invention is applied not only to the PLL unit 5 having the slice unit 41 of FIGS. 4 and 15 described above, but also to the PLL unit having a slice unit that outputs a temporary determination value. Can be applied in exactly the same way.

  Further, for example, the method of the present invention is not limited to the PLL unit 5 in the examples of FIGS. 4 and 15 described above, but an A / D conversion unit without using an interpolation filter unit as shown in FIG. The present invention can be applied to a PLL unit using a VCO (Voltage Controlled Oscillator) that changes the sampling frequency and phase of the same. That is, FIG. 16 shows a configuration example different from the examples of FIGS. 4 and 15 of the PLL unit to which the present invention is applied.

  In the example of FIG. 16, the PLL unit 61 includes an analog equalization unit 101, an A / D conversion unit 102, a phase error information detection unit 31, a loop filter unit 103, a D / A conversion unit 104, and a VCO unit 105. ing.

  The analog equalization unit 101 generates an analog signal shaped into a predetermined PR method, for example, PR (1, −1) equalization, from the reproduced RF signal, and supplies the analog signal to the A / D conversion unit 102.

  The A / D conversion unit 102 generates digital synchronous sampling data by synchronously sampling the analog signal from the analog equalization unit 101 so as to synchronize with the frequency of the VCO output signal from the VCO unit 105, and outputs it. To do.

  The synchronous sampling data from the A / D conversion unit 102 is also supplied to the phase error information detection unit 31. This phase error information detection unit 31 is also employed in the PLL unit 5 in the example of FIG. 4 described above. Therefore, the description of the phase error information detection unit 31 is omitted.

  The loop filter unit 103 performs a loop filter operation using a predetermined loop filter coefficient and a predetermined initial value as necessary in addition to the phase error information supplied from the phase error information detection unit 31, The calculation result is provided to the D / A converter 104.

  The D / A conversion unit 104 converts the digital signal that is the loop filter calculation result of the loop filter unit 103 into an analog signal, and provides the analog signal to the VCO unit 105 as a VCO input signal.

  The VCO unit 105 generates a VCO output signal corresponding to the voltage level of the VCO input signal from the D / A conversion unit 104 and provides it to the A / D conversion unit 102 and the like.

  Although not shown, the method of the present invention is also applied to a PLL unit that employs the phase error information detection unit 61 of FIG. 15 instead of the phase error information detection unit 31 with respect to the PLL unit 91 of FIG. be able to.

  As described above, the method of the present invention can be applied to various PLLs such as the PLL unit 5 in the examples of FIGS. 4 and 15 and the PLL unit 91 in the example of FIG. In other words, instead of the conventional phase error information detection unit 12 of FIG. 3, the phase error information detection unit 31 of the example of FIG. 4 and the phase error information detection unit 61 of the example of FIG. It is possible to easily realize a PLL to which the method is applied.

  Furthermore, the PLL to which the present invention is applied can be applied not only to the data reproduction apparatus of FIG. 1 but also easily to various apparatuses and systems (the system will be described later).

  In addition, for example, the technique of the present invention includes a predetermined filter unit that generates an analog signal that can be adapted to predetermined PR equalization from a reproduced RF signal, instead of the differential filter unit 1 of FIG. 1 described above. The present invention can also be applied to the adopted data reproducing apparatus.

  Furthermore, for example, the technique of the present invention is also applicable to a data reproducing apparatus in which a data detection unit capable of detecting an RLL code from synchronous sampling data from the PLL unit 5 is used instead of the PRML unit 6 in FIG. Applicable.

  By the way, the above-described series of processes (or a part of them) can be executed by hardware, but can also be executed by software.

  In this case, the entire data reproducing apparatus in FIG. 1 or a part thereof (for example, the PLL unit 5) or the PLL unit 91 in FIG. 16 can be configured by, for example, a computer shown in FIG.

  In FIG. 17, a CPU (Central Processing Unit) 201 executes various processes according to a program recorded in a ROM (Read Only Memory) 202 or a program loaded from a storage unit 208 to a RAM (Random Access Memory) 203. To do. The RAM 203 also appropriately stores data necessary for the CPU 201 to execute various processes.

  The CPU 201, the ROM 202, and the RAM 203 are connected to each other via the bus 204. An input / output interface 205 is also connected to the bus 204.

  The input / output interface 205 includes an input unit 206 composed of a keyboard and a mouse, an output unit 207 composed of a display, a storage unit 208 composed of a hard disk, and a communication unit 209 composed of a modem and a terminal adapter. It is connected. The communication unit 209 performs communication processing with other devices (not shown) via a network including the Internet.

  A drive 210 is also connected to the input / output interface 205 as necessary, and a removable recording medium 211 made of a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is appropriately installed, and a computer program read therefrom Are installed in the storage unit 208 as necessary.

  When a series of processing is executed by software, the program that constitutes the software executes a variety of functions by installing a computer embedded in dedicated hardware or various programs. It is installed from a network or a recording medium on a computer (for example, a general-purpose personal computer) that can perform the above-described operation.

  As shown in FIG. 17, the recording medium including such a program is distributed to provide a program to the user separately from the apparatus main body, and a magnetic disk (including a floppy disk) on which the program is recorded, Removable recording media (package media) consisting of optical disks (including compact disk-read only memory (CD-ROM), DVD (digital versatile disk)), magneto-optical disks (including MD (mini-disk)), or semiconductor memory ) 211, but also includes a ROM 202 in which a program is recorded and a hard disk included in the storage unit 208 provided to the user in a state of being incorporated in the apparatus main body in advance.

  In the present specification, the step of describing the program recorded on the recording medium is not limited to the processing performed in chronological order according to the order, but is not necessarily performed in chronological order, either in parallel or individually. The process to be executed is also included.

  In addition, as described above, in this specification, the system represents the entire apparatus including a plurality of processing devices and a plurality of processing units.

It is a figure which shows the structural example of one Embodiment of the data reproduction apparatus to which this invention is applied. 3 is a flowchart for explaining an example of data reproduction processing of the data reproduction apparatus of FIG. 1. It is a figure which shows the structural example of the conventional Digital ITR type PLL. FIG. 2 is a diagram showing a configuration example of an embodiment of a phase synchronization apparatus to which the present invention is applied, which is a PLL unit mounted in the data reproduction apparatus of FIG. 1. It is a flowchart explaining an example of the phase error information detection process of the phase error information detection part of FIG. FIG. 4 is a diagram illustrating an example of a conventional algorithm of the conventional phase error information detection unit of FIG. 3 in PR (1, -1) equalization. FIG. 5 is a diagram illustrating an example of an algorithm of a phase error information detection unit in FIG. 4 in d = 1 and PR (1, −1) equalization based on the present invention. FIG. 5 is a diagram showing another example of the algorithm of the phase error information detection unit in FIG. 4 in d = 1 and PR (1, -1) equalization based on the present invention. FIG. 5 is a diagram showing another example of the algorithm of the phase error information detection unit in FIG. 4 in d = 1 and PR (1, -1) equalization based on the present invention. FIG. 5 is a diagram showing another example of the algorithm of the phase error information detection unit in FIG. 4 in d = 1 and PR (1, -1) equalization based on the present invention. FIG. 4 is a diagram illustrating an example of a conventional algorithm of the conventional phase error information detection unit in FIG. 3 in PR (1, 0, −1) equalization. FIG. 5 is a diagram showing an example of an algorithm of a phase error information detection unit in FIG. 4 in d = 1 and PR (1, 0, −1) equalization based on the present invention. FIG. 5 is a diagram showing another example of the algorithm of the phase error information detection unit of FIG. 4 in d = 1 and PR (1, 0, −1) equalization based on the present invention. FIG. 5 is a diagram showing another example of the algorithm of the phase error information detection unit of FIG. 4 in d = 1 and PR (1, 0, −1) equalization based on the present invention. It is a figure which shows the structural example of embodiment different from FIG. 4 of the phase synchronizing apparatus with which this invention is applied. It is a figure which shows the structural example of embodiment different from FIG.4 and FIG.15 of the phase synchronizing apparatus with which this invention is applied. It is a figure which shows the example of a structure about embodiment in which all or one part of the data reproduction apparatus and phase-synchronization apparatus to which this invention is applied was comprised by the computer.

Explanation of symbols

  1 differential filter section, 2 A / D conversion section, 3 EQ section, 4 AGC / DCC section, 5 PLL section, 6 PRML section, 7 decoding section, 11 interpolation filter section, 13 loop filter section, 14 remainder accumulation section, 31 phase error information detection unit, 41 slice unit, 42 phase error detection unit, 51 specific pattern detection unit, 52 phase error information calculation unit, 61 phase error information detection unit, 72 phase error detection unit, 81, 82 specific pattern detection unit , 101 analog equalization unit, 102 A / D conversion unit, 103 loop filter unit, 104 D / A conversion unit, 105 VCO unit, 201 CPU, 202 ROM, 208 storage unit, 211 removable recording medium

Claims (27)

When data recorded on a predetermined recording medium as an RLL recording code with d> 0 is read asynchronously at a predetermined frequency, synchronous data synchronized with the predetermined frequency is generated from the asynchronous data. In the phase synchronization device to
Phase error information detecting means for detecting phase error information indicating a phase error of the synchronization data;
The phase error information detection means includes
Specific pattern determining means for determining whether or not the predetermined information related to the sampling value to be processed among the sampling values constituting the synchronization data is a predetermined specific pattern, based on information based on the run restriction;
A phase error information calculating unit that calculates the phase error information by distinguishing between the case where it is determined that the specific pattern is determined by the specific pattern determining unit and the case where it is not.
The specific pattern is a pattern that cannot exist when the state within a predetermined range including the sampling value to be processed among the sampling values constituting the synchronization data is an ideal state,
When the specific pattern determination unit determines that the specific pattern is the specific pattern, the specific pattern determination unit further determines which type of the specific pattern is classified into a plurality of types,
The phase error information calculating means further calculates the phase error information by distinguishing each of a plurality of types of the specific pattern. As the plurality of types of the specific pattern, a first type generated due to a phase position of sampling data within the predetermined range including the sampling data to be processed being deviated from an ideal state position, and the predetermined pattern 2. The phase synchronization apparatus according to claim 1, wherein there is at least a second type that does not depend on a phase position of the sampling data within the range and cannot exist in an ideal state. The phase error information calculation unit calculates the phase error information according to a first calculation method as a reference when the specific pattern determination unit determines that the specific pattern is not, and the phase error information calculation unit calculates the phase error information of the specific pattern. When it is determined that it is one type, the phase error information is calculated according to a second calculation method, and when it is determined that it is the second type of the specific pattern, according to a third calculation method The phase synchronization apparatus according to claim 2, wherein the phase error information is calculated. The phase synchronization apparatus according to claim 3, wherein at least one of the second calculation method and the third calculation method is a method of outputting a fixed 0 as the phase error information. At least one of the second calculation method and the third calculation method uses a value of a different sign for the value calculated as the phase error information according to the first calculation method. The phase synchronization device according to claim 3 , wherein the phase synchronization device is calculated as follows. The first calculation method is a method of outputting a calculation value based on a predetermined calculation formula as the phase error information,
At least one of the second calculation method and the third calculation method is a method of outputting a value obtained by inverting the sign of the calculation value according to the predetermined calculation formula as the phase error information. The phase synchronizer according to claim 3 . When data recorded on a predetermined recording medium as an RLL recording code with d> 0 is read asynchronously at a predetermined frequency, synchronous data synchronized with the predetermined frequency is generated from the asynchronous data. In the phase synchronization method of the phase synchronization device to
A phase error information detection step of detecting phase error information indicating a phase error of the synchronization data,
The phase error information detection step includes:
A specific pattern determination step for determining whether or not the predetermined information related to the sampling value to be processed among the sampling values constituting the synchronization data is a predetermined specific pattern, based on information based on the run restriction;
A phase error information calculation step for calculating each of the phase error information by distinguishing between the case where it is determined that the specific pattern is determined by the processing of the specific pattern determination step and the case where it is not.
The specific pattern is a pattern that cannot exist when the state within a predetermined range including the sampling value to be processed among the sampling values constituting the synchronization data is an ideal state,
When it is determined that the specific pattern is determined by the processing of the specific pattern determination step, it is further determined which type of the specific pattern is classified into a plurality of types,
In the phase error information calculating step, the phase error information is calculated by distinguishing each of the plurality of types of the specific pattern. When data recorded on a predetermined recording medium as an RLL recording code with d> 0 is read asynchronously at a predetermined frequency, synchronous data synchronized with the predetermined frequency is generated from the asynchronous data. A program to be executed by a computer that controls processing to be performed,
A phase error information detection step of detecting phase error information indicating a phase error of the synchronization data,
The phase error information detection step includes:
A specific pattern determination step for determining whether or not the predetermined information related to the sampling value to be processed among the sampling values constituting the synchronization data is a predetermined specific pattern, based on information based on the run restriction;
A phase error information calculation step for calculating each of the phase error information by distinguishing between the case where it is determined that the specific pattern is determined by the processing of the specific pattern determination step and the case where it is not.
The specific pattern is a pattern that cannot exist when the state within a predetermined range including the sampling value to be processed among the sampling values constituting the synchronization data is an ideal state,
When it is determined that the specific pattern is determined by the processing of the specific pattern determination step, it is further determined which type of the specific pattern is classified into a plurality of types,
In the phase error information calculation step, the phase error information is calculated by distinguishing each of the plurality of types of the specific pattern. In a data reproducing apparatus for reproducing data recorded on a predetermined recording medium as an RLL recording code of d> 0,
Differentiating means for generating a differential response signal of the analog signal when the data is read out from the predetermined recording medium as an analog signal;
Sampling means for generating asynchronous data by asynchronously sampling the differential response signal of analog generated by the differentiating means at a predetermined frequency;
Phase synchronization means for generating synchronous data synchronized with the predetermined frequency from the asynchronous data generated by the sampling means, and
The phase synchronization means includes phase error information detection means for detecting phase error information indicating a phase error of the synchronization data according to an algorithm of PR (1, -1) equalization,
The phase error information detection means includes
Specific pattern determining means for determining whether or not the predetermined information related to the sampling value to be processed among the sampling values constituting the synchronization data is a predetermined specific pattern, based on information based on the run restriction;
A phase error information calculating unit that calculates the phase error information by distinguishing between the case where it is determined that the specific pattern is determined by the specific pattern determining unit and the case where the specific pattern is not determined;
Slice means for comparing each of the sampling values constituting the synchronous sample with a predetermined threshold and calculating a slice value based on the result of the comparison,
The specific pattern is a pattern that cannot exist when the state within a predetermined range including the sampling value to be processed among the sampling values constituting the synchronization data is an ideal state,
Among the sampling values constituting the synchronization data, the sampling data to be processed is a first value, and the value immediately before the first value is the second value,
The specific pattern determining means includes
Of the slice values calculated by the slicing means, based on a combination of a second slice value corresponding to the second value and a first slice value corresponding to the first value, Determine whether it is a specific pattern,
The phase error information calculation means includes
If it is determined that it is not the specific pattern,
The first value is data_now, the second value is data_D, the first slice value is slice_now, the second slice value is slice_D, and the phase error information is phase_err.
phase_err = (data_now * slice_D)-(data_D * slice_now)
The phase error information is calculated according to a first calculation method that uses an arithmetic expression represented by:
If it is determined that the specific pattern, further determine which type of the specific pattern is classified into a plurality of types, distinguish each of the plurality of types of the specific pattern, A data reproducing apparatus, wherein the phase error information is calculated according to a calculation method different from the first calculation method. The data reproducing apparatus according to claim 9, wherein at least a first type and a second type exist as the plurality of types of the specific pattern. The phase error information calculation unit calculates the phase error information according to the first calculation method when the specific pattern determination unit determines that the specific pattern is not the specific pattern, and the first error of the specific pattern is calculated. When it is determined that the type is a type, the phase error information is calculated according to a second calculation method different from the first calculation method, and the second type of the specific pattern is determined. The data reproduction apparatus according to claim 9, wherein the phase error information is calculated according to a third calculation method different from the first calculation method. At least one of the second calculation method and the third calculation method is:
The phase error information as rev_phase_err
rev_phase_err = -phase_err
The data reproducing apparatus according to claim 11, wherein the calculation method uses an arithmetic expression represented by: At least one of the second calculation method and the third calculation method is:
When the sign of phase_err is +, it is-and when the sign of phase_err is-, it is described as (inverted sign of phase_err output),
Let RLEV be a predetermined constant,
The phase error information as rev_phase_err
rev_phase_err = (inverted sign of phase_err output) × RLEV
The data reproducing apparatus according to claim 11, wherein the calculation method uses an arithmetic expression represented by: The data reproducing apparatus according to claim 11, wherein at least one of the second calculation method and the third calculation method is a method of outputting a predetermined value as the phase information. D = 1 of the RLL recording code recorded on the recording medium,
The data reproducing apparatus according to claim 9, wherein the phase error information detecting means detects the phase error information according to a PR (1,0, -1) equalization algorithm. Among the sampling values constituting the synchronization data, the sampling data to be processed is a first value, and the value immediately before the first value is the second value, The value immediately before the second value is the third value,
The specific pattern determination unit includes a third slice value corresponding to the third value and a second slice value corresponding to the second value among the slice values calculated by the slicing unit. Determining whether the specific pattern is based on a combination with a first slice value corresponding to the first value;
The phase error information calculation means includes
If it is determined that it is not the specific pattern,
The first value is data_now, the second value is data_D, the first slice value is slice_now, the second slice value is slice_D, and the phase error information is phase_err,
When slice_now and slice_D are not 0,
phase_err = (data_now * slice_D)-(data_D * slice_now)
The phase error information is calculated according to a first calculation method that uses an arithmetic expression represented by:
The data reproducing apparatus according to claim 15, wherein when the pattern is determined to be the specific pattern, the phase error information is calculated according to a calculation method different from the first calculation method. The data reproducing apparatus according to claim 16, wherein the calculation method different from the first calculation method is a method of outputting a predetermined value as the phase error information. When the specific pattern determination unit determines that the specific pattern is the specific pattern, the specific pattern determination unit further determines which type of the specific pattern is classified into a plurality of types,
The data reproduction device according to claim 16, wherein the phase error information calculation unit further calculates the phase error information by distinguishing each of the plurality of types of the specific pattern. The data reproducing device according to claim 18, wherein at least a first type and a second type exist as the plurality of types of the specific pattern. The phase error information calculation unit calculates the phase error information according to the first calculation method when the specific pattern determination unit determines that the specific pattern is not the specific pattern, and the first error of the specific pattern is calculated. When it is determined that the type is a type, the phase error information is calculated according to a second calculation method different from the first calculation method, and the second type of the specific pattern is determined. The data reproduction apparatus according to claim 19, wherein the phase error information is calculated according to a third calculation method different from the first calculation method. At least one of the second calculation method and the third calculation method is:
The phase error information as rev_phase_err
rev_phase_err = -phase_err
The data reproducing apparatus according to claim 20, wherein the calculation method uses an arithmetic expression represented by: At least one of the second calculation method and the third calculation method is:
When the sign of phase_err is +, it is-and when the sign of phase_err is-, it is described as (inverted sign of phase_err output),
Let RLEV be a predetermined constant,
The phase error information as rev_phase_err
rev_phase_err = (inverted sign of phase_err output) × RLEV
The data reproducing apparatus according to claim 20, wherein the calculation method uses an arithmetic expression represented by: The data reproducing apparatus according to claim 20, wherein at least one of the second calculation method and the third calculation method is a method of outputting a predetermined value as the phase information. The second calculation method is
The third value is data_2D,
The third slice value is slice_2D,
phase_err_2D = (data_now x slice_D)-(data_2D x slice_D)
The phase error information as rev_phase_err_2D
rev_phase_err_2D = −phase_err_2D
Is an arithmetic method using the arithmetic expression shown in FIG.
The data reproducing apparatus according to claim 20, wherein the third calculation method is a method of outputting a predetermined value as the phase error information. The second calculation method is
The third value is data_2D,
The third slice value is slice_2D,
phase_err_2D = (data_now x slice_D)-(data_2D x slice_D)
When the sign of phase_err_2D is +, it is-and when the sign of phase_err_2D is-, it is described as (inverted sign of phase_err_2D output),
Let RLEV be a predetermined constant,
The phase error information as rev_phase_err_2D
rev_phase_err_2D = (inverted sign of phase_err_2D output) × RLEV
Is an arithmetic method using the arithmetic expression shown in FIG.
The data reproducing apparatus according to claim 20, wherein the third calculation method is a method of outputting a predetermined value as the phase error information. In a data reproduction method of a data reproduction apparatus for reproducing data recorded on a predetermined recording medium as an RLL recording code of d> 0,
A differentiation step for generating a differential response signal of the analog signal when the data is read out from the predetermined recording medium as an analog signal;
A sampling step for generating asynchronous data by sampling the analog differential response signal generated by the processing of the differential step asynchronously to a predetermined frequency;
A phase synchronization step for generating synchronization data synchronized with the predetermined frequency from the asynchronous data generated by the processing of the sampling step,
The phase synchronization step includes a phase error information detection step of detecting phase error information indicating a phase error of the synchronization data according to an algorithm of PR (1, -1) equalization;
The phase error information detection step includes:
A specific pattern determination step for determining whether or not the predetermined information related to the sampling value to be processed among the sampling values constituting the synchronization data is a predetermined specific pattern, based on information based on the run restriction;
A phase error information calculating step for distinguishing between the case where it is determined that the specific pattern is determined by the processing of the specific pattern determination step and the case where it is not, and calculating the phase error information respectively.
A step of comparing each of the sampling values constituting the synchronous sample with a predetermined threshold, and calculating a slice value based on a result of the comparison,
The specific pattern is a pattern that cannot exist when the state within a predetermined range including the sampling value to be processed among the sampling values constituting the synchronization data is an ideal state,
Among the sampling values constituting the synchronization data, the sampling data to be processed is a first value, and the value immediately before the first value is the second value,
In the processing of the specific pattern determination step,
Based on the combination of the second slice value corresponding to the second value and the first slice value corresponding to the first value among the slice values calculated by the processing of the slice step. , It is determined whether the specific pattern,
In the processing of the phase error information calculation step,
If it is determined that it is not the specific pattern,
The first value is data_now, the second value is data_D, the first slice value is slice_now, the second slice value is slice_D, and the phase error information is phase_err,
phase_err = (data_now * slice_D)-(data_D * slice_now)
The phase error information is calculated according to a first calculation method using an arithmetic expression represented by:
If it is determined that the specific pattern, further determine which type of the specific pattern is classified into a plurality of types, distinguish each of the plurality of types of the specific pattern, The data reproduction method, wherein the phase error information is calculated according to a calculation method different from the first calculation method. A program to be executed by a computer that controls processing for reproducing data recorded on a predetermined recording medium as an RLL recording code of d> 0,
A differentiation step for generating a differential response signal of the analog signal when the data is read out from the predetermined recording medium as an analog signal;
A sampling step for generating asynchronous data by sampling the analog differential response signal generated by the processing of the differential step asynchronously to a predetermined frequency;
A phase synchronization step for generating synchronization data synchronized with the predetermined frequency from the asynchronous data generated by the processing of the sampling step,
The phase synchronization step includes a phase error information detection step of detecting phase error information indicating a phase error of the synchronization data according to an algorithm of PR (1, -1) equalization;
The phase error information detection step includes:
A specific pattern determination step for determining whether or not the predetermined information related to the sampling value to be processed among the sampling values constituting the synchronization data is a predetermined specific pattern, based on information based on the run restriction;
A phase error information calculation step for calculating each of the phase error information by distinguishing between the case where it is determined that the specific pattern is determined by the processing of the specific pattern determination step and the case where it is not.
A step of comparing each of the sampling values constituting the synchronous sample with a predetermined threshold, and calculating a slice value based on a result of the comparison,
The specific pattern is a pattern that cannot exist when the state within a predetermined range including the sampling value to be processed among the sampling values constituting the synchronization data is an ideal state,
Among the sampling values constituting the synchronization data, the sampling data to be processed is a first value, and the value immediately before the first value is the second value,
In the processing of the specific pattern determination step,
Based on the combination of the second slice value corresponding to the second value and the first slice value corresponding to the first value among the slice values calculated by the processing of the slice step. , It is determined whether the specific pattern,
In the processing of the phase error information calculation step,
If it is determined that it is not the specific pattern,
The first value is data_now, the second value is data_D, the first slice value is slice_now, the second slice value is slice_D, and the phase error information is phase_err,
phase_err = (data_now * slice_D)-(data_D * slice_now)
The phase error information is calculated according to a first calculation method using an arithmetic expression represented by:
If it is determined that the specific pattern, further determine which type of the specific pattern is classified into a plurality of types, distinguish each of the plurality of types of the specific pattern, The phase error information is calculated according to a calculation method different from the first calculation method.

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