JP4687082B2 - Electronic device and wireless communication terminal - Google Patents

Description

  The present invention relates to an electronic device and a wireless communication terminal that incorporate elements that require high-speed data transfer, such as display elements and imaging elements.

In recent years, functions of televisions, notebook computers and the like have been remarkably improved, screens have become larger, and resolution and resolution have been increasing. In particular, in digital high-vision using a flat panel display, the display device is large in size and has a very large number of pixels, and the frequency band of the drive signal is very wide.
FIG. 12 is a block diagram showing a typical configuration of a display device using an active matrix liquid crystal display as a display element, and FIG. 13 is a time chart thereof.

  As shown in FIG. 12, the CPU 1201 generates image data to be displayed in accordance with a predetermined procedure of the program of the main body, and writes the image data in the video memory 1202. Here, the main body means a main body including a computer input / output device such as a main circuit including a tuner and a demodulator in a television and a DVD player reproducing unit. The CPU 1201 generates image data to be displayed by decompressing or calculating the image signal, a compressed image such as JPEG or MPEG, or moving image data, stores the image data in the video memory 1202, and sequentially rewrites and updates it as necessary. The liquid crystal controller 1203 generates various timings necessary for the liquid crystal display, that is, the X clock signal 1215 and the horizontal synchronizing signal 1214 of the X driver 1213 and the vertical synchronizing signal 1218 of the Y shift register 1207, and the order to be displayed from the video memory 1202. Then, the image data is read out and sent to the drivers (X driver 1213 and Y shift register 1207) of the liquid crystal display 1208.

  Here, the X driver 1213 includes an m-stage X shift register 1204, an m-word latch 1205, and m DA converters 1206 when the pixels of the liquid crystal display 1208 are configured by n rows and m columns. . The m-stage X shift register 1204, m-word latch 1205, and m DA converters 1206 are usually divided into a plurality of sets, integrated on a semiconductor integrated circuit, and arranged around the liquid crystal display 1208.

  When the liquid crystal controller 1203 reads the first pixel of the display frame, it generates a vertical synchronization signal 1218 and sends it to a Y driver (shift register) 1207. At the same time, the liquid crystal controller 1203 reads data to be displayed on the pixel in the first row and the first column of the liquid crystal display 1208 from the video memory 1202 and sends the data as a display data signal 1216 to the data terminal of the latch 1205. Here, the display data signal 1216 has, for example, 8 bits for each of R, G, and B for each pixel, and they are transmitted in parallel as 24 bits of parallel data using 24 transmission paths, or after 24 bits after parallel conversion. It is transmitted as serial data at a double transmission rate.

  As shown in FIG. 13, the X shift register 1204 reads the horizontal synchronization signal 1214 generated by the liquid crystal controller 1203 in synchronization with the X clock signal 1215, and latches the signal X1 latch ( FIG. 13 (c)) is generated. Data displayed on the pixel in the first row and the first column is latched in the first column of the latch 1205 by the signal X1 latch. Subsequently, the liquid crystal controller 1203 reads data to be displayed on the next pixel from the video memory 1202 and outputs the data to the data terminal of the latch 1205. When data to be displayed on the next pixel is output to the data terminal of the latch 1205, the X shift register 1204 of the X driver 1213 shifts the horizontal synchronization signal 1214 by one, and the image data in the second column is changed. A signal X2 latch for latching (FIG. 13D) is generated to cause the latch 1205 to latch the image data in the first row and the second column.

  Thereafter, the X shift register 1204 sequentially shifts the horizontal synchronizing signal 1214 and causes the latch 1205 to sequentially latch the data to be displayed in the first row. In such an operation, when the display data signal 1216 is sent as parallel data for each pixel through a plurality of transmission lines, the display data is read into the latch 1205 in parallel every X clock, and serial data When it is sent as data, it will not be necessary to explain that it is read into the latch 1205 in parallel after the serial-to-parallel conversion.

  When the latch 1205 finishes storing the data for one row, the next horizontal synchronizing signal 1214 (FIGS. 13A and 13H, FIG. 13A to FIG. 13F and FIG. 13G to FIG. Note that the time scale of the horizontal axis is changed at (), so that (h) is re-displayed in addition to (a) for the horizontal synchronizing signal 1214 which is the same signal), and the DA converter 1206 is output. D / A converts the data held in the latch 1205 and outputs the converted data to the i-th (1 ≦ i ≦ m) of the column electrode 1210. At the same time, the Y shift register 1207 outputs a selection signal Y1 to the row electrode 1209 of the first row. Similarly, the Y shift register 1207 sequentially shifts the selection signal Yj to the jth (1 ≦ j ≦ n) of the row electrode 1209 every time the horizontal synchronization signal 1214 is output.

  A circle indicated by a one-dot chain line in FIG. 12 is an enlarged view of one pixel portion of the liquid crystal display 1208 arranged in a matrix. When the j-th row electrode 1209 is selected, the active switch element 1211 transmits the output of the DA converter 1206 output to the i-th column electrode 1210 to the pixel electrode 1212 in the j-th row and i-th column. Note that one DA converter 1206 may be placed on the liquid crystal controller 1203 side, and the display data signal 1216 may be transmitted as an analog signal. In this case, the latch 1205 is an analog sample and hold circuit. Although this method can reduce the number of DA converters 1206 and has been used in the past, the average value of the voltage value finally applied to the pixel electrode 1212 becomes a predetermined value even though the DA converter 1206 is used. It is sufficient that a digital circuit can be used for pulse width modulation and the like, and an analog sample and hold circuit is not required. Therefore, the method described here has become mainstream along with the higher density of LSI.

However, in this method, since the display data signal 1216 is transmitted as a digital signal, the number of signal lines becomes very large. For example, a total of 24 signals of 8 bits × 3 primary colors are transmitted to transmit the display data signal 1216. A line is required. Further, the amount of image data necessary for displaying one frame is multiplied by this resolution (number of pixels).
It should be noted that after the display data signal 1216 at the right end of the row is output from the liquid crystal controller 1203, the time until the display data signal 1216 at the left end of the next row is output, or the display data signal 1216 at the bottom row of the screen is output. The time from when the display data signal 1216 of the first row of the next frame is output is called a (horizontal, vertical) blanking period or blanking period. In CRT, the electron beam is reciprocated. However, in the liquid crystal display, it may be 0 because the selection of the pixel electrode 1212 is performed by the switching operation of the active switch element 1211. FIG. 13 illustrates a case where a horizontal blanking period for one pixel and a vertical blanking period for one row are taken.

  With the recent increase in size and resolution of the liquid crystal display 1208, the speed of image data to be transferred from the liquid crystal controller 1203 exceeds gigabit per second. For example, if a high-definition class screen with a resolution of 1920 × 1080 pixels is displayed for 60 frames per second, a data transfer rate of 1920 × 1080 × 24 × 60≈2.986 Gbps (bits per second) is required. .

  In addition, with the era of multimedia, various functions are often incorporated in the main body, and it is desirable that the liquid crystal display body 1208 and the main body be separable. Due to such a requirement, the mounting substrate is separated into a plurality of cases, and in that case, the mounting substrate is often separated by a one-dot chain line 1217-1217 'in FIG. Inevitably, the connection between the substrate on which the CPU 1201 is mounted and the liquid crystal display 1208 becomes long.

  Further, as the resolution of the liquid crystal display 1208 increases, the frequency of signals transmitted through these lines increases, making it difficult to connect the separated mounting boards. In addition, the display screen itself becomes large, and it is practically impossible to distribute data at high speed by serialization. A method of reducing the transmission speed of each line by arranging display data in parallel and providing many lines is adopted. It is done. However, in many cases, the number of lines becomes very large, exceeding several tens.

In order to solve this problem, as a high-speed data transmission system, for example, LVDS (Low Voltage Differential Signaling) is used for connection of a display driver (Patent Document 1 and Patent Document 2). In Patent Document 3 and Patent Document 4 and the like, a new method is also proposed because sufficient resolution cannot be obtained even with this method.
Patent publication 3086456 (column 44) Patent publication 3330359 (column 46) Patent publication 3349426 Patent publication 3349490

However, recent progress in the enlargement of display bodies is remarkable, and sufficient performance cannot be obtained even with these technologies. In order to obtain sufficient anti-noise characteristics (interference resistance and coherence), careful design and adjustment are required. Further, in LVDS, since the signal level is small, an analog signal is inevitably handled by a digital IC, and there is a problem that power consumption increases.
In addition, in order to transmit a signal with high accuracy, matched impedance termination is required. However, since the number of lines that need impedance termination is large and the transmission impedance is about 100 ohms at most, the termination resistance is not limited. There was also a problem that the power consumed was unacceptably large.

  Furthermore, when the mounting substrate is divided by the alternate long and short dash lines 1217-1217 ′ in FIG. 12, it is necessary to transmit a large amount of data at high speed through a line drawn by a long wiring. For this reason, the radiation electromagnetic field from a track | line increases, and becomes a factor of the electromagnetic wave interference to another electronic device or an own apparatus. In the conventional signal transmission through the signal line, the amplitude level at the power receiving end is defined, and even if sufficient quality can be ensured at the power receiving end, the amplitude level of the signal cannot be lowered. In other words, it is difficult to take measures against EMI, resulting in restrictions on device design and cost increase. On the transmitting side, in addition to the load at the receiving end, the stray capacitance of the line is also driven at the same time, so extra energy is required for signal transmission. That is, the result is an increase in power consumption.

In addition, when the number of wirings increases as the transfer data speeds up, the physical space for wiring increases, which naturally imposes great restrictions on the device design.
In particular, when the wiring passes through a movable part such as a hinge part, the characteristic impedance changes depending on the bending state of the movable part. Therefore, impedance mismatch occurs depending on the situation, and signal degradation is caused by reflection at the bent part. For this reason, there are problems that the speed of data to be transmitted is limited and that the mounting method and the arrangement of parts are restricted. Further, since the number of signals to be exchanged exceeds 100, there are disadvantages that the cost of the flexible board and the connector for making this connection is high and the connection reliability is low.

The various problems and limitations of high-speed data transmission as described above can be solved at once by using wireless transmission by electromagnetic waves, not by wire. However, the wireless transmission of a transmission line that has been conventionally transmitted by wire involves a modulation / demodulation operation for wireless transmission. Therefore, the cost and power consumption for the operation are emerging as new problems.
Therefore, the present invention provides a wireless transmission line that can be realized at the same low cost and low power consumption as the conventional transmission line using a wire such as copper for constructing a wireless transmission line at a close distance in the same housing. An object of the present invention is to realize an electronic device and a wireless communication terminal that are low-cost, low-power-consuming, and highly reliable.

An electronic device according to the present invention includes a first semiconductor integrated circuit having a first oscillation unit that generates a first pulse train, a signal generation unit that is mounted on the first semiconductor integrated circuit and generates a transmission signal, wherein mounted on a first semiconductor integrated circuits, a modulation unit modulating the first pulse train generated by the first oscillation portion in the transmitting signal, the modulated signal by the modulation unit converted into electromagnetic signals, and a transmitting antenna unit for radiating the electromagnetic wave signal, a receiving antenna unit that receives the electromagnetic wave signal radiated by the transmitting antenna unit, a second oscillation section for generating a second pulse train A second semiconductor integrated circuit having the second semiconductor integrated circuit, and a received signal received by the receiving antenna unit using the second pulse train generated by the second oscillating unit and mounted on the second semiconductor integrated circuit and a demodulator for demodulating the Characterized in that it.

According to the above configuration of the present invention, the modulation / demodulation circuit necessary for wireless transmission and the oscillation circuit generating high frequency can all be configured on the semiconductor integrated circuit, so that it is not necessary to mount these circuits individually and the number of parts can be reduced. Even when the wireless transmission function is installed in an electronic device, a low-power consumption and inexpensive system can be realized.
An electronic device according to the present invention includes a first semiconductor integrated circuit having a first oscillation unit that generates a first pulse train, a signal generation unit that is mounted on the first semiconductor integrated circuit and generates a transmission signal, wherein mounted on a first semiconductor integrated circuits, a modulation unit modulating the first pulse train generated by the first oscillation portion in the transmitting signal, the modulated signal by the modulation unit converted into electromagnetic signals, and a transmitting antenna unit for radiating the electromagnetic wave signal, a receiving antenna unit that receives the electromagnetic wave signal radiated by the transmitting antenna unit, a second oscillation section for generating a second pulse train A second semiconductor integrated circuit having the second semiconductor integrated circuit, and a received signal received by the receiving antenna unit using the second pulse train generated by the second oscillating unit and mounted on the second semiconductor integrated circuit a demodulator for demodulating a The transmission path of the serial electromagnetic signals to transmit synchronization signals in a different path, taking the first oscillation unit and / or the modulation unit, the synchronization between the second oscillation portion and / or the demodulator synchronization and having a part.

According to the above configuration of the present invention, a signal for synchronization of a communication packet necessary for synchronization and modulation / demodulation of an oscillation circuit necessary for signal transmission / reception can be transmitted by wire, and thus a wireless transmission function is mounted on an electronic device. Even in this case, the circuit for synchronization can be simplified, and the reliability can be improved and the price can be reduced.
The synchronization unit of an electronic device according to the present invention includes a frequency divider for dividing said first pulse train generated by the first oscillator section, the synchronous frequency-divided signal by the division unit and characterized in that it comprises a wired transmission unit to be transmitted to the second semiconductor integrated circuit as a signal, and said second synchronization control unit for synchronizing the generated second pulse train to said synchronization signal by the oscillation unit To do.

According to the above configuration of the present invention, since the synchronization signal is obtained by dividing the output of the oscillation circuit on the transmission side, it can be easily configured on a semiconductor integrated circuit. In addition, since the synchronization signal is transmitted to the reception side by wire, a circuit for capturing synchronization is not necessary on the reception side, and it is easy to configure on a semiconductor integrated circuit, and has low power consumption and high reliability. Can be realized.
The synchronization unit of an electronic device according to the present invention includes a frequency divider for dividing said first pulse train generated by said second oscillator section, the synchronous frequency-divided signal by the division unit and characterized in that it comprises a wired transmission unit that transmits to the first semiconductor integrated circuit as a signal, and said first synchronization control unit for synchronizing the generated second pulse train to said synchronization signal by the oscillation unit To do.

According to the above configuration of the present invention, since the synchronization signal is obtained by dividing the output of the oscillation circuit on the receiving side, it can be easily configured on a semiconductor integrated circuit. In addition, the synchronization signal is transmitted to the transmission side by wire, and the transmission side transmits a signal to the reception side in synchronization with this signal. Therefore, a circuit for capturing synchronization is not necessary on the reception side, and the circuit is configured on a semiconductor integrated circuit. An electronic device that is easy to perform, low power consumption, and high reliability can be realized.

The synchronization unit of the electronic device according to the present invention includes a third oscillation unit , a wired transmission unit that transmits the output of the third oscillation unit to the first and second semiconductor integrated circuits as the synchronization signal, and having a synchronization control unit for synchronizing the second pulse train generated by said first pulse train and said second oscillation unit generated by the first oscillation unit to the synchronizing signal .
According to the above configuration of the present invention, the synchronization signal is obtained from the third oscillating unit and transmitted to both transmission and reception by wire, so that synchronization is achieved between transmission and reception, and no circuit for synchronization acquisition is required on the reception side. It becomes. For this reason, it is easy to configure with a semiconductor integrated circuit, and an electronic device with low power consumption and high reliability can be realized.

The synchronization control unit of the electronic device according to the invention consists of a phase locked loop unit including an oscillation portion having a voltage controlled oscillator, synchronizing the output of the oscillator circuit portion of the frequency of the synchronization signal multiplied by the sync signal It is characterized by making it.
According to the above configuration of the present invention, since the oscillation circuit between the transmission and reception can be synchronized by the phase lock loop (PLL), the variation in the oscillation frequency accuracy of the oscillation circuit on the transmission side and the reception side does not become an error. Further, a circuit for capturing synchronization is not required on the receiving side, and an electronic device that can be easily configured with a semiconductor integrated circuit, has low power consumption, and high reliability can be realized.

The synchronization control unit of the electronic device according to the present invention includes an oscillation unit having a voltage-controlled oscillation unit, a phase lock loop unit that multiplies and outputs the frequency of the synchronization signal, and a communication packet that is transmitted in synchronization with the synchronization signal and having a preamble and a compares the output signal of the oscillator transfer Sosuru phase shifter according placed a predetermined bit sequence in place of the inner.
According to the above configuration of the present invention, the phase synchronization and the packet synchronization for modulation / demodulation of the oscillation circuit on the transmission side and the reception side can be simultaneously obtained by the same synchronization signal. As a result, a circuit for synchronization acquisition and packet synchronization is not required, and an electronic device that is easy to configure with a semiconductor integrated circuit, low power consumption, and high reliability can be realized.

The modulation unit of the electronic device according to the invention is characterized in that phase-modulating the first pulse train generated by the first oscillation portion in the transmission signal.
According to the above configuration of the present invention, since phase modulation is adopted as a modulation method, it is easy to configure on a semiconductor integrated circuit, and a low-power consumption and highly reliable communication path can be secured.
The demodulator of the electronic device according to the invention is characterized by phase demodulation by multiplying the reception signal and the generated second pulse train at the second oscillation unit.

According to the above configuration of the present invention, the demodulation of the phase modulation is performed by multiplying the output of the oscillation circuit and the received signal. Therefore, it is easy to configure the demodulation circuit on the semiconductor integrated circuit, and low power consumption and high reliability are achieved. A communication path can be secured.
The first and second oscillating units of the electronic device according to the present invention are each composed of a single-phase or multi-phase ring oscillation circuit configured on the first and second semiconductor integrated circuits.

According to the above configuration of the present invention, since the oscillation circuit is a ring oscillation circuit, the oscillation circuit can be configured using a transistor, and can be easily configured on a semiconductor integrated circuit, and can oscillate at a high frequency at low cost. It can be realized with low power consumption.
Electronic device according to the present invention includes a storage unit for storing display information, and a display unit for displaying the display information, the display control unit, wherein the display information to read output from the storage unit in accordance with the driving order of the display unit characterized in that it has a said driving that drive the display unit moving unit based on the display information read out by the display control unit.

  According to the above configuration of the present invention, display information to be displayed on the liquid crystal can be transmitted through the space without complicating the system, and wiring for that is unnecessary, and wiring such as a flexible board and a connector is simplified. This eliminates the problem of high cost and reliability caused by these. In addition, it is possible to avoid the problem of power consumption that rises due to termination for impedance matching and an increase in data transmission speed. Also, restrictions on wiring routing and component placement can be relaxed, and the design and usability of the electronic device can be improved. Furthermore, since the electromagnetic waves used for signal transmission are performed within a short distance within the same system, it is only necessary to ensure communication within this distance, without being restricted by the definition of the amplitude level at the power receiving end. Since the intensity of the radiated electromagnetic wave can be lowered to the limit, the EMI characteristic is essentially improved and the countermeasure can be facilitated.

Electronic device according to the invention is characterized by having an imaging unit, an imaging control section for outputting read an image signal captured by the imaging unit.
According to the above configuration of the present invention, since the exchange of signals between the image sensor and the host side using the image data obtained by the image sensor is wireless, no wiring is required between them, and the image sensor is increased in size. It is possible to avoid various problems that have been revealed. In other words, it can be easily mounted even in a clamshell structure, there is no need for wiring using a flexible substrate or connector, and there is no cost or reliability problem caused by these, which can cope with high transmission speeds. effective. In particular, in the camera, the optical system and the electronic component must be mounted in the same housing, and there are many restrictions on mounting the electronic component. However, the above-described configuration of the present invention can ease this restriction.

The wireless communication terminal according to the present invention includes a first housing portion, a second housing portion, and the first housing portion so that the positional relationship between the first housing portion and the second housing portion can be changed. a connecting portion connecting the the body portion second housing portion, and a front Symbol first internal wireless communication antenna mounted on the first housing portion, the second mounted on the second housing part An internal wireless communication antenna, a first internal wireless communication control unit that is mounted on the first housing unit and that controls internal wireless communication performed via the first internal wireless communication antenna, A second internal wireless communication control unit that is mounted on the second housing unit and controls internal wireless communication performed via the second internal wireless communication antenna; and is mounted on the first housing unit, mounting of the first and the first semiconductor integrated circuit having an oscillation portion, the first semiconductor integrated circuit for generating a first pulse train A signal generator for generating a transmission signal, the being mounted on the first semiconductor integrated circuits, said been said first pulse train generated by the first oscillation unit and modulated by the transmission signal of the first a modulation unit for sending via the internal wireless communication antenna, is mounted on the second housing portion, a second semiconductor integrated circuit having a second oscillation section for generating a second pulse train, said second mounted on the semiconductor integrated circuits, a demodulator for demodulating a received signal received in the second said using said second pulse train generated by the oscillation section the second internal wireless communication antenna the mounted to the first housing portion or the second housing portion, for transmitting a portion of information communicated between the first semiconductor integrated circuit and the second semiconductor integrated circuit by wire It characterized by having a wired communication unit.

According to the above configuration of the present invention, it is possible to wirelessly transmit data between housings of wireless communication terminals while assisting wireless communication with wired communication. Therefore, in response to the increase in resolution of the display unit mounted on the wireless communication terminal, even when the amount of data exchanged between the cases increases, while suppressing the increase in the number of wires between the cases, Data communication between the cases can be performed without any delay. As a result, even when the clamshell structure is adopted for the wireless communication terminal, it is possible to suppress the complexity of the structure of the connecting portion, and it is possible to prevent the mounting process from becoming complicated and increase the cost. It is possible to reduce the size and thickness of the wireless communication terminal and increase the reliability while suppressing the wireless communication terminal, and to increase the screen size and multifunction of the wireless communication terminal without impairing the portability of the wireless communication terminal. be able to.
The wireless communication terminal according to the present invention is mounted on the external wireless communication antenna unit mounted on the first casing unit or the second casing unit, and on the first casing unit or the second casing unit, An external wireless communication control unit that controls external wireless communication performed via the external wireless communication antenna unit, and a display unit mounted on the second housing unit.

  As described above, according to the above configuration of the present invention, transmission of data transmitted and received between functional blocks in an electronic device is transmitted by electromagnetic waves by an oscillation circuit and a modulation / demodulation circuit built in a semiconductor integrated circuit. It is possible to transmit data using a space as a medium while suppressing an increase in the mounting scale of equipment circuits necessary for wireless transmission, and to eliminate various problems and mounting problems associated with conventional high-speed data transmission Accordingly, a display device with low cost, high reliability, and low power consumption can be realized.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a perspective view showing a state when a clamshell mobile phone to which the wireless communication control method of the present invention is applied is opened, and FIG. 2 is a clamshell mobile phone to which the wireless communication control method of the present invention is applied. It is a perspective view which shows a state when a telephone is closed.
In FIG. 1 and FIG. 2, an operation button 4 is disposed on the surface of the first housing unit 1, and a microphone 5 is provided at the lower end of the first housing unit 1. An external wireless communication antenna 6 is attached to the upper end. In addition, a display body 8 is provided on the surface of the second housing portion 2, and a speaker 9 is provided on the upper end of the second housing portion 2. In addition, a display body 11 and an imaging element 12 are provided on the back surface of the second housing portion 2. As the display bodies 8 and 11, for example, a liquid crystal display panel, an organic EL panel, a plasma display panel, or the like can be used. As the image sensor 12, a CCD or CMOS sensor can be used. The first housing unit 1 and the second housing unit 2 include internal wireless communication antennas 7 and 10 that perform internal wireless communication between the first housing unit 1 and the second housing unit 2, respectively. Is provided.
And the 1st housing | casing part 1 and the 2nd housing | casing part 2 are connected via the hinge 3, and the 2nd housing | casing part 2 is made into 1st by rotating the 2nd housing | casing part 2 by using the hinge 3 as a fulcrum. It can be folded on the housing part 1. The operation button 4 can be protected by the second housing unit 2 by closing the second housing unit 2 on the first housing unit 1, and the operation button 4 may be mistaken when carrying the mobile phone. Operation can be prevented. Further, by opening the second housing part 2 from the first housing part 1, the operation button 4 can be operated while viewing the display body 8, a telephone call can be made using the speaker 9 and the microphone 5, and the operation button 4 can be operated. Imaging can be performed while operating.

Here, by using the clamshell structure, the display body 8 can be disposed on almost the entire surface of the second housing portion 2, and the size of the display body 8 can be increased without deteriorating the portability of the mobile phone. It is possible to improve visibility.
Further, by providing the internal wireless communication antennas 7 and 10 in the first housing portion 1 and the second housing portion 2, respectively, the first housing is achieved by internal wireless communication using the internal wireless communication antennas 7 and 10. Data transmission between the unit 1 and the second housing unit 2 can be performed. For example, image data and audio data captured by the first housing unit 1 via the external wireless communication antenna 6 are transferred to the second housing unit 2 by internal wireless communication using the internal wireless communication antennas 7 and 10. , And an image can be displayed on the display body 8 or sound can be output from the speaker 9. In addition, image data captured by the image sensor 12 is sent from the second housing unit 2 to the first housing unit 1 by internal wireless communication using the internal wireless communication antennas 7 and 10, and is used for external wireless communication. It can be sent to the outside via the antenna 6.

  Thereby, it is not necessary to perform data transmission between the first casing unit 1 and the second casing unit 2 by wire, and it is not necessary to pass the flexible wiring board having multiple pins through the hinge 3. For this reason, it becomes possible to suppress the complexity of the structure of the hinge 3 and to prevent the mounting process from becoming complicated, thereby reducing the size and thickness of the mobile phone and increasing the reliability while suppressing an increase in cost. It is possible to increase the screen size and functionality of the mobile phone without impairing the portability of the mobile phone.

  The external wireless communication antenna 6 is mounted on the first casing 1, but may be mounted on the second casing 2. In this case, the external radio communication antenna 6 is not blocked by the second casing 2 during use, and efficient communication can be expected. In this case, power is supplied to the external wireless communication antenna 6 from the communication control unit of the mobile phone built in the first housing unit 1 by a coaxial cable or the like.

FIG. 3 is a perspective view showing the appearance of a rotary mobile phone to which the wireless communication control method of the present invention is applied.
In FIG. 3, an operation button 24 is disposed on the surface of the first housing portion 21, a microphone 25 is provided at the lower end of the first housing portion 21, and an upper end of the first housing portion 21 is provided. An external radio communication antenna 26 is attached. A display body 28 is provided on the surface of the second housing part 22, and a speaker 29 is provided on the upper end of the second housing part 22. The first casing portion 21 and the second casing portion 22 have internal wireless communication antennas 27 and 30 that perform internal wireless communication between the first casing portion 21 and the second casing portion 22, respectively. Is provided.

  The first housing portion 21 and the second housing portion 22 are connected via a hinge 23, and the second housing portion 22 is rotated horizontally around the hinge 23 as a fulcrum, thereby The first housing portion 21 can be placed on top of the first housing portion 21, or the second housing portion 22 can be shifted from the first housing portion 21. The operation button 24 can be protected by the second housing portion 22 by arranging the second housing portion 22 on the first housing portion 21, and the operation button 24 can be used when carrying the mobile phone. Can be prevented from being operated by mistake. Further, by rotating the second housing portion 22 horizontally and shifting the second housing portion 22 from the first housing portion 21, the operation button 24 can be operated while viewing the display body 28, the speaker 29 and It is possible to talk while using the microphone 25.

  Here, by providing the antennas 27 and 30 for internal wireless communication in the first housing part 21 and the second housing part 22 respectively, the first housing is used for internal wireless communication using the antennas 27 and 30 for internal wireless communication. Data transmission between the body part 21 and the second housing part 22 can be performed. For example, image data and audio data captured by the first housing unit 21 via the external wireless communication antenna 26 are transferred to the second housing unit 22 by internal wireless communication using the internal wireless communication antennas 27 and 30. The image can be displayed on the display body 28, or the sound can be output from the speaker 29.

  As a result, it is not necessary to pass the flexible wiring board having a large number of pins through the hinge 23, and it is possible to suppress the complexity of the structure of the hinge 23 and to prevent the mounting process from becoming complicated. . For this reason, it is possible to reduce the size and thickness of the mobile phone and increase the reliability while suppressing an increase in cost, and to increase the screen size and functionality of the mobile phone without impairing the portability of the mobile phone. Can be achieved.

  In the above-described embodiment, a mobile phone has been described as an example, but the present invention can also be applied to a video camera, a PDA (Personal Digital Assistance), a notebook personal computer, and the like.

  FIG. 4 is a block diagram showing an embodiment of the electronic apparatus according to the present invention. The CPU 401 generates display data to be displayed by calculation or the like and records it in the video memory 402. The liquid crystal controller 403 reads display data 419 to be displayed on the display body from the video memory 402 in a predetermined order, and outputs it together with the vertical synchronization signal 421 and the horizontal synchronization signal 420. Since the display data 419 is normally read out as data in parallel in units of pixels from the video memory 402, the display data 419 is converted into parallel data by the parallel-to-serial conversion circuit 404 and transmitted to the logic circuit 407.

  The logic circuit 407 receives the signal output from the parallel-to-serial conversion circuit 404 and the horizontal synchronization signal 420 and the vertical synchronization signal 421 output from the liquid crystal controller 403 to generate a packet. The logic circuit 407 also performs synchronous detection. A preamble is added to the packet for synchronization required for communication such as the timing. The packet is modulated by the modulation circuit 408 by the carrier frequency generated by the PLL 409 and transmitted from the transmission antenna 410 via the final stage circuit 406. At the same time, the horizontal synchronization signal 420 is transmitted as synchronization information to the reception side via the wired path 428.

  The oscillation circuit 405 oscillates and supplies a reference clock necessary for the operation of the CPU 401 and the liquid crystal controller 403. Since the liquid crystal controller 403 and the CPU 401 operate in synchronization with the reference clock, the reading of the display data 419 and the horizontal synchronization signal 420 and the vertical synchronization signal 421 generated by the liquid crystal controller 403 are synchronized with the reference clock. Become. The horizontal synchronization signal 420 and the vertical synchronization signal 421 are obtained by dividing the reference clock by the liquid crystal controller 403. Since the PLL 409 multiplies the horizontal synchronizing signal 420 to generate a carrier frequency, the output of the PLL 409 is also synchronized with the horizontal synchronizing signal.

  The reception antenna 411 receives the electromagnetic wave signal transmitted from the transmission antenna 410, and the reception signal is amplified by the preamplifier 412, and then the unnecessary band component is removed by the band pass filter 413 and input to the demodulation circuit 414. . The demodulating circuit 414 demodulates the received signal by using the carrier frequency restored by multiplying the frequency of the horizontal synchronizing signal 420 transmitted through the wired path 428 by the PLL 415 as synchronization information. The logic circuit 418 detects the preamble in the received signal packet in response to the horizontal synchronization signal 420 transmitted as the synchronization information from the transmission side through the wired path 428, detects the synchronization timing necessary for packet synchronization, and performs serial parallel processing. This is transmitted to the conversion circuit 417. The serial-parallel conversion circuit 417 extracts display data from the received packet restored by the demodulation circuit 414 based on this signal, performs serial-parallel conversion to drive the liquid crystal display, and outputs it.

  In addition, the logic circuit 418 generates a synchronization signal for driving the liquid crystal. The logic circuit 418 divides the carrier frequency restored by the PLL 415 and generates a transfer clock 425 for the X driver. In addition, a horizontal synchronization signal 423 and a vertical synchronization signal 424 for driving the liquid crystal display body are generated based on a horizontal synchronization signal 420 transmitted from the transmission side through the wired path 428, and interface processing such as level conversion is performed and output. To do. That is, the logic circuit 418 outputs to the driver of the liquid crystal display as signals corresponding to the horizontal synchronizing signal 1214, the vertical synchronizing signal 1218, and the X clock signal 1215 of FIG.

In the logic circuit 418, there are only the carrier wave multiplied and restored by the PLL 415 as an input and the horizontal synchronization signal 420 transmitted from the transmission side via the wired path 428 and the reception signal demodulated by the demodulation circuit 414. Can be detected by a method such as
That is, the timing of the vertical synchronization signal can be detected by a method such as making the pulse width of the horizontal synchronization signal 420 different from the normal width, or making the preamble pattern different. Further, since the number of horizontal synchronization signals per frame is determined, once the frame synchronization is established, the horizontal synchronization signals may be counted and the vertical synchronization signal output for each scanning line. Further, since the vertical synchronization signal has a low frequency, the vertical synchronization signal can be transmitted by wire.

As the carrier frequency, a frequency that does not interfere with the original purpose of an electronic device that uses radio waves such as a radio receiver or a mobile phone is selected. If a frequency of 2 GHz or more is selected, even if data of 100 Mbps is transmitted, the occupied band is about 200 MHz, and in most cases, it can be used without any problem.
In general, in wireless communication, the modulation circuit 408 on the transmission side and the demodulation circuit 414 on the reception side need to have the same carrier frequency, and high accuracy is required for the carrier frequency between transmission and reception. The error of the carrier frequency handled in the network appears as direct communication quality degradation. However, according to the above-described configuration of the present invention, the modulation circuit 408 and the demodulation circuit 414 use the same reference, that is, a carrier wave multiplied by the PLL 409 or the PLL 415 from the horizontal synchronization signal 420, and therefore, between the transmission and the reception. There is no carrier frequency error.

  If the characteristics of the PLL 409 and the PLL 415 are designed to be the same, the carrier wave generated by them coincides with the frequency and phase, and high-accuracy synchronous detection is possible. Further, the accuracy of the PLLs 409 and 415 is not a problem, and can be realized by the PLLs 409 and 415 using an oscillation circuit that is not so high as to be integrated on a semiconductor integrated circuit, and has a great cost reduction effect. Note that the PLL 415 is not essential, and the output of the PLL 409 may be sent directly to the demodulation circuit 414. However, since the carrier frequency is generally high, it is difficult to transmit the wired path 428. As in the above configuration, it is more feasible to provide two PLLs 409 and 415 on the transmission side and the reception side, respectively, and restore the same carrier from both the transmission and reception from the same reference clock. A method of attaching the preamble and its operation, and more detailed implementation methods and circuit examples of the PLLs 409 and 415, the modulation circuit 408, and the demodulation circuit 414 will be described later.

  The evaluation circuit 427 evaluates the reception status from the output of the demodulation circuit 414 using, for example, a reception error rate by CRC, and feeds back the evaluation result to the final stage circuit 406 through the wired path 428. The final-stage circuit 406 controls the power supplied to the transmission antenna 410 so that the minimum transmission power that can ensure sufficient communication quality on the reception side of the electromagnetic wave signal is obtained. This makes it possible to maintain communication quality with much less radiated power than unnecessary radiated power generated from a conventional wired transmission line whose reception signal level must be kept at a predetermined value, which is a fundamental EMI countermeasure. .

  Further, it is possible to add pre-emphasis or pre-distortion to the electromagnetic field generated so as to compensate the propagation path characteristic of the radiated electromagnetic field by this feedback information. Thereby, a predetermined communication quality can be obtained with a predetermined radiation field power. In addition, transmission power and propagation path characteristics vary greatly depending on component placement, etc., and it was necessary to adjust parameters by trial and error, such as by trial manufacture, at the initial stage of device design. Since this is done automatically, there is a significant reduction in development man-hours. Such a method of this embodiment for controlling the transmission side by feedback information sent from the reception side and maintaining communication quality controls the receiver sensitivity (gain) by providing an AGC (automatic gain control) circuit on the reception side. This is a concept that is significantly different from the conventional wireless communication technology that has been used, and has the effect of simplifying the system configuration and minimizing unnecessary radiation.

  Here, on the transmission side, the parallel-to-serial conversion circuit 404, the logic circuit 407, the modulation circuit 408, the final stage circuit 406, and the PLL 409 can be integrated on the first semiconductor integrated circuit 430. In addition, the first semiconductor integrated circuit 430 is integrated on the chip of the liquid crystal controller 403, and in some cases, the CPU 401, the video memory 402, and the oscillation circuit 405 are also integrated on the same semiconductor substrate. Cost can be reduced. When the signal to be transmitted is transmitted wirelessly as in this embodiment, the number of connections to the outside of the semiconductor chip is reduced, and a wide range of circuit blocks can be mounted on the same semiconductor substrate, and the cost is further increased. Contributes to reduction.

  On the other hand, on the receiving side, a preamplifier 412, a bandpass filter 413, a demodulation circuit 414, a serial-parallel conversion circuit 417, a logic circuit 418, a PLL 415, and an evaluation circuit 427 may be incorporated in each liquid crystal driver as the second semiconductor integrated circuit 431. I can do it. These circuits are not large in scale and have little effect on the cost increase of each liquid crystal driver chip, but the number of wiring between the liquid crystal drivers can be greatly reduced, mounting density is increased, high reliability, Cost reduction can be achieved.

  By adopting the above configuration, it is possible to wirelessly display a large amount of display data on the display body, and power consumption, wiring position restrictions, EMI countermeasures, ensuring reliability, etc. that have become apparent due to the increase in the size of the display body Various problems caused by wired transmission can be eliminated. In particular, according to this configuration of the present embodiment, all necessary circuit elements can be integrated on a semiconductor chip, and can be realized at a lower cost than conventional data transmission using a wire such as copper.

FIG. 5A is a block diagram showing a main part of another embodiment of the electronic apparatus according to the present invention, and is a diagram illustrating the modulation circuit 408 and the demodulation circuit 414 of the first embodiment in more detail.
In FIG. 5A, an oscillation circuit 502 is an oscillation circuit that oscillates a carrier wave for data transmission, and corresponds to the PLL 409 of the first embodiment. The multiplication circuit 501 multiplies the output of the oscillation circuit 502 and the input data 503, outputs it as a transmission signal 504, and sends it to the transmission antenna 410 of FIG. In this case, since the communication transmission distance is very close as in the case of the same electronic device casing, harmonic interference to other electronic devices and the like can be kept low from the beginning. There is little need to consider unnecessary radiation outside the signal band.

  Therefore, the carrier wave does not need to be a sine wave with less distortion, and a rectangular pulse train is sufficient. Then, since the input data 503 and the output of the oscillation circuit 502 are both digital signals, the multiplication circuit 501 may be an exclusive OR circuit. When an analog value of a value “1” is associated with a logic “0” and an analog value of a value “−1” is associated with a logic “1”, the input / output of the exclusive OR circuit functions as the multiplication circuit 501. Further, in order to suppress harmonic interference given to other systems and the like, a filter or the like usually installed between the antenna and the modulation circuit output becomes unnecessary.

The demodulator operates as follows.
The reception signal received by the reception antenna 411 in FIG. 4 is amplified and the unnecessary band is removed, and then input to the multiplication circuit 505 as the reception signal 500, multiplied by the carrier wave reproduced by the PLL 508, and then by the low-pass filter 506. The high frequency component is removed, and a demodulated signal 509 is output. The low-pass filter 506 removes the high frequency component (the narrow pulse component generated by a slight phase shift difference between the reception signal 500 and the reproduction clock waveform of the PLL 508) from the output of the multiplication circuit 505 and outputs it as a demodulated signal 509.

  The carrier waves need to be synchronized on the transmission side and the reception side, but in this embodiment, the synchronization is achieved by a method different from that in the first embodiment. That is, the frequency dividing circuit 507 divides the carrier wave generated by the oscillation circuit 502, reduces the frequency, and transmits the signal to the receiving side by wire. On the receiving side, the signal divided by the frequency dividing circuit 507 is multiplied by the PLL 508 with reference to the signal, and the carrier frequency before frequency division is reproduced.

  In this way, the carrier wave between transmission and reception coincides with the phase and frequency, and synchronous detection is possible. Since the phase and frequency of the carrier wave between transmission and reception can always be matched by the action of the PLL 508, the oscillation accuracy of the oscillation circuit 502 may not be high, and these circuits can be integrated on a semiconductor integrated circuit. It is. In addition, the carrier wave output from the oscillation circuit 502 may be directly transmitted to the reception side and input to the multiplication circuit 505. However, in this case, the frequency of the carrier wave is high and the characteristics of the transmission path become a problem. By adopting the configuration as in the present invention, it is possible to avoid the problem of the frequency characteristics of the transmission line.

  6A to 6C show time charts of the modulation circuit described above. 10A shows a carrier clock signal generated by the oscillation circuit 502, FIG. 10B shows transmission data 503, and FIG. 10C shows an output transmission signal 504. If the time diagram of FIG. 4 is viewed as a digital circuit, the modulation circuit 408 of FIG. 4 is an exclusive OR circuit, and if viewed as an analog value that takes a value of “± 1”, the modulation circuit 408 of FIG. It is.

  FIGS. 6D to 6F show time charts of the demodulation circuit according to the second embodiment. 10D shows the received signal, FIG. 8E shows the pulse train generated from the PLL 508, FIG. 5F shows the output of the multiplier circuit 505, and the low-pass filter 506 receives the received signal 500 and the PLL 508 from this signal. A high frequency component generated by a slight phase difference of the output is removed, and the demodulated signal 509 is restored.

  As is clear from the figure, the demodulation does not work well if the carrier clock (FIG. 6A) and the recovered clock (FIG. 6E) are different in frequency or out of phase. In conventional wireless communication, a high-accuracy oscillation circuit is separately provided on the transmission side and the reception side to minimize errors. According to this configuration of the present embodiment, since the reproduction clock on the reception side is based on the output of the oscillation circuit 502 on the transmission side, a reproduction clock having the same frequency as that on the transmission side can always be secured on the reception side. No error due to stability or frequency accuracy. Even with an inexpensive oscillation circuit 502, a circuit with extremely high stability can be constructed.

  If the time chart of FIG. 6 is viewed as a digital circuit, the demodulation circuit 414 of FIG. 4 is an exclusive OR circuit, and if viewed as an analog value that takes a value of “± 1”, the demodulation circuit 414 of FIG. It is. The wireless signal transmission used in the present embodiment has a short communication distance and can secure communication quality with a sufficiently high SN ratio, so that the signal can be amplified to a level that can be regarded as a digital value. In this case, the amplified signal level increases to the logical value level, but the load driven by the logical value is not a long distance with a large stray capacitance such as from the CPU to the display body, but in the same semiconductor chip. Since the load is extremely short and low, power consumption does not increase.

  Even if the received signal is an analog level that is not amplified to a logical value level, the output of the PLL 508 is a rectangle (which takes a value of “± 1”), so that multiplication can be realized with a simple switch circuit. That is, an inverting amplification circuit and a forward amplification circuit having the same absolute value of amplification and opposite polarities are prepared for the received signal. When the output of the PLL 508 is a logic level “1”, the output of the inverting amplification circuit is selected by a switch. When the logic level is “0”, this can be realized by selecting the output of the normal amplifier circuit. A circuit having such a structure may be used as the multiplication circuit 505. A circuit example of the multiplier circuit 505 will be described in more detail in another embodiment.

  According to the above configuration, the modulation circuit can be realized very simply by the exclusive OR circuit, the demodulation circuit can be realized by one exclusive OR circuit, or the amplifier circuit and the switch circuit having positive and negative amplification degrees, and the low-pass filter.

FIG. 5B is a block diagram showing a main part of an embodiment of the electronic device according to the present invention, and is a diagram illustrating in more detail another example of the modulation circuit 408 and the demodulation circuit 414 of the first embodiment. In the second embodiment, the BPSK modulation is simplified, but in this embodiment, an example based on the QPSK modulation is given to show a case where more general phase modulation is used.
An oscillation circuit 520 that oscillates a carrier wave is placed on the receiving side and oscillates a carrier wave having a carrier frequency. The frequency dividing circuit 517 divides the carrier wave oscillated by the oscillation circuit 520 and transmits it to the transmission side. On the transmission side, the output of the frequency dividing circuit 517 is received and multiplied by the PLL 513 to generate a carrier having the same frequency and phase as the carrier on the receiving side. In QPSK modulation, a transmission signal is encoded and transmitted by allocating 2 bits (ie, data bit a and data bit b) for each symbol. That is, the phase shift amount is encoded and modulated as shown in Table 1 for transmission with respect to the reference carrier wave. The encoder 512 controls the phase shift circuit 514 and the multiplication circuit 515 so as to have the phases shown in Table 1 according to the bit pattern of the data bit a and the data bit b.

  6 (g) to 6 (j) are time charts showing the operation of each part of the modulation circuit shown in FIG. 5 (b). Data bit a (FIG. 6 (h)) and data bit b (FIG. 6 (i)) of the transmission data are encoded by the encoder 512, and the carrier wave (FIG. 6 (g)) generated by the PLL 513 is converted by the phase shift circuit 514. Whether or not to perform 90 ° phase shift and further whether or not to invert the carrier wave (180 ° phase shift) is controlled by the multiplication circuit 515, and finally the QPSK modulated transmission signal 516 (FIG. 6 (j)) Is output.

  On the reception side, the carrier wave (FIG. 6 (l)) output from the oscillation circuit 520 is multiplied by the reception signal 518 (FIG. 6 (k)) by the first multiplication circuit 519 and transmitted to the first low-pass filter 523, After the high frequency component is removed, it is transmitted to the discrimination circuit 525. At the same time, the received signal 518 is multiplied by a pulse train (FIG. 6 (o)) obtained by shifting the carrier wave generated by the oscillation circuit 520 by 90 ° by the 90 ° phase shift circuit 522 and the second multiplication circuit 521, After the high-frequency component is removed by the low-pass filter 524, it is transmitted to the discrimination circuit 525. The discriminating circuit 525 determines transmission data from the outputs (FIG. 6 (n) and (q)) of the first and second low-pass filters 523 and 524, demodulates the received signal 518, and outputs a demodulated signal 526.

  According to the above configuration, the speed of data transmission can be increased without increasing the occupied band of the transmission signal 516. Further, since the modulation / demodulation circuit can be realized by a simple digital circuit, it can be incorporated in a semiconductor chip, and an increase in cost and power consumption can be ignored. Since the carrier wave is synchronized with the carrier wave generated by the oscillation circuit 520 on the reception side on the transmission side and the phase and frequency are matched between transmission and reception, an error due to the accuracy of the carrier frequency between transmission and reception does not occur. Therefore, stable data transmission is possible even with an inexpensive oscillation circuit 520.

  In addition, in order to match the carrier frequency between transmission and reception, the carrier wave which is generally a high frequency is not directly transmitted, but the carrier wave is divided by the frequency dividing circuit 517 and transmitted to the transmission side, which is multiplied by the PLL 513. Therefore, transmission via a wired path is easy, and unnecessary radiation such as EMI is small. Even if the receiving side changes the oscillation frequency of the oscillation circuit 520 unidirectionally, the output frequency of the PLL 513 on the transmitting side always follows the receiving side. When the frequency is received, the frequency without interference can be selected and the oscillation frequency can be changed unilaterally. In other words, it is possible to remarkably facilitate interference and countermeasures against the intended communication of an electronic device such as a communication device.

  In addition, since the output cycle of the frequency dividing circuit 517 can be made sufficiently long, the packet frame boundary can be easily detected on the receiving side if the transmitting side transmits the packet in synchronization with this signal. Packet synchronization can be greatly simplified.

FIG. 7 is a diagram showing in more detail the main part of another embodiment according to the present invention, in particular, the PLL and demodulator on the receiving side. A specific internal structure is shown. FIG. 8 is a time chart showing an outline of the operation.
In FIG. 7, a voltage controlled oscillation circuit 701, a frequency dividing circuit 708, a phase comparison circuit 710, and a low pass filter (LPF) 711 constitute a PLL, and a synchronization signal 705 from the transmission side is input as a reference phase. As shown in FIG. 8 (f), the synchronization signal 705 is a signal having the same frequency as that of the horizontal synchronization signal (FIG. 8 (k)) but only in phase, and a position where a preamble (described later (FIG. 8 (h))) exists. Represents. Such a signal can be easily output from the liquid crystal controller 403 of FIG. In the voltage controlled oscillation circuit 701, two differential amplifier circuits A1 and A2 are connected in cascade, and as shown in FIG. 7, the outputs of the differential amplifier circuits A1 and A2 are inverted and fed back to the input so that the phase is 90. It is possible to generate oscillation signals Q1 to Q4 for four phases that are different from each other. The oscillation frequency of the oscillation signals Q1 to Q4 can be controlled by changing the bias of the differential amplifier circuits A1 and A2.

When such a ring-type oscillation circuit is formed on a semiconductor substrate, the upper limit is determined by the stray capacitance of the semiconductor element, and the semiconductor integrated circuit can oscillate at the highest frequency that can be oscillated. Conversely, once the oscillation frequency is determined, the power consumption can be minimized in order to oscillate that frequency. Since the output of the voltage controlled oscillation circuit 701 is unbalanced in duty ratio due to the load, the output of the voltage controlled oscillation circuit 701 is taken out by the buffer circuit 702 so as to be a load having good symmetry. (Fig. 8 (a), (b), (c), (d))
From the transmission side, QPSK modulation as shown in the third embodiment is performed using the oscillation signals Q1 to Q4 for four phases generated by the voltage controlled oscillation circuit 701, and the buffer circuits B1 and B2 are transmitted by transmission bit pattern. , B3, or B4 is selected and transmitted.

On the receiving side, the delay amounts of the outputs of the buffer circuits B1 and B2 having a phase difference of 90 ° are adjusted by the delay circuit 703, and then multiplied by the reception signal 704 by the multiplying circuits 706 and 707. The outputs of the multiplication circuits 706 and 707 include transmission data information, and after the high frequency component is removed by the bit determination circuit 713, the bit determination is performed to obtain the demodulated output 714.
The output of the buffer circuit B4 is frequency-divided by a frequency dividing circuit 708. The frequency-divided signal and the synchronizing signal 705 are compared by a phase comparison circuit 710, and after passing through a low-pass filter 711, are fed back to the differential amplifier circuits A1 and A2. The The oscillation frequency of the voltage controlled oscillation circuit 701 is adjusted so that the phase difference between the output of the frequency dividing circuit 708 and the synchronization signal 705 is always zero, so the oscillation frequency of the voltage controlled oscillation circuit 701 is the frequency division of the frequency of the synchronization signal 705. The frequency division ratio by the circuit 708 is fixed. Since the frequency of the synchronization signal 705 is the same as that of the horizontal synchronization signal, the carrier frequency can be synchronized between transmission and reception.

As shown in FIG. 4, the timing at which the horizontal synchronization signal, the vertical synchronization signal, and the display data are read out by the liquid crystal controller can be divided by the liquid crystal controller 403 on the transmission side. Therefore, on the receiving side, various timings and clocks such as the head of the packet from the transmitting side, the bit boundary of display data, and the X clock signal for driving the driver of the liquid crystal display are multiplied by the synchronization signal 705. This can be easily obtained by dividing the output signal of the voltage controlled oscillation circuit 701. The frequency dividing circuit 709 divides the output of the buffer circuit B3 to generate a horizontal synchronizing signal 721 (FIG. 8 (k)), a vertical synchronizing signal 719 and an X clock 715, and also detects a bit boundary to detect a bit boundary signal. 718 is transmitted to the bit determination circuit 713 to provide timing for bit determination.

Even if the carrier wave is reproduced on the receiving side by the PLL in this way, there is a slight phase shift between the horizontal synchronization signal transmitted through the wired path and the data bit signal propagating in the space. Exists. This phase shift can be removed as follows.
That is, as shown in FIG. 8, a fixed bit pattern is transmitted as an electromagnetic wave signal as a preamble at a predetermined position in one packet. The synchronization signal is a signal indicating a section where this preamble exists. Figure 8 (e) shows the electromagnetic wave signal in the preamble, as a bit pattern of the preamble, and transmits the data as the same as the phase of the buffer circuit B1. FIGS. 8F to 8K are illustrated by reducing the time scale of FIGS. 8A to 8E. The preamble is created by inserting a predetermined number of fixed bits at predetermined positions in one communication packet (for example, one horizontal synchronization interval). The position of the preamble can be known from the synchronization signal 705 (FIG. 8 (f)) sent on the receiving side, and the horizontal synchronization signal 721 is generated from the oscillation signals Q1 to Q1 of the voltage controlled oscillation circuit 701 as described above. It can be easily generated by counting Q4.

  The delay amount control circuit 712 receives the synchronization signal 705 and controls the delay amount of the delay circuit 703 so that the output of the multiplier circuit 707 in the preamble period becomes a predetermined value. Since the preamble is to transmit a predetermined bit pattern, if the preamble period is known on the receiving side, the phase of the waveform of the received signal 704 and the oscillation signal Q1 oscillated by the voltage controlled oscillation circuit 701 during this period. The phase of the carrier wave between transmission and reception can be synchronized by matching the phases of .about.Q4. The delay amount control circuit 712 adjusts the delay amount of the delay circuit 703 to a predetermined amount during the preamble period, and maintains a constant value until the next preamble period.

  The predetermined amount is maximum when the phase of the carrier wave multiplied by the multiplication circuit 707 is a signal in phase with the preamble, zero when the phase difference is 90 degrees, and minimum when the phase is opposite. It means that. In the example of FIG. 7, the preamble signal is in phase with the output of the buffer circuit B1, but the phase of the carrier wave multiplied by the multiplication circuit 707 is inverted by the delay circuit 703. Therefore, the delay amount control circuit 712 includes the multiplication circuit. The delay circuit 703 must be controlled so that the output of 707 is minimized.

  The delay circuit 703 controls the current flowing into each inverter by inserting the transistors T3, T6, T7, T10 into the respective sources of the inverters of the transistors T4, T5 or T8, T9, thereby controlling the delay time of the inverter. I have control. The transistors T1 and T2 are current mirrors, and have an effect of improving the symmetry between the P-channel transistor and the N-channel transistor.

  The output of the buffer circuit B2 is not in the loop like the output of the buffer circuit B1, but the transistors T4, T5, T3, T6 and T8, T9, T7, T10 are very close to each other on the same semiconductor substrate. Since the same delay amount as that of the output of the buffer circuit B1 can be obtained by mounting with good symmetry in the distance and driving with the same control voltage 717, any of the oscillation signals Q1, Q2, Q3, Q4 of the voltage controlled oscillation circuit 701 can be obtained. By putting one of them in the loop, the phase delay amount of the other oscillation signals Q1, Q2, Q3, and Q4 can be corrected.

The vertical synchronization signal 719 is a bit pattern different from the preamble when there is a vertical synchronization signal, or an information bit indicating that it is a vertical synchronization signal is inserted as an electromagnetic wave signal at a predetermined position in one horizontal scanning section, If it is detected on the receiving side, it can be detected more easily.
By the method as described above, it is possible to reproduce a demodulation carrier wave that is completely synchronized with the received signal in both phase and frequency. In addition, any of these circuits can be integrated on a semiconductor integrated circuit and can be operated with minimum power consumption. As a result, it is possible to provide an inexpensive and highly reliable circuit with extremely high feasibility.

FIG. 9 is a block diagram showing the main part of another embodiment of the electronic apparatus according to the present invention, and shows an example of an electronic apparatus using an image sensor.
In FIG. 9, the image sensor 901 is activated by a horizontal synchronization signal 920 and a vertical synchronization signal 921 generated from the control circuit 902, and outputs captured image data 919. The logic circuit 903 receives these signals and constructs a packet for wireless transmission. The packet modulates the carrier wave generated by the oscillation circuit 906 by the modulation circuit 905 and is radiated from the transmission antenna 907 as an electromagnetic wave. The control circuit 902 divides and uses the carrier wave signal generated by the oscillation circuit 906 as a clock signal. Therefore, the image data signal 919, the horizontal synchronization signal 920, the vertical synchronization signal 921, and the wireless transmission packet are all synchronized with the carrier wave generated by the oscillation circuit 906.

  An electromagnetic wave signal transmitted from the transmission antenna 907 propagates through a wireless propagation path (space) 922, is received by the reception antenna 908, is amplified by the preamplifier 909, and an unnecessary out-of-band signal is removed by the band-pass filter 910. , Input to the demodulation circuit 912. The PLL 915 generates a carrier wave by multiplying the horizontal synchronization signal 920 sent from the transmission side through the wired path 923 to the carrier frequency, and inputs the carrier wave to the demodulation circuit 912.

  In addition, the logic circuit 916 counts the output of the PLL 915 from the horizontal synchronization signal 920 transmitted through the wired path 923, and detects the synchronization timing necessary for demodulation, the boundary of the packet, and the timing necessary for serial-parallel conversion. Then, information is correctly extracted from the demodulated received signal. The serial-parallel conversion circuit 914 receives a signal from the logic circuit 916, extracts an image data portion from the demodulated reception packet, performs serial-parallel conversion for each pixel, and generates pixel data.

The logic circuit 916 further generates a memory address for writing to the video memory 917 in accordance with the demodulated pixel data, and writes the image data to the address of the video memory 917 directly or via the CPU 918. The CPU 918 accesses the video memory 917 and uses the image data for various applications.
Each of these circuits can be mounted as a single semiconductor integrated circuit, and a circuit that is physically close can be integrated. That is, the control circuit 902, the logic circuit 903, the modulation circuit 905, and the oscillation circuit 906 are integrated on the first semiconductor integrated circuit 925, and the preamplifier 909, the band pass filter 910, the demodulation circuit 912, the serial-to-parallel conversion circuit 914, and the logic circuit are integrated. By integrating 916 and PLL 915 on the second semiconductor integrated circuit 924, there are significant effects in terms of mounting, cost, and reliability.

  Normally, the CPU 918 performs control such as activation of the image sensor 901, but a method of transmitting information related to this activation to the control circuit 902 of the image sensor 901 may be transmitted by wire because the bit rate is low, but wireless transmission You can also In that case, both the CPU 918 side and the image sensor 901 side have transmission / reception means to perform bidirectional communication. In particular, in a clamshell mobile phone, the image sensor 901 and the display element are placed close to each other and are often on the side opposite to the CPU 918 side, and the captured image data is sent to the CPU 918 side for processing. Then, it is sent back to the display element side. Such a case can be realized by adopting a configuration in which the present embodiment and the first embodiment are placed back to back. That is, this can be realized by adopting a structure in which the blocks in FIGS. 4 and 9 are arranged so that the CPU 401 in FIG. 4 and the CPU 918 in FIG. 9 are shared.

Further, the clock necessary for the operation of the CPU 918 can be used by appropriately dividing the output of the PLL 915. In addition, the oscillation circuit 405 of the CPU 401 of the first embodiment can be placed on the CPU 918 side, a horizontal synchronization signal can be sent to the transmission side, and the carrier frequency can be reproduced using the PLL on the transmission side, or the clock of the control circuit 902 can be created. It is.
As described above, by wirelessly transmitting data from the image sensor 901, it is caused by wired transmission such as an increase in power consumption, wiring position restrictions, EMI problems, reliability degradation, and the like that have become apparent due to an increase in the size of the image sensor 901. Various problems can be eliminated. On the receiving side, since a synchronization timing signal necessary for demodulation is transmitted by wire, there is no need to acquire synchronization, and the circuit can be greatly simplified. In addition, since the carrier wave generated by the same oscillation source between transmission and reception is used as a reference, the frequency accuracy required for the oscillation circuit 906 is remarkably relaxed, and most of the components including the oscillation circuit 906 are on the semiconductor integrated circuits 924 and 925. It can be incorporated into the device, and the cost can be significantly reduced.

FIG. 10 shows a detailed example of the main part of still another embodiment of the electronic apparatus according to the present invention. It is an example of the oscillation circuit and multiplication circuit which are used in Examples 1-5. FIG. 10A shows a four-phase oscillation circuit suitable for a CMOS integrated circuit, and FIG. 10B shows its oscillation waveform.
In FIG. 10A, the oscillation circuit is provided with transistors T11 to T22, and the transistors T13 to T17 constitute the differential amplifier circuit A1 of FIG. 7, and the transistors T18 to T22 are different from FIG. A dynamic amplifier circuit A2 is configured. Then, these differential amplifier circuits A1 and A2 are connected in cascade, and the outputs of the differential amplifier circuits A1 and A2 are inverted and fed back to the inputs, so that 90 ° from each other from the drains of the transistors T19, T21, T17, and T14. The four-phase oscillation signals Q1, Q2, Q3, and Q4 having different phases can be extracted. It is also possible to configure a voltage controlled oscillation circuit that can control the current flowing into the differential pair by the voltage applied to the terminal Vc and change the oscillation frequency, or to configure the PLL of the above embodiment.

FIG. 5C shows an example of a differential type multiplier circuit that can be used in the first to fifth embodiments, and is particularly suitable for a CMOS integrated circuit.
In FIG. 10C, the sources of the transistors T31 and T32 are connected to the constant current source ID through the transistor T33, and the sources of the transistors T34 and T35 are connected to the constant current source ID through the transistor T36. . The drains of the transistors T31 and T34 are connected to the power supply potential Vdd through the resistor R1, and the drains of the transistors T32 and T35 are connected to the power supply potential Vdd through the resistor R2.

  Then, weak analog signals (differential) received signals RF1 and RF2 are input to the gates of the transistors T33 and T36, respectively, and a relatively large amplitude can be obtained at the gates of the transistors T31 and T35 and the gates of the transistors T32 and T34. By inputting the differential signals L1 and L2 of the oscillation circuit, the multiplication results of both are obtained as differential signals Q11 and Q12 from the drains of the transistors T31 and T34 and the drains of the transistors T32 and T34, respectively.

  As described in the second embodiment, when both inputs of the multiplication circuits 501 and 505 are digital values, an exclusive OR circuit can be used, but the multiplication circuit 505 used for demodulation on the receiver side is In many cases, the level of the received signal 500 cannot be amplified to a digital logic level, which is often a multiplication of a weak analog signal and a carrier wave by a local oscillation circuit. The present embodiment is a multiplication circuit suitable for a CMOS integrated circuit which is optimal in such a case, and can also be used as a frequency conversion circuit.

  Any of these circuits can be integrated on a semiconductor substrate as a CMOS integrated circuit and can be operated with low power consumption. If these circuits are used, large-scale integration with other functional blocks is possible, and a significant cost reduction and highly reliable device can be realized.

  FIG. 11 shows a detailed example of the main part of still another embodiment of the electronic apparatus according to the present invention. Here, a QPSK modulation circuit is taken as an example. In the third embodiment, the encoder 512 uses the phase shift circuit 514 and the multiplication circuit 515 to shift and modulate the carrier wave generated by the PLL 513 so that the phase shift amount shown in Table 1 is obtained. When there is a four-phase oscillation circuit as shown in the sixth embodiment, a more direct modulation operation can be performed.

  In FIG. 11, a four-phase voltage controlled oscillation circuit 100 is provided in the modulation circuit. Here, the voltage controlled oscillation circuit 100 is provided with transistors T51 to T62, and the transistors T53 to T57 and the transistors T58 to T61 constitute a pair of differential amplifier circuits. The pair of differential amplifier circuits are connected in cascade, and the outputs of the differential amplifier circuits are inverted and fed back to the input, so that the phases of the transistors are shifted from each other by 90 ° from the drains of the transistors T59, T61, T54, and T57. Different four-phase oscillation signals Q11, Q12, Q13, and Q14 can be extracted.

  The oscillation signals Q11, Q12, Q13, and Q14 are used via the buffers B11, B12, B13, and B14 so that the balance of the phase shift amount is not disturbed by the load, and any one of the outputs (buffer B14 in FIG. 11). Is divided by the frequency dividing circuit 111 and phase-compared with the synchronizing signal input to the terminal 112 by the phase shift comparison circuit 113. The synchronization signal input to the terminal 112 corresponds to the output (FIG. 5B) of the frequency dividing circuit 517 of the third embodiment. Then, after the high-frequency component is removed from the output of the phase comparison circuit 113 by the low-pass filter 114, the output is fed back to the control terminal Vc of the voltage controlled oscillation circuit 100, so that a PLL can be configured.

  Thereby, the carrier wave oscillated by the voltage controlled oscillation circuit 100 is phase-locked to the synchronization signal. In addition, the encoder 115 encodes the bits a and b of the transmission data bits, selects the outputs of the buffers B11, B12, B13, and B14 by the selector 116 so that the transfer amount shown in Table 1 is obtained, and modulates it. Output signal 117 is output. Here, the selector 116 is provided with AND circuits P1 to P4 and an OR circuit Q1, and the outputs of the buffers B11, B12, B13, and B14 are input to one input of the AND circuits P1 to P4, respectively, and the encoder 115 Are respectively input to the other inputs of the AND circuits P1 to P4. The outputs of the AND circuits P1 to P4 are input to the OR circuit Q1, and the modulation output signal 117 is output from the OR circuit Q1.

  Any of these circuits can be integrated on a semiconductor substrate as a CMOS integrated circuit and can operate with low power consumption. If these circuits are used, large-scale integration with other functional blocks is possible, and a significant cost reduction and highly reliable device can be realized.

As described above, according to the present invention, high-speed data transmission, which has been difficult in the past, is made wireless, so that EMI, power consumption, mounting space and reliability associated with speeding up, restrictions on device design, communication data, etc. Various problems such as reliability can be solved at once.
In addition, any circuit for realizing wireless communication can be integrated on a semiconductor integrated circuit as a CMOS integrated circuit, and the cost can be greatly reduced compared with conventional mounting parts such as connectors during wired transmission. It is highly useful.

  The present invention has been described by taking a large-sized television display device as an example. However, the present invention is not limited to the above-described embodiment, and can be used in a wide range of applications such as connection with a display in electronic devices such as notebook computers and mobile phones. Applicable to.

The perspective view which shows a state when the clamshell type mobile telephone to which the radio | wireless communication control method of this invention is applied is opened. The perspective view which shows a state when the clamshell type mobile telephone to which the radio | wireless communication control method of this invention is applied is closed. The perspective view which shows the external appearance of the rotary mobile telephone to which the radio | wireless communication control method of this invention is applied. The block diagram which shows the principal part of one Example of this invention. The block diagram which shows the principal part of the other Example of this invention. The time chart which shows operation | movement of one Example of this invention. The block diagram which shows the principal part of the further another Example of this invention. The time chart which shows the operation | movement of other Example of this invention. The block diagram which shows the principal part of the further another Example of this invention. The block diagram which shows the principal part of the further another Example of this invention. The block diagram which shows the principal part of the further another Example of this invention. FIG. 10 is a block diagram illustrating a display device having a conventional liquid crystal display body. The time chart explaining operation | movement of the display apparatus with the conventional liquid crystal display body.

Explanation of symbols

  1, 21 First housing part, 2, 22 Second housing part, 3, 23 Hinge, 4, 24 Operation button, 5, 25 Microphone, 6, 26 External wireless communication antenna, 7, 10, 27, 30 Internal wireless communication antenna, 8, 11, 28 Display, 9, 29 Speaker, 401, 918 CPU, 402, 917 Video memory, 403 Liquid crystal controller, 405, 502, 520, 906 Oscillator, 408, 905 Modulator, 414, 912 Demodulator, 409, 415, 508, 513, 915 PLL, 410, 907 Transmit antenna, 411, 908 Receive antenna, 514, 522 Phase shift circuit, 507, 517, 708, 709, 111 Divider circuit, 501 , 505, 515, 519, 706, 707 Multiplication circuit, 506, 523, 524, 711 Filter, 701,100 VCO circuit, 702 a buffer circuit, 703 a delay circuit, 113,710 phase comparator circuit, 901 an imaging device, 116 a selector, 512,115 encoder

Claims (13)

A first semiconductor integrated circuit having a first oscillator for generating a first pulse train;
A signal generator mounted on the first semiconductor integrated circuit for generating a transmission signal;
A modulation unit mounted on the first semiconductor integrated circuit and modulating the first pulse train generated by the first transmission unit with the transmission signal generated by the signal generation unit ;
A transmitting antenna section for converting a signal modulated by the modulating section into an electromagnetic wave signal and radiates the electromagnetic wave signal,
A receiving antenna unit that receives the electromagnetic wave signal radiated by the transmitting antenna unit,
A second semiconductor integrated circuit having a second oscillation unit for generating a second pulse train;
A demodulator that is mounted on the second semiconductor integrated circuit and demodulates a received signal received by the receiving antenna unit using the second pulse train generated by the second oscillating unit;
An information transmission unit that transmits a synchronization signal and is mounted on the first semiconductor integrated circuit;
Receiving the synchronization signal , and an information receiving unit mounted on the second semiconductor integrated circuit;
A wired path for transmitting the synchronization signal from the information transmitter to the information receiver ;
A synchronization unit that synchronizes between the first transmission unit and / or the modulation unit and the second oscillation circuit and / or the demodulation circuit;
An electronic device comprising:
Demodulating the received signal while the synchronization unit is synchronized based on the synchronization signal transmitted via the wired path,
An electronic device characterized by that. The synchronization unit is
A frequency divider that divides the first pulse train generated by the first oscillator;
A wired transmission unit that transmits the signal frequency-divided by the frequency dividing unit to the second semiconductor integrated circuit as the synchronization signal;
A synchronization control unit that synchronizes the second pulse train generated by the second oscillation unit with the synchronization signal,
The electronic device according to claim 1. The synchronization unit is
A frequency divider that divides the first pulse train generated by the second oscillator;
A wired transmission unit that transmits the signal frequency-divided by the frequency dividing unit to the first semiconductor integrated circuit as the synchronization signal;
A synchronization control unit that synchronizes the second pulse train generated by the first oscillation unit with the synchronization signal,
The electronic device according to claim 1. The synchronization unit is
A third oscillation unit;
A wired transmission unit that transmits the output of the third oscillation unit to the first and second semiconductor integrated circuits as the synchronization signal;
A synchronization control unit that synchronizes the first pulse train generated by the first oscillation unit and the second pulse train generated by the second oscillation unit with the synchronization signal;
The electronic device according to claim 1. The synchronization control unit is configured by a phase lock loop unit including an oscillation unit having a voltage controlled oscillation unit, and multiplies the frequency of the synchronization signal to synchronize the output of the oscillation unit with the previous synchronization signal,
The electronic device according to claim 2, wherein the electronic device is an electronic device. The synchronization control unit
An oscillation unit having a voltage controlled oscillation unit;
A phase-locked loop that multiplies and outputs the frequency of the synchronization signal; and
A phase shift unit that compares and shifts a preamble by a predetermined bit string arranged at a predetermined position in a communication packet transmitted in synchronization with the synchronization signal and an output signal of the oscillation unit;
The electronic device according to claim 2, wherein the electronic device is an electronic device. The modulation unit phase-modulates the first pulse train generated by the first oscillation unit with the transmission signal;
The electronic device according to claim 2, wherein the electronic device is an electronic device. The demodulator performs phase demodulation by multiplying the second pulse train generated by the second oscillator and the received signal.
The electronic device according to claim 2, wherein the electronic device is an electronic device. 9. The first and second oscillating units are configured by single-phase or multi-phase ring oscillation circuits configured on the first and second semiconductor integrated circuits, respectively. The electronic device according to any one of the above. A storage unit for storing display information;
A display unit for displaying the display information;
A display control unit that reads and outputs the display information from the storage unit in accordance with the driving order of the display unit;
A drive unit for driving the display unit based on the display information read by the display control unit;
The electronic device according to claim 2, comprising: An imaging unit;
An imaging control unit that reads out and outputs an image signal captured by the imaging unit;
The electronic device according to claim 2, wherein the electronic device is an electronic device. A first housing part;
A second housing part;
A connecting portion that connects the first housing portion and the second housing portion so as to change a positional relationship between the first housing portion and the second housing portion;
A first antenna for internal wireless communication mounted on the first housing part;
A second internal radio communication antenna mounted on the second casing;
A first internal wireless communication control unit that is mounted on the first housing unit and controls internal wireless communication performed via the first internal wireless communication antenna;
A second internal wireless communication control unit that is mounted on the second housing unit and controls internal wireless communication performed via the second internal wireless communication antenna;
A first semiconductor integrated circuit mounted on the first housing unit and having a first oscillation unit for generating a first pulse train;
A signal generator mounted on the first semiconductor integrated circuit for generating a transmission signal;
Modulation that is mounted on the first semiconductor integrated circuit, modulates the first pulse train generated by the first oscillation unit with the transmission signal, and transmits the modulated signal through the first internal radio communication antenna. And
A second semiconductor integrated circuit mounted on the second housing part and having a second oscillation part for generating a second pulse train;
Demodulation mounted on the second semiconductor integrated circuit and demodulating a received signal received by the second internal radio communication antenna using the second pulse train generated by the second oscillation unit And
An information transmission unit that transmits a synchronization signal and is mounted on the first semiconductor integrated circuit;
Receiving the synchronization signal transmitted by the information transmission unit, and an information reception unit mounted on the second semiconductor integrated circuit;
A wired path for transmitting the synchronization signal from the information transmitter to the information receiver ;
A synchronization unit that synchronizes between the first transmission unit and / or the modulation unit and the second oscillation circuit and / or the demodulation circuit;
A wireless communication terminal having
Demodulating the received signal while the synchronization unit is synchronized based on the synchronization signal transmitted via the wired path,
A wireless communication terminal characterized by the above. An antenna unit for external wireless communication mounted on the first housing unit or the second housing unit;
An external wireless communication control unit that is mounted on the first housing unit or the second housing unit and controls external wireless communication performed via the external wireless communication antenna unit;
A display unit mounted on the second housing unit,
The wireless communication terminal according to claim 12.

Images