JP4682541B2 - Semiconductor crystal growth method - Google Patents

Description

The present invention relates to crystal growth how the semiconductor exhibiting high insulating properties.
The present invention is very useful for manufacturing, for example, field effect transistors.

  As conventional field effect transistors, for example, semiconductor devices such as HEMTs in which a non-doped GaN layer is introduced as a channel layer have been developed. In these conventional devices, a nucleation layer (that is, a lattice constant difference relaxation layer) is developed. There is a problem in that an undesired conductive layer forming a part of the short-circuit path is formed in the vicinity of the upper interface. If such a conductive layer is generated in the element, the pressure resistance of the element deteriorates, which is not desirable.

  In order to solve this problem, for example, a field effect transistor described in Patent Document 1 below has been devised. In this field effect transistor, by adding an IIB group impurity such as Zn to the buffer layer stacked next to the nucleation layer, the buffer layer is buffered from a high resistivity semiconductor layer in which the impurity hardly diffuses into the channel layer. This is characterized in that the layer is formed. With this field effect transistor, electrical element isolation and insulation withstand voltage are improved.

Moreover, as a semiconductor layer with high sheet resistance used for power HFET, the non-doped GaN layer etc. which are described in the following nonpatent literature 1, etc. are known, for example. The non-doped GaN layer used here was laminated to a film thickness of 2 μm at a crystal growth temperature of 1050 ° C. The sheet resistance of this GaN layer was 100 MΩ / cm ² (resistivity: 2 × 10 ⁴ Ωcm). It has been reported that it can be made larger.
JP 2002-57158 A Yoshida Kiyoteru, “AlGaN / GaN Power FET” Furukawa Electric Time Report, No. 109, January 2002

However, when a semiconductor layer to which an impurity is added at a high concentration is formed, it is not always easy to stack a non-doped layer having a sufficiently low impurity concentration after that. This is due to circumstances such as impurities remaining in the crystal growth furnace, or impurities still diffusing between the stacked semiconductor layers.
When such an impurity is mixed in a semiconductor in which a channel is to be formed, it becomes difficult to form a channel having high mobility. This is because carriers are scattered during movement by impurities contained in a semiconductor layer forming a channel.

On the other hand, when trying to manufacture a semiconductor device with high pressure resistance, a sheet resistance of about 100 MΩ / cm ² is not necessarily sufficient. Therefore, in the technique described in Non-Patent Document 1 described above, In addition, it is difficult to grow a semiconductor having a sufficiently high insulating property to meet the required performance. In addition to the above, nothing can be known about the specific countermeasures from Non-Patent Document 1 described above.

The present invention has been made to solve the above-described problems, and an object of the present invention is to realize a non-doped semiconductor layer having excellent insulating properties.
A further object of the present invention is to realize a semiconductor device in which both the mobility of carriers moving in the channel and the breakdown voltage of the element are both high.
However, it is sufficient that the above individual objects are achieved individually by at least one of the individual means of the present invention, and the individual invention of the present application (the individual means described below) It does not necessarily guarantee that there is a specific embodiment that solves all of the above problems at the same time.

In order to solve the above problems, the following means are effective.
That is, the first means of the present invention is to provide a buffer layer made of a group III nitride compound semiconductor and a barrier layer on a semiconductor crystal growth substrate made of Al _x Ga _1-x N (0 ≦ x ≦ 1). In the method of manufacturing a field effect transistor having a channel formed on the interface side of the buffer layer with respect to the barrier layer, at least a part of the buffer layer is made of non-doped Al _x Ga _1-x N (0 ≦ x ≦ 1). The crystal growth temperature of the high-resistance semiconductor layer A is 1120 ° C. or higher and 1160 ° C. or lower at least in the initial stage of crystal growth of the high-resistance semiconductor layer A. The growth rate is 65 nm / min or more and 100 nm / min or less. In the crystal growth process of the high resistance semiconductor layer A, the V / III ratio of the crystal material gas supplied into the reaction chamber is 1400 or more. , Is that it 1550 or less.
However, the above-mentioned initial stage means the first approximately one minute after the crystal growth of the high-resistance semiconductor layer A is started.

A second means of the present invention is to form the high-resistance semiconductor layer A from a non-doped GaN crystal in the first means.

According to a third means of the present invention, in the first or second means described above, at least the crystal growth rate in the initial stage of crystal growth of the high-resistance semiconductor layer A is 70 nm / min or more and 90 nm / min or less. That is.

According to a fourth means of the present invention, in any one of the first to third means described above, the crystal growth temperature of the high resistance semiconductor layer A at least in the initial stage of crystal growth is 1130 ° C. or higher and 1150 ° C. or lower. Is to do. More preferably, the crystal growth temperature is 1130 ° C. or higher and 1140 ° C. or lower.

In the present invention, at least in the initial stage of crystal growth of the high-resistance semiconductor layer A, the V / III ratio of the crystal material gas supplied into the reaction chamber is set to 1400 or more and 1550 or less .
However, the V / III ratio of the crystal material gas referred to here is the number of moles per unit volume of the crystal material gas of the group V element constituting the semiconductor layer to be crystal-grown, of the crystal material gas of the group III element. It is the ratio to the number of moles per unit volume.

  By the above means of the present invention, the above-mentioned problem can be effectively or rationally solved.

The effects obtained by the above-described means of the present invention are as follows.
That is, according to the present onset bright, the semiconductor layer having a high resistivity is grown, an insulating the semiconductor layer (high-resistance semiconductor layer A) can be higher than conventional. Therefore, according to the first means of the present invention, an ideal non-doped high resistance layer having both good flatness and good crystallinity of the upper interface can be formed.

  Under such conditions of crystal growth, the principle of operation that can form a highly insulating semiconductor layer has not yet been fully elucidated, but a nucleation layer and a semiconductor on which crystal is grown. The interface state conventionally formed at the interface with the layer becomes difficult to be formed under the above-mentioned crystal growth conditions, and as a result, the above-described conventional conductive layer formed in the vicinity of the interface disappears. Therefore, it is considered that the above effect can be obtained. The period on the crystal growth process that is particularly deeply related to the formation of the interface states is the initial stage of the crystal growth process of the high-resistance semiconductor layer A, and the period seems to be within the first few minutes.

Further, crystal growth rate of the high-resistance semiconductor layer A (growth rate) is 65 nm / min or more. That is, at least in the initial stage of the crystal growth process of the high-resistance semiconductor layer A, the high-resistance semiconductor layer A is crystal-grown at such a relatively high growth rate, so that the above-described operations and effects can be obtained more reliably. Can do.

According to the second means of the present invention, the high-resistance semiconductor layer A can be formed of a semiconductor layer made of non-doped GaN. A semiconductor layer made of non-doped GaN is very useful as a base substrate or base layer of any semiconductor device. Further, for example, as illustrated in examples described later, it is very useful for a buffer layer of a field effect transistor. Therefore, according to the second means of the present invention, it is possible to manufacture a highly resistive semiconductor layer made of GaN which is extremely useful in industry.

The crystal growth conditions shown below are sufficiently effective for an arbitrary aluminum composition ratio x related to the above-described high-resistance semiconductor layer A, but are particularly optimized for a GaN crystal (x = 0). It is set.

For example, the crystal growth rate of the high resistance semiconductor layer A is preferably 100 nm / min or less . In this case, the crystallinity of the high resistance semiconductor layer A can be ensured well while maintaining the good insulation of the high resistance semiconductor layer A. Furthermore, the flatness or smoothness of the upper interface or surface of the high-resistance semiconductor layer A can be ensured satisfactorily.
Therefore, for example, when the buffer layer of the field effect transistor is formed of such a high-resistance semiconductor layer A, carriers that move in the channel are less likely to be scattered, and thus an element with high carrier mobility can be manufactured.

A more desirable range regarding the crystal growth rate of the high-resistance semiconductor layer A is 70 nm / min or more and 90 nm / min or less .
A more desirable range for the crystal growth rate of the high-resistance semiconductor layer A is 1130 ° C. or higher and 1150 ° C. or lower .
In order to actually realize the crystal growth conditions of the present invention easily, the V / III ratio of the crystal material gas is set to 1400 or more and 1550 or less .

According to these crystal growth conditions, an ideal non-doped high resistance layer having both good flatness of the upper interface and good crystallinity can be formed more reliably. In other words, these crystal growth conditions are extremely important in achieving a very high level of solution for two different problems of ensuring the flatness of the interface or surface of the semiconductor layer and ensuring the pressure resistance of the semiconductor device. It becomes an important condition.
Further, if a non-doped high resistance layer satisfying these conditions is used, for example, a buffer layer of a field effect transistor can be formed extremely well, and the operating performance and pressure resistance of the device are simultaneously improved.

  Further, if the crystal growth temperature of the nucleation layer (that is, the lattice constant difference relaxation layer) is set to less than 800 ° C., the nucleus density of the semiconductor (nucleation layer) that provides a crystal growth surface to the high-resistance semiconductor layer A As a result, the shape of each core and the shape of each nucleus are optimized or optimized, and favorable ELO growth or facet growth of the high resistance semiconductor layer A in the vicinity of the interface between the semiconductor and the high resistance semiconductor layer A is promoted well. As a result, both the crystallinity and the insulating properties of the high resistance semiconductor layer A are ensured satisfactorily. This method is particularly effective when a sapphire substrate is used, but it is also useful when using other substrates.

The growth temperature of the semiconductor (nucleation layer) at this time is more preferably 600 ° C. or less, and more preferably about 400 ° C. It is thought that better results are obtained under these conditions because the nucleation density and the individual nuclei shape of the nucleation layer are optimized under these conditions.
As for the effect of such facet growth or ELO growth, for example, the following Reference 1 describes related known cases.
(Reference 1): Amano, Akasaki, “Group III nitride on sapphire substrate” Applied Physics, Vol. 68, No. 7 (1999), p. 700-772.

The group II nitride compound semiconductor (: high resistance semiconductor layer A) manufactured by the above method, that is, any one of the first to seventh means of the present invention is as described above. Since these semiconductors exhibit a very high resistivity of 1 × 10 ⁸ Ωcm or more, these semiconductors are extremely useful industrially .

Also, in a field effect transistor, it is possible to form an ideal undoped buffer layer having both excellent flatness of the upper surface and good crystallinity, the purpose of having a high mobility performance Therefore, it is possible to ensure the pressure resistance of the field effect transistor significantly higher than that of the conventional one.

Also, it is possible to form a high-resistance layer of an ideal undoped having both good flatness of the upper surface and good crystallinity. For this reason, in the target semiconductor device, at least the crystal quality of the high resistance layer can be ensured satisfactorily, and at the same time, the pressure resistance of the semiconductor device can be ensured significantly higher than before.

  As a method for crystal growth of the semiconductor layer, there are molecular beam vapor phase epitaxy (MBE), halide vapor phase epitaxy (HVPE) and the like in addition to metal organic compound vapor phase epitaxy (MOVPE). It is valid.

In addition to hydrogen (H ₂ ) gas, an inert gas can be used as the carrier gas used to carry the crystal material gas of the semiconductor layer during crystal growth. As these inert gases, rare gases (He, Ne, Ar, Kr, Xe, Rn), nitrogen (N ₂ ) gas, or a mixed gas thereof can be used. Moreover, when using these mixed gases as an inert gas, the mixing ratio may be arbitrary. In addition, when these inert gases are used as the main carrier gas (that is, the main component of the carrier gas), hydrogen (for example, hydrogen (unless there is a possibility that undesirable atoms and molecules remain in the semiconductor crystal to be crystal-grown), for example. Even if other gases such as H ₂ ) gas are mixed in the carrier gas in a trace amount or a slight amount, the operation of the present invention is not particularly disturbed.

As a material for the crystal growth substrate constituting the field effect transistor of the present invention, silicon carbide (SiC) is most suitable in terms of heat resistance and heat dissipation, but relatively inexpensive sapphire, silicon (Si), etc. May be used. In addition, using a GaN substrate is not necessarily advantageous in terms of cost and heat dissipation, but adoption of the GaN substrate does not particularly impede application of the present invention.
In addition, as a form of forming the ohmic electrode or the Schottky electrode constituting the field effect transistor of the present invention, any known form can be adopted. For example, the gate electrode may be formed on the uppermost layer of the barrier layer via a thin insulating film.

  The barrier layer constituting the field effect transistor of the present invention may be formed from a non-doped semiconductor layer or an impurity-added semiconductor layer depending on the type and function of the element. These barrier layers may be formed from a plurality of semiconductor layers having different compositions. The same applies to the buffer layer constituting the field effect transistor of the present invention. However, the semiconductor layer constituting the channel is preferably formed from a non-doped semiconductor layer in order to prevent carrier scattering and improve carrier mobility. Therefore, it is desirable to form at least the uppermost layer of the semiconductor layers constituting the buffer layer from a non-doped semiconductor layer.

Hereinafter, the present invention will be described based on specific examples.
However, the embodiments of the present invention are not limited to the following examples.

  FIG. 1 is a cross-sectional view of a sample 10 manufactured by the MOVPE method of Example 1 having a non-doped high-resistance semiconductor layer 13. The substrate 11 is made of silicon carbide (4H—SiC), and a high-temperature growth nucleation layer 12 made of AlN having a thickness of about 200 nm grown at a growth temperature of 1140 ° C. is laminated thereon. Yes. The film thickness of the high-resistance semiconductor layer 13 made of non-doped GaN stacked on the high-temperature growth nucleation layer 12 was about 2 μm, and the crystal growth conditions were as follows.

(Crystal growth conditions for the high-resistance semiconductor layer 13)
Carrier gas: Hydrogen (H ₂ ) gas Growing furnace total pressure: 1013 [hPa]
Crystal growth rate: 80 [nm / min]
V / III ratio: 1473
Crystal growth temperature: (a) 1120 [° C.], (b) 1130 [° C.],
(C) 1140 [° C], (d) 1150 [° C]

(Evaluation for pressure resistance)
The above-mentioned non-doped high-resistance semiconductor layer 13 is laminated according to the above crystal growth conditions, and a total of four types of samples 10 in FIG. 1 are produced for each crystal growth temperature (a) to (d). An electrode made of a vanadium (V) layer having a thickness of about 15 nm was formed near the left and right ends of the upper surface of each high resistance semiconductor layer 13, and the leakage current of the high resistance semiconductor layer 13 was measured.

FIG. 2 shows the relationship between the crystal growth temperature ((a) to (d)) of the high-resistance semiconductor layer 13 at this time and the leakage current at an applied voltage of 200V. From this result, in the case of forming a high resistance semiconductor layer from a non-doped GaN layer, the crystal growth temperature is set to 1120 ° C. or higher in order to suppress the leakage current at an applied voltage of 200 V to 1 × 10 ⁻⁴ [A] or lower. It turns out that it is necessary to do. In order to suppress the leakage current to 1 × 10 ⁻⁶ [A] or lower, the crystal growth temperature is preferably set to 1130 ° C. or higher.
The high-resistance semiconductor layer 13 made of non-doped GaN formed at a crystal growth temperature (c) of 1140 [° C.] showed a very high resistivity of 1 × 10 ⁸ Ωcm.

(Evaluation for crystallinity)
On the other hand, as a result of measuring the FWHM (: Full Width Half Maximum) of each high resistance semiconductor layer 13 of each sample 10 using the same sample 10 ((a) to (d)) as described above, the graph of FIG. Obtained. FIG. 3 shows the relationship between the crystal growth temperature of each high resistance semiconductor layer 13 and FWHM. The smaller the FWHM value, the better the crystallinity. Conversely, when this value exceeds 300 (arcsec), the crystallinity of the high-resistance semiconductor layer 13 begins to deteriorate gradually, and this value is 400 ( If it exceeds arcsec), it has been empirically found that the flatness of the surface of the high-resistance semiconductor layer 13 is often inferior to such an extent that it adversely affects device characteristics such as carrier mobility. .

  Therefore, when a high-performance field effect transistor is manufactured using such a high-resistance semiconductor layer 13 made of non-doped GaN, the crystal growth temperature should be 1160 ° C. or lower. These tendencies related to crystallinity could be confirmed visually using an optical microscope.

  From the above experimental results, when manufacturing at least a high-performance field effect transistor, the crystal growth temperature of the high-resistance semiconductor layer 13 is desirably in the range of 1120 ° C. to 1160 ° C., and more desirably 1130 ° C. to 1150 ° C. It can be said that the range of ° C is most suitable.

  FIG. 4 is a cross-sectional view of a sample 20 manufactured by the MOVPE method of Example 2 having a non-doped high-resistance semiconductor layer 23. The substrate 21 is made of sapphire having a c-plane as a main surface, and a low-temperature growth nucleation layer 22 made of AlN having a film thickness of about 40 nm grown at a growth temperature of 400 ° C. is laminated thereon. ing. The film thickness of the non-doped high-resistance semiconductor layer 23 laminated on the high-temperature growth nucleation layer 22 was about 2 μm, and the crystal growth conditions were as follows.

(Crystal growth conditions for the high-resistance semiconductor layer 23)
Carrier gas: Hydrogen (H ₂ ) gas Growing furnace total pressure: 1013 [hPa]
Crystal growth temperature: 1150 [° C]
V / III ratio: 1473
Crystal growth rate: (e) 659 [Å / min], (f) 827 [Å / min],
(G) 968 [min / min]

(Evaluation for pressure resistance)
The above-mentioned non-doped high-resistance semiconductor layer 23 is laminated according to the above crystal growth conditions, and a total of three types of samples 20 shown in FIG. 4 are produced for each crystal growth rate (e) to (g). An electrode made of a vanadium (V) layer having a thickness of about 15 nm was formed near the left and right ends of the upper surface of each high resistance semiconductor layer 23, and the leakage current of the high resistance semiconductor layer 23 was measured.

The graphs and tables in FIGS. 5A and 5B show the relationship between the crystal growth rate ((e) to (g)) of the high-resistance semiconductor layer 23 and the leakage current at an applied voltage of 40V. From this result, when forming a high resistance semiconductor layer from a non-doped GaN layer, in order to suppress the leakage current at an applied voltage of 40 V to 1 × 10 ⁻⁸ [A] or less, the crystal growth rate is about 65 nm / min. It turns out that it is good to do it above.
Note that the high-resistance semiconductor layer 23 made of non-doped GaN formed at a crystal growth rate (g) of 968 [〕 / min] exhibited a very high resistivity of 1 × 10 ⁸ Ωcm.

(Evaluation for crystallinity)
On the other hand, when the crystal growth rate is about 90 [nm / min] or more, the crystallinity of the high-resistance semiconductor layer 23 begins to gradually deteriorate, and when it exceeds about 100 [nm / min], the mobility of carriers and the like Experience has shown that the flatness of the surface of the high-resistance semiconductor layer 23 is often inferior to the extent that it adversely affects device characteristics. Accordingly, when a high-performance field effect transistor is manufactured using such a high-resistance semiconductor layer 23 made of non-doped GaN, the crystal growth rate should be 100 nm / min or less. These tendencies related to crystallinity could be confirmed visually using an optical microscope.

  From the above experimental results, when manufacturing at least a high-performance field effect transistor, the crystal growth rate of the high-resistance semiconductor layer 23 is desirably in the range of 65 nm / min to 100 nm / min, and more desirably 70 nm / min. It can be said that the range of min to 90 nm / min is most suitable.

  FIG. 6 is a cross-sectional view of the field effect transistor 100 of the third embodiment. This field effect transistor 100 is a semiconductor element formed by sequentially stacking group III nitride compound semiconductors by crystal growth, and the crystal growth substrate 101 is made of silicon carbide (4H—SiC) having a thickness of about 500 μm. Is formed. On this crystal growth substrate 101, a nucleation layer 102 (: lattice constant difference relaxation layer) made of AlN having a thickness of about 200 nm is laminated.

A semiconductor layer 103 made of non-doped GaN having a thickness of about 2 μm is formed on the nucleation layer 102. The semiconductor layer 103 corresponds to the high resistance semiconductor layer A of the present invention. A barrier layer 104 made of non-doped Al _0.25 Ga _0.75 N having a thickness of about 40 nm is stacked on the semiconductor layer 103 (high resistance semiconductor layer A). The thickness of the barrier layer 104 is such that the tunnel effect of carriers (electrons) between the channel formed in the vicinity of the upper interface of the semiconductor layer 103 and the following individual ohmic electrodes (105, 107) is reliable and It is set to express well.

  Reference numerals 105, 106, and 107 denote a source electrode (ohmic electrode), a gate electrode (Schottky electrode), and a drain electrode (ohmic electrode), respectively. Each ohmic electrode (source electrode 105 and drain electrode 107) is formed by laminating a thin metal layer made of titanium (Ti) with a thickness of about 100 mm and depositing aluminum (Al) thereon with a thickness of about 3000 mm. A metal layer is further laminated by vapor deposition. These ohmic electrodes are well adhered and alloyed by heat treatment at about 700 ° C. to 900 ° C. by flash annealing for less than 1 second. On the other hand, the gate electrode 106 is a Schottky electrode formed by depositing a metal layer made of nickel (Ni) of about 100 Å by vapor deposition, and further depositing a metal layer made of gold (Au) on it about 3000 Å. .

Hereinafter, the manufacturing method of the above-described field effect transistor 100 will be described focusing on the characteristic part of the present invention (semiconductor layer 103: high-resistance semiconductor layer A).
Each of the semiconductor layers (semiconductor layers 102, 103, 104) of the field effect transistor 100 is grown by vapor phase growth using a metal organic compound vapor phase growth method (MOVPE). The gases used here are carrier gas (H ₂ or N ₂ ), ammonia gas (NH ₃ ), trimethyl gallium (Ga (CH ₃ ) ₃ ), trimethyl aluminum (Al (CH ₃ ) ₃ ), etc. It is.

First, in this vapor phase growth, the crystal growth substrate 101 is first baked at 1140 ° C., and a nucleation layer 102 (: lattice constant difference relaxation layer) made of AlN is formed on the crystal growth substrate 101 at 1140 ° C. The crystal was grown to a thickness of about 200 nm.
Next, crystal growth of the semiconductor layer 103 made of non-doped GaN crystal having a thickness of about 2 μm was performed according to the following crystal growth conditions.
(Crystal growth conditions of the semiconductor layer 103)
(1) Crystal growth temperature: 1140 [° C.]
(2) Crystal growth rate: 80 [nm / min]
Next, the semiconductor layer 104 (buffer layer) made of non-doped Al _0.25 Ga _0.75 N crystal having a thickness of about 40 nm was stacked. However, the crystal growth temperature at this time was about 1000 ° C.

  The field effect transistor 100 shown in FIG. 6 was manufactured through these crystal growth steps. As a result, a desired field effect transistor (HFET) having high mobility and extremely good electrical characteristics and a small leakage current could be realized. . Such field effect transistors (HFETs) are very advantageous compared to conventional ones in terms of device performance and reliability, as well as device miniaturization and high integration. is there.

  FIG. 7 is a cross-sectional view of the field effect transistor 200 (MISFET) of the fourth embodiment. The greatest difference of the field effect transistor 200 with respect to the previous field effect transistor 100 is that an insulating film 208 made of silicon nitride (SiN) is provided between the gate electrode 206 and the barrier layer 204. These parts (201 to 207) are formed in the same manner as the corresponding parts (101 to 107) of the field effect transistor 100 described above.

  According to such a configuration, even when a MISFET is manufactured, the operation and effect of the present invention can be obtained in the same manner as in Example 3 based on the means of the present invention. Also, according to this configuration, a field effect transistor having an excellent gate breakdown voltage can be manufactured.

[Other variations]
The embodiment of the present invention is not limited to the above-described embodiment, and other modifications as exemplified below may be made. Even with such modifications and applications, the effects of the present invention can be obtained based on the functions of the present invention.

(Modification 1)
For example, in Example 3 above, silicon carbide (SiC) is used for the substrate of the field effect transistor, but a sapphire substrate or the like is also useful as the crystal growth substrate. The semiconductor layer 102 and the semiconductor layer 103 of the field effect transistor 100 shown in FIG. If formed, even in such a case, the action and effect of the present invention can be obtained based on the means of the present invention.

  In this case, as can be seen from Example 2 and the like, as the nucleation layer (semiconductor layer 102 in FIG. 6), it is desirable to grow a semiconductor layer made of AlN having a thickness of about 40 nm at a low temperature at about 400 ° C. . Further, as the high resistance semiconductor layer A (semiconductor layer 103 in FIG. 6) constituting the buffer layer, it is desirable to stack a non-doped GaN crystal about 2 μm at a growth temperature of 1150 ° C. and a crystal growth rate of 90 nm / min.

(Modification 2)
For example, various barrier layers such as the semiconductor layer 104 and the semiconductor layer 204 may be formed of InAlN, InAlGaN, or the like. These barrier layers are formed of a general group III nitride compound semiconductor having a band gap energy which is necessary and sufficiently larger than the band gap energy of the buffer layer immediately below (for example, the semiconductor layer 103 and the semiconductor layer 203). can do.

(Modification 3)
Further, instead of these barrier layers, an n-type semiconductor layer may be stacked there. For example, a MESFET can be manufactured by stacking an n-type semiconductor layer in place of the semiconductor layer 104 in FIG.

  That is, various field effect transistors such as HFET, MISFET, and MESFET can be manufactured by arbitrarily applying these various modifications to the above-described embodiments and modifications.

  The non-doped semiconductor layer (high-resistance semiconductor layer A) having high resistance and excellent insulation according to the present invention realizes extremely high insulation while completely wiping off the adverse effects of impurities, such as FETs and HEMTs. The present invention is not limited to the field effect transistor, and can be used for any other semiconductor device such as a semiconductor light emitting element such as a semiconductor laser or LED, a semiconductor light receiving element, or a pressure sensor.

Sectional view of sample 10 having non-doped high-resistance semiconductor layer 13 (Example 1) The graph which shows the relationship between the crystal growth temperature of the high resistance semiconductor layer 13, and leakage current The graph which shows the relationship between the crystal growth temperature of the high resistance semiconductor layer 13, and FWHM Sectional view of sample 20 having non-doped high-resistance semiconductor layer 23 (Example 2) The graph which shows the relationship between the growth rate of the high resistance semiconductor layer 23, and leakage current Table showing relationship between growth rate of high-resistance semiconductor layer 23 and leakage current Sectional drawing of the field effect transistor 100 of Example 3 Sectional drawing of the field effect transistor 200 of Example 4

10: Sample having a non-doped high-resistance semiconductor layer (Example 1)
11: Silicon carbide substrate (4H-SiC)
12: High temperature growth nucleation layer (AlN)
13: Non-doped high-resistance semiconductor layer 20: Sample having a non-doped high-resistance semiconductor layer (Example 2)
21: Sapphire substrate 22: Low temperature growth nucleation layer (AlN)
23: Non-doped high-resistance semiconductor layer 100: Field effect transistor (Example 3)
101: Crystal growth substrate (SiC)
102: AlN layer (buffer layer)
103: Semiconductor layer (buffer layer) made of GaN
104: Semiconductor layer (barrier layer) made of AlGaN
105: Source electrode (ohmic electrode)
106: Gate electrode (Schottky electrode)
107: drain electrode (ohmic electrode)
208: Insulating film (SiN)

Claims (4)

A buffer layer made of a group III nitride compound semiconductor and a barrier layer are provided on a semiconductor crystal growth substrate made of Al _x Ga _1-x N (0 ≦ x ≦ 1), and the buffer layer with respect to the barrier layer In the method of manufacturing a field effect transistor in which a channel is formed on the interface side,
At least a part of the buffer layer is formed of a high-resistance semiconductor layer A made of non-doped Al _x Ga _1-x N (0 ≦ x ≦ 1),
At least in the initial stage of crystal growth of the high-resistance semiconductor layer A,
The crystal growth temperature of the high resistance semiconductor layer A is 1120 ° C. or higher and 1160 ° C. or lower ,
The crystal growth rate of the high-resistance semiconductor layer A is 65 nm / min or more and 100 nm / min or less,
In the crystal growth process of the high-resistance semiconductor layer A, a V / III ratio of a crystal material gas supplied into a reaction chamber is 1400 or more and 1550 or less, and a method for manufacturing a field effect transistor. 2. The method of manufacturing a field effect transistor according to claim 1, wherein the high-resistance semiconductor layer A is made of a non-doped GaN crystal. The crystal growth rate of the high-resistance semiconductor layer A is 70 nm / min or more and 90 nm / min or less at least in the initial stage of crystal growth of the high-resistance semiconductor layer A. 3. The manufacturing method of the field effect transistor of description. In at least the crystal growth early stages of the high resistance semiconductor layer A, the crystal growth temperature of the high-resistance semiconductor layer A, 1130 ° C. or more, any one of claims 1 to 3, characterized in that at 1150 ° C. or less 2. A method for producing a field effect transistor according to item 1.

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