JP4679603B2 - Recording / playback device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a recording and reproducing device for suppressing unauthorized use by an unauthorized user as much as possible while preventing digital data from being degraded as much as possible when the digital data is used by an authorized user. <P>SOLUTION: The recording and reproducing device includes: a memory cell array including memory cells arranged in a matrix, each memory cell having a resistance variable element 10 which can be written by changing a resistance thereof with a current; a user authentication circuit 60 which determines whether a user is authorized or not; and a read current circuit 42 which, when the user authentication circuit determines that the user is an unauthorized user, makes a read current larger than when the user is an authorized user, to supply the current to the memory cell. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a recording / reproducing apparatus using a resistance variable nonvolatile memory that performs writing by flowing current to a memory cell.

  As the variable resistance nonvolatile memory, a magnetoresistive random access memory (hereinafter also referred to as MRAM (Magnetoresistive Random Access Memory)), a PRAM (Phase change Random Access Memory), a ReRAM (Resistance Random Access Memory), and the like are known. These memories use resistance changes associated with changes between two states, such as magnetization direction, crystallinity, and phase transition, for storing information. Data “0” and data “1” are defined corresponding to the two states. Reading of information is performed by flowing a current through the memory cell and detecting a resistance value. Among MRAMs, a spin-injection type MRAM that uses spin transfer torque as a writing principle has attracted attention as a memory excellent in miniaturization. In the spin injection type MRAM, PRAM, and ReRAM, information writing is changed from one of the “0” and “1” states to the other by passing a current through the memory cell. These memories include at least one memory cell, and the memory cell usually includes a resistance change element whose state changes when a current is passed, and a selection transistor for selecting the resistance change element. Yes.

  Such a variable resistance nonvolatile memory is convenient for use in a recording / reproducing apparatus that stores and reproduces digital contents such as video data and music data in terms of application. From the user's point of view, the use of a resistance change type nonvolatile memory in the recording / reproducing apparatus has an advantage that digital data can be kept almost completely and for a long period. On the other hand, in the case of video data and music data stored in analog, it is vulnerable to aging, corrosion, mold, and the like. However, the variable resistance nonvolatile memory is not easily affected by such a thing and has high storage stability. This is a problem that digital data stored in the variable resistance nonvolatile memory with little deterioration can be freely viewed and copied by non-regular users as many times as possible, that is, digital data with little deterioration. However, there is a problem that it is illegally used by non-regular users.

Therefore, in order to prevent the browsing of digital content freely, a storage device in which the number of readings is limited has been proposed (for example, see Patent Document 1). This storage device uses an MRAM, counts the number of times data is read from the MRAM, and restricts reading when the count value exceeds a predetermined number. In the case of this storage device, the digital data can only be completely read out, or when it exceeds a predetermined number of times, it cannot be read out at all. In addition, the information stored in the MRAM has only a state of remaining in a complete form or being completely erased. If hacking is performed so that the counter can be read even if the counter value is hacked, that is, the count value exceeds a predetermined number of times, the data may be completely stolen.
JP 2005-182799 A

  Further, as will be described later, the variable resistance nonvolatile memory has a problem in that erroneous writing due to reading occurs due to a reading current that flows during reading. That is, even if it is a regular user, there is a problem that digital data deteriorates over the years of use.

  The present invention has been made in consideration of the above circumstances, and prevents unauthorized use of unauthorized users as much as possible without degrading digital data as much as possible when used by authorized users. An object of the present invention is to provide a recording / reproducing apparatus capable of performing the above.

  A recording / reproducing apparatus according to one embodiment of the present invention includes a memory cell array in which memory cells having resistance change elements that can be written by flowing current and changing resistance are arranged in a matrix, and whether the user is a regular user or a non-regular user A user authentication circuit that authenticates whether the user is a user, and when the user authentication circuit authenticates the non-regular user, a read current is made to flow through the memory cell with a read current larger than that of a regular user And a current circuit.

  According to the present invention, it is possible to provide a recording / reproducing apparatus capable of suppressing unauthorized use of an unauthorized user as much as possible without degrading digital data as much as possible when used by an authorized user. .

BEST MODE FOR CARRYING OUT THE INVENTION

  First, before describing an embodiment of the present invention, an example of a variable resistance nonvolatile memory and the principle of the present invention will be described.

  In general, the resistance change type nonvolatile memory includes at least one memory cell. As shown in FIG. 1, the memory cell includes a resistance change element 10 that changes its state by flowing a current, and the resistance change element 10. And a selection transistor 20 for selecting.

  An MRAM, which is a first example of a variable resistance nonvolatile memory, is a memory device using a ferromagnetic tunnel junction (MTJ) element having a large magnetoresistance effect as a variable resistance element of a memory cell that stores information. It attracts attention as a next-generation memory device characterized by infinite rewrite resistance, high-speed operation, large capacity, and non-volatility.

  A spin injection type MRAM will be described as the MRAM. The MTJ element as a variable resistance element includes two ferromagnetic layers 12 and 16 and a tunnel barrier layer 14 sandwiched between them. As shown in FIGS. 2A and 2B, one of the ferromagnetic layers is a reference layer 12 whose magnetization direction is unchanged before and after energization, and the other is a storage layer whose magnetization direction is variable by energization. 16 When the magnetization directions of the reference layer 12 and the storage layer 16 are parallel, the MTJ element 10 is in a low resistance state, and when it is antiparallel (AP), the MTJ element 10 is in a high resistance state. Information can be stored by associating these low resistance state and high resistance state with “0” and “1” of binary information. Writing is performed by reversing the direction of magnetization of the storage layer 16 by spin transfer torque generated by passing a write current through the MTJ element 10. For example, as shown in FIG. 2A, when the magnetization directions of the reference layer 12 and the recording layer 16 are antiparallel before the write current is passed, electrons are transferred from the reference layer 12 to the recording layer 16 via the tunnel barrier layer 14. , So that the magnetization direction of the recording layer 16 is parallel to the magnetization direction of the reference layer 12. As shown in FIG. 2B, when the magnetization directions of the reference layer 12 and the recording layer 16 are parallel before the write current is passed, electrons are transferred from the recording layer 16 to the reference layer 12 via the tunnel barrier layer 14. , So that the magnetization direction of the recording layer 16 is antiparallel to the magnetization direction of the reference layer 12. In this specification, the case where the magnetization direction of the recording layer 16 is parallel to the magnetization direction of the reference layer 12 is defined as data “0”, and the case where the magnetization direction is antiparallel is defined as data “1”. The reverse may be possible. The current required for magnetization reversal, that is, the switching current, is preferably as small as possible within a range in which resistance to thermal disturbance can be secured. Further, in order to reduce erroneous writing, it is desirable that the variation of each bit (memory cell) of the switching current is small.

  As shown in FIGS. 3A and 3B, the stored information is read by detecting whether the MTJ element 10 is in a low resistance state or a high resistance state by passing a current through the MTJ element 10. Therefore, it is preferable that the MTJ element used in the MRAM has a large resistance change rate (MR ratio) due to the magnetoresistive effect. In order to perform reading accurately, it is desirable that the variation in resistance of the MTJ element is small. The stored information is non-volatile and usually has memory retention characteristics of 10 years or more. However, there is a slight probability that a part of the binary information stored by the thermal disturbance will change. Furthermore, as described later, there is a small probability that a part of the binary information will be changed by an action of reading.

In the MRAM, there is a phenomenon in which information is changed by a read current I _{read that} is passed during reading. This is a phenomenon called “wrong writing by reading”. First, a basic 1-bit operation will be described. Consider a case where the read current is supplied in the same direction as the write current written from “0” (P) to “1” (AP). In general, it is known that the probability p that the magnetization is reversed to “1” after t seconds after flowing the read current Iread in the “0” state is expressed by the following equation from the viewpoint of thermal disturbance (for example, M Pakala, Y. Huai, T. Valet, Y. Ding, and Z. Diao, Journal of Applied Physics, Vol. 98, 056107 (2005)).

であり、ｆ_０は試行頻度であり、１０^９Ｈｚ〜１０^１０Ｈｚ程度である。ΔＥは磁化反転の際に越えなければならないエネルギーバリア（ｅｒｇ）、Ｋ_ｕは磁気異方性エネルギー密度（ｅｒｇ／ｃｍ^３）、Ｖは記憶層の体積（ｃｍ^３）、ｋ_Ｂはボルツマン定数、Ｔは絶対温度（Ｋ）である。Ｉ_ｃは電流パルス幅が１／ｆ_０秒の場合の磁化反転電流である。（２）式の右辺の係数
Δ_{ｔｈｅｒｍ}＝Ｋ_ｕＶ／（ｋ_ＢＴ）
を熱擾乱パラメータと呼ぶ。（１）式と（２）式から、大きな電流で読み出すほど、読出しパルスがかかっている時間ｔの間に情報が変化する確率が高くなることが分かる。 here

F ₀ is the trial frequency, which is about 10 ⁹ Hz to ^{10 10} Hz. ΔE must exceed the time of the magnetization reversal energy barrier (erg), _{K u} is the magnetic anisotropy energy density (erg / ^cm 3), V is the volume of the storage layer ^(cm 3), _{k B} is the Boltzmann constant, T is the absolute temperature (K). I _c is a magnetization reversal current when the current pulse width is 1 / f ₀ seconds. (2) Coefficient on the right side of the equation Δ _therm = K _u V / (k _B T)
Is called the thermal disturbance parameter. From the equations (1) and (2), it can be seen that the larger the current is read, the higher the probability that the information will change during the time t when the read pulse is applied.

  Therefore, in one embodiment of the present invention, a circuit for correcting these slight errors is provided in the MRAM. This correction circuit uses a technique called an error correction code (hereinafter also referred to as ECC (Error Correction Coding)), which corrects an error even when “erroneous writing by reading” occurs. For example, in an error correction method called an extended Hamming code (Extended Hamming code), 64 bits are regarded as one block and 8 bits of redundant bits are added to the information to detect a 1-bit error in one block. You can correct that. If there is an error of 2 bits in one block, it can be known that there is an error, but it cannot be corrected. There are two stages to using ECC in MRAM. As the first stage of ECC, the read data is inspected, corrected, and output. At this stage, the data in the original MRAM is not corrected. In the second stage of ECC, when an error is found in the ECC, the corrected data is rewritten in the original MRAM to correct it. If the second stage is not performed, an error of 1 bit in one block at first will become an error of 2 bits in one block as time passes, and correction cannot be performed. The second-stage rewriting may be performed every time data is read, or may be inspected, corrected, and rewritten once every time a certain number of times such as 1000 times are read.

  In addition, the PRAM which is the second example of the variable resistance nonvolatile memory uses a chalcogenide glass such as Ge—Sb—Te as the resistor material, and utilizes the fact that the resistance is different between the crystalline state and the amorphous state. (Reference: YJ Song et al., “Highly Reliable 256Mb PRAM with Advanced Ring Contact Technology and Novel Encapsulating Technology”, 2006 Symposium on VLSI Technology Digest of Technical Papers (2006)). The writing principle will be described with reference to FIG. The distinction between writing of data “0” and data “1” is performed by changing the temperature rise of the resistor by changing the way of applying the current pulse. The reset pulse gives a large current in a short time. As a result, the resistor is heated beyond the melting point (Tm) of the resistor, and then rapidly cooled, so that the resistor becomes an amorphous high resistance state. The set pulse gives a smaller current with a longer pulse width than the reset pulse. As a result, the resistor is heated above the crystallization temperature (Tx), but is maintained at a temperature lower than the melting point, and crystallizes into a low resistance state. The PRAM also has a problem of “wrong writing by reading”. In PRAM, reading is performed with a smaller current than writing, but if the reading current is large, the reading current may have the same effect as the set operation due to variations in cell characteristics. If the read current is large, erroneous writing occurs in which a bit in a high resistance state is changed to a low resistance state by a read operation.

In addition, ReRAM, which is a third example of a resistance variable nonvolatile memory, uses NiO, TiO ₂ or an impurity added to the resistor material (reference: R. Jung et al., Applied Physics Letters). , Vol. 91, 022112 (2007)). The principle that the resistance changes is not necessarily clear, but for example, when a voltage is applied, a filament-like conduction path is created and becomes a resistance state, and then when a large current is applied, the conduction path is broken and becomes a high resistance state. , That is considered. The writing principle is shown in FIG. Set operation, for example to limit the current in the state of being limited to a small gate voltage V _G of the select transistor 20 shown in FIG. 1 (e.g. 0.7 V), it supplies a voltage to the variable resistance element 10. As a result, the variable resistance element is in a low resistance state. In the reset operation, by increasing the gate voltage _{V G} (e.g. 1.8V), a large current flows to the variable resistance element 10. As a result, the variable resistance element enters a high resistance state. The ReRAM also has a problem of “wrong writing by reading”. Reading is performed with a smaller current than writing, but if the reading current is large, the reading current may have the same effect as the set operation due to variations in cell characteristics. When the read current is large, erroneous writing occurs in which a bit (memory cell) in a high resistance state is changed to a low resistance state by a read operation.

Another example of ReRAM is one that utilizes the electric field induced resistance change of Mn perovskite oxide. An example of the resistor material is a laminated film in which (Sm, Ca) MnO ₃ and (La, Sr) MnO ₃ are joined (reference: A. Sawa, T. Fujii, M. Kawasaki, and Y. Tokura, Applied Physics Letters, Vol. 88, 232112 (2006)). In this case, the distinction between “0” and “1” writing is performed by changing the voltage application direction. When a forward voltage is applied to the bonding interface, the state changes from a high resistance state to a low resistance state, and when a voltage is applied in the reverse direction, the state changes from a low resistance state to a high resistance state. This ReRAM also has a problem of “wrong writing by reading”. Reading is performed with a current smaller than that of writing, but if the reading current is large, erroneous writing occurs in which the reading current causes a writing operation due to variations in cell characteristics.

In one embodiment of the present invention, even if “erroneous writing due to reading” occurs for an authorized user, digital data is prevented from being deteriorated as much as possible, and for an unauthorized user, an active Thus, “wrong writing by reading” is caused to prevent unauthorized use. Therefore, according to one embodiment of the present invention, in the recording / reproducing apparatus using the resistance change type nonvolatile memory in which data is written by flowing current to the memory cell, it is determined whether the user is a regular user, The read current is changed depending on whether the user is a regular user or a non-regular user. For example, in the case of a non-regular user, the read current is increased to actively cause “erroneous writing by reading”. As a result, the digital data gradually deteriorates according to the number of readings. In the case of a regular user, the read current is set to be small so that the probability that magnetization reversal will occur once or less even after 10 ¹⁶ readings. As a result, digital data deterioration due to reading does not occur.

When ECC is used for digital data correction, there are the following three methods in order to perform the same function.
1) In the case of a non-regular user, the read current is increased to cause “erroneous writing by reading” so that it cannot be corrected by ECC. In the case of a regular user, the read current is set to be small so that the probability of occurrence of “erroneous writing due to reading” is suppressed within a range that can be sufficiently corrected by ECC.
2) In the case of a non-regular user, the read current is increased and the correction write (rewrite) in the second stage of the ECC is not performed. If the second stage of ECC is not performed, a 1-bit error in one block initially becomes a 2-bit error in one block as time passes, and correction cannot be performed. Digital data gradually deteriorates. In this case, the first stage of ECC may or may not be performed for non-regular users. In the case of a non-regular user, if the first stage of ECC is not performed, degraded data is output. In the case of a regular user, since the read current is reduced and the second stage of rewriting is always performed to correct the correct data, the digital data does not deteriorate.
3) In the case of a non-regular user, the read current is increased and the data read out in the first stage of ECC is not inspected and corrected. That is, even if there is an error in the data, it is output as it is. Over time, errors accumulate and digital data degrades gradually. In this case, the second stage of ECC may or may not be performed for non-regular users. In the case of a non-regular user, the progress of data deterioration is faster if the second stage of ECC is not performed. In the case of a regular user, since the read current is reduced and the first and second stages of ECC are performed, the digital data does not deteriorate.

  In addition, it is necessary to carefully set the degree of data degradation when a non-regular user reads data, and for that purpose, it is necessary to carefully set the probability of “wrong writing by reading” when the reading current is set large. .

これを使って、「読出しによる誤書き込み」の確率p_rdは以下の式で計算される。

Hereinafter, the probability of “wrong writing by reading” in the case of the spin injection type MRAM will be described in detail. The thermal disturbance parameter Δ _therm is normally designed to be Δ _therm = 70 to ₁₁₀ . In particular, the present inventors have found a new method instead of the conventional equation (2) as a method of obtaining the probability of “wrong writing by reading”. It has been found that the effective _Δtherm decreases depending on the current I when a current is passed. The effect is approximately expressed by the following equation.

Using this, the probability p _rd of “wrong writing by reading” is calculated by the following equation.

である。 here,

It is.

である。Δ(Ｉ＝０)とΔ（Ｉ＝Ｉｃ)はそれぞれ実験から求めることが出来る。それを使って、

となる。Δ（Ｉ＝０）は、磁場印加した場合のスイッチング磁界のスイープ速度依存性から求めることができる。また、高温放置した場合の磁化反転確率からも求めることができる。Δ（Ｉ＝Ｉｃ）は、Ｉｃ程度の電流を流してスピン・トランスファ・トルクによる磁化反転をさせた場合の、誤書込み確率と正書込み確率から求めることができる。こうして（３）式を使って従来よりも正確に、「読出しによる誤書き込み」の確率が求められることが判明した。 The parameter β representing the effect of current depends on the material and dimensions of the memory layer. This parameter can be obtained as follows.

It is. Δ (I = 0) and Δ (I = Ic) can be obtained from experiments. Use it

It becomes. Δ (I = 0) can be obtained from the sweep speed dependence of the switching magnetic field when a magnetic field is applied. It can also be obtained from the magnetization reversal probability when left at high temperature. Δ (I = Ic) can be obtained from an erroneous write probability and a positive write probability when a current of about Ic is passed to cause magnetization reversal by spin transfer torque. Thus, it has been found that the probability of “erroneous writing by reading” can be calculated more accurately than in the past using equation (3).

この場合、電流に依存する実効的なΔ（Ｉ）は以下の式で表される。

In a typical example of a storage layer currently in use, β is in the following order.

In this case, the effective Δ (I) depending on the current is expressed by the following equation.

  Thus, in the spin injection MRAM, the probability of “erroneous writing by reading” can be accurately calculated from the writing principle. Therefore, there is an advantage that the degree of data deterioration when read by an unauthorized user can be precisely controlled and set. Similarly, PRAM and ReRAM can cause “erroneous writing by reading”.

  Next, an embodiment of the present invention will be described.

(First embodiment)
FIG. 6 shows a recording / reproducing apparatus according to the first embodiment of the present invention. As shown in FIG. 6, the recording / reproducing apparatus of the present embodiment includes a variable resistance nonvolatile memory 40 and a user authentication circuit 60. The variable resistance nonvolatile memory 40 is, for example, a spin injection type MRAM, and a CMOS circuit (not shown) serving as a drive circuit is formed on a Si substrate, and an interlayer insulating film (not shown) is formed on the CMOS circuit. Thus, a memory cell array in which a plurality of memory cells are arranged in a matrix is formed. As shown in FIG. 1, each memory cell includes a resistance change element 10 and a selection transistor 20 connected in series to the resistance change element 10. In the present embodiment, the resistance change element 10 is the MTJ element 10 shown in FIGS. 2 (a) and 2 (b). The MTJ element 10 is manufactured by sputtering a lower electrode, an underlayer, a reference layer, a tunnel barrier layer, a recording layer, an upper electrode, and a wiring layer. In some cases, an antiferromagnetic layer is provided on the opposite side of the tunnel barrier layer from the reference layer in order to make the magnetization direction of the reference layer unchanged before and after energization. In the present embodiment, the variable resistance nonvolatile memory 40 is provided with a read current circuit 42.

The user authentication circuit 60 determines whether the user is a regular user or a non-regular user based on user information such as a password or a fingerprint. It is convenient to store user information in a resistance variable nonvolatile memory such as an MRAM. Based on the authentication result by the user authentication circuit 60, the read current of the memory cell output from the read current circuit 42 is controlled. For example, as shown in FIG. 7, the user authentication circuit 60 is provided with a selection circuit 62. Based on the authentication result of the user authentication circuit 60, the selection circuit 62 selects a load voltage V _LOAD and a clamp voltage V _CLMP described later of the read current circuit 42, and the user is a regular user or a non-regular user. A read current corresponding to this is passed through the memory cell.

A specific example of the read current circuit is shown in FIG. The read current circuit of this specific example includes a load pMOS transistor 43 whose source is connected to the power supply voltage V _DD and whose gate receives the load voltage V _LOAD , and whose drain is connected to the drain of the load pMOS transistor 43 and whose gate is the clamp voltage V _CLMP . And a clamp nMOS transistor 44 whose source is connected to one end (bit line BL) of the memory cell 41. By controlling the load voltage V _LOAD and the clamp voltage V _CLMP , the voltage of the bit line BL is controlled and the read current value is determined. In other words, the read current can be changed by controlling the load voltage _VLOAD and the clamp voltage _VCLMP . The switching circuit 62 switches the values of the load voltage V _LOAD and the clamp voltage V _CLMP to be different between the regular user and the non-regular user based on the authentication result of the user authentication circuit 60. For example, in the case of a non-regular user, by controlling the load voltage V _LOAD and the clamp voltage V _CLMP , the read current is increased to actively cause “erroneous writing by reading”. As a result, the digital data gradually deteriorates according to the number of readings. On the other hand, in the case of a regular user, the read current is set to be small so that the probability that magnetization reversal will occur once or less even after 10 ¹⁶ readings. As a result, digital data deterioration due to reading does not occur.

  A read circuit including read current circuits 45A and 45B and a sense amplifier 47 is shown in FIG. The read current circuit 45A includes a load pMOS transformer M11 and a clamp nMOS transistor M13 connected in series, and causes a read current to flow through the bit line BL connected to a selected memory cell from which data is to be read. The read current circuit 45B has a load pMOS transformer M12 and a clamp nMOS transistor M14 connected in series, and allows a read current to flow through the bit line connected to the reference cell.

On the other hand, the sense amplifier 47 includes pMOS transistors M1, M2, M5, M6, and Meq, and nMOS transistors M3, M4, M7, M9, and M10. In the pMOS transistors M5 and M6, the sources are connected to the power supply voltage V _DD , the gates are connected in common, and the drains are connected to the output terminals bOUT and OUT, respectively. Note that an inverted signal of the output terminal OUT is output from the output terminal bOUT. In the pMOS transistor Meq, the gate is connected to the gates of the pMOS transistors M5 and M6, one of the source and the drain is connected to the output terminal bOUT, and the other is connected to the output terminal OUT. The pMOS transistor M1, the nMOS transistor M3, and the nMOS transistor M9 are connected in series. The pMOS transistor M1 has a source connected to the power supply voltage _VDD , a drain connected to the output terminal bOUT, and a gate connected to the gate of the nMOS transistor M3 and the output terminal OUT. The nMOS transistor M3 has a drain connected to the output terminal bOUT and a source connected to the drain of the nMOS transistor M9. The nMOS transistor M9 has a gate connected to the drain of the load pMOS transistor M11 of the read current circuit 45A, and a source connected to the drain of the nMOS transistor M7. The nMOS transistor M7 receives the gate voltage SE1 of the pMOS transistors M5 and M6 at the gate, and the source is grounded.

The pMOS transistor M2, the nMOS transistor M4, and the nMOS transistor M10 are connected in series. The pMOS transistor M2 has a source connected to the power supply voltage _VDD , a drain connected to the output terminal OUT, and a gate connected to the gate of the nMOS transistor M4 and the output terminal bOUT. The nMOS transistor M4 has a drain connected to the output terminal OUT and a source connected to the drain of the nMOS transistor M10. The nMOS transistor M10 has a gate connected to the drain of the load pMOS transistor M12 of the read current circuit 45B, and a source connected to the drain of the nMOS transistor M7.

  In the readout circuit configured as described above, it is possible to read out whether the data stored in the memory cell of the variable resistance nonvolatile memory is “0” or “1”.

  As described above, according to the present embodiment, it is possible to suppress unauthorized use of an unauthorized user as much as possible without degrading digital data as much as possible when the authorized user uses it.

(Second Embodiment)
Next, a recording / reproducing apparatus according to the second embodiment of the present invention is shown in FIG. The recording / reproducing apparatus of this embodiment is the same as the recording / reproducing apparatus of the first embodiment shown in FIG. 7 except that the user authentication circuit 60 is provided with a variable resistance nonvolatile memory 66 for storing user information and the A circuit 48 and a rewrite circuit 49 are provided.

In the present embodiment, the selection circuit 62 selects parameters (the load voltage V _LOAD and the clamp voltage V _CLMP ) of the read current circuit 42 based on the authentication result authenticated by the user authentication circuit 60, and the ECC first Whether to perform the first stage and the second stage is also selected. The rewrite circuit 49 performs rewrite for correction in the memory cell array based on the error correction of the ECC circuit 48.

Hereinafter, a method for setting the read current in the case of the spin injection MRAM will be described in detail. In the case of a regular user, normally, the read current is set to be small so that the probability of magnetization reversal occurring once is 10 ¹⁶ times or less. In other words, when the read pulse width is 10 nsec, the read current I _read and the thermal disturbance parameter Δ _therm are designed so that p <10 ⁻¹⁶ at t = 10 nsec × 10 ¹⁶ = 10 ⁸ sec.

Depending on the magnitude of the read current, the probability of magnetization reversal due to “erroneous writing by reading” changes. FIG. 11 shows the dependence of the magnetization reversal probability on the number of readings. This fits well with formulas (3) to (10), which are new ways of finding the probability of “wrong writing by reading” found by the present inventors. The case shown here is when K _u V / k _B T = 80, f ₀ = 10 ⁹ Hz, and read pulse width = 10 nsec. When I _read / I _c is set to a small value of 0.1678, the probability of “erroneous writing due to reading” occurring even if reading is continued for 10 years is 1 bit or less per 1 Gbit as shown by the solid line in FIG. That is, there is virtually no data degradation. This memory operating state is provided to authorized users.

On the other hand, if I _read / I _c is set to a large value of 0.7, the sound quality and image quality are deteriorated by reading 3 to 10 times as shown by the broken line in FIG. This status is provided to non-regular users. In other words, it is possible to obtain information that is close to perfect at first, but if you try to enjoy it repeatedly, the quality will drop rapidly. If you want to enjoy quality digital content repeatedly, you need to become a regular user.

The advantage of this embodiment is that the digital content supply side can freely set how many times data is read out. For example, it is often desirable to allow a non-regular user to have a trial viewing only once. In this case, it is desirable to set so that 10% of data is lost by one reading. At this time, when there is no ECC, it is appropriate to set I _read / I _c ′ = 0.798. Here, I _c ′ is a current that causes magnetization reversal. In addition, non-regular users may be allowed to listen to their favorite music up to 1000 times. In this case, when there is no ECC, it is desirable to set so that 10% of data is lost after 1000 readings. In this case, setting I _read / I _c ′ = 0.6296 is just right. In practical use, between the two cases, that is, the case where 10% of data is lost by one reading and the case where 10% of data is lost by 1000 readings, it is used for non-regular users. It is desirable that I _read / I _c ′ be set to 0.63 or more and 0.8 or less. Here, I _c ′ is a magnetization reversal current. When the variation of the magnetization reversal current is sufficiently small between bits in the memory, for example, when the standard deviation is 1% or less of the average value, the average magnetization reversal current between bits. I _c ^average may be used. If the variation in the magnetization reversal current cannot be ignored, I _c ′ may be set as follows from the typical data capacity. Assume that the typical capacity of data is x bits. Consider y = 0.9 × x bits of memory. Of the y bits, the bit with the smallest magnetization reversal current is separated from the average magnetization reversal current I _c ^{average by} z × σ. Here, σ is a standard deviation and a unit of current. In this case, Ic ′ = I _c ^average −z × σ may be set. For example, in the case of music, the data capacity of a 6-minute song is about x = 50 Mbits. In this case, y = 45M bits and z = 5.49.

Further, in the present embodiment using the spin injection MRAM, I _read / I is divided into more hierarchies and is not divided into only two types of regular users and non-regular users as viewed from the digital content supply side. It is also possible to set _c ′. It can be divided into a user who allows trial viewing only once, a user who allows viewing up to 10 times with a small amount of money, and a user who allows viewing permanently with a large amount of money.

  On the other hand, FIG. 12 shows the probabilities of “erroneous writing due to reading” calculated by the equations (1) to (2) which have been conventionally known. The magnetization reversal probability is quite different from FIG. It can be seen that the conventional method cannot correctly evaluate the probability of “wrong writing by reading” and cannot provide an operation state suitable for an unauthorized user.

  Next, an example of how this recording / reproducing apparatus is actually used will be described.

  It is common to download music and video programs from the network for a fee and view them on a personal computer or mobile phone. In this case, the recording / reproducing apparatus according to the embodiment of the present invention is very useful. The second embodiment shown in FIG. 10 will be described as an example. The digital content is downloaded and stored in the resistance variable nonvolatile memory. The digital content contains password information that distinguishes regular users from non-regular users. In the case of a regular user who has paid a regular usage fee, a password is simultaneously distributed and stored in the resistance change type memory 66 for storing user information. If the distributed password information matches the password information in the digital content, the user is recognized as a legitimate user, the selection circuit 62 selects a legitimate user parameter, and a small read current is supplied from the read current circuit 42. Digital content can be enjoyed any number of times without data degradation due to "wrong writing".

  On the other hand, password information is not distributed to users who do not pay regular usage fees and only want to try and watch. As a result, the user authentication circuit 60 determines that the user is a non-regular user, the selection circuit 62 selects a parameter for the non-regular user, and a large read current flows from the read current circuit 42. Data degradation occurs.

  Another example is a case where the recording / reproducing apparatus of one embodiment of the present invention is used in a rental store. In the rental store, music and video programs are stored in advance in the resistance variable nonvolatile memory 40. When renting a user who pays a large amount of money and allows permanent viewing, a regular password is taught separately. If you take your recording / playback device home, set it in your viewing device, and enter your regular password, you can enjoy digital content as many times as you like without any data degradation due to “wrong writing by reading”. Instead of the password, fingerprint information or the like may be stored in the variable resistance nonvolatile memory 66 for storing user information. For users who pay a small amount and allow up to one viewing, do not give the password or give another password. As a result, at the time of reading, a large read current flows through the read current circuit 42, and data deterioration occurs every time reading is performed due to “wrong writing by reading”.

  For a legitimate user, it is effective to provide a protection circuit and a safety device so that data deterioration due to “erroneous writing by reading” does not occur.

  As described above, according to each embodiment of the present invention, it is possible to suppress unauthorized use of unauthorized users as much as possible without degrading digital data as much as possible when used by authorized users. Can be provided.

Schematic diagram of variable resistance nonvolatile memory cell The figure explaining the write principle of a spin injection magnetoresistive effect random accelerator memory. The figure explaining the read-out principle of a spin injection magnetoresistive effect random accelerator memory. The figure explaining the write-in principle of PRAM. The figure explaining the write-in principle of ReRAM. 1 is a block diagram showing a recording / reproducing apparatus according to a first embodiment of the present invention. 1 is a block diagram showing a specific configuration of a recording / reproducing apparatus according to a first embodiment. FIG. 3 is a circuit diagram showing a specific example of a read current circuit. FIG. 6 is a circuit diagram illustrating a specific example of a reading circuit. The block diagram which shows the recording / reproducing apparatus by 2nd Embodiment of this invention. The figure which shows the magnetization reversal probability depending on the frequency | count of reading in the recording / reproducing apparatus by one Embodiment of this invention. The figure which evaluated the magnetization reversal probability depending on the frequency | count of reading by the conventional method.

Explanation of symbols

10 Resistance change element (MTJ element)
12 reference layer 14 tunnel barrier layer 16 recording layer 20 selection transistor 40 variable resistance nonvolatile memory 41 memory cell 42 read current circuit 43 load pMOS transistor 44 clamp nMOS transistor 48 ECC circuit 60 user authentication circuit 62 selection circuit 66 resistance for user information storage Changeable non-volatile memory

Claims (4)

A variable resistance nonvolatile memory including a memory cell array in which memory cells having variable resistance elements that can be written by passing a current and changing resistance are arranged in a matrix;
A user authentication circuit for authenticating whether the user is a regular user or a non-regular user;
When the user authentication circuit is authenticated as the non-regular user, a read current circuit that causes the read current to flow through the memory cell with a larger read current than in the case of a regular user;
A recording / reproducing apparatus comprising: If the read current circuit is authenticated by the user authentication circuit, the read current flows so that the probability of magnetization reversal is 1 or less even after 10 ¹⁶ readings. The recording / reproducing apparatus according to claim 1. An error correction circuit that performs error correction of read information;
A rewrite circuit for performing rewrite for correction to the memory cell array based on error correction of the error correction circuit;
Further comprising
When the user authentication circuit authenticates the user, the error correction circuit performs error correction on the read information, and the rewrite circuit performs rewriting for correction based on the error correction. ,
3. The recording / reproducing according to claim 1, wherein when the user authentication circuit authenticates the user as an unauthorized user, at least one of error correction of the read information and rewriting for correction is not performed. apparatus.   4. The recording / reproducing apparatus according to claim 1, wherein the variable resistance element has a ferromagnetic tunnel junction.

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