JP4660632B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a memory device that stores information in a nonvolatile manner and has an error correction circuit.

  Depending on the type of the non-volatile storage device, the state of the physical quantity responsible for storing data changes with time. When the passage of time reaches a certain length, data may be lost. Various storage devices having such characteristics are included. As one of such memory devices, for example, there is a nonvolatile semiconductor memory device using a transistor having a so-called stacked gate structure as a memory cell.

  The stacked gate structure includes a tunnel insulating film, a floating gate electrode, an interelectrode insulating film, and a control gate electrode that are sequentially stacked on the substrate. In order to store information in the memory cell, electrons are injected from the substrate into the floating gate electrode through the tunnel insulating film. Information is held by the charges accumulated in the floating gate electrode. The electric charge accumulated in the floating gate electrode leaks to the substrate through the tunnel insulating film as time passes. For this reason, as time passes, information held in the memory cell may be lost (an error may occur in the information).

  If the passage of time from the time when the information is stored is short, the possibility that the information has an error is low. On the other hand, if the time has passed since the information was stored, there is a high possibility that the information has an error. In such a memory device having a plurality of memory cells, an error correction mechanism for correctly restoring erroneous information may be provided.

  In general, a correction mechanism with high error correction capability is required to correct errors even when there are many errors in the data consisting of multiple bits due to the fact that time has passed since the recording of information. is there. A correction mechanism having high error correction capability has a large circuit scale, large power consumption, and requires time for processing. Usually, a correction mechanism having a high error correction capability is provided in order to ensure that correct information can be restored even after a long time has elapsed since the information was stored. A high-performance error correction mechanism is applied uniformly regardless of the length of time elapsed since the information was stored.

  For this reason, such a high-performance error correction mechanism is also used when reading information for which only a short time has elapsed since storage. As a result, a high-performance error correction mechanism is uselessly used in spite of reading information that does not include so many errors. This leads to wasteful consumption of the power consumption of the storage device.

  Furthermore, in general, in order to increase the error correction capability, it is required to increase the information to be corrected. For example, instead of generating an error correction code for 512-byte data, an error correction code is generated using, for example, 4 kbytes of data obtained by concatenating a plurality of 512-byte data as one unit. By doing so, the error correction capability can be enhanced. However, this method leads to the fact that, for example, 4 kbytes of data must be read although 512 bytes of data are to be read. This also forces the storage device to consume useless power.

  Prior art document information related to the invention of this application includes the following.

JP-A-63-275225

  It is an object of the present invention to provide a semiconductor memory device in which power consumption and circuit scale are suppressed without impairing error correction capability.

  A semiconductor memory device according to an aspect of the present invention includes a detection code generation unit that generates a plurality of detection codes for detecting errors in a plurality of first data, each first data, and a corresponding detection code. The first unit data is composed of a first correction code generation unit that generates a plurality of first correction codes for correcting errors in the plurality of first unit data, and A second correction code generating unit configured to generate a second correction code for correcting an error in the second unit data, the second unit data, the plurality of first correction codes, and A semiconductor memory for storing the second correction code in a nonvolatile manner, a first correction unit for correcting an error in the plurality of first unit data using the plurality of first correction codes, and the plurality of detection codes Using the above A detection unit that detects errors in the plurality of first data corrected by the correction unit, and generates first error information indicating presence / absence of errors for each of the plurality of corrected first data; A second correction unit that performs a chain search on the one of the plurality of corrected first data including an error using the first error information and the second correction code, and corrects the error; The error correction capability of the second correction code is higher than the error correction capability of the first correction code.

  According to the present invention, it is possible to provide a semiconductor memory device in which power consumption and circuit scale are suppressed without impairing error correction capability.

1 is a block diagram schematically showing a semiconductor memory device according to an embodiment of the present invention. The block diagram which shows the principal part regarding the data writing of an error correction circuit. The figure which shows the state of the data in the temporary memory circuit 3 at the time of writing. The figure which shows the state following FIG. The figure which shows the state following FIG. The block diagram which shows the principal part regarding the data reading of an error correction circuit. The figure which shows an example of operation | movement in a 2nd error correction part. The figure which shows the relationship between the elapsed time from writing and required correction capability. The figure which shows the concept of assignment of the range in charge of the 1st error correction part 11 and the 2nd error correction part 13. FIG. The figure which shows the relationship between an error rate and the utilization probability of a 2nd error correction part. The figure which shows the relationship between an error rate and the average chain search by a 2nd error correction part.

  Embodiments of the present invention will be described below with reference to the drawings. In the following description, components having substantially the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

  In addition, each embodiment shown below exemplifies an apparatus and a method for embodying the technical idea of the present invention, and the technical idea of the present invention includes the material, shape, structure, The layout is not specified as follows. The technical idea of the present invention can be variously modified within the scope of the claims.

  Each functional block in each embodiment of the present invention can be realized as either hardware, computer software, or a combination of both. For this reason, each block is generally described below in terms of their functionality so that it is clear that they are any of these. Whether such functionality is implemented as hardware or software depends upon the specific implementation or design constraints imposed on the overall system. Those skilled in the art can implement these functions in various ways for each specific embodiment, and determining such implementation is within the scope of the invention.

  FIG. 1 is a block diagram schematically showing a semiconductor memory device according to an embodiment of the present invention.

  As shown in FIG. 1, the semiconductor memory device 10 includes an error correction circuit 1 and a semiconductor memory 2. The error correction circuit 1 and the semiconductor memory 2 are provided on one semiconductor chip as one semiconductor integrated circuit, for example. The semiconductor memory 2 may be any storage device as long as it stores information in a nonvolatile manner and the stored data has characteristics that can cause changes. An example of such a semiconductor memory 2 is a NAND flash memory.

  The NAND flash memory has a plurality of memory cells. Each memory cell is composed of a so-called stacked gate structure type MOSFET (metal oxide semiconductor field effect transistor). A MOS transistor having a stacked gate structure includes a tunnel insulating film, a floating gate electrode, an interelectrode insulating film, a control gate electrode, and a source / drain diffusion layer. Each memory cell transistor changes the threshold voltage according to the number of electrons stored in the floating gate electrode, and stores information corresponding to the difference in the threshold voltage. The memory cell transistor may be configured to store 1-bit information or may be configured to store multiple bits of information. Then, the control circuit including the sense amplifier and the potential generation circuit in the semiconductor memory 2 writes the data supplied to the semiconductor memory 2 to the memory cell transistor, and stores the data stored in the memory cell transistor in the semiconductor memory 2. It has a configuration capable of outputting to the outside.

  Control gate electrodes of memory cell transistors belonging to the same row are connected to the same word line. Select gate transistors are provided at both ends of memory cell transistors belonging to the same column and connected in series. One select gate transistor is connected to the bit line. In accordance with this rule, a memory cell transistor, a select gate transistor, a word line, and a bit line are provided. Data writing and reading are performed for each set of a plurality of memory cell transistors, and a storage area including the set of memory cell transistors corresponds to one page. A block is composed of a plurality of pages. The NAND flash memory erases data in units of blocks.

  Data (write data) requested to be written to the semiconductor memory 2 from the outside is supplied to the semiconductor memory device 10. The error correction circuit 1 adds an error correction code and an error detection code to the write data and supplies them to the semiconductor memory 2. The semiconductor memory 2 stores write data to which an error correction code and an error detection code are added.

  Further, the semiconductor memory 12 performs error correction on the data (read data) requested to be read and the error correction code and error detection code added thereto in response to a control signal supplied to the semiconductor memory device 10. Supply to circuit 1. The error correction circuit 1 detects and corrects errors in read data. If an error exists, it is corrected, the error correction code and the error detection code are removed, and the read data is output to the outside.

[Configuration of write circuit]
FIG. 2 is a block diagram showing a main part related to data writing of the error correction circuit 1. The error correction circuit 1 generates an error correction code with each of a plurality of write data of a predetermined size as one unit, and generates another error correction code with the plurality of write data as one unit. To do. The number of write data is determined according to the error correction capability desired to be achieved and the error correction code employed, and an example in which there are eight write data will be described below.

  As shown in FIG. 2, the error correction circuit 1 is supplied with write data Da1, Da2, Da3, Da4, Da5, Da6, Da7, Da8. The first unit size can be made to coincide with the unit size of write and read data by the semiconductor memory 2, for example. More specifically, when a NAND flash memory is used as the semiconductor memory 2, the size of the write data corresponds to the size of one page and is, for example, 512 bytes. Hereinafter, for convenience of explanation, a case where the first unit size is 512 bytes is used as an example.

  The error correction circuit 1 has a temporary storage circuit 3. The temporary storage circuit 3 includes, for example, a volatile storage circuit, and can be a dynamic random access memory (DRAM), for example. The temporary storage circuit 3 has a function as a temporary storage area when generating an error detection code and an error correction code for data written to the semiconductor memory 2 at the time of writing. The temporary storage circuit 3 is supplied with write data Da1 to Da8 at the time of writing. The temporary storage circuit 3 stores write data Da1 to Da8.

  Write data Da1, Da2, Da3, Da4, Da5, Da6, Da7, Da8 are respectively supplied to error detection code generators 41, 42, 43, 44, 45, 46, 47, 48 (only a part is shown). The

  The error detection code generation units 41, 42, 43, 44, 45, 46, 47, and 48 are error detection codes (data) Db1 for the write data Da1, Da2, Da3, Da4, Da5, Da6, Da7, Da8, respectively. , Db2, Db3, Db4, Db5, Db6, Db7, Db8. The error detection codes Db1 to Db8 are used to detect errors in the write data Da1 to Da8, respectively. As the error detection codes Db1 to Db8, those that achieve this purpose, have a simple code calculation, and consume less power of the error detection code generation unit 12 are used. For example, CRC (cyclic redundancy checksum) 32, CRC 16 or the like can be used as the error detection code. The error detection codes Db1 to Db8 are supplied to the temporary storage circuit 3.

  The error detection codes Db1, Db2, Db3, Db4, Db5, Db6, Db7, and Db8 are supplied to the first error correction code generation units 61, 62, 63, 64, 65, 66, 67, and 68, respectively. . Further, write data Da1 to Da8 are supplied to the first error correction code generators 61 to 68, respectively.

  The first error correction code generators 61 to 68 generate first error correction codes using the write data Da1 to Da8 and the error detection codes Db1 to Db8, respectively. The first error correction code generated by the first error correction code generation unit 61 is used to correct errors in the write data Da1 and the error detection code data Db1. Similarly, the first error correction codes generated by the first error correction code generators 62 to 68 are used to correct errors in the write data Da2 to Da8 and the error detection code data Db2 to Db8, respectively. .

  As the first error correction code, the correction capability is not so high, for example, about 1-bit error correction capability, but does not require high power and long time for calculation, and the scale of the circuit used for execution is Smaller ones can be used. More specifically, for example, a Hamming code or the like can be used as the first error correction code.

  The first error correction code generators 61 to 68 output first error correction codes (data) Dc1, Dc2, Dc3, Dc4, Dc5, Dc6, Dc7, and Dc8, respectively. The first error correction codes Dc1 to Dc8 are supplied to the temporary storage circuit 3.

  The error detection codes Db1 to Db8 are supplied to the second error correction code generation unit 8. The second error correction code generation unit 8 is also supplied with write data Da1 to Da8. The second error correction code generation unit 8 generates a second error correction code using the write data Da1 to Da8 and the error detection code data Db1 to Db8. The second error correction code is used to correct errors in the write data Da1 to Da8 and the error detection codes Db1 to Db8.

  As the second error correction code, for example, a code capable of correcting an error with a higher capability than an error correction using the first error correction code, which has a large calculation amount but can correct a multi-bit error, is used. More specifically, for example, a BCH code, a Reed-Solomon (RS) code, an LDPC code (low density parity check code), or the like can be used as the second error correction code. Since the second error correction code generation unit 8 has a large calculation amount, the circuit scale, power consumption, and calculation time are larger than those of the first error correction code generation units 61 to 68, but the first error correction code generation unit 61 The error correction capability is higher than 68.

  The second error correction code generator 8 supplies the second error correction code (data) Dd to the temporary storage circuit 3. Further, the temporary storage circuit 3 stores write data Da1 to Da8, error detection codes Db1 to Db8, first error detection codes Dc1 to Dc8, and second error detection code Dd in the semiconductor memory 2 having a structure as described below. Supply.

[Operation when writing data]
Next, the operation of the error correction circuit 1 during data writing will be described with reference to FIGS. 3 to 6 schematically show the state of data in the temporary storage circuit 3 at the time of writing.

  First, as shown in FIG. 3, eight pieces of write data Da1 to Da8 to be written into the semiconductor memory 2 are supplied to the error correction circuit 1. The write data Da1 to Da8 are stored in the temporary storage circuit 3.

  Next, as shown in FIG. 4, the write data Da1 to Da8 are supplied to the error detection code generators 41 to 48, respectively. The error detection code generation units 41 to 48 generate error detection codes Db1 to Db8 for the write data Da1 to Da8, respectively. When CRC32 is used as the error detection code, the size of each error detection code Db1 to Db8 is 32 bits.

  The write data Da1 and the error detection code Db1 connected behind the write data Da1 constitute first unit data D1 constituting an error correction unit. Similarly, the first unit data D2 to D8 are constituted by the write data Da2 to Da8 and the error detection codes Db2 to Db8 connected to the back of each. The first unit data D1 to D8 are stored in the temporary storage circuit 3. The detailed configuration of the error detection code generators 41 to 48 is known to those skilled in the art, and a description thereof is omitted here. In the present embodiment, the error detection code generation units 41 to 48 perform detection code generation operations in parallel. Thus, the processing time can be shortened by operating the error detection code generation units 41 to 48 in parallel.

  Next, as shown in FIG. 5, the first unit data D1 to D8 are supplied to the first error correction code generators 61 to 68, respectively. The first error correction code generator 61 uses the first unit data D1 to generate a first error correction code Dc1 for correcting an error in the first unit data D1. The first error correction code Dc1 is stored in the temporary storage circuit 3 in a form concatenated after the error detection code Db1 and before the write data Da2.

  Similarly, the first error correction code generators 62 to 68 use the first unit data D2 to D8 to correct the errors of the first unit data D2 to D8, respectively. Is generated. The first error correction code Dc2 is stored in the temporary storage circuit 3 in a form concatenated after the error detection code Db2 and before the write data Da3. Similarly, the first error correction codes Dc3 to Dc7 are connected after the error detection codes Db3 to Db7 and before the write data Da4 to Da8, and the first error correction code Dc8 is connected after the error detection code Db8. And stored in the temporary storage circuit 3.

  When a Hamming code is used as the first error correction code, each of the first unit data D1 to D8 has a size consisting of 4096 bits of each write data + 32 bits of an error detection code. In order to perform 1-bit error correction in each of the first unit data D1 to D8, the size of each of the first error correction codes Db1 to Db8 is, for example, 13 bits. The detailed configuration of the first error correction code generators 61 to 68 is known to those skilled in the art and will not be described here. In the present embodiment, the first error correction code generation units 61 to 68 perform correction code generation operations in parallel. Thus, the processing time can be shortened by operating the first error correction code generation units 61 to 68 in parallel.

  The first unit data D1 to D8 are concatenated in order to form second unit data, and the second unit data is supplied to the second error correction code generation unit 8. The second unit data is a unit of data used when the second error correction code generation unit generates the second error correction code. The second error correction code generation unit 8 generates a second error correction code Dd for correcting an error in the second unit data using the second unit data. The second error correction code Dd is stored in the temporary storage circuit 3 in a form concatenated after the second unit data.

  When the RS code is used as the second error correction code, the second unit data has a size of 4096 bits of write data × 8 + 32 bits of error detection code × 8, and 12 bits in the second unit data. Correct the error. In order to correct the error of the second unit data having such a size, the size of the second error correction code Dd is, for example, 192 bits. A detailed configuration of the second error correction code generation unit 8 is known to those skilled in the art, and a description thereof is omitted here.

  Through the steps so far, the second error correction code Dd is connected after the second unit data, so that transfer unit data (configuration in the temporary storage circuit 3 in FIG. 5) is obtained. The transfer unit data is supplied to the semiconductor memory 2. The semiconductor memory 2 performs a process of storing data for each transfer unit data.

[Configuration of readout circuit]
FIG. 6 is a block diagram showing a main part related to data reading of the error correction circuit 1.

  As shown in FIG. 6, the signal S <b> 1 is supplied from the semiconductor memory 2 to the first error correction unit 11. The signal S1 is composed of transfer unit data (configuration in the temporary storage circuit 3 in FIG. 5).

  When there is an error in the first unit data D1 to D8, the first error correction unit 11 uses the first error correction codes Dc1 to Dc8 in the signal S1, and falls within the capability range of the first error correction unit 11. Thus, the errors in the first unit data D1 to D8 are respectively corrected. That is, the first error correction unit 11 corrects an error in the first unit data D1 using the first error correction code Dc1. Similarly, the first error correction unit 11 corrects errors in the first unit data D2 to D8 using the error correction codes Dc2 to Dc8 within the capability of the first error correction unit 11, respectively.

  Thus, the first error correction unit 11 outputs the signal S2 in a form in which the error correction using the first error correction code is performed on the signal S1. If the number of error bits in each of the first unit data D1 to D8 before error correction is equal to or less than the error correction capability of the first error correction unit 11, the first unit data D1 to D8 after error correction in the signal S2 There are no errors in it. On the other hand, if the number of error bits in each of the first unit data D1 to D8 before error correction exceeds the error correction capability of the first error correction unit 11, the first unit data after error correction in the signal S2. Errors are included in D1 to D8.

  The signal S2 is supplied to the error detection unit 12 and the second error correction unit 13. The error detection unit 12 detects errors in the write data Da1 to Da8 using the error detection codes Db1 to Db8, respectively. Then, the error detection unit 12 supplies the signal S2 to the selection unit 14 as it is. Further, the error detection unit 12 supplies the selection unit 14 with a signal S3 indicating whether no error has been detected in all the first unit data D1 to D8 or whether an error has been detected. Further, the error detection unit 12 supplies the second error correction unit 13 with a signal S4 including information on which of the first unit data D1 to D8 has detected an error in addition to whether or not an error has been detected. .

  The second error correction unit 13 analyzes the signal S4 to know whether or not an error has been detected as a result of error detection by the error detection unit 12. If no error is detected, no further error correction is required. For example, the second error correction unit 13 stops power supply from a power supply circuit (not shown) or a clock circuit (not shown). The operation of the signal S2 to be processed is stopped, for example, by stopping the supply of the clock signal from.

  On the other hand, when the second error correction unit 13 learns from the analysis of the signal S4 that an error has been detected in the signal S2, the second error correction unit 13 uses the second error correction code Dd to generate the first unit data D1 to D8. Correct the error in At this time, the second error correction unit 13 performs error correction only on the first unit data D1 to D8 including an error, using the information in the signal S4. An example of this is shown in FIG.

  FIG. 7 shows an example in which an error is detected in the first unit data D2, D4, D5. The second error correction unit 13 targets all of the first unit data D1 to D8 for the calculation of the syndrome using the second error correction code Dd. On the other hand, the second error correction unit 13 targets only the first unit data D2, D4, and D5 in which an error is detected for the Chien Search. The second error correction unit 13 corrects errors in the first unit data D2, D4, and D5 using the second error correction code Dd. The second error correction unit 13 outputs a signal S5 in a form in which error correction is performed on the signal S2 using the second error correction code.

  The error correction in the second error correction unit 13 is sequentially performed on the first unit data D1 to D8 in which an error is detected, unlike the conventional case. That is, no error correction circuit dedicated to each of the first unit data D1 to D8 is provided. By doing so, the circuit scale and power consumption of the second error correction unit 13 can be reduced.

  On the other hand, depending on the number of first unit data to be error-corrected, more time is required than when error correction is performed in parallel by providing a circuit dedicated to the first unit data D1 to D8. However, in the present embodiment, the second error correction unit 13 performs a chain search only for the first unit data D1 to D8 in which an error is detected. In addition, as will be described later, the first error correction code can correct most of the errors in the first unit data D1 to D8 (ratio close to 100%) only by correction using the first error correction code. Designed as such. For this reason, the case of using the second error correction code is rare. Therefore, in the present embodiment, by sharing the error correction circuit for the first unit data D1 to D8, the circuit scale and power consumption of the second error correction unit 13 can be reduced without increasing the processing time.

  In addition, for example, in a process in which certain transfer unit data is repeatedly read from the storage device, it is assumed that the error detection unit 12 does not detect an error in the transfer unit data at the first reading of the transfer unit data. In such a case, at the time of reading the transfer unit data for the second and subsequent times, at least one of power supply and clock signal supply to the second error correction unit 13 is stopped in advance. As a result, when the same transfer unit data is read in this way, the power consumption in the error correction circuit 1 is greatly reduced.

  Next, how to determine the correction capability of the first error correction unit 11 and the second error correction unit 13 will be described. Note that the correction capability of the first error correction unit 11 includes processing in which the first error correction code generation units 61 to 68 generate the first error correction codes Dc1 to Dc8. Similarly, the correction capability of the second error correction unit 13 includes a process in which the second error correction code generation unit 8 generates the second error correction code Dd.

  FIG. 8 is a diagram showing the relationship between the elapsed time after writing data in the semiconductor memory 2 and the required correction capability. As shown in FIG. 8, when the elapsed time becomes longer, the number of errors in the data written in the semiconductor memory 2 increases. Therefore, the error correction capability is changed as the number of errors increases. Then, the error correction capabilities of the first error correction unit 11 and the second error correction unit 13 are determined so that excessive or insufficient error correction capability is not used. Specifically, while the elapsed time is short, the error correction can be performed only by the first error correction unit 11 and the first error correction is performed after the elapsed time has passed a predetermined time (the time when the number of errors increases rapidly). The error correction capability of the first error correction unit 11 and the second error correction unit 13 is determined so that the error can be corrected by the unit 11 and the second error correction unit 13.

  FIG. 9 shows the concept of assignment of the assigned range of the first error correction unit 11 and the second error correction unit 13 of the present embodiment. The horizontal axis of FIG. 9 indicates the number of errors per predetermined range (a page in the NAND flash memory) of the semiconductor memory 2. The vertical axis indicates the error occurrence probability. A broken line indicates a relationship before the semiconductor memory 2 is deteriorated (immediately after data writing). On the other hand, the solid line shows the relationship after the semiconductor memory 2 is deteriorated (after the compensated data retention time has elapsed).

  As shown in FIG. 9, in the range where the number of errors per predetermined range is small, the error correction capability of the first error correction unit 11 is determined so that all errors are corrected only by the first error correction unit 11. . Specifically, the number of correctable bits, the error correction method, the number of bits of the error correction code, and the like are determined. For example, the error correction capability of the first error correction unit 11 is determined so that the first error correction unit 11 can correct approximately 100% error before the deterioration and about 99% error after deterioration. On the other hand, the error correction capability of the second error correction unit 13 is determined so that the remaining error of about 1% can be corrected after deterioration.

  As a result, as shown in FIG. 10, the use probability of the second error correction unit 13 increases as the error rate increases.

  As described above, the first error correction unit 11 with small error correction capability but low processing time and power consumption is responsible for almost all error correction, and second error correction with high processing time and power consumption but high error correction capability. Part 13 is responsible for correcting the remaining errors. For this reason, the error correction circuit 1 can have a short processing time, low power consumption, and a small circuit scale while maintaining a high level of error correction capability.

  FIG. 11 shows the relationship between the error rate and the average chain search range by the second error correction unit 13. In the present embodiment (solid line), as described above, the error correction capability of the first error correction unit 11 is set so that errors in most cases can be corrected only by the first error correction unit 11. For this reason, compared with the conventional case (broken line), even if the error rate is high, the second error correction unit 13 is less involved in error correction.

  As described above, according to the semiconductor memory device according to the embodiment, the plurality of first unit data D1 to D8 each including one of the plurality of write data are configured, and the plurality of first unit data D1 to D8 are configured. A plurality of first error correction codes Dc1 to Dc8 are respectively generated for D8, and a second error correction code Dd is generated for the second unit data composed of the plurality of first unit data D1 to D8. When the number of error bits is small, correction is performed using the first error correction codes Dc1 to Dc8 that have low capacity but low power consumption and a small circuit size, and when the number of error bits is large, Correction is performed by using both the second error correction code Dd and the first error correction codes Dc1 to Dc8 that are consumed and require a large circuit scale but can be corrected with high performance. Therefore, a semiconductor memory device in which the circuit scale and power consumption of the error correction circuit 1 are optimized and the error correction time is short is provided without impairing the error correction capability.

  In the present embodiment, the second error correction code Dd is applied only to the first unit data D1 to D8 including errors even after error correction is performed using the first error correction codes Db1 to Db8. The used error correction is performed. For this reason, the scale of the second error correction unit 13 is significantly smaller than an example in which a circuit that performs error correction using the second error correction code Dd is provided in each of the plurality of first unit data D1 to D8.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

  DESCRIPTION OF SYMBOLS 1 ... Error correction circuit, 2 ... Semiconductor memory, 3 ... Temporary memory circuit, 10 ... Semiconductor memory device, 41 thru | or 48 ... Error detection code generation part, 61 thru | or 68 ... 1st error correction code generation part, 8 ... 2nd error Correction code generation unit, Da1 to Da8 ... write data, Db1 to Db8 ... error detection code, Dc1 to Dc8 ... first error correction code, Dd ... second error correction code, 11 ... first error correction unit, 12 ... error detection Part, 13 ... second error correction part, 14 ... selection part.

Claims (3)

A detection code generator for generating a plurality of detection codes for detecting errors in the plurality of first data,
First correction code generation for generating a plurality of first correction codes for correcting respective errors in the plurality of first unit data, wherein the first unit data is composed of each first data and the corresponding detection code. And
A second correction code generating unit configured to generate a second correction code for correcting an error in the second unit data, the second unit data being composed of the plurality of first unit data;
A semiconductor memory for storing the second unit data, the plurality of first correction codes, and the second correction code in a nonvolatile manner;
A first correction unit that corrects each error in the plurality of first unit data using the plurality of first correction codes;
The plurality of detection codes are used to detect errors in the plurality of first data corrected by the first correction unit, and indicate the presence / absence of errors in each of the corrected plurality of first data A detector that generates first error information;
Using the first error information and the second correction code, a second correction unit that performs a chain search on the corrected first data including an error and corrects the error;
Comprising
The semiconductor memory device characterized in that the error correction capability of the second correction code is higher than the error correction capability of the first correction code. 2. The semiconductor memory device according to claim 1, wherein the second correction unit stops correction processing when there is no error in the plurality of first data corrected by the first correction unit. The semiconductor memory device according to claim 1, wherein the semiconductor memory is a NAND flash memory.

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