JP4660251B2 - Input circuit - Google Patents

Description

  The present invention relates to an input circuit mounted on an integrated circuit (IC) to which an input signal having a potential equal to or higher than a power supply potential is input.

  For the purpose of reducing power consumption, the voltage of the high-level power supply (VDD) of the IC has been lowered, and an input circuit capable of dealing with an input signal having an amplitude greater than the power supply potential of the IC has been required. When a signal having an amplitude greater than or equal to the power supply potential is input to an input circuit mounted on the IC, a circuit configuration that can handle an amplitude greater than or equal to a withstand voltage defined in the IC manufacturing process is required. An input circuit including an n-type channel MOS transistor for potential drop (hereinafter referred to as an “nMOS transistor”) is known as an input circuit that can handle an input signal having an amplitude greater than or equal to a power supply potential (for example, a patent) Reference 1). That is, the input signal is input to the drain of the nMOS transistor, is limited (clamped) to a potential corresponding to the gate potential, and is output from the source. In this case, the potential of the high potential power supply (VDD) is supplied to the gate of the nMOS transistor. Therefore, the gate-drain potential Vgd of the nMOS transistor to which the input signal is input is at most the potential difference between the high-level potential of the input signal and the potential of the high-level power supply, and therefore the operation within the range of the gate breakdown voltage of the nMOS transistor. Is possible.

However, in order to suppress standby power, a method of stopping the power supply to the IC while the power of the entire device on which the IC is mounted is turned on has begun to be used. In this case, a signal is input to the IC whose power supply is stopped. When the power supply is stopped, the gate potential of the nMOS transistor described above becomes 0 [V]. Therefore, there is a possibility that the gate-drain potential Vgd of the nMOS transistor does not fall within the range of the gate breakdown voltage of the nMOS transistor, causing a problem in IC reliability.
JP-A-10-135818

  The present invention provides an input circuit that can maintain high reliability with respect to an input signal having an amplitude greater than or equal to the power supply potential both when the power is supplied and when the power is stopped.

  One embodiment of the present invention includes a potential generation circuit that detects an input signal and generates a potential, a potential selection circuit that selects a potential from a high-level power supply when power is supplied, and selects a potential from the potential generation circuit when the power is stopped; The gist of the present invention is that the input circuit includes a limiting circuit that limits the potential of the input signal according to the potential selected by the potential selection circuit.

  According to the present invention, it is possible to provide an input circuit that can maintain high reliability with respect to an input signal having an amplitude greater than or equal to the power supply potential both when the power is supplied and when the power is stopped.

  Next, embodiments will be described with reference to the drawings. In the following description of the drawings in the first and second embodiments, the same or similar parts are denoted by the same or similar reference numerals.

(First embodiment)
An integrated circuit (IC) 10 according to the first embodiment of the present invention is connected to, for example, an external bus 20 as shown in FIG. The IC 10 includes an input circuit 11a connected to the input terminal 30 and an internal circuit 12 connected to the input circuit 11a. As the internal circuit 12, for example, a signal processing circuit such as a video signal processing circuit or an audio signal processing circuit can be used. The input circuit 11a includes a potential generation circuit 1a, a potential selection circuit 2a, a limiting circuit 4, and a buffer circuit 3a. The potential generation circuit 1a detects the input signal Vin and generates a potential Vgen. The potential selection circuit 2a selects the potential from the high-level power supply VDD when power is supplied, and selects the potential Vgen from the potential generation circuit 1a when the power is stopped. Here, “when the power supply is stopped” means that the supply of the high-level power supply VDD to the IC 10 is stopped in a state where the power supply of the entire device on which the IC 10 is mounted is turned on for the purpose of suppressing standby power. Therefore, the state where the power supply of the entire device on which the IC 10 is mounted is not turned on is not included. The limiting circuit 4 limits the potential of the input signal Vin according to the potential selected by the potential selection circuit 2a. The buffer circuit 3a includes two stages of inverters 31 and 32, and shapes the output signal of the limiting circuit 4 into a waveform. A protective circuit for protecting the input circuit 11a and the internal circuit 12 from a surge potential applied to the input terminal 30 may be provided between the input terminal 30 and the input circuit 11a.

The limiting circuit 4 includes a potential limiting transistor MN1 having a drain connected to the input node n ₁ for transmitting the input signal Vin from the input terminal 30, a gate connected to the potential selecting circuit 2a, and a source connected to the buffer circuit 3a. Prepare. For example, an nMOS transistor can be used as the potential limiting transistor MN1.

The input signal Vin having an amplitude equal to or higher than the power supply potential of the high-level power supply VDD is input to the IC 10 from a controller or an analog circuit (not shown) connected to the external bus 20 both when the power is supplied to the IC 10 and when the power is stopped. Input to terminal 30.
The input signal Vin input from the external bus 20 via the input terminal 30 is input to the drain of the potential limiting transistor MN1, and is limited (clamped) to a potential corresponding to the gate potential Vg and output from the source. The source potential Vs of the potential limiting transistor MN1 is limited to the gate potential Vg or less.

When power is supplied to the IC 10, the potential from the high potential power supply VDD is supplied to the gate of the potential limiting transistor MN1. Specifically, when the high power supply potential is VDD, the source potential of the potential limiting transistor MN1 is Vs, the gate potential is Vg, and the threshold voltage is VThN,

Vs = VDD- (VthN + a) (1)

Holds. In equation (1), the symbol “a” is a constant depending on the process.

  Therefore, even if the amplitude (potential) of the input signal Vin is equal to or higher than the high-level power supply VDD, the amplitude of the input signal Vin is attenuated by the threshold voltage VTh of the potential limiting transistor MN1 by the potential limiting transistor MN1, and the subsequent buffer circuit 3a The waveform is shaped and output. Therefore, even when the amplitude of the input signal Vin is equal to or higher than the high-level power supply VDD, the buffer circuit 3a can be prevented from being destroyed.

On the other hand, when the power of the IC 10 is stopped, the potential Vgen from the potential generation circuit 1a is supplied to the gate of the potential limiting transistor MN1. Assuming that the potential from the potential generation circuit 1a is Vgen, the source potential of the potential limiting transistor MN1 is Vs, the gate potential is Vg, and the threshold voltage is VThN,

Vs = Vgen- (VthN + a) (2)

Holds. In the following description, for convenience of explanation, explanation will be made without considering the constant “a” depending on the process.

  When the power supply is stopped, the potential Vgen generated by the potential generation circuit 1a is supplied to the gate of the potential limiting transistor MN1, so that the gate-drain potential Vgd of the potential limiting transistor MN1 becomes the gate breakdown voltage of the potential limiting transistor MN1. Can be prevented.

  In the buffer circuit 3a, the output signal of the inverter 31 is an inverted signal of the source potential Vs of the potential limiting transistor MN1. Since the inverter 32 further inverts the output signal of the inverter 31, the output signal Vout of the inverter 32 is a signal in phase with the input signal Vin and the source potential Vs of the potential limiting transistor MN1.

  Further, as shown in FIG. 2, the potential selection circuit 2a automatically selects either the high-level power supply VDD or the potential Vgen generated by the potential generation circuit 1a. As a result, the gate potential Vg of the potential limiting transistor MN1 is set to the potential of the higher power supply VDD when the power is supplied, and is set to the potential Vgen when the power is stopped.

  The potential generation circuit 1a generates the potential Vgen from the high level potential VinH of the input signal Vin. As described above, the value of the potential Vgen is not related to the normal operation of the input circuit 11a, and is not when the power is stopped (high-level power supply). Used for the purpose of maintaining the reliability of VDD: OFF).

For this reason, the potential Vgen need only be lower than the maximum value (maximum potential that does not cause a problem as a reliability) Vmax of the IC 10 and higher than the high level potential VinH−Vmax of the input signal Vin, and accuracy is not particular. That is, when the maximum value of the allowable potential of the IC 10 is Vmax and the high level potential of the input signal Vin is VinH, the potential Vgen is

(VinH-Vmax) <Vgen <Vmax (3)

Holds.

Potential generation circuit 1a, as shown in FIG. 3, comprises a first resistor R1 and second resistor R2 connected in series between the input node n ₁ and the low potential power supply VSS. Although FIG. 3 shows an example in which the potential generation circuit 1a includes two resistors, that is, the first resistor R1 and the second resistor R2, three or more resistors may be used. In addition, not only when a resistance element is used as a resistor, for example, a wiring resistance or an on-resistance of a transistor may be used.

  The first resistor R1 and the second resistor R2 divide the potential of the input signal Vin to generate a potential Vgen. The resistance ratio between the first resistor R1 and the second resistor R2 is designed so as to satisfy the condition of Expression (3).

  Further, the potential selection circuit 2a includes a first switch circuit SW1, a second switch circuit SW2, and a switching control circuit 21a. The first switch circuit SW1 switches whether to supply the potential from the high-level power supply VDD to the limiting circuit 4. The second switch circuit SW2 switches whether to supply the potential Vgen from the potential generation circuit 1a to the limiting circuit 4.

  As shown in FIG. 4, the switching control circuit 21a turns on and off the first and second switch circuits SW1 and SW2 when power is supplied, and turns off the first and second switch circuits SW1 and SW2 when power is stopped. Conduction and conduction. As a result, the gate potential Vg of the potential limiting transistor MN1 is set to either the potential of the high potential power supply VDD or the potential Vgen.

  The switching control circuit 21a includes a first inverter 211 and a second inverter 212 as shown in FIG. The first inverter 211 and the second inverter 212 utilize the fact that the high-level power supply VDD is at the high level when the power is supplied and the high-level power supply VDD is at the low level when the power is stopped. SW2 switching is controlled.

  The first inverter 211 operates between the potential from the potential generation circuit 1a and the potential from the low potential power supply VSS, and inverts the potential from the high potential power supply VDD. The second inverter 212 operates between the potential from the potential generation circuit 1a and the potential from the low power supply VSS, and inverts the output signal IV1 of the first inverter 211.

  That is, the first inverter 211 and the second inverter 212 use the potential Vgen and the lower power supply VSS as the operating potential (power supply). Therefore, the operation of the switching control circuit 21a can be ensured even when the power supply is stopped (high-level power supply VDD = 0 [V]).

  The first switch SW1 includes a first switch transistor MP12 having a source connected to the high-level power supply VDD, a gate connected to the switching control circuit 21a, and a drain connected to the gate of the potential limiting transistor MN1. The second switch SW2 includes a second switch transistor MP13 having a source connected to the potential generation circuit 1a, a gate connected to the switching control circuit 21a, and a drain connected to the gate of the potential limiting transistor MN1. As each of the first switch transistor MP12 and the second switch transistor MP13, for example, a p-type channel MOS transistor (hereinafter referred to as “pMOS transistor”) can be used.

  Further, the first inverter 211 includes a first pMOS transistor MP10 and a first nMOS transistor MN10. The first pMOS transistor MP10 has a source connected to the potential generation circuit 1a and a gate connected to the high-level power supply VDD. The first nMOS transistor MN10 has a drain connected to the drain of the first pMOS transistor MP10, a gate connected to the high power supply VDD, and a source connected to the low power supply VSS.

  The second inverter 212 includes a second pMOS transistor MP11 and a second nMOS transistor MN11. The second pMOS transistor MP11 has a source connected to the potential generation circuit 1a and a gate connected to the output of the first inverter 211. The second nMOS transistor MN11 has a drain connected to the drain of the second pMOS transistor MP11, a gate connected to the output of the first inverter 211, and a source connected to the lower power supply VSS.

Next, the operation of the input circuit 11a according to the first embodiment will be described with reference to FIGS. As shown in FIG. 6C, the period from time T _{0 to} T ₁ is when power is supplied (high-level power supply VDD: on), and the period from time T _{1 to} T ₂ is when power is stopped (high-level power supply VDD: off). ). That is, a case where the high-level power supply VDD of the IC 10 is turned off (0 [V]) at the timing of time T ₁ will be described.

(A) At time t ₁ , the input signal Vin shown in FIG. 6A rises from a low level (0 [V]) to a high level. When the input signal Vin rises from the low level to the high level, the first resistor R1 and the second resistor R2 shown in FIG. 5 divide the high level input signal VinH. As a result, the potential Vgen is generated as shown at time t ₁ in FIG. Here, the potential Vgen is set to a value satisfying Equation 3.

In (B) the time t _1, as shown in FIG. 6 (d), the output signal IV1 of the first inverter 211 shown in FIG. 5 to the high potential power supply VDD shown in FIG. 6 (c) is at a high level low level To maintain. The first switch transistor MP12 to which the output signal IV1 of the first inverter 211 is supplied to the gate maintains an on (conducting) state.

  (C) As a result, as shown in FIG. 6F, the gate potential Vg of the potential limiting transistor MN1 is set to the potential of the high potential power supply VDD. Since the gate potential Vg of the potential limiting transistor MN1 is set to the potential of the high-level power supply VDD, as shown in FIG. 6G, the source potential Vs of the potential limiting transistor MN1 is set to a value that satisfies Equation (1). Is set. As shown in FIG. 6 (h), the buffer circuit 3a outputs an output signal Vout in phase with the source potential Vs of the potential limiting transistor MN1.

In (D) the time T _1, as shown in FIG. 6 (d), the high potential power supply VDD is turned off (0 [V]). At time t ₃ , the input signal Vin shown in FIG. 6A rises from the low level to the high level. Therefore, as shown in FIG. 6D, the output signal IV1 of the first inverter 211 is at a high level (potential Vgen). As shown in FIG. 6E, the output signal IV2 of the second inverter 212 is at a low level (0 [V]). As a result, at time t _3, as shown in FIG. 6 (f), the gate potential Vg of the potential limiting transistor MN1 is set to the potential Vgen.

  (E) Since the gate potential Vg of the potential limiting transistor MN1 is set to the potential Vgen, as shown in FIG. 6G, the source potential Vs of the potential limiting transistor MN1 is set to a value satisfying Expression (2). Is set. Here, as shown in FIG. 6H, since the high-level power supply VDD supplied to the buffer circuit 3a is 0 [V], the buffer circuit 3a does not operate.

  As described above, according to the input circuit 11a according to the first embodiment, when the input signal Vin having an amplitude greater than or equal to the high power supply VDD is input to the IC 10, the gate of the potential limiting transistor MN1 depends on the potential state of the high power supply VDD. It can be switched automatically. Therefore, the potential limiting transistor MN1 can be operated within the gate breakdown voltage. For this reason, it is possible to provide the input circuit 11a that can maintain a high reliability with respect to the input signal Vin having an amplitude greater than or equal to the power supply potential even when the power supply is stopped, while ensuring a stable operation during power supply.

(First modification of the first embodiment)
The input circuit 11b according to the first modification of the first embodiment of the present invention is different from FIG. 5 in that the switching control circuit 21b includes only the first inverter 211 as shown in FIG. Further, the second switch circuit SW20 includes a second switch transistor MP130 having a source connected to the potential generation circuit 1a, a gate connected to the high potential power supply VDD, and a drain connected to the gate of the potential limiting transistor MN1. Is different from FIG.

  Similarly to FIG. 5, the first switch transistor MP12 supplies the potential from the high potential power supply VDD to the gate of the potential limiting transistor MN1 in accordance with the output signal IV1 of the first inverter 211.

  The second switch transistor MP130 supplies the potential Vgen from the potential generation circuit 1a to the gate of the potential limiting transistor MN1 according to the potential from the high potential power supply VDD.

  At the time of power supply, since the high-level power supply VDD is at a high level, the output signal IV1 of the first inverter 211 is at a low level, the first switch transistor MP12 is turned on, and the second switch transistor MP130 is turned off. . As a result, the gate potential Vg of the potential limiting transistor MN1 is equal to the high potential power supply VDD.

  On the other hand, when the power supply is stopped, the high-level power supply VDD is low level, the output signal IV1 of the first inverter 211 is high level (potential Vgen), the first switch transistor MP12 is non-conductive, and the second switch transistor MP130 is It becomes a conductive state. Therefore, the gate potential Vg of the potential limiting transistor MN1 is equal to the potential Vgen.

  Thus, according to the potential selection circuit 2b shown in FIG. 7, the circuit scale can be reduced as compared with the potential selection circuit 2a shown in FIG.

(Second modification of the first embodiment)
The input circuit 11c according to the second modification of the first embodiment of the present invention is different from FIG. 5 in that the switching control circuit 21b includes only the first inverter 211 as shown in FIG. The second switch circuit SW21 has a drain connected to the potential generation circuit 1a, a gate connected to the output of the first inverter 211, and a second switch transistor MN12 whose source is connected to the gate of the potential limiting transistor MN1. 5 is different from FIG. For example, an nMOS transistor can be used as the second switch transistor MN12.

  The first switching transistor MP12 supplies the potential from the high-level power supply VDD to the gate of the potential limiting transistor MN1 according to the output signal IV1 of the first inverter 211.

  In response to the output signal IV1 of the first inverter 211, the second switch transistor MN12 supplies the potential Vgen from the potential generation circuit 1a to the gate of the potential limiting transistor MN1.

  At the time of power supply, the high-level power supply VDD is at a high level, the output signal IV1 of the first inverter 211 is at a low level, the first switch transistor MP12 is turned on, and the second switch transistor MN12 is turned off. As a result, the gate potential Vg of the potential limiting transistor MN1 is equal to the high potential power supply VDD.

  On the other hand, when the power supply is stopped, the high level power supply VDD is low level, the output signal IV1 of the first inverter 211 is high level (potential Vgen), the first switch transistor MP12 is non-conductive, and the second switch transistor MN12 is conductive. It becomes.

  Here, the gate potential Vg attenuates by the threshold voltage VTh of the second switch transistor MN12. Therefore, the gate potential Vg becomes potential Vgen−threshold voltage VThN. Therefore, in the potential generation circuit 1a, a desired value can be obtained by designing the first and second resistors R1 and R2 so that the potential Vgen is increased by the threshold voltage VThN in advance.

  Thus, according to the potential selection circuit 2c shown in FIG. 8, the circuit scale can be reduced as compared with the potential selection circuit 2a shown in FIG.

(Second Embodiment)
Input circuit 11d according to a second embodiment of the present invention, as shown in FIG. 9, the potential generating circuit 1b has a drain connected to the input node n _1, the connection node of the first resistor R1 and second resistor R2 5 is different from FIG. 5 in that it further includes a potential control transistor MN9 having a gate connected and a source connected to the potential selection circuit 2a. For example, an nMOS transistor can be used as the potential control transistor MN9.

  The potential control transistor MN9 generates the potential Vgen by controlling the potential of the input signal Vin according to the divided output VR by the first resistor R1 and the second resistor R2 with respect to the input signal Vin input to the drain. .

The potential Vgen becomes a divided output VR by the first resistor R1 and the second resistor R2−the threshold voltage VThN of the potential control transistor MN9. Therefore, when the maximum value of the allowable potential of the IC 10 is Vmax, the divided output by the first resistor R1 and the second resistor R2 is VR, and the threshold voltage of the potential control transistor MN9 is VThN.

VR-VthN <Vmax (4)

Holds. That is,

VR <Vmax + VthN (5)

A desired potential Vgen can be obtained by designing the first resistor R1 and the second resistor R2 so as to satisfy the above.

  Further, the buffer circuit 3b includes an inverter 31, an inverter 32, and an nMOS transistor MN92. In the nMOS transistor MN92, the drain and gate are connected to the high-level power supply VDD, and the source is connected to the inverter 31. By using the nMOS transistor MN92 whose gate is connected to the high-level power supply VDD, the high level of the inverter 31 is limited to the high-level power supply VDD−threshold voltage VThN, like the potential limiting transistor MN1. As a result, the inverter 31 has a threshold optimized for the source potential Vs of the potential limiting transistor MN1, and a stable operation can be obtained.

  The inverter 31 includes a pMOS transistor MP94 and an nMOS transistor MN94. In the pMOS transistor MP94, the source is connected to the source of the nMOS transistor MN92, and the gate is connected to the source of the potential limiting transistor MN1. In the nMOS transistor MN94, the drain is connected to the drain of the pMOS transistor MP94, the gate is connected to the source of the potential limiting transistor MN1, and the source is connected to the low potential power supply VSS.

  The inverter 32 includes a pMOS transistor MP95 and an nMOS transistor MN95. In the pMOS transistor MP95, the source is connected to the high-level power supply VDD, and the gates are connected to the drains of the pMOS transistor MP94 and the nMOS transistor MN94. In the nMOS transistor MN95, the drain is connected to the drain of the pMOS transistor MP95, the gate is connected to each drain of the pMOS transistor MP94 and the nMOS transistor MN94, and the source is connected to the low power supply VSS. Other configurations are the same as those in FIG.

  Next, the operation of the input circuit 11d according to the second embodiment will be described with reference to FIGS. However, redundant description of operations similar to those of the input circuit 11a according to the first embodiment is omitted.

  (A) When the input signal Vin shown in FIG. 10A is at the high level VinH, the potential Vgen shown in FIG. 10B is a voltage-divided output obtained by dividing VinH by the first resistor R1 and the second resistor R2. The potential is limited by VR (divided voltage output VR−threshold voltage VThN of potential control transistor MN9). On the other hand, when the input signal Vin is at a low level, VR = 0 [V] and the potential control transistor MN9 is turned off, so that the potential Vgen gradually drops due to parasitic leakage.

  (B) As a result, the potential Vgen shown in FIG. 10B, the output signal IN1 of the first inverter 211 shown in FIG. 10D, the output signal IN2 of the second inverter 211 shown in FIG. The gate potential Vg of the potential limiting transistor MN1 shown in 10 (f) has a direct current (DC) waveform.

  Thus, according to the second embodiment, as in the first embodiment, the gate-drain potential Vgd of the potential limiting transistor MN1 does not exceed the breakdown voltage (Vmax) even when the power supply is stopped. The input circuit 11d that does not cause a problem in reliability can be realized.

(Modification of the second embodiment)
As shown in FIG. 11, the potential generating circuit 1c according to the modification of the second embodiment of the present invention includes a first load transistor MP60 and a second load transistor MP60 connected in series between the input node n ₁ and the low-level power supply VSS. The difference from the potential generation circuit 1b shown in FIG. 9 is that a load transistor MP61 is provided. That is, the first load transistor MP60 and the second load transistor MP61 are used as the first resistor R1 and the second resistor R2 shown in FIG. As the first load transistor MP60 and the second load transistor MP61, for example, a pMOS transistor can be used.

The first load transistor MP60 has a source and a back gate connected to the input node n _1, a drain and a gate connected to the gate potential control transistor MN9.

  In the second load transistor MP61, the source and the back gate are connected to the gate of the potential control transistor MN9, and the drain and the gate are connected to the low potential power supply VSS.

  The back gate bias of the first load transistor MP60 and the second load transistor MP61 is not the high power supply VDD but is connected to its own source. As a result, the first load transistor MP60 and the second load transistor MP61 function as resistance elements having a floating well structure.

  Therefore, the desired potential Vgen can be obtained by designing the sizes of the first load transistor MP60 and the second load transistor MP61 so as to satisfy Expression (5).

  Alternatively, a desired potential Vgen may be obtained by increasing the number of load transistors.

  According to the potential generation circuit 1c according to the modification of the second embodiment, since the first load transistor and the second load transistor are used, the area of the potential generation circuit 1c can be reduced as compared with the case where a resistor is used.

(Other embodiments)
As described above, the present invention has been described according to the first and second embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  The potential selection circuit 2b according to the first modification example of the first embodiment and the potential selection circuit 2c according to the second modification example of the first embodiment described above are the potential generation circuit 1b according to the second embodiment or the second implementation example. It can be used in combination with the potential generation circuit 1c according to the modification of the embodiment.

  In the first and second embodiments described above, an example in which a MOS transistor is used as a switching element has been described. However, the switching element is not limited to a MOS transistor, and an MIS transistor can be used. The “MIS transistor” means a switching element having a metal / insulator / semiconductor structure, and includes a metal / oxide / semiconductor MOS transistor.

  Thus, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the invention specifying matters in the scope of claims reasonable from this disclosure.

1 is a block diagram illustrating a configuration example of an integrated circuit according to a first embodiment. FIG. 6 is a diagram illustrating an operation example of the potential selection circuit according to the first embodiment (No. 1). It is a block diagram which shows the structural example of the input circuit which concerns on 1st Embodiment. FIG. 6 is a diagram illustrating an operation example of the potential selection circuit according to the first embodiment (No. 2). It is a circuit diagram showing an example of composition of an input circuit concerning a 1st embodiment. It is a time chart which shows the operation example of the input circuit which concerns on 1st Embodiment. It is a circuit diagram which shows the structural example of the input circuit which concerns on the 1st modification of 1st Embodiment. It is a circuit diagram which shows the structural example of the input circuit which concerns on the 2nd modification of 1st Embodiment. It is a circuit diagram which shows the structural example of the input circuit which concerns on 2nd Embodiment. It is a time chart which shows the operation example of the input circuit which concerns on 2nd Embodiment. It is a block diagram which shows the structural example of the electric potential generation circuit which concerns on the modification of 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a-1c ... Potential generation circuit 2a-2c ... Potential selection circuit 4 ... Limit circuit 11a-11e ... Input circuit 21a, 21b ... Switching control circuit SW1 ... 1st switch circuit SW2 ... 2nd switch circuit R1 ... 1st resistance R2 ... Second resistor MN9 ... Potential control transistor

Claims (2)

A potential generation circuit that detects an input signal and generates a potential;
A potential selection circuit that selects a potential from a high-level power supply when power is supplied and selects a potential from the potential generation circuit when the power is stopped;
A limiting circuit that limits the potential of the input signal according to the potential selected by the potential selection circuit;
The potential selection circuit includes:
A first switch circuit for switching whether to supply a potential from the high-level power supply to the limiting circuit;
A second switch circuit for switching whether to supply the potential from the potential generation circuit to the limiting circuit;
A switching control circuit for making the first and second switch circuits conductive and non-conductive when the power is supplied, and for making the first and second switch circuits non-conductive and conductive when the power is stopped, respectively.
The switching control circuit includes:
A first inverter that operates between a potential from the potential generation circuit and a potential from a low-level power supply and inverts a potential from the high-level power supply;
A second inverter that operates between a potential from the potential generation circuit and a potential from the lower power supply, and inverts an output signal of the first inverter;
The first switch circuit is said first conductive according to the inverter output signal, the second switch circuit input circuitry you characterized by conducting in response to the output signal of the second inverter. A potential generation circuit that detects an input signal and generates a potential;
A potential selection circuit that selects a potential from a high-level power supply when power is supplied and selects a potential from the potential generation circuit when the power is stopped;
A limiting circuit that limits the potential of the input signal according to the potential selected by the potential selection circuit;
The potential generation circuit includes:
A plurality of resistance components for dividing the potential of the input signal;
As a control voltage the input signal divided by said plurality of resistance components, the input to control a potential of the input signal you characterized by obtaining Bei the potential control transistor to be supplied to the potential selection circuit circuit.

Images