JP4658812B2 - Nonvolatile semiconductor memory device and writing method thereof - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more specifically to a writing method for a write target memory cell group including a plurality of memory cells to be written to the nonvolatile semiconductor memory device. The present invention particularly relates to a writing method useful for a writing operation of a multi-value type nonvolatile semiconductor memory device capable of storing data of three or more values in a single memory cell.

  As a typical example of a nonvolatile semiconductor memory device, there is a flash memory described in Non-Patent Document 1 below. This is an electrically programmable read-only memory (flash EEPROM) capable of flash erasing (electrical batch erasing) constituted by an electrically insulated MOS gate called a floating gate. FIG. 7 shows an example of a memory cell structure of a conventional flash EPROM. The floating gate 1 directly controls the channel 2 and has a stacked structure including the floating gate 1 for storing data (electrons) and the control gate 4 on the insulating film 3 thereon. As shown in the equivalent circuit diagram of FIG. 8, the floating gate is completely floating from the external terminal by the insulating film, and this potential is controlled by capacitive coupling from the other four terminals. The data write operation uses a hot carrier phenomenon similar to the write principle of the UV erasable EPROM as a mechanism, and gives the electrons sufficient energy to exceed the barrier height of the tunnel gate oxide film 5 which is an insulating film. Electrons are injected into the gate 1. In the erasing operation, electrons are emitted through the tunnel oxide film 5 in the overlapping region of the floating gate 1 and the source diffusion 6 by using the Fowler-Nordheim tunneling mechanism. Thereby, the number of electrons in the floating gate 1 is adjusted. As with the normal MOS NOR type memory, reading is performed by detecting the difference in the accumulated data (number of electrons) of the drive current of the bit selected by the bit line (drain 7) and the word line (control gate 4). Read.

  Further, as shown in Patent Document 1 below, as an alternative to the above-described floating gate, a charge holding layer such as a silicon nitride film is disposed, and charges are injected and accumulated in this portion to similarly function as a nonvolatile memory device. There are also examples.

  FIG. 9 is a block diagram showing a configuration of a general nonvolatile memory device. A sense amplifier circuit 11 and a column decoder 12 are connected to each bit line of the memory cell array 10 to select a bit line and detect data. A row (row) decoder 13 is connected to each word line, and a word line is selected. A column voltage control circuit 14 and a row voltage control circuit 15 are connected to the column decoder 12, the row decoder 13, and the sense amplifier circuit 11, respectively, and voltages necessary for various operations are supplied from these. In the column decoder 12 and the row decoder 13, an address signal input from the outside via the address buffer 18 is divided into a row address and a column address and input separately. The data in the memory cell array 10 read by the sense amplifier circuit 11 is output to the outside via the input / output buffer 17 in accordance with the difference in memory operation mode (read mode or write / erase mode) at that time. Alternatively, it is used for a write / erase verification process (verify) in the write / erase mode.

  A state machine 16 is connected to the sense amplifier circuit 11, the column voltage control circuit 14, the row voltage control circuit 15, the column decoder 12, and the row decoder 13. The state machine 16 controls the entire memory operation for the flash memory array based on a command input from the outside via the command state logic interface 19.

  An example of a writing method for a multi-level flash memory will be described with reference to Patent Document 2 below.

  FIG. 10 shows a threshold voltage distribution DE after erasure and a natural threshold voltage distribution DP1 after at least one write pulse is applied to all bits in the conventional example. The threshold voltage distribution DP1 is divided into n groups. For example, the first group A1 includes memory cells having a threshold voltage lower than the voltage V1, and the second group A2 includes memory cells having a threshold voltage not lower than the voltage V1 and lower than the voltage V2. In this way, different write bit line voltages corresponding to the respective voltage levels are applied to n classes A1 to An divided by predetermined threshold voltage levels V0, V1,..., Vn. Thus, the memory cell threshold voltage distribution width after writing is controlled to be narrow.

  Next, as another example, a flash memory writing method described in Patent Document 3 below will be described. As shown in FIG. 11, the write voltage increment ΔVpgm1 from the first write pulse application to the second write pulse application to the memory cell control gate, the second and third write voltage increments ΔVpgm2, and thereafter After the write voltage increment ΔVpgm3, the mutual relationship between the voltage increments is ΔVpgm1> ΔVpgm2 = ΔVpgm3.

  FIGS. 12 to 16 show how the write operation is performed while increasing the write voltage applied to the control gate.

  First, FIG. 12 shows a state where the first write voltage pulse is applied. The threshold voltage distribution DP1 after the write pulse is applied to all the memory cells to be written is a distribution due to natural variations. In this state, it is assumed that no memory cell has reached the write completion reference threshold voltage Vpv. After the first write pulse is applied, it is determined whether or not the write completion reference threshold voltage Vpv has been reached (verify operation). Here, the second write voltage pulse is selectively applied to the memory cells that have not reached the write completion reference threshold voltage Vpv. The second write voltage is increased by ΔVpgm1 with respect to the first write voltage. As a result, the entire threshold voltage distribution DP1 for which writing has not been completed moves to the high voltage side by a threshold voltage fluctuation ΔVth1 corresponding to the writing voltage difference of ΔVpgm1, as shown in FIG. As a result, since the memory cells in the region indicated by X1 in the moved threshold voltage distribution DP2 have reached the write completion reference threshold voltage Vpv, these memory cells do not receive the application of the next third write voltage pulse. Similarly, a third write voltage pulse that is increased by ΔVpgm2 with respect to the second write voltage pulse is applied to the memory cells that have not reached the write completion reference threshold voltage Vpv, and the post-write threshold value as shown in FIG. The voltage distribution DP3 moves from the previous threshold voltage distribution DP2 to the high voltage side by a threshold voltage fluctuation ΔVth2 corresponding to the write voltage difference of ΔVpgm2. As a result, it is newly determined that the memory cell in the region X2 shown in FIG. 14 is completely written, and the subsequent write pulse is not applied. At this point, the threshold voltage distributions of the memory cells in the region X1 in FIG. 13 and the region X2 in FIG. 14 are combined to form a threshold voltage distribution DX as shown in FIG. In the same procedure, as shown in FIG. 15, the fourth write voltage pulse is applied, and the threshold voltage distributions of the memory cells in the region X3 where writing is completed are further combined to form the threshold voltage distribution DY. Finally, a threshold voltage distribution DZ after writing as shown in FIG. 16 is formed. In the above example, the distribution width Wvtp of the threshold voltage distribution DZ finally formed in this way is the write voltage increase ΔVpgm2 (= ΔVpgm3) and the standard deviation constituting the natural variation threshold voltage distribution DP1. Furthermore, the variation factors such as the standard deviation of the fluctuation noise of the write voltage and the standard deviation of the read noise are statistically superimposed and become a value larger than the normal write voltage increase ΔVpgm2.

JP 2000-514946 JP 2005-129194 A JP 2004-185658 A S. Mukherjee et. al, "A Single Transistor EEPROM Cell and implementation in 512k CMOS EEPROM", IEDM Technical Digest, p. 616, (1985)

  In a multi-value type nonvolatile semiconductor memory device, it is necessary to control the threshold voltage distribution width after writing with high accuracy. In other words, it is required to control the distribution width as narrow as possible and to take a sufficiently wide separation width of the threshold voltage between the multi-value states.

  However, in order to narrow the threshold voltage distribution width described above, in the conventional example disclosed in Patent Document 3, it is necessary to reduce the write voltage increase width ΔVpgm, but as is clear from the above example, When ΔVpgm is reduced, the corresponding threshold voltage change amount ΔVth is reduced, the number of times of application of the write pulse obtained by dividing the natural threshold voltage distribution width by ΔVth is increased, and the write time is increased.

  Further, even if the write voltage increase width ΔVpgm is reduced, the above-described various variations are statistically superimposed. Therefore, after writing is completed, only a threshold voltage distribution having a wider distribution width than ΔVth corresponding to ΔVpgm can be obtained. There was a problem.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a nonvolatile semiconductor memory device capable of narrowly controlling a threshold voltage distribution width after completion of writing with a small number of application times of writing voltage and writing thereof. It is to provide a method.

In order to achieve the above object, a writing method of a nonvolatile semiconductor memory device according to the present invention includes all or one of the write target memory cell groups including a plurality of memory cells having a MOSFET structure to be written to the nonvolatile semiconductor memory device. For each of the set of memory cells, each of the memory cells is defined by a threshold voltage distribution range according to a threshold voltage of the MOSFET structure that changes according to a storage state of the memory cell. A classification process for classifying the above classes, an evaluation process for deriving the number of the memory cells belonging to each class classified in the classification process as an evaluation value for each class, and for the memory cells of each class Te, write conditions for changing the amount of change in the write voltage applied to the predetermined electrode of the memory cell in accordance with the evaluation value of each class In that the writing process for writing process, that has a first feature.

Further, in the writing method of the nonvolatile semiconductor memory device according to the first feature, in the evaluation step, the upper limit value or the lower limit value of the threshold voltage distribution of each class is used as a reference voltage for the memory cells in the set. The number of the memory cells on either the high voltage side or the low voltage side with respect to the reference voltage among the threshold voltages of the memory cells read by the class And calculating the difference between the numbers of the adjacent classes, and deriving the evaluation value of each class.

Furthermore, the write method for a nonvolatile semiconductor memory device of the first aspect, the memory of the in the evaluation step, said the set multiple of the write voltage of the voltage difference corresponding to the width of the threshold voltage distribution of each class run by sequentially applied to the cell, one of said each time a write operation in the write voltage is finished, the writing is performing a read operation for the reference voltage to the reference threshold voltage that defines the write state of the memory cell state The number of the memory cells is totaled, a difference in the total number between the adjacent classes is obtained, and the evaluation value of each class is derived.

Furthermore, the write method for a nonvolatile semiconductor memory device of the first aspect, the memory of the in the evaluation step, said the set multiple of the write voltage of the voltage difference corresponding to the width of the threshold voltage distribution of each class run by sequentially applied to the cell, each time a write operation in one of the write voltage is finished, the first read operation and the reference voltage to the first reference threshold voltage defining a write state of the memory cell And a second read operation using a second reference threshold voltage having a voltage difference on the erase side by the threshold voltage distribution width of the class to be evaluated as a reference voltage, and erasing in the first read operation The number of the memory cells that are in the state is totaled, and the number of the memory cells that are in the writing state in the second read operation is totalized, and a difference between the two numbers of totals is obtained. Characterized by sequentially derives the evaluation value of the class to be evaluated.

Further, in the writing method of the nonvolatile semiconductor memory device according to the first feature, the amount of change in the write voltage is changed according to the evaluation value of each class among the write conditions used in the write step. conditions, and the standard deviation of the threshold voltage distribution across the set at the time of the writing process has been finished for the entire said set, and characterized in that it is derived based on the number of the memory cells belonging to the each class To do.

Further, in the writing method of the nonvolatile semiconductor memory device according to the first feature, in the writing step, the writing process is sequentially executed while changing the amount of change of the writing voltage under the writing condition . said upon transitioning the sequentially written state memory cell, the amount of change in the write voltage, by the write voltage after the change is applied to the class in which a group of the memory cells belonging to the transition to the write state The smaller the evaluation value, the smaller the setting.

Furthermore, in the writing method of the nonvolatile semiconductor memory device according to the first feature, as the number of execution times of the writing process sequentially executed while changing the amount of change of the writing voltage in the writing condition in the writing step, The write voltage is changed so that the change amount of the write voltage has a minimum value.

Further, the write method of the nonvolatile semiconductor memory device according to the first feature is characterized in that the write voltage is a write gate voltage applied to the gate electrode of the memory cell.

Furthermore, in the writing method of the nonvolatile semiconductor memory device according to the first feature, in the writing step, when determining the amount of change in the writing voltage applied to the writing process for the memory cells of each class, an arbitrary number When the evaluation value N _i of the i-th class is greater than the evaluation value N _{j of the} arbitrary number j of the class different from the arbitrary number _i (N _i > N _j ), the arbitrary number i of the class When the memory cell belonging to the class is in the threshold voltage region immediately before writing, the write voltage Vpgm (i) in the write process one time before the write voltage Vpgm (i) in the write process for the memory cell belonging to the class. Change amount ΔVpgm (i) from (-1) is a threshold immediately before the memory cell belonging to the arbitrary number j of the class is written. Change amount ΔVpgm (j) from Vpgm (j−1) of the write voltage in the write process one time before the write voltage Vpgm (j) in the write process to the memory cell belonging to the class in the pressure region It is determined to be smaller.

Furthermore, in the writing method of the nonvolatile semiconductor memory device according to the first feature, in the writing step, when determining the amount of change in the writing voltage applied to the writing process for the memory cells of each class, an arbitrary number The write voltage in the write process one time before the write voltage Vpgm (i) in the write process for the memory cell belonging to the class when the memory cell belonging to the i-th class is in the threshold voltage region immediately before the write The amount of change ΔVpgm (i) from Vpgm (i−1) is given by the recurrence formula shown in the following equation 1,
(Equation 1)
ΔVpgm (i + 1) -ΔVpgm ( i) = - 2 × (k i + 1 -k i) × S 0

K _{i + 1} and k _i if the arbitrary number i of the number of 1 is 1 or more, the reciprocal of the evaluation value N _i (i + 1) th of the evaluation value N _{i + 1} and i-th of said classes of the class Each inverse function when the given probabilities P _{i + 1} and P _i are expressed by the cumulative distribution functions Pr {k _{i + 1} } and Pr {k _i } of the normal distribution as shown in the following equations 2 and 3. Given,

The probability P ₀ given by the reciprocal of the number N ₀ of the memory cells in the whole set is k ₀ when the arbitrary number i in the number 1 is 0. It is given as an inverse function when expressed by a cumulative probability distribution function Pr {k ₀ },

ΔVpgm (0) in the case where the arbitrary number i in the equation 1 is 0, the change amount ΔVpgm (i) is fixed to a constant value regardless of the arbitrary number i, and the writing process of the memory cells in the entire set is performed. When the threshold voltage distribution width of the entire set becomes the target threshold voltage distribution width when completed, the change amount is given as S ₀ in the _equation 1, and the change amount ΔVpgm (i) is changed to the arbitrary number i. Regardless of whether or not ΔVpgm (0) is fixed and the write processing of the memory cells in the entire set is completed, the standard deviation of the threshold voltage distribution of the entire set is given.

Further, in any of the above-described characteristics of the nonvolatile semiconductor memory device writing method, the classification step and the evaluation step may be performed before the writing step is actually executed in the nonvolatile semiconductor memory device. It is executed in advance by an experiment or simulation using a sample different from the storage device, and the write condition corresponding to the evaluation value of each class obtained as a result of the execution is derived in advance and then the nonvolatile The second feature is that the data is stored in the semiconductor memory device.

Furthermore, the nonvolatile semiconductor memory device according to the present invention can be obtained by using the nonvolatile semiconductor memory device writing method according to the first feature, in which all or part of a write target memory cell group including a plurality of write target memory cells. A non-volatile semiconductor memory device writable with respect to the set of memory cells, classification means capable of executing the classification step of the writing method, and evaluation means capable of executing the evaluation step of the writing method; And a writing unit capable of executing the writing step of the writing method.

Also, the non-volatile semiconductor memory device of the first aspect, wherein the evaluation means, within said set, wherein the threshold voltage is provided with a collecting unit which can aggregate the number of predetermined reference voltage below or above the memory cells This is the second feature.

  Further, the nonvolatile semiconductor memory device according to the second feature is characterized in that the evaluation means includes a register circuit for storing the number of the memory cells counted by the counting means.

Furthermore, the nonvolatile semiconductor memory device according to any one of the above features has the evaluation value of each class as an input, and the write voltage and the change amount of the write voltage in the write condition set in advance for the evaluation value Or a write condition comparison table that outputs a change amount of the change amount of the write voltage .

Furthermore, in the nonvolatile semiconductor memory device according to the first to third features, when the writing unit receives the evaluation value of each class, the write voltage under the write condition and the amount of change in the write voltage Alternatively, a fifth circuit is characterized in that a sequential circuit that outputs the change amount of the write voltage change amount is provided.

According to another aspect of the nonvolatile semiconductor memory device of the present invention, all or part of a write target memory cell group including a plurality of memory cells to be written can be obtained by the writing method of the nonvolatile semiconductor memory device according to the second feature. A nonvolatile semiconductor memory device capable of writing to the set of memory cells, wherein the writing according to the evaluation value of each class obtained by executing the classification step and the evaluation step of the writing method in advance A sixth feature includes: a storage circuit that stores conditions as a comparison table; and a writing unit that can execute the writing step of the writing method based on the writing conditions stored as the comparison table. To do.

Further, the fourth to sixth nonvolatile semiconductor memory device of the features of the writing means, wherein the write voltage in the write condition in accordance with the evaluation value of each class, the amount of change in the write voltage, or, A seventh feature is that a write voltage generation circuit is provided that outputs a write voltage to be applied to a predetermined electrode of the memory cell based on a change amount of the change amount of the write voltage.

  Further, in the nonvolatile semiconductor memory device according to the seventh feature, the write voltage generation circuit is constituted by a D / A conversion circuit, and the write voltage is an analog output selected by a digital input of the D / A conversion circuit. When the entire voltage range of the distribution is equally divided into three or more sections, the number of analog outputs selected is higher in the section closer to the center of the distribution.

  When the physical quantity that defines the storage state of the memory cell is distributed with a certain distribution width due to the characteristic variation of each memory cell, the writing process is performed on each class obtained by subdividing the distribution width in all the memory cells to be written. When this is done, the distribution after completion of writing of a class in which writing is completed in each writing process varies more as the number of memory cells in that class increases.

  Therefore, according to the present invention, the write process is performed under the write condition corresponding to the evaluation value represented by the number of memory cells belonging to each class. The write condition that is the rough write control that allows the distribution after the completion of the write to spread to a certain extent is applied to the class having a small number of memory cells by applying the write condition that becomes the fine write control that can be controlled narrowly. In order to keep the distribution width of the physical quantity of all the memory cells to be written within a certain range, the programming for uniformly controlling the distribution after the programming is completed uniformly for all classes. There is no need to apply conditions. That is, the number of write processes can be reduced for a class with a small number of memory cells in order to keep the distribution width of all the memory cells to be written after the completion of writing of the physical quantity within a certain range. It is possible to reduce the total number of write processes required until the cell is completely written, and to shorten the overall write time. That is, the distribution width after the writing is completed can be controlled with a small number of writing processes.

  Further, the memory cell has a MOSFET structure, the physical quantity is defined as a threshold voltage of the MOSFET structure, and a condition that changes according to an evaluation value of each class among the write conditions used in the write process is as follows. Assuming that the amount of change in the write voltage applied to the gate electrode is assumed, the above effect will be theoretically explained.

When writing is performed until writing is completed for all the memory cells to be written with the change amount ΔVpgm of the writing voltage being constant, the distribution width of the threshold voltage after writing is wider than ΔVpgm and becomes a value of ΔVpgm + α. Is as described above. In this case, the threshold voltage distribution is a distribution close to a normal distribution based on a certain standard deviation. As shown in the writing process shown in FIGS. 12 to 16, in the middle of writing, the natural writing threshold distribution gradually moves toward the target threshold voltage distribution by the threshold voltage corresponding to ΔVpgm, The above-mentioned post-write distribution is as if the individual small distributions obtained by decomposing the natural threshold voltage distribution shown in FIG. 12 with the threshold voltage width corresponding to ΔVpgm are superimposed with the write completion reference threshold voltage Vpv as the minimum value. It is formed. Therefore, each class Ai in which the natural threshold voltage distribution is divided by the ΔVpgm width is the same standard as the standard deviation S ₀ representing the threshold voltage distribution after the completion of writing immediately after exceeding the write completion reference threshold voltage Vpv. it may be considered to be the threshold voltage distribution having a deviation S _0.

Accordingly, as shown in FIG. 17, the width of the threshold voltage distribution of each class A _i (normal distribution) is wider as the number of memory cells is large for each class A _i, becomes narrower as the number of memory cells is small. That is, a class _{A i} of the number of memory cells _{N i,} with respect to Class _{A j} of the number of memory cells _{N j,} when N i> _{N j} holds, class _A i, the shape of the threshold voltage distribution of _{A j} are similar figures Respectively, and follows a normal distribution N (Vthu, S ₀ ) where the average value is Vthu and the standard deviation is S ₀ . Since N _i > N _j holds for the number of memory cells in each class, the distribution width of two similar threshold voltage distributions, that is, the difference between the maximum and minimum values R _i and R _j is R _i > R _j .

In the example shown in FIG. 17, it is assumed that two classes A _i and A _j are written with the same ΔVpgm, and the average of the threshold voltage distribution of each class is equal. For this reason, there is a difference in the maximum value. This difference is due to the difference in the number of memory cells in both classes. Furthermore, the difference between the maximum value for the class A _j, a useless width, the maximum value of the threshold voltage distribution after completion writing class A _j is even equal to that of the class A _i, as a whole The distribution width of the threshold voltage after completion of writing does not change. Therefore, with respect to the class A _j , even if the change width ΔVpgm of the write voltage applied to the memory cells belonging to this class is made larger than the class A _{i and the} number of write processes until the write is completed is reduced, the same result (class A threshold voltage distribution that falls within the threshold voltage distribution of _i ).

  In the present invention, a set of all or a part of a memory cell group to be written consisting of a plurality of memory cells to be written is changed according to a physical quantity distribution range that changes according to the storage state of the memory cell such as a threshold voltage. As shown in FIG. 18, by classifying into three or more classes that are defined and optimizing the amount of change ΔVpgm of the write voltage for each class, assuming a difference in the number of memory cells belonging to each class in advance. In particular, by designing the maximum value of the threshold voltage distribution after completion of writing of the class Aj with a small number of memory cells to be aligned with the maximum value of the same threshold voltage distribution of the class having the maximum number of memory cells, the number of write processes can be reduced. Enables effective reduction.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a nonvolatile semiconductor memory device and a writing method thereof (hereinafter abbreviated as “the device of the present invention” and “the method of the present invention” as appropriate) will be described below with reference to the drawings.

<First Embodiment>
FIG. 1 shows a block diagram of a configuration example of the device of the present invention. The block configuration of the device of the present invention shown in FIG. 1 is similar to the block configuration of the conventional general non-volatile memory device shown in FIG. 9, and is a memory cell array 10, sense amplifier circuit 11, column decoder 12, row ( A row) decoder 13, a column voltage control circuit 14, a row voltage control circuit 15, a state machine 16, an input / output buffer 17, an address buffer 18, a command state logic interface 19, and the like. The basic function of each part is the same as that of the conventional general non-volatile memory device shown in FIG. 9, and a duplicate description is omitted.

  As shown in FIG. 1, in order to carry out the method of the present invention, which will be described later in detail, the device of the present invention further includes an evaluation value counting register used in the classification process and the evaluation process of the method of the present invention. A circuit 20 and a nonvolatile memory circuit 21 storing a comparison table used in the writing process of the method of the present invention are provided. The evaluation value counting register circuit 20 is connected to the state machine 16 that controls the processing procedure of the method of the present invention and the row decoder 13, and the non-volatile storage circuit 21 that stores the comparison table is connected to the state machine 16, The state machine 16 is configured to be able to use the comparison table when controlling the writing process.

  When the state machine 16 recognizes a data write operation to the memory cell array 10 by a command input, the state machine 16 includes the evaluation value counting register circuit 20 and the storage circuit 21 based on a predetermined algorithm capable of executing the method of the present invention. Control of each circuit unit to be connected is executed.

  In the present embodiment, the memory cell array 10 is assumed to have a structure in which flash EPROM memory cells having a MOSFET structure having a floating gate illustrated in FIG. 7 are arranged in a matrix in the row direction and the column direction. The control gate 4 of each memory cell in the same row is connected to a common word line extending in the row direction, and the drain electrode 7 of each memory cell in the same column is connected to a common bit line extending in the column direction. The source electrode 6 of each memory cell in the same block divided separately is connected to a common source line. Here, each word line is selected by the row decoder 13 and supplied with the word line voltage supplied from the row voltage control circuit 15. Further, each bit line is selected by the column decoder 12 and supplied with the bit line voltage supplied from the column voltage control circuit 14. A ground voltage is supplied to the source line except during erasing, and a predetermined erasing voltage is applied during erasing. However, in FIG. 1, since it is not directly related to the writing operation, an erasing voltage applying circuit to the source line is applied. Is omitted.

  Next, an example of the method of the present invention executed by the control of the state machine 16 in the block configuration shown in FIG. 1 will be described.

  In the method of the present invention described below, a memory cell group belonging to a part or all of an address space defining a data storage area in the memory cell array 10 is set as a write target, and data in the memory cell group is erased in advance. Then, it is assumed that data is written by selecting only memory cells that need to be written from the erased state based on write data input from the outside via the input / output buffer 17 as write targets. In the following description, for the sake of brevity, it is assumed that binary data is stored, and the case where there is one writing state will be described. However, even in the case of multi-value data storage, the writing state is divided into a plurality of states. The method of the present invention can be similarly applied to a write operation from an erase state to each write state and a write operation from one write state to another write state.

In the method of the present invention, each of the memory cells to be written (hereinafter simply referred to as “memory cells”) is applied with a write voltage once from the erased state. In a state in which a natural threshold voltage distribution corresponding to the characteristic variation is exhibited, the natural threshold voltage distribution is subdivided into three or more classes A _i (i is a natural number, and increases by 1 from a higher threshold voltage to a lower threshold voltage). decomposes), evaluation for counting and classification step of the each memory cell each threshold voltage grading depending on whether they fall in a class, the number of memory cells N _i belonging to each class a _i as an evaluation value of each class a _i a step, in the write condition corresponding to the evaluation value N _i of each class a _i, a writing process for writing process to the memory cells belonging to each class a _i, respectively executed.

Hereinafter, each of the classification process, the evaluation process, and the writing process will be described in detail. In this embodiment, the above steps are not executed for all classes one by one, but are sequentially performed for each class A _i while sequentially shifting to the next class. The execution method will be described.

In the above write process, a write voltage is applied to the control gate and drain of each memory cell via a word line and a bit line. In this embodiment, the write voltage applied to the control gate is one time before. It will be described of changing in accordance with increase of the writing process to the evaluation value N _i.

  First, preliminary writing is performed so that all memory cells in the erased state exhibit a natural threshold voltage distribution. At this stage, as shown in FIG. 12, it is assumed that the threshold voltage of all the memory cells is less than the write completion reference voltage Vp and the write state has not been reached, and the preliminary write conditions are derived statistically or empirically in advance. Use things.

Next, the first writing process (i = 1) is executed. By the write voltage Vpgm is applied by the first writing process (1), the memory cell of rank A ₁ is write completion. Since the natural threshold voltage distribution of all the memory cells follows a substantially normal distribution, the class A ₁ is an end region on the higher side of the threshold voltage, and therefore the number of memory cells N ₁ is small. With respect to the width Wvtp, the increase amount ΔVpgm (1) of Vpgm (1) from preliminary writing can be set larger than the distribution width Wvtp, and the first writing voltage Vpgm (1) is also derived statistically or empirically. Use the same thing.

At the stage of starting an arbitrary number i-th process after the second time, the memory cells of the class A _i are in a state immediately before writing, that is, in a writing completion state in the i-th writing process. Here, the classification process and the evaluation process for the class A _i are executed simultaneously. Specifically, by a read operation (verification process) in which the first reference voltage is set to the write completion reference voltage Vp for all memory cells in the unwritten state (memory cells after class A _i ) or all memory cells, The number of memory cells whose threshold voltage is less than the first reference voltage is counted. Next, an increase ΔVpgm (i−1) {= Vpgm (i−1) −Vpgm in Vpgm (i−1) used in the (i−1) th writing process one time before the write completion reference voltage Vp. (I−2)} is subtracted from the voltage (Vp−ΔVpgm (i−1)) as the second reference voltage, the verify process is performed on the memory cell that is the target of the previous verify process, and the threshold value The number of memory cells whose voltage is less than the second reference voltage is counted. The count values in the two verify processes are stored in the evaluation value count register circuit 20, and the difference between them is calculated.

Through the above processing, the memory cells within the distribution range from the threshold voltage (Vp−ΔVpgm (i−1)) to the write completion reference voltage Vp are classified as the class A _i , and the difference between the count values in the two verification processes Is derived as the number of memory cells (evaluation value) N _i of class A _i .

Next, the state machine 16 uses the evaluation value N _i stored in the evaluation value counting register circuit 20 to evaluate the write voltage increase amount ΔVpgm (i) corresponding to the evaluation value N _i in the storage circuit 21. to get access to the control table of the values _{N i} with .DELTA.Vpgm (i). Then, the row voltage control circuit 15 is controlled to supply the row decoder 13 with Vpgm (i) {= Vpgm (i−1) + ΔVpgm (i)} corresponding to the acquired ΔVpgm (i). Write processing is executed for all memory cells to be written. As a result, the threshold voltages of all unwritten memory cells are increased by a voltage corresponding to the increase amount ΔVpgm (i), and the threshold voltages of all or almost all of the memory cells of the class A _i are equal to or higher than the write completion reference voltage Vp. The writing is completed. At this point, the next class A _{i + 1} is in a state immediately before writing, and the next cycle of the classification process, the evaluation process, and the writing process can be started.

  Thereafter, the classification process, the evaluation process, and the writing process are repeatedly executed for each class until the writing of all the memory cells is completed.

However, in this sequential execution method, since the write voltage increase amount ΔVpgm (i−1) in the previous write process is used as the threshold voltage distribution width of the class A _i , the write voltage increase amount ΔVpgm (derived in the write process) is used. There is a slight error with i), but in the evaluation process, it is impossible to use the unknown write voltage increase ΔVpgm (i) at that time, and the derived write voltage increase ΔVpgm (i) is used again. If the evaluation process is re-executed, it becomes a circular reference, and there is a possibility that the process will not converge.

Next, a description will be given control table of the storage circuit 21 incorporated in the evaluation values N _i with .DELTA.Vpgm (i) used in the writing process.

First, the evaluation values (number of memory cells) of a certain continuous class A _i , A _i-1 are set to N _i , N _i-1, and the total number of all memory cells to be written is set to the evaluation value N ₀ , Then, the probability P _i , P _i−1 , P ₀ given by the reciprocals of the evaluation values N _i , N _i−1 , N ₀ is expressed as a cumulative probability distribution function of a normal distribution as shown in the following equations 5 to 7. Pr {k _i }, Pr {k _i-1 } Pr {k ₀ }, and the inverse function of each cumulative probability distribution function Pr {k _i }, Pr {k _i-1 } Pr {k ₀ }, k _i , k _i−1 , and k ₀ are respectively defined.

On the other hand, when the write processing for all the memory cells is performed with the write voltage increase amount ΔVpgm (i) fixed to a constant value regardless of the number of write processes i, the target threshold voltage distribution width after the completion of write is realized. When the write voltage increase amount is ΔVpgm (0) and the write processing is performed on all the memory cells with the write voltage increase amount ΔVpgm (0), the standard deviation S ₀ of the threshold voltage distribution after the completion of writing is described. Is defined in advance as a known number.

Next, using the k _i , k _i−1 , k ₀ and S ₀ defined in the above manner, the class A _i of the evaluation value N _i is applied to the memory cell of the class A _i when it is just before the completion of writing. The amount of increase ΔVpgm (i) from the write voltage Vpgm (i−1) of the write process one time before the write voltage Vpgm (i) to be determined is determined by the recurrence formula shown in Equation 8 below. Note that k _i , k _i−1 , k _0, and S _{0 to be used} are derived in advance as known numbers and incorporated in a sequential circuit in the state machine 16, or are included in software code executed by the state machine 16. Store it.

(Equation 8)
ΔVpgm (i) = ΔVpgm (i -1) -2 × (k i -k i-1) × S 0

In Equation 8, ΔVpgm (i-1), when the class _{A i-1} of the evaluation value _{N i-1} in step memory cell before writing process to be written immediately before the completion of the class _{A i} is immediately before the completion of writing The increase amount of the write voltage Vpgm (i−1) applied to the memory cell of class A _{i−1 from} the write voltage Vpgm (i−2) of the previous write process.

  As described above, since the first write voltage ΔVpgm (1) uses a value determined statistically or empirically in advance as described above, ΔVpgm (1) obtained by Equation 8 is calculated in the first write step. Not used.

An example of the comparison table derived as described above is shown in FIG. In the comparison table shown in FIG. 2, the evaluation value N _i of the class A _i immediately before the completion of writing, the write voltage increase ΔVpgm (i) in the writing process in which writing to the memory cell of the class A _i is completed, and writing one time before The difference {ΔVpgm (i) −ΔVpgm (i−1)} of the write voltage increase amount ΔVpgm (i−1) in the writing process in which the memory cell of the class A _i−1 that was immediately before completion is written is described. Yes. Accordingly, the current write voltage increase amount ΔVpgm (i) can be calculated by sequentially adding the difference to the previous write voltage increase amount ΔVpgm (i−1). Further, the write voltage Vpgm (i) to be applied this time can be derived by adding the calculated current write voltage increase ΔVpgm (i) to the write voltage Vpgm (i−1) used in the previous write process. .

In the comparison table shown in FIG. 2, all the memory cells to be written are classified into 13 classes, and the write voltage increase ΔVpgm (i) (i = 5 to 8) is 0 for the classes A _{5 to} A _{8 having} the large evaluation value. .1V. As described above, the threshold voltage distribution width after completion of writing of each class becomes wider as the evaluation value (the number of memory cells) becomes larger, but the write voltage increase amount ΔVpgm (i) (i = 5 to 8) with respect to these classes. ). Further, for other classes A _j (j = 1 to 4, 9 to 13) having a small evaluation value, the threshold voltage distribution width after writing is narrowed by the amount of the evaluation value N _j being small. Even if the write voltage increase amount ΔVpgm (j) is increased according to the degree, the write voltage increase amount ΔVpgm (j) can be kept within the threshold voltage distribution after completion of writing of the classes A _{5 to} A ₈ . That is, the relationship between the evaluation value _{N j} small class _{A j} for the write voltage increment .DELTA.Vpgm (j) the evaluation value _{N i} write voltage increase .DELTA.Vpgm to the maximum of class _{A i} (i) is the number 8 The recurrence formula shown in

As an example, in the comparison table shown in FIG. 2, since the minimum value of the write voltage increase amount ΔVpgm (i) is 0.1 V, the threshold voltage distribution width after completion of writing of all the memory cells is also close to 0.1 V. Become. In other words, according to the method of the present invention, in order to realize the threshold voltage distribution width after the completion of 0.1 V writing, the writing process is performed on all the memory cells with an even writing voltage increase amount ΔVpgm (i) of 0.1 V. There is no need to perform this, and the number of writing steps can be greatly reduced. As a comparative example, the relationship between the number of write steps i and the write voltage increase amount ΔVpgm (i) when the write process is performed on all the memory cells with a uniform write voltage increase amount ΔVpgm (i) of 0.1 V is shown. As shown in FIG. The write voltage Vpgm (i) in this embodiment shown in FIG. 2 covers a voltage range of about 6 to 8 V by repeating the write process 13 times, whereas the conventional write method shown in FIG. The same voltage range is covered by repeating the writing process 19 times.

  2 and 3, in the present embodiment, writing of all the memory cells is completed in 13 writing processes, whereas in the conventional writing method, 19 writing processes are required. It can be seen that the write processing time can be reduced by about 32%.

  Actually, when two kinds of writing processes are executed with the writing voltage Vpgm (i) shown in FIGS. 2 and 3 using the memory cells in the same address area of the same sample, The threshold voltage distribution width after completion of the same writing could be obtained.

  FIG. 4 shows the relationship between the write voltage Vpgm (i) derived in the above manner and the number of write processes i. Further, FIG. 5 shows the relationship between the write voltage increase amount ΔVpgm (i) derived in the above manner and the number of write processes i.

As shown in FIG. 4 and FIG. 5, when the write process repeated three times or more is divided into three stages in time, the write voltage Vpgm (i) changes greatly between the first and last stages, that is, the write voltage. The increase amount ΔVpgm (i) is large, and in the intermediate stage, the write voltage increase amount ΔVpgm (i) is smaller than the first and last stages and takes a minimum value. More specifically, if the evaluation value N _i of the class A _i that is written in the i-th writing step is larger than the evaluation value N _j of the class A _j that is written in the j-th writing step, i The write voltage increase amount ΔVpgm (i) from the previous time in the first write step is smaller than the write voltage increase amount ΔVpgm (j) from the previous time in the jth write step. That is, by sequentially repeating the writing process, writing is completed from a class having a small evaluation value to a class having a large evaluation value, and from the point when the writing of about half of the memory cells is completed, the evaluation value is evaluated from the class having a large evaluation value. FIGS. 4 and 5 show how writing is completed to a small class.

  As described above, in the present embodiment, in the writing process, the state machine 16 accesses the comparison table built in the storage circuit 21 to acquire ΔVpgm (i) or equivalent information, and the row voltage control circuit 15 Control is performed so that Vpgm (i) {= Vpgm (i−1) + ΔVpgm (i)} corresponding to the acquired ΔVpgm (i) is supplied to the row decoder 13, and write processing is performed on all unwritten memory cells. Execute.

  Here, the row voltage control circuit 15 (corresponding to the write voltage generation circuit) includes, for example, a D / A conversion circuit as an example. This D / A conversion circuit is a circuit that receives a digital input corresponding to a voltage value of ΔVpgm (i) and outputs an analog voltage of a voltage value of ΔVpgm (i). By the way, as shown in FIGS. 4 and 5, when the write process repeated three times or more is divided into three stages in time, the write voltage Vpgm (i) greatly changes in the first and last stages, that is, The write voltage increase amount ΔVpgm (i) is large, and in the intermediate stage, the write voltage increase amount ΔVpgm (i) is smaller than in the first and last stages, so the write voltage Vpgm (i) which is an analog output of the D / A conversion circuit. If the discrete distribution of is divided into three or more sections evenly in the entire voltage range of the distribution, by setting the number of analog outputs to be selected as the section closer to the center of the distribution, Efficient D / A conversion processing is possible.

Second Embodiment
In the present embodiment, the categorization process and the evaluation process of the method of the present invention executed in the course of the actual write operation in the first embodiment are performed in advance based on experiments and simulations, and the results are written in the write process. A comparison table showing the relationship between the number of times i and at least one of the write voltage increase amount ΔVpgm (i), the change amount of the write voltage increase amount ΔVpgm (i), and the write voltage Vpgm (i) is created and stored. It is built in the circuit 21.

  In addition, the natural threshold voltage distribution shape (distribution width, etc.) of all the memory cells can be predicted in advance based on experiments and simulations. A natural threshold voltage distribution predicted based on simulation is used.

  Therefore, in the present embodiment, in the writing operation executed by the apparatus of the present invention, the classification process and the evaluation process are not performed, and only the writing process is executed using the comparison table storing the results of the classification process and the evaluation process.

  In the writing process, in the i-th writing process, the state machine 16 accesses the comparison table built in the memory circuit 21 with the number of times i as an input, and writes the write voltage increase amount ΔVpgm (i) and the write voltage increase amount ΔVpgm ( At least one of the change amount of i) and the write voltage Vpgm (i) is acquired, and the write voltage Vpgm (i) is derived. Then, the row voltage control circuit 15 is controlled so as to supply the derived write voltage Vpgm (i) to the row decoder 13, and a write process is executed for all unwritten memory cells. This writing process is repeated until all the memory cells are completely written.

  As a result, in this embodiment, the classification process and the evaluation process can be omitted in the actual writing operation, so that the processing procedure of the writing operation in the apparatus of the present invention is simplified and the throughput is improved. In the present embodiment, the evaluation value counting register circuit 20 used in the first embodiment is not required in the device of the present invention.

In this embodiment, the classification process and the evaluation process can be separately performed separately from the writing process. Therefore, in addition to the sequential execution method shown in the first embodiment, all the memory cells are once written in the evaluation process. The method of completing can be adopted. That is, a plurality of write voltages Vpgm (i) having a voltage difference corresponding to the width of the threshold voltage distribution of each class A _i are sequentially applied to all the memory cells, and each time the write process by the application of the write voltage Vpgm (i) is completed. Then, a read operation (verify process) using the write completion reference voltage Vp as a reference voltage is executed to count the number of memory cells in a write state, and a difference in the total number between adjacent classes A _i-1 is obtained. , it can be derived evaluation value _{N i} of each class _{a i.} Note that the increase amount ΔVpgm (i) between the adjacent classes A _i and A _{i−1 of} the write voltage Vpgm (i) is derived according to the recurrence formula of Equation 8 as in the first embodiment. Shall.

<Third Embodiment>
In the present embodiment, another embodiment of the classification process and the evaluation process of the method of the present invention will be described. The evaluation step of this embodiment, unlike the first and second embodiments, only a read operation (verification processing) without writing process to derive the evaluation value N _i of each class A _i.

Specifically, first, in the classification process, the range between the lower limit value Vth ₀ and the upper limit value Vth _N of the natural threshold voltage distribution of all the memory cells is divided into N regions and assigned to each class A _i .

Subsequently, in the evaluation process, the verify process is executed on all the memory cells using the upper limit value Vth _i or the lower limit value Vth _i−1 of the threshold voltage distribution of each class A _i as a reference voltage, and reading is performed for each class A _i. among the threshold voltage of each memory cell aggregates the number of memory cells in the lower limit value Vth _i-1 from the high-voltage side or the upper limit value Vth _i on either side of the low-voltage side relative to the reference voltage, the adjacent The difference of the total number between classes A _i and A _i-1 or between classes A _{i + 1} and A _i can be obtained, and the evaluation value N _i of each class A _i can be derived. The derived evaluation value N _i is stored in the evaluation value counting register circuit 20.

Here, the probability P _i given by the reciprocal of the evaluation value N _i of the class A _i is expressed by the cumulative probability distribution function Pr {k _i } of the normal distribution as shown in the above formula 5, and the cumulative probability distribution function Pr {k _i } Define k _i by the inverse function of. Further, the total number of all memory cells to be written is set as an evaluation value N ₀ .

On the other hand, when the write voltage increase amount ΔVpgm (i) is fixed to a constant value regardless of the number of write processes i (that is, the threshold voltage distribution width of each class A _i ), When the write voltage increase amount when the target threshold voltage distribution width after completion of write is realized is ΔVpgm (0), and write processing is performed on all the memory cells with the write voltage increase amount ΔVpgm (0). The standard deviation S ₀ of the threshold voltage distribution after completion of writing is defined as a known number in advance.

Here, the predicted value of the threshold voltage distribution width W _i after the writing is completed when the writing process is performed independently for each class A _i memory cell and the writing is completed is calculated by the following equation (9). .

(Equation 9)
W _i = 2 × k _i × S ₀

The known set value or function previously derived on the change amount of the threshold voltage in the write conditions for obtaining the distribution width W _i, the upper limit value of the shape and position (distribution of the threshold voltage distribution after the writing process of each class A _i And lower limit).

Therefore, in the write process, the write voltage under the individual write condition is applied to each class A _i memory cell by using the predicted value of the threshold voltage distribution width W _i after the completion of the write of each class A _i obtained in Equation 9. By applying Vpgm (i), the write condition of each class A _i is set so that the threshold voltage distribution after the write process of each class A _i falls within the threshold voltage distribution after the completion of the write of all the target memory cells. Set. In the setting of the write condition, it is possible to align the upper limit value of the threshold voltage distribution after the writing process of each class A _i, the lower limit value, the median value or the like in each class A _i.

In the write process, a write process is executed for each class _Ai memory cell under the write conditions set in the above manner. The writing process is repeated until the writing of all the memory cells of all classes is completed.

Here, each of the evaluation value calculation process in the evaluation process, the write condition setting process in the write process, and the write process is performed sequentially for each class A _i , and all class memory cells On the other hand, it is possible to use both batch execution methods for executing each process in a batch. However, in the case of the collective execution method, a recording area for storing evaluation values N _i and writing conditions for all classes A _i together is required.

  Next, another embodiment of the device of the present invention and the method of the present invention will be described.

  <1> In each of the above embodiments, as shown in FIG. 1, the nonvolatile storage circuit 21 for storing the contents of the comparison table is provided. However, instead of storing the comparison table in the storage circuit 21, FIG. As shown in FIG. 6, it may be incorporated in the sequential circuit 16a in the state machine 16 or may be stored in software code executed by the state machine 16.

<2> In each of the above embodiments, as an example, a D / A conversion circuit is provided in the low voltage control circuit 15, and this D / A conversion circuit accepts a digital input corresponding to a voltage value of ΔVpgm (i). However, instead of providing a comparison table, the D / A conversion circuit has an evaluation value N _i of class A _i that is an input of the comparison table. A configuration may be adopted in which the number i of the writing process is received as a digital input, and a writing voltage having a voltage value ΔVpgm (i) is directly output as an analog signal.

<3> In the above embodiments, the description has been given of the case of changing depending on the evaluation value N _i increasing amounts of the writing process of the previous one write voltage applied to the control gate, depending on the evaluation value N _i The write condition to be changed is not necessarily limited to the write voltage applied to the control gate. Depending on the writing principle of the memory cell, the voltage applied to the other electrode of the memory cell may be the control target.

  <4> In each of the above embodiments, the flash EPROM memory cell having the MOSFET structure provided with the floating illustrated in FIG. 7 is assumed as the memory cell, but the structure of the memory cell is a stack type floating structure illustrated in FIG. It is not limited to.

  INDUSTRIAL APPLICABILITY The nonvolatile semiconductor memory device and the writing method thereof according to the present invention can be used for a nonvolatile semiconductor memory device, and more specifically, a write target memory including a plurality of memory cells to be written to the nonvolatile semiconductor memory device. This is effective for a writing method for a cell group.

The block diagram which shows typically the structure in one Embodiment of the non-volatile semiconductor memory device based on this invention The figure explaining the comparison table | surface which shows the correspondence of the evaluation value of each class used with the non-volatile semiconductor memory device which concerns on this invention, and the write voltage increase amount Comparison table showing the relationship between the number of write steps and the amount of increase in write voltage in the conventional write method Explanatory drawing which shows the relationship between the write-in voltage derived | led-out obtained with the writing method of the non-volatile semiconductor memory device based on this invention, and the frequency | count of a write-in process The figure which shows the relationship between the write voltage increase amount derived | led-out obtained with the writing method of the non-volatile semiconductor memory device based on this invention, and the frequency | count of a write-in process The block diagram which shows typically the structure in another embodiment of the non-volatile semiconductor memory device which concerns on this invention Device sectional view schematically showing an example of a memory cell structure of a conventional flash EPROM 7 is an equivalent circuit diagram of the memory cell shown in FIG. A block diagram schematically showing a configuration example of a conventional nonvolatile semiconductor memory device The figure which shows the threshold voltage distribution after erasing and the natural threshold voltage distribution in the conventional nonvolatile semiconductor memory device The figure which shows the relationship between the frequency | count of writing in the conventional non-volatile semiconductor memory device, and a write voltage. The figure explaining transition of the threshold voltage distribution of the memory cell during the write operation in the conventional nonvolatile semiconductor memory device The figure explaining transition of the threshold voltage distribution of the memory cell during the write operation in the conventional nonvolatile semiconductor memory device The figure explaining transition of the threshold voltage distribution of the memory cell during the write operation in the conventional nonvolatile semiconductor memory device The figure explaining transition of the threshold voltage distribution of the memory cell during the write operation in the conventional nonvolatile semiconductor memory device The figure explaining transition of the threshold voltage distribution of the memory cell during the write operation in the conventional nonvolatile semiconductor memory device The figure which shows the relationship of the threshold voltage distribution of the class from which the number of memory cells differs in the conventional non-volatile semiconductor memory device The figure which shows the relationship of the threshold voltage distribution of the class from which the number of memory cells differs in the non-volatile semiconductor memory device which concerns on this invention

1: floating gate 2: channel 3: insulating film 4: control gate 5: tunnel gate insulating film 6: source diffusion, source electrode 7: drain diffusion, drain electrode 10: memory cell array 11: sense amplifier circuit 12: column (column) Decoder 13: Row (row) decoder 14: Column voltage control circuit 15: Row voltage control circuit 16: State machine 16a: Sequential circuit (reference table)
17: I / O buffer 18: Address buffer 19: Command state logic interface 20: Evaluation value counting register circuit 21: Memory circuit (reference table)
A _i , A _j : Class DE: Threshold voltage distribution after erasure DP1: Natural threshold voltage distribution DP2 to DP4: Moved threshold voltage distribution after application of write voltage DX, DY, DZ: Write completed for each write voltage application Area combined threshold voltage distribution R _i , R _j : Threshold voltage distribution width Vpgm: Write voltage Vpv: Write completion reference threshold voltage Wvtp: Threshold voltage distribution width after final write completion X1 to X3: Threshold after write voltage application Write completed area in voltage distribution ΔVpgm: Increase in write voltage

Claims (19)

For a set of all or part of the memory cells to be written consisting of a plurality of memory cells having a MOSFET structure to be written to the nonvolatile semiconductor memory device,
A classification step of classifying each of the memory cells into three or more classes defined by a distribution range of the threshold voltage according to a threshold voltage of the MOSFET structure that changes according to a storage state of the memory cell;
An evaluation step of deriving the number of the memory cells belonging to each class classified in the classification step as an evaluation value of each class;
A writing step of performing a writing process on the memory cells of each class under a write condition that changes a change amount of a write voltage applied to a predetermined electrode of the memory cell according to the evaluation value of each class;
A writing method for a nonvolatile semiconductor memory device, comprising: In the evaluation step, each memory read out by each class by performing a read operation on the memory cells in the set using the upper limit value or the lower limit value of the threshold voltage distribution of each class as a reference voltage Summing up the number of the memory cells on either the high voltage side or the low voltage side with respect to the reference voltage among the threshold voltages of the cells, obtaining the difference of the summation number between the adjacent classes, The method for writing to a nonvolatile semiconductor memory device according to claim 1 , wherein the evaluation value of each class is derived. In the evaluation process, the run by a plurality of the write voltage of the voltage difference corresponding to the width of the threshold voltage distribution of each class is sequentially applied to the memory cells in the set, writing in one of the write voltage Each time the operation is completed, a read operation is performed using a reference threshold voltage that defines a write state of the memory cell as a reference voltage, and the number of the memory cells in the write state is counted, and the adjacent classes are classified. the calculated aggregate number of the difference, nonvolatile writing method of the semiconductor memory device according to claim 1, wherein the deriving the said evaluation value of each class. In the evaluation process, the run by a plurality of the write voltage of the voltage difference corresponding to the width of the threshold voltage distribution of each class is sequentially applied to the memory cells in the set, writing in one of the write voltage Every time the operation is completed, a voltage difference between the first read operation using the first reference threshold voltage that defines the write state of the memory cell as a reference voltage and the threshold voltage distribution width of the class to be evaluated is erased. And performing a second read operation using a second reference threshold voltage as a reference voltage to count the number of memory cells in an erased state in the first read operation, and The number of the memory cells that are in a write state in two read operations is totaled, a difference between the two total numbers is obtained, and the evaluation values of the classes to be evaluated are sequentially derived. Writing method of the nonvolatile semiconductor memory device according to Motomeko 1. The condition for changing the amount of change in the write voltage according to the evaluation value of each class among the write conditions used in the write process is as follows when the write process is completed for the entire set. 5. The nonvolatile semiconductor memory according to claim 1 , wherein the nonvolatile semiconductor memory is derived based on a standard deviation of a threshold voltage distribution of the entire set and a number of the memory cells belonging to each class. Device writing method. In the write step, by sequentially executing the write process while changing the amount of change in the write voltage in the write condition, when sequentially transitioning the memory cells in the set to a write state,
The amount of change in the write voltage, characterized in that a group of the memory cells to transition to the write state by the write voltage after the change is applied to set smaller the larger the evaluation value of the class belonging writing method of the nonvolatile semiconductor memory device according to any one of claims 1 to 5. In the write process, the progresses of execution times of the writing process of sequentially executed while changing the amount of change in the write voltage, the write voltage to have a variation amount minimum value of the write voltage is changed in the write condition A writing method for a nonvolatile semiconductor memory device according to claim 1 , wherein: The write voltage, the writing method of the nonvolatile semiconductor memory device according to any one of claims 1-7, characterized in that a write gate voltage applied to the gate electrode of the memory cell. In determining the amount of change in the write voltage applied to the write process for the memory cells of each class in the write step,
When the evaluation value N _i of the arbitrary number i-th class is greater than the evaluation value N _{j of the} arbitrary j-th class different from the arbitrary number _i (N _i > N _j ),
In the write process one time before the write voltage Vpgm (i) in the write process to the memory cell belonging to the class when the memory cell belonging to the arbitrary number i-th class is in the threshold voltage region immediately before the write The amount of change ΔVpgm (i) from Vpgm (i−1) of the write voltage is the memory belonging to the class when the memory cell belonging to the arbitrary number j-th class is in the threshold voltage region immediately before writing. The write voltage Vpgm (j) in the write process for the cell is determined to be smaller than a change amount ΔVpgm (j) of the write voltage from Vpgm (j−1) in the write process one time before. A method for writing into a nonvolatile semiconductor memory device according to claim 1 or 8 . In determining the amount of change in the write voltage applied to the write process for the memory cells of each class in the write step,
When the memory cell belonging to an arbitrary number i of the class is in the threshold voltage region immediately before writing, the writing voltage Vpgm (i) in the writing process for the memory cell belonging to the class is written one time before the writing process. A change amount ΔVpgm (i) of the write voltage from Vpgm (i−1) is given by a recurrence formula shown in the following equation (1).
(Equation 1)
ΔVpgm (i + 1) -ΔVpgm ( i) = - 2 × (k i + 1 -k i) × S 0

K _{i + 1} and k _i if the arbitrary number i of the number of 1 is 1 or more, the reciprocal of the evaluation value N _i (i + 1) th of the evaluation value N _{i + 1} and i-th of said classes of the class Each inverse function when the given probabilities P _{i + 1} and P _i are expressed by the cumulative distribution functions Pr {k _{i + 1} } and Pr {k _i } of the normal distribution as shown in the following equations 2 and 3. Given,


The probability P ₀ given by the reciprocal of the number N ₀ of the memory cells in the whole set is k ₀ when the arbitrary number i in the number 1 is 0. It is given as an inverse function when expressed by a cumulative probability distribution function Pr {k ₀ },

ΔVpgm (0) in the case where the arbitrary number i in the equation 1 is 0, the change amount ΔVpgm (i) is fixed to a constant value regardless of the arbitrary number i, and the writing process of the memory cells in the entire set is performed. When completed, the threshold voltage distribution width of the entire set is given by the amount of change when it becomes the target threshold voltage distribution width,
When S _{0 in} Equation (1) completes the writing process of the memory cells in the entire set by fixing the change amount ΔVpgm (i) to ΔVpgm (0) regardless of the arbitrary number i. writing method of the nonvolatile semiconductor memory device according to claim 1 or 8, characterized in that given a standard deviation of threshold voltage distributions. The classification step and the evaluation step are executed in advance by an experiment or simulation using a sample different from the nonvolatile semiconductor memory device before the writing step is actually executed in the nonvolatile semiconductor memory device. The write condition according to the evaluation value of each class obtained as an execution result is derived in advance and stored in the nonvolatile semiconductor memory device. 11. The writing method of the nonvolatile semiconductor memory device according to any one of 10 above. A method for writing into a nonvolatile semiconductor memory device according to any one of claims 1 to 10 , wherein all or part of a set of memory cells in a write target memory cell group including a plurality of memory cells to be written is set. A non-volatile semiconductor memory device that can be written to,
Classification means capable of executing the classification step of the writing method;
Evaluation means capable of executing the evaluation step of the writing method;
Writing means capable of executing the writing step of the writing method;
A non-volatile semiconductor memory device comprising: Before Symbol evaluation means, within said set, non of claim 12, wherein the threshold voltage is characterized by comprising an aggregate capable aggregator a number of predetermined reference voltage below or above the memory cells Semiconductor memory device. 14. The nonvolatile semiconductor memory device according to claim 13 , wherein the evaluation unit includes a register circuit that stores the number of the memory cells counted by the counting unit. The writing means receives the evaluation value of each class and inputs the write voltage , the change amount of the write voltage, or the change amount of the write voltage in the write condition set in advance for the evaluation value. The nonvolatile semiconductor memory device according to claim 12 , further comprising a write condition comparison table that outputs a change amount. When the evaluation value of each class is input to the writing means, a sequential circuit that outputs the write voltage , the change amount of the write voltage, or the change amount of the change amount of the write voltage under the write condition . The nonvolatile semiconductor memory device according to claim 12, comprising: The nonvolatile semiconductor memory device writing method according to claim 11 , wherein the nonvolatile memory capable of writing to all or a part of the set of memory cells of the write target memory cell group including a plurality of memory cells to be written. A semiconductor memory device,
A storage circuit that stores the write conditions according to the evaluation values of the classes obtained by executing the classification step and the evaluation step in advance as a comparison table;
Writing means capable of executing the writing step of the writing method based on the writing conditions stored as the comparison table;
A non-volatile semiconductor memory device comprising: The writing means is configured to determine a predetermined voltage of the memory cell based on a write voltage, a change amount of the write voltage, or a change amount of the change amount of the write voltage in the write condition according to the evaluation value of each class. The nonvolatile semiconductor memory device according to claim 15 , further comprising a write voltage generation circuit that outputs the write voltage applied to the electrode. The write voltage generation circuit is composed of a D / A conversion circuit,
When the discrete distribution of the write voltage, which is an analog output selected by the digital input of the D / A conversion circuit, is equally divided into three or more sections, the distribution voltage is closer to the center of the distribution. 19. The non-volatile semiconductor memory device according to claim 18 , wherein the number of analog outputs to be selected is larger for each of the categories.