JP4654574B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device in which a low potential reference circuit and a high potential reference circuit are mixedly mounted. More specifically, the present invention relates to a semiconductor device including a high breakdown voltage MOS that mediates signal transmission between a low potential reference circuit and a high potential reference circuit.

  Conventionally, a semiconductor device in which a low potential reference circuit and a high potential reference circuit are mixedly used is widely used for a power device or the like. Such a semiconductor device generally has a structure as shown in FIG. That is, a low potential reference circuit region 1 and a high potential reference circuit region 2 are provided, and the high potential reference circuit region 2 is surrounded by a high breakdown voltage isolation region 3 formed by a RESURF structure or the like. A high breakdown voltage NMOS 5 and a high breakdown voltage PMOS 6 are provided for signal transmission (level shift) between the low potential reference circuit region 1 and the high potential reference circuit region 2. Specifically, for the level shift from the low potential reference circuit region 1 to the high potential reference circuit region 2, a high breakdown voltage NMOS 5 disposed in the low potential reference circuit region 1 is used. On the other hand, for the level shift from the high potential reference circuit region 2 to the low potential reference circuit region 1, a high breakdown voltage PMOS 6 disposed in the high potential reference circuit region 2 is used. Each drain wiring is drawn from the input side region to the output side region across the high breakdown voltage isolation region 3.

  FIG. 17 shows an example of a circuit that performs a level shift from the low potential reference circuit region 1 to the high potential reference circuit region 2. This circuit includes a high breakdown voltage NMOS 5, a pull-up resistor 101, and a Zener diode 102. As the high voltage NMOS 5 is turned on / off, a potential difference corresponding to the power supply voltage in the high potential reference circuit region 2 is generated at the drain. Thereby, a level shift between the low potential reference circuit region 1 and the high potential reference circuit region 2 is performed. For example, it is assumed that the power supply voltages in the low potential reference circuit region 1 and the high potential reference circuit region 2 are both 15V, and the potential difference between the low potential reference circuit region 1 and the high potential reference circuit region 2 is 1000V. In this case, a signal swung at 0-15V in the low potential reference circuit region 1 is converted into a signal swinging at 1000-1015V through this circuit. As a result, the signal sent from the low potential reference circuit 1 can be used in the high potential reference circuit 2.

  Thus, in a semiconductor device that performs a level shift between the low potential reference circuit region 1 and the high potential reference circuit region 2, a signal is transmitted through a metal wiring (drain wiring) formed on the surface. The drain wiring passes over the low potential reference circuit region 1 and the high breakdown voltage isolation region 3 through the interlayer insulating film. At that time, the potential difference between the drain wiring having a high potential and the surface of the semiconductor device having a low potential increases. Therefore, there is a problem that the breakdown voltage is lowered by the drain wiring. Usually, in order to solve this problem, a thick interlayer insulating layer is formed between the drain wiring and the surface of the semiconductor device. However, if the potential difference between the high potential reference circuit region and the low potential reference circuit region exceeds 600 V, the wiring process becomes difficult and the cost increases due to the increase in thickness.

  As a technique for solving the above problem, for example, in Patent Document 1, a high breakdown voltage isolation region and a high-voltage MOS drift layer for level shift are integrally formed, and a drain is formed in a circuit region on the output side. An apparatus is disclosed. In this semiconductor device, since the drain wiring is not wired across the high breakdown voltage isolation region or the low potential reference circuit region, it is said that level shift can be performed without causing a breakdown voltage problem.

  In addition to this, for example, Patent Document 2 discloses a semiconductor device in which a part of an N-type high withstand voltage isolation region is divided by a P-type slit region and a high-voltage NMOS for level shift is formed at that part. It is disclosed. That is, the drain N-type layer of the high breakdown voltage NMOS and the N-type layer in the high potential reference circuit region are opposed to each other through the P-type slit region. A high potential drain wiring is disposed above the slit region. In this semiconductor device, the slit region is pinched off (integration of a depletion layer formed from both N-type layers). When pinched off, the surface of the P-type slit region has almost the same potential as the N-type layers on both sides. This is supposed to suppress the influence of the drain wiring.

In addition to this, for example, Patent Document 3 discloses a semiconductor device having an SOI structure in which an insulating region extending from the main surface of the semiconductor device to the buried insulating layer is provided, and a drain wiring is provided on the insulating region. A semiconductor device is disclosed. Thus, the distance between the drain wiring and the semiconductor layer that is at a high potential can be increased, so that the influence of the drain wiring can be suppressed.
JP-A-9-55498 JP-A-9-283716 Japanese Patent No. 3201719

  All of the semiconductor devices disclosed in these prior arts are devised so that the potential difference between the drain wiring and the surface of the semiconductor device does not become large when performing level shift. However, these semiconductor devices have the following problems.

  That is, in the semiconductor device disclosed in Patent Document 1, when the high breakdown voltage MOS is an NMOS, the drain N type layer of the high breakdown voltage NMOS is formed in contact with the N type layer in the high potential reference circuit region. . Therefore, the drain N-type layer of the high breakdown voltage NMOS and the N-type layer of the high potential reference circuit region are electrically connected. Therefore, there is a need for a mechanism that increases the parasitic resistance between the drain N-type layer of the high breakdown voltage NMOS and the N-type layer in the high potential reference circuit region. For this reason, in the semiconductor device disclosed in Patent Document 1, the high breakdown voltage isolation region is curved in the direction of the low potential reference circuit region, and a high breakdown voltage NMOS is formed in that portion. That is, the parasitic resistance is increased by increasing the distance between the drain N-type layer of the high breakdown voltage NMOS and the N-type layer in the high potential reference circuit region. However, the bending causes an increase in the chip area and prevents the entire substrate from being made compact. Further, since it is impossible to completely insulate the drain N-type layer of the high breakdown voltage NMOS and the N-type layer in the high potential reference circuit region, the generation of leakage current is inevitable. Therefore, power is wasted.

  Further, the semiconductor device disclosed in Patent Document 2 employs an arrangement in which the space between the drain N-type layer of the high breakdown voltage NMOS and the N-type layer in the high potential reference circuit region is depleted. However, if this distance is too close, punch-through breakdown occurs between the drain N-type layer of the high breakdown voltage NMOS and the N-type layer in the high potential reference circuit region. In other words, the distance between the two needs to be determined in consideration of the trade-off between breakdown voltage and punch-through breakdown. For this reason, depending on the required specification voltage, this trade-off relationship cannot be satisfied and the operating voltage is limited.

  In the semiconductor device disclosed in Patent Document 3, the thickness of the insulating region formed below the drain wiring must be increased. In Patent Document 3, this insulating region is formed by a LOCOS method (local oxidation method). However, the thickness of the oxide film that can be formed by the LOCOS method is about 1 to 2 μm. Therefore, it cannot be applied to high breakdown voltage type devices. In addition to the LOCOS method, a method of forming a trench in a semiconductor layer and filling the inside of the trench with an oxide film or a polycrystalline silicon layer is also conceivable. However, in this case as well, in order to increase the breakdown voltage between the drain wiring and the semiconductor layer, it is not sufficient to increase the thickness of the insulating region, and it is necessary to provide a certain width of the insulating region. However, if a wide trench exceeding 2 μm is formed, it is difficult to fill the trench with an oxide film or a polycrystalline silicon film, and the feasibility is poor. Further, in the semiconductor device disclosed in Patent Document 3, since the semiconductor layer constituting the element is divided by the insulating region, the potential distribution becomes non-uniform at the boundary with the insulating region, and electric field concentration tends to occur at that portion. .

  The present invention has been made to solve the problems of the conventional semiconductor device described above. That is, the subject is a semiconductor device in which a low-potential reference circuit and a high-potential reference circuit are mixedly mounted, and can be level-shifted between the low-potential reference circuit and the high-potential reference circuit, and is compact. Another object is to provide a semiconductor device with excellent breakdown voltage.

A semiconductor device designed to solve this problem is a semiconductor device in which a low-potential reference circuit and a high-potential reference circuit are mixedly mounted, and signals are transmitted between them. A relay semiconductor element that mediates transmission of signals to and from the circuit and is surrounded by an insulating partition wall in which an insulator is filled in a trench-like groove, and a plurality of relay semiconductor elements are provided ; The region of the low potential reference circuit and the region of the high potential reference circuit are partitioned by a region formed by annularly combining the insulating partition wall surrounding the relay semiconductor element, and the output wiring of the relay semiconductor element is connected to the insulating partition wall. Are arranged in the circuit area on the output side. Even in this semiconductor device, punch-through and leakage current between the relay semiconductor element and the circuit region on the output side can be avoided. Further, since the low potential reference circuit and the high potential reference circuit are partitioned by the relay semiconductor element, almost the same potential distribution is obtained in any part. Therefore, the problem of electric field concentration is alleviated.

Another semiconductor device of the present invention includes a first conductivity type semiconductor substrate, a second conductivity type first region formed on a main surface of the semiconductor substrate and forming a low potential reference circuit region, and a first region. And a second conductivity type second region which is formed on the semiconductor substrate and forms a high potential reference circuit region, and is located between the first region and the second region, and the first region and the second region, combining mediate the transmission of signals between a plurality of relay semiconductor device insulator in the trench-shaped groove is surrounded filled insulating partition wall, an insulating partition wall that surrounds the relay semiconductor device, the annularly surface And a third region formed so as to surround one of the first region and the second region as viewed from above, and the output wiring of the relay semiconductor element in the third region straddles the insulating partition, and the circuit region on the output side It is characterized by being arranged in.

Another semiconductor device according to the present invention includes a semiconductor substrate of the first conductivity type or the second conductivity type, an insulating film formed on the main surface of the semiconductor substrate, a low potential reference circuit formed on the insulating film. A first conductivity type first region forming a region, a second conductivity type second region formed on the insulating film and spaced apart from the first region, forming a high potential reference circuit region, the first region, and the second region A plurality of relay semiconductor elements that are located between the regions, mediate signal transmission between the first region and the second region, and are surrounded by an insulating partition filled with an insulator in a trench-like groove ; And a third region formed so as to surround one of the first region and the second region when viewed from the surface , and an insulating partition wall surrounding the relay semiconductor element. The output wiring of the element is arranged in the circuit area on the output side across the insulating partition. It is an.

  In the semiconductor device of the present invention, a relay semiconductor element is provided in the high breakdown voltage isolation region, and the output wiring of the relay semiconductor element is arranged so as to straddle the insulating partition. Thereby, the influence by the output wiring which is a high potential can be avoided. In addition, the relay semiconductor element is insulated from other circuit areas by an insulating partition. Therefore, it is not necessary to take measures against leakage current such as a curved portion. Therefore, according to the present invention, there is provided a semiconductor device in which a low potential reference circuit and a high potential reference circuit are mixedly mounted, and a level shift can be performed between the low potential reference circuit and the high potential reference circuit. In addition, a semiconductor device having an excellent breakdown voltage has been realized.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying the present invention will be described below in detail with reference to the accompanying drawings. In this embodiment, the present invention is applied to a power MOS mounted on an electric vehicle or the like.

[First embodiment]
The semiconductor device 100 according to the first embodiment has a structure shown in the plan view of FIG. Note that components having the same symbols as those of the conventional semiconductor device shown in FIG. 16 have the same functions as those components. The semiconductor device 100 includes a low potential reference circuit region 1 and a high potential reference circuit region 2, and constitutes a structure (Resurf structure) in which the high potential reference circuit region 2 is surrounded by a high breakdown voltage isolation region 3. By this high breakdown voltage isolation region 3, the low potential reference circuit region 1 and the high potential reference circuit region 2 are separated. Furthermore, a trench 4 is formed at the outer edge of the high breakdown voltage isolation region 3. The trench 4 is filled with an insulator such as silicon oxide. Therefore, the high potential reference circuit region 2 is insulated from the low potential reference circuit region 1. A part of the high breakdown voltage isolation region 3 is partitioned by a trench 4, and a high breakdown voltage NMOS 5 or a high breakdown voltage PMOS 6 is provided in the partitioned part. These MOSs are for performing signal transmission (level shift) between the low potential reference circuit region 1 and the high potential reference circuit region 2. Specifically, for the level shift from the low potential reference circuit region 1 to the high potential reference circuit region 2, a high breakdown voltage NMOS 5 in which the drain wiring 5d is arranged in the high potential reference circuit region 2 is used. On the other hand, for the level shift from the high potential reference circuit region 2 to the low potential reference circuit region 1, a high breakdown voltage PMOS 6 in which the drain wiring 6d is disposed in the low potential reference circuit region 1 is used.

FIG. 2 is a view showing a cross section of the AA portion in the semiconductor device 100 shown in FIG. That is, it is a diagram showing a cross section of the high breakdown voltage NMOS 5. The high breakdown voltage NMOS 5 is defined by the trench 4 among the N type epitaxial layers (low potential reference N type layer 81, high potential reference N type layer 82, and drift layer 85 in NMOS) formed on the P ⁻ type substrate 7. It is formed at the site. The high breakdown voltage NMOS 5 includes a gate polysilicon 50g, a gate oxide film 50x, a source N ⁺ region 50s, a drain N ⁺ region 50d, a body P ⁻ region 50b, and a body contact P ⁺ region 50bc. Yes. Furthermore, the body P ^- (typically 0V) region 50b and the same potential biased resurf P in ^- area 50r is provided. In addition, an NMOS drift layer 85, a field oxide film 9, an isolation P ⁺ diffusion region 10 and the like are provided. Further, as shown in FIG. 1, gate wiring 5g (not shown in FIG. 2), source wiring 5s, and drain wiring 5d are provided on the surface of the semiconductor device 100, and a level shift is performed thereby. It has become. An interlayer insulating film 11 is formed between the wirings 5g, 5s, 5d and the N type epitaxial layer. In the high breakdown voltage NMOS 5 having such a structure, a channel effect is caused in the body P ⁻ region 50b by applying a voltage to the gate polysilicon 50g, thereby establishing conduction between the source N ⁺ region 50s and the drain N ⁺ region 50d. Controlling.

FIG. 3 is a view showing a cross section of the BB portion in the semiconductor device 100 shown in FIG. That is, it shows a cross section of the high voltage PMOS 6. The high breakdown voltage PMOS 6 is also divided by the trench 4 among the N type epitaxial layers (low potential reference N type layer 81, high potential reference N type layer 82, and N type layer 86 in the PMOS) arranged on the P ⁻ type substrate 7. Formed at the site. The high breakdown voltage PMOS 6 is provided with a gate polysilicon 60g, a gate oxide film 60x, a source P ⁺ region 60s, a drain P ⁺ region 60d, and a sub-contact N ⁺ region 60sc. Further, a drift P ⁻ region 60dr formed of the same diffusion layer as the RESURF P ⁻ region 50r of the high breakdown voltage NMOS 5 is provided. In addition, similarly to the high breakdown voltage NMOS 5, a field oxide film 9, an isolation P ⁺ diffusion region 10 and the like are provided. Further, as shown in FIG. 1, the level shift is performed by each of the gate wiring 6g (not shown in FIG. 3), the source wiring 6s, and the drain wiring 6d. In the high breakdown voltage PMOS 6 having such a structure, a channel effect is caused in the N-type layer 86 in the PMOS by applying a voltage to the gate polysilicon 60g, and thus conduction between the source P ⁺ region 60s and the drain P ⁺ region 60d. Is controlling.

FIG. 4 is a view showing a cross section of the CC section in the semiconductor device 100 shown in FIG. That is, it is a view showing a cross section of the high breakdown voltage isolation region 3. The high breakdown voltage isolation region 3 is substantially the same as the high breakdown voltage NMOS 5 except that the trench 4 on the high potential reference circuit region 2 side and the gate polysilicon 50g are unnecessary compared to the high breakdown voltage NMOS 5 of FIG. It has a structure. The P-type diffusion regions 30b and 30bc in the high breakdown voltage isolation region 3 are regions corresponding to the body P ⁻ region 50b and the body contact P ⁺ region 50bc in the high breakdown voltage NMOS 5, respectively. The N-type diffusion region 30sc is a region corresponding to the sub-contact N ⁺ region 30sc in the high voltage PMOS 6 respectively. The surface potential distribution is designed to be substantially the same as that of the high breakdown voltage NMOS 5 and the high breakdown voltage PMOS 6.

FIG. 5 is a view showing a cross section of the DD portion in the semiconductor device 100 shown in FIG. That is, FIG. 3 is a view showing a cross section of the high voltage NMOS 5 orthogonal to the cross section of FIG. The high breakdown voltage NMOS 5 is surrounded by the trench 4, and the bottom of the trench 4 reaches the P ⁻ type substrate 7. Therefore, the drift layer 85 in NMOS is electrically insulated from the isolation region N-type layer 83 in addition to the low potential reference N-type layer 81 and the high potential reference N-type layer 82.

The feature of the semiconductor device 100 of this embodiment is that the high breakdown voltage NMOS 5 and the high breakdown voltage PMOS 6 are arranged in a region where the high breakdown voltage isolation region 3 is partitioned by the trench 4. In the semiconductor device 100, the high potential drain wiring 5d in the high breakdown voltage NMOS 5 (the low potential drain wiring 6d in the high breakdown voltage PMOS 6) does not straddle the low potential portion (the high potential portion in the high breakdown voltage PMOS 6). Therefore, the problem of withstand voltage does not occur. This is the same as the semiconductor device disclosed in Patent Document 1 or the like, but in the semiconductor device 100, the high voltage NMOS 5 is completely separated from the high potential reference circuit region 2 by the trench 4. Therefore, no leak current or punch-through breakdown occurs between the drain N ⁺ region 50d and the high potential reference N-type layer 82. Therefore, it is not necessary to provide a curved portion like the semiconductor device of Patent Document 1, and the area loss is suppressed. Further, unlike the semiconductor device disclosed in Patent Document 2, it is not necessary to consider the trade-off between the breakdown voltage and the punch-through breakdown, and the use voltage is not limited. In the semiconductor device 100 of this embodiment, the breakdown voltage between the drain wiring 5d and the substrate is determined by the depth of the trench 4. Further, the breakdown voltage between the drain N ⁺ region 50 d and the high potential reference N-type layer 82 is determined by the width of the trench 4. Therefore, the breakdown voltage can be adjusted by the size of the trench 4.

Further, the width of the trench 4 in the semiconductor device 100 of this embodiment is smaller than the width of the P-type slit region exposed on the surface of the semiconductor device of Patent Document 2. Therefore, the area loss is small even when compared with the semiconductor device of Patent Document 2. Specifically, the width 2L of the P-type slit region needs to satisfy at least the following formula (1) in order to ensure a withstand voltage against punch-through breakdown.
2L> √ (2εV _PT / qN _P ) (1)
In equation (1), “ε” means the dielectric constant of silicon, “V _PT ” means the withstand voltage against punch-through breakdown, “q” means the amount of charge of electrons, and “N _P ” means the concentration of the P-type substrate. Yes. For example, when the substrate concentration N _P = 1.0 × 10 ¹⁴ cm ⁻³ generally used in punch-through breakdown voltage V _PT = 50 V and 1000 V class high breakdown voltage semiconductor devices is applied to the equation (1), 2L≈ 26 μm. On the other hand, in the semiconductor device 100 of this embodiment, when a silicon oxide film is used as the trench 4, it is generally necessary to select a film thickness that is 3 MV / cm or less. It ’s enough. Therefore, it can be seen that the area loss is small as compared with the semiconductor device of Patent Document 2.

In addition, since the trench 4 is formed in the semiconductor device 100 of this embodiment, the cost increases due to an increase in the number of process steps as compared with the conventional semiconductor device. However, the chip area can be greatly reduced by applying the trench 4 to isolation from a circuit such as bipolar or CMOS mounted on the semiconductor device 100. Therefore, the total cost can be reduced rather. In particular, in this type of high voltage semiconductor device, a circuit such as a CMOS is mounted on an N type epitaxial layer formed on a high resistance P ⁻ type substrate 7. Therefore, the thickness of the N-type epitaxial layer should be ensured so that punch-through breakdown does not occur between the P-type well region for CMOS or the P-type base region for bipolar and the P ⁻ -type substrate 7. Designed to. For example, to mount a 35V circuit, the thickness of the N-type epitaxial layer generally needs to be 25 μm or more. On the other hand, when the separation P ⁺ diffusion region is formed by thermal diffusion as in the prior art, the width of the region is required to be 15 μm or more along with the expansion in the width direction. Therefore, the method of dividing the region in the P ⁺ diffusion region has a larger area loss than the method of separating the region in the trench 4 as in the present embodiment. Therefore, the application of the trench 4 does not necessarily increase the total cost.

[Second form]
The semiconductor device 200 according to the second embodiment has a structure shown in the plan view of FIG. The semiconductor device 200 includes a low potential reference circuit region 1 and a high potential reference circuit region 2, and has a structure in which the high potential reference circuit region 2 is surrounded by the high breakdown voltage isolation region 3 as in the semiconductor device 100 of the first embodiment. It is composed. Furthermore, trenches 41 and 42 are formed in a part of the high breakdown voltage isolation region 3, and the high breakdown voltage isolation region 3 is partitioned into a plurality of regions. A high breakdown voltage NMOS 5 or a high breakdown voltage PMOS 6 is provided in the partitioned part. The difference from the semiconductor device 100 of the first embodiment is that the trenches 41 and 42 do not surround a part of the high voltage NMOS 5 and the high voltage PMOS 6, respectively. Specifically, no trench is formed on the source wiring side. Moreover, there is no trench formed at the outer edge of the high breakdown voltage isolation region 3.

FIG. 7 is a diagram showing a cross section of the EE portion in the semiconductor device 200 shown in FIG. That is, it is a diagram showing a cross section of the high breakdown voltage NMOS 5. In the high breakdown voltage NMOS 5, an N type epitaxial layer (a low potential reference N type layer 81, a high potential reference N type layer 82, a drift layer 85 within NMOS) is formed on the P ⁻ type substrate 7. The difference from the semiconductor device 100 of the first embodiment is that the trench 41 does not exist on the source wiring 5s side. Instead, the potential of the P ⁻ -type substrate 7 is taken by the isolation P ⁺ diffusion region 12 whose bottom reaches the P ⁻ -type substrate 7 from the low potential reference N-type layer 81 and the drift layer 85 in NMOS. On the other hand, the trench 41 separates the drift layer 85 in the NMOS and the high potential reference N-type layer 82. Further, by providing the left end in FIG. 6 in the trench 41 on the left side of the source N ⁺ region 50s, the high potential reference region 2 and the high breakdown voltage NMOS 5 are insulated. Therefore, no leak current or punch-through breakdown occurs between the high breakdown voltage NMOS 5 and the high potential reference circuit region 2. Furthermore, the total volume of the trench is small as compared with the semiconductor device 100 of the first embodiment. Therefore, the yield in the manufacture of the trench is good.

[Third embodiment]
The semiconductor device 300 according to the third embodiment has a structure shown in the plan view of FIG. The semiconductor device 300 includes a low potential reference circuit region 1 and a high potential reference circuit region 2, and has a structure in which the high potential reference circuit region 2 is surrounded by the high withstand voltage isolation region 3 as in the semiconductor device 100 of the first embodiment. It is composed. A high breakdown voltage NMOS 5 is provided in a part of the high breakdown voltage isolation region 3. Further, an outer wall trench 43 and an inner wall trench 44 are provided. In the semiconductor device 300 of this embodiment, unlike the semiconductor device 100 of the first embodiment, there is no trench that partitions the high breakdown voltage isolation region 3. Therefore, it is possible to prevent a decrease in breakdown voltage due to crystal defects or the like that are likely to occur in the vicinity of the trench.

If the purpose is to prevent the breakdown voltage from being lowered due to the crystal defects or the like of the trench, it can be achieved by using a trenchless structure like the semiconductor device 310 shown in FIG. However, in the semiconductor device 310, the drain N ⁺ region of the high breakdown voltage NMOS 5 and the high potential reference N-type layer are not separated and are electrically connected. Further, when a plurality of high breakdown voltage NMOSs 5 or high breakdown voltage PMOSs 6 are provided in the high breakdown voltage isolation region 3, they cannot be separated. In order to solve this problem, the semiconductor device 300 of this embodiment is provided with an inner wall trench 44 that completely surrounds the high potential reference circuit region 2. As a result, the drain N ⁺ region of the high breakdown voltage NMOS 5 is insulated from the high potential reference N-type layer. A parasitic resistance in the high breakdown voltage isolation region 3 is formed along the inner wall trench 44. In the semiconductor device 300 of this embodiment, the potential of the N ⁺ region 50 d on the high potential reference circuit region 2 side in the high breakdown voltage isolation region 3 is taken at the portion 13. The parasitic resistance between this portion 13 and the N ⁺ region 50d (drain N ⁺ region) of the high breakdown voltage NMOS 5 is a combined resistance of the parasitic resistance path 38 and the parasitic resistance path 39 in FIG. That is, by disposing them sufficiently apart, the resistance value can be increased, and the influence of leakage current and the like can be reduced.

[Fourth form]
The semiconductor device 400 according to the fourth embodiment has a structure shown in the plan view of FIG. The semiconductor device 400 includes a low potential reference circuit region 1 and a high potential reference circuit region 2, and has a structure in which the high potential reference circuit region 2 is surrounded by a high breakdown voltage isolation region 3. By this high breakdown voltage isolation region 3, the low potential reference circuit region 1 and the high potential reference circuit region 2 are separated. Furthermore, a loop-shaped trench group 40 is formed in the high breakdown voltage isolation region 3 so as to match the shape of the high breakdown voltage isolation region 3. Each trench of the trench group 40 is filled with an insulator. The high breakdown voltage isolation region 3 is provided with a portion partitioned by the trench 4, and a high voltage NMOS 5 or a high breakdown voltage PMOS 6 for level shift is provided in the partitioned portion.

FIG. 11 is a diagram showing a cross-section of the FF portion in the semiconductor device 400 shown in FIG. The semiconductor device 400 of this embodiment has an SOI structure, and includes a P ⁺ type substrate 7 and an epitaxial layer (low potential reference N type layer 81, high potential reference N type layer 82, isolation region N type). A buried insulating layer 75 is provided between the layer 83). That is, the P ⁺ type substrate 7 and the epitaxial layer are insulated by the buried insulating layer 75. The substrate located below the buried insulating layer 75 may be P-type or N-type. The isolation region N-type layer 83 is partitioned into a plurality of regions by a trench group 40 whose bottom reaches the insulating oxide film 7. Of the regions partitioned by the trench group 40, regions closest to the low potential reference circuit region 1 correspond to the body P ⁻ region 50b and the body contact P ⁺ region 50bc in the high breakdown voltage NMOS 5 (see FIG. 12), respectively. P-type diffusion regions 30b and 30bc are provided. Further, an N-type diffusion region 30 d corresponding to the drain N ⁺ region 50 d in the high breakdown voltage NMOS 5 is provided in the region closest to the high potential reference circuit region 2. The P type diffusion regions 30b and 30bc have the same potential as the ground, and the N type diffusion region 30d has the same potential as the power source of the high potential reference circuit region 2. Further, the potential of the main surface rises stepwise from the low potential reference circuit region 1 toward the high potential reference circuit region 2 due to the effect of parasitic capacitance coupling generated in the trench group 40. The parasitic capacitance coupling ratio can be adjusted by the width of each trench in the trench 40 group at the design stage.

12 is a diagram showing a cross section of the GG portion in the semiconductor device 400 shown in FIG. That is, it is a diagram showing a cross section of the high breakdown voltage NMOS 5. The high breakdown voltage NMOS 5 is formed in a portion defined by the trench group 40 and the trench 4 in the N type epitaxial layer formed on the P ⁺ type substrate 7. The high breakdown voltage NMOS 5 includes a gate polysilicon 50g, a gate oxide film 50x, a source N ⁺ region 50s, a drain N ⁺ region 50d, a body P ⁻ region 50b, and a body contact P ⁺ region 50bc. Yes. Further, an NMOS drift layer 85 that functions as a drift layer is provided on the P ⁺ type substrate 7. Further, a RESURF P ⁻ region 50 r is formed above the drift layer 85 in the NMOS. When a high voltage is applied between the source and drain, a depletion layer is formed from the PN junction between the isolation region N-type layer 83 and the RESURF P ⁻ region 50r, thereby increasing the breakdown voltage. . At this time, the potential of the main surface rises almost linearly between the source and drain.

FIG. 13 is a view showing a cross section of the HH portion in the semiconductor device 400 shown in FIG. That is, it shows a cross section of the high voltage PMOS 6. The high breakdown voltage PMOS 6 is also formed in a region partitioned by the trench group 40 and the trench 4 in the N type epitaxial layer disposed on the P ⁺ type substrate 7. The high breakdown voltage PMOS 6 is provided with a gate polysilicon 60g, a gate oxide film 60x, a source P ⁺ region 60s, a drain P ⁺ region 60d, and a sub-contact N ⁺ region 60sc. Further, a drift P ⁻ region 60dr formed of the same diffusion layer as the RESURF P ⁻ region 50r of the high breakdown voltage NMOS 5 is provided. When a high voltage is applied between the source and drain, the potential of the main surface rises almost linearly between the source and drain.

The semiconductor device 400 according to the present embodiment is characterized in that the high breakdown voltage NMOS 5 and the high breakdown voltage PMOS 6 are arranged in a region in which the high breakdown voltage isolation region 3 is partitioned by the trench 4, and a loop shape is formed in the high breakdown voltage isolation region 3. The trench group 40 is formed. Thereby, the potential of the main surface gradually rises from the low potential reference circuit region 1 toward the high potential reference circuit region 2 in any part of the high breakdown voltage isolation region 3, the high breakdown voltage NMOS 5, and the high breakdown voltage PMOS 6. That is, in the semiconductor device 400 of the present embodiment, the electric field distribution approximated at any part in the high breakdown voltage isolation region 3. Similarly to the semiconductor device of the first embodiment, the high potential drain wiring 5d in the high breakdown voltage NMOS 5 (low potential drain wiring 6d in the high breakdown voltage PMOS 6) has a low potential portion (high potential portion in the high breakdown voltage PMOS 6). There is no straddle. Therefore, compared with the conventional semiconductor device, the low breakdown voltage is suppressed and the electric field concentration is suppressed by a simple structure.

[Fifth embodiment]
A semiconductor device 500 according to the fifth embodiment has a structure shown in the plan view of FIG. That is, the semiconductor device 500 includes a low potential reference circuit region 1 and a high potential reference circuit region 2. The high potential reference circuit region 2 is configured to be surrounded by a plurality of high breakdown voltage NMOSs 5 (or high breakdown voltage PMOSs 6). Each high breakdown voltage NMOS 5 is surrounded by a trench 4.

  The semiconductor device 500 of this embodiment is characterized by the following points. That is, the potential distribution in the separation region between the low potential reference circuit region 1 and the high potential reference circuit region 2 is uniform. In the semiconductor device 400 of the fourth embodiment (see FIG. 10), both the potential distribution in the high breakdown voltage isolation region 3 (see FIG. 11) and the potential distribution in the high breakdown voltage NMOS 5 (see FIG. 12) rise gently. However, there is a slight difference. As a result, the problem of breakdown voltage may occur. On the other hand, in the semiconductor device 500 of this embodiment, although the unnecessary high breakdown voltage NMOS 5 is generated, the potential distribution and the electric field concentration problem do not occur because the potential distribution is almost the same in any part. Although some unnecessary high-breakdown-voltage NMOSs 5 may be arranged, there is no problem if the gate is kept off.

[Sixth embodiment]
A semiconductor device 600 according to the sixth embodiment has a structure shown in the plan view of FIG. That is, the semiconductor device 600 includes a low potential reference circuit region 1 and a high potential reference circuit region 2. A high potential reference circuit region 2 is surrounded by a trench 4. Of course, the trench 4 is filled with an insulator. That is, the region between the low potential reference circuit region 1 and the high potential reference circuit region 2 is filled with an insulator. Further, a high-voltage NMOS 5 and a high-voltage PMOS 6 for level shift are provided at the sites partitioned by the trench 4.

In the semiconductor device 600 of this embodiment, the potential of the trench 4 portion rises linearly from the low potential reference circuit region 1 toward the high potential reference circuit region 2. As a result, similar to the fifth embodiment, the potential distribution is almost the same in any part, so that the problem of withstand voltage does not occur. Further, it is possible to narrow the width of the trench 4 other than the portion adjacent to the high breakdown voltage NMOS 5 and the high breakdown voltage PMOS 6. Therefore, the chip area can be reduced. Generally, the vicinity of the high breakdown voltage MOS is about 10 μm / V, for example, about 100 μm is required at a breakdown voltage of 1000 V, while the other parts are about 3 × 10 ⁻³ μm / V, that is, about ³ μm at a breakdown voltage of 1000 V. It is enough.

As described in detail above, in the semiconductor device 100 of the first embodiment, the high breakdown voltage isolation region 3 is provided between the low potential reference circuit region 1 and the high potential reference circuit region 2. Furthermore, a trench 4 whose bottom reaches the P ⁻ type substrate 7 is formed at the outer edge of the high breakdown voltage isolation region 3 to completely separate the low potential reference circuit region 1 and the high potential reference circuit region 2. Further, the high breakdown voltage isolation region 3 is partitioned by the trench 4, and the high breakdown voltage NMOS 5 or the high breakdown voltage PMOS 6 is provided in the partitioned part. The drain wiring 5d of the high breakdown voltage NMOS 5 is formed on the surface of the semiconductor device so as to straddle the trench 4. Thus, the drain wiring 5d does not straddle the high breakdown voltage isolation region 3, and is not affected by the drain wiring 5d having a high potential (low potential in the high breakdown voltage PMOS 6). Further, since each high voltage MOS is completely insulated from the low potential reference circuit region 1 and the high potential reference circuit region 2 in the trench 4, no leakage current is generated, and the parasitic resistance is increased. There is no need to provide a curved portion. Further, in the semiconductor device 100, since the withstand voltage can be adjusted by the size of the trench 4, even when the required voltage is different, it can be easily handled at the design stage. That is, the degree of freedom in design is high. Accordingly, a semiconductor device in which a low-potential reference circuit and a high-potential reference circuit are mixedly mounted, can perform level shift between the low-potential reference circuit and the high-potential reference circuit, is compact, and has excellent withstand voltage. A semiconductor device is realized.

  In the semiconductor device 200 of the second embodiment, no trench is formed on the wall surface on the source wiring side and the outer wall of the high breakdown voltage isolation region 3. Thereby, the yield can be improved and the semiconductor device can be made compact. In the semiconductor device 300 of the third embodiment, there is no trench that partitions the high breakdown voltage isolation region 3 and the high breakdown voltage NMOS 5. Therefore, it is possible to prevent a decrease in breakdown voltage due to crystal defects or the like that are likely to occur in the vicinity of the trench.

In the semiconductor device 400 of the fourth embodiment, a loop-shaped trench 4 group is formed in the high breakdown voltage isolation region 3. As a result, the potential of the main surface in the high withstand voltage isolation region 3 gradually rises from the low potential reference circuit region 1 toward the high potential reference circuit region 2, thereby mitigating the problem of electric field concentration. In the semiconductor device 500 of the fifth embodiment, the high potential reference circuit region 2 is surrounded by a high voltage MOS. As a result, in the region between the low potential reference circuit region 1 and the high withstand voltage reference circuit region 2, almost the same potential distribution is obtained in any part, and the problem of withstand voltage in the isolation region does not occur. In the semiconductor device 600 of the sixth embodiment, the region between the low potential reference circuit region 1 and the high potential reference circuit region 2 is filled with an insulator. Even in such a form, almost the same potential distribution is obtained in any part of the region filled with the insulator, and the problem of withstand voltage in the isolation region does not occur.

  Note that this embodiment is merely an example, and does not limit the present invention. Therefore, the present invention can naturally be improved and modified in various ways without departing from the gist thereof. For example, for each semiconductor region, P-type and N-type may be interchanged. Also, the semiconductor is not limited to silicon, but may be other types of semiconductors (SiC, GaN, GaAs, etc.).

It is a top view which shows the structure of the semiconductor device which concerns on a 1st form. FIG. 2 is a cross-sectional view showing the structure of the AA cross section in the semiconductor device of FIG. 1. FIG. 2 is a cross-sectional view showing a structure of a BB cross section in the semiconductor device of FIG. 1. FIG. 2 is a cross-sectional view showing a structure of a CC cross section in the semiconductor device of FIG. 1. FIG. 2 is a cross-sectional view showing a structure of a DD cross section in the semiconductor device of FIG. 1. It is a top view which shows the structure of the semiconductor device which concerns on a 2nd form. FIG. 7 is a cross-sectional view showing the structure of the EE cross section in the semiconductor device of FIG. 6. It is a top view which shows the structure of the semiconductor device which concerns on a 3rd form. It is a top view which shows the structure of the trenchless semiconductor device which is an application example of the semiconductor device which concerns on a 3rd form. It is a top view which shows the structure of the semiconductor device which concerns on a 4th form. FIG. 11 is a cross-sectional view showing the structure of the FF cross section in the semiconductor device of FIG. 10. FIG. 11 is a cross-sectional view illustrating a structure of a GG cross section in the semiconductor device of FIG. 10. FIG. 11 is a cross-sectional view showing a structure of an HH cross section in the semiconductor device of FIG. 10. It is a top view which shows the structure of the semiconductor device which concerns on a 5th form. It is a top view which shows the structure of the semiconductor device which concerns on a 6th form. It is a top view which shows the structure of the semiconductor device which concerns on the conventional form. It is a figure which shows the circuit structure of the semiconductor device which concerns on the conventional form.

Explanation of symbols

1 Low-potential reference circuit area (low-potential reference circuit, first area)
2 High potential reference circuit area (high potential reference circuit, second area)
3 High breakdown voltage isolation region (third region)
4 Trench (insulating partition)
5 High voltage NMOS (relay semiconductor device, 4th region)
6 High voltage PMOS (relay semiconductor device, 4th region)
7 P ^- type substrate (substrate region, semiconductor substrate)
40 trench group (insulating partition wall group)
50d Drain N ⁺ region (drain)
50g gate polysilicon (gate)
50s source N ⁺ region (source)
75 buried insulating layer (insulating film)
100 Semiconductor device

Claims (5)

In a semiconductor device in which a low potential reference circuit and a high potential reference circuit are mixedly mounted and signals are transmitted between the two,
Comprising a relay semiconductor element surrounded by an insulating partition wall, in which a signal is transmitted between the low potential reference circuit and the high potential reference circuit, and a trench-like groove is filled with an insulating material;
A region of the low potential reference circuit and the high potential reference circuit are formed by a region in which a plurality of the relay semiconductor devices are provided and the plurality of the relay semiconductor devices and the insulating partition wall surrounding the relay semiconductor device are annularly combined. The semiconductor device is characterized in that the output wiring of the relay semiconductor elements is arranged in the circuit region on the output side across the insulating partition. The semiconductor device according to claim 1,
A substrate region located below the low potential reference circuit and the high potential reference circuit;
An insulating layer that is located between the low potential reference circuit and the high potential reference circuit and the substrate region, and that insulates the low potential reference circuit and the high potential reference circuit from the substrate region;
The insulating partition has a bottom that reaches the insulating layer and surrounds the relay semiconductor element as viewed in the thickness direction. A first conductivity type semiconductor substrate;
A first region of a second conductivity type formed on a main surface of the semiconductor substrate and forming a low potential reference circuit region;
A second region of a second conductivity type formed on the semiconductor substrate apart from the first region and forming a high potential reference circuit region;
An insulating partition located between the first region and the second region, mediating signal transmission between the first region and the second region, and having a trench-like groove filled with an insulator. a plurality of relay semiconductor device surrounded, the combined insulating partition wall, an annularly formed so as viewed from the surface surrounding the one of the first region or the second region surrounding the relay semiconductor device A third region,
An output wiring of the relay semiconductor element in the third region is arranged in the circuit region on the output side across the insulating partition. A first conductivity type or second conductivity type semiconductor substrate;
An insulating film formed on the main surface of the semiconductor substrate;
A first region of a second conductivity type formed on the insulating film and forming a low potential reference circuit region;
A second region of a second conductivity type formed on the insulating film apart from the first region and forming a high potential reference circuit region;
An insulating partition located between the first region and the second region, mediating signal transmission between the first region and the second region, and having a trench-like groove filled with an insulator. A plurality of surrounding relay semiconductor elements and the insulating partition wall surrounding the relay semiconductor elements are combined in a ring shape , and are formed so as to surround one of the first region and the second region when viewed from the surface. A third region,
An output wiring of the relay semiconductor element in the third region is arranged in the circuit region on the output side across the insulating partition. In the semiconductor device according to claim 3 or 4,
The semiconductor device according to claim 1, wherein the insulating partition reaches the semiconductor substrate or the insulating film whose bottom is positioned below.

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