JP4644443B2 - Video display device - Google Patents

Description

  The present invention relates to a video display device that performs various signal processing on an input video signal.

  In the video display device, various video signal processings for the purpose of improving the image quality of the video and converting the display area of the video are performed. For example, after performing interlace / progressive conversion (hereinafter abbreviated as IP conversion) and scaling processing on an input video signal, the luminance dynamic range is further adjusted according to the average signal level of the video signal. A video display device has been proposed (see, for example, Patent Document 1).

  The video display device includes a video format conversion unit, a frame memory, a dynamic range setting unit, and a dynamic range adjustment unit.

  The video format conversion unit performs IP conversion processing and scaling processing of an input video signal using a frame memory.

Further, the dynamic range setting unit calculates the average signal level of the video signal, and sets the dynamic range of the calculated average signal level. Further, the dynamic range adjustment unit adjusts the video signal based on the set dynamic range. Thereby, the image quality of the video is adjusted.
JP 2002-333858 A

  In recent years, there has been a demand for higher image quality. Along with this, it has been proposed to provide a video display apparatus with an additional video signal processing circuit to achieve high image quality and sharpness of the video.

  For example, a new video signal processing circuit is added to the video display device. In this case, the video signal converted by the video format conversion unit is further subjected to signal processing by the video signal processing circuit.

  Here, the video signal adjusted by the dynamic range adjustment unit needs to correspond to the video signal used by the dynamic range setting unit for calculating the average signal level.

  However, simply adding a new video signal processing circuit between the video format conversion unit and the dynamic range adjustment unit uses the video signal adjusted by the dynamic range adjustment unit and the dynamic range setting unit for calculating the average signal level. The video signal will be different. As a result, the average signal level of the video signal processed by the video signal processing circuit may not match the average signal level calculated by the dynamic range setting unit, which may cause a reduction in image quality.

  Therefore, a new new frame memory is added, the video signal processed by the video signal processing circuit is delayed by one frame (field), and then input to the dynamic range adjustment unit to adjust the dynamic range adjustment unit. The video signal to be used is matched with the video signal used by the dynamic range setting unit for calculating the average signal level.

  However, in such a configuration, an additional frame memory is required in addition to the frame memory for video format conversion, so that the circuit scale increases and the manufacturing cost increases.

  An object of the present invention is to provide a video display device capable of reducing the circuit scale and reducing the cost while realizing processing of a desired video signal.

A video display device according to the present invention is a video display device that displays video based on an input video signal, and stores a video display panel and a video signal for one field including a plurality of pixel data. And a storage device capable of storing information indicating the enlargement / reduction ratio of the size of the video display area, and using the storage device, the number of pixel data for one field of the input video signal is used as information. A first processing circuit that performs processing for generating a video signal including the changed number of pixel data, and signal levels and information of a plurality of pixel data for one field of the input video signal. a second processing circuit for performing a process of multiplying each of a driving device for driving the panel based on the video signal outputted from the first processing circuit, the average signal les average value of the multiplication result of the second processing circuit A first relationship between the average signal level calculation unit and a constant for adjusting the luminance of the video displayed on the panel by adjusting the operation of the driving device and the average signal level. An adjustment circuit that stores and determines a constant corresponding to the average signal level calculated by the average signal level calculation unit based on the first relationship, and adjusts the operation of the driving device based on the determined constant It is.

In this case, the first processing circuit changes the number of the plurality of pixel data for one field of the input video signal based on the information indicating the enlargement / reduction ratio of the size of the video display area, and the size of the display area is changed. A modified video signal is generated. This process is performed using a storage device . The panel is driven based on the video signal output from the first processing circuit by the driving device, and the video is displayed on the panel. On the other hand, the second processing circuit multiplies the signal level of the plurality of pixel data for one field of the input video signal by the information. The average signal level calculation unit calculates the average value of the multiplication results of the second processing circuit as the average signal level. The adjustment circuit stores a predetermined first relationship. The adjustment circuit determines a constant corresponding to the average signal level calculated by the average signal level calculation unit based on the first relationship, adjusts the operation of the driving device based on the determined constant, and displays it on the panel. The brightness of the recorded image is adjusted.

Accordingly, the panel driving condition is adjusted based on the video signal that has been processed equivalent to the processing by the first processing circuit, so that the panel corresponding to the video signal output from the first processing circuit is adjusted. The driving conditions are adjusted. Thereby, processing of a desired video signal based on the processing by the first processing circuit is realized.

The input video signal is stored for one field by the storage device . Thereby, the video signal processed by the first processing circuit can be delayed by one field with respect to the video signal processed by the second processing circuit . As a result, the driving device drives the panel based on the video signal in the same field as the video signal field used by the adjustment circuit for adjusting the operation of the driving device, so that the panel driving conditions are optimally adjusted. As a result, processing of a desired video signal based on the processing by the first processing circuit is realized.

Furthermore, since the second processing circuit performs processing equivalent to the processing by the first processing circuit without using a storage device, it is not necessary to provide a storage device corresponding to the second processing circuit . As a result, the circuit scale is reduced, and cost reduction and ease of manufacture are realized.

  Each pixel data of the input video signal consists of one luminance signal and two color difference signals, and the video display device consists of each primary pixel signal of each pixel data of the video signal generated by the first processing circuit. First inverse matrix transformation using a first coefficient group including a plurality of coefficients of the first number of bits in the video signal generated by the first processing circuit without using a storage device in order to convert to pixel data A third processing circuit for performing processing, and a first bit in the input video signal without using a storage device in order to convert each pixel data of the input video signal into pixel data composed of three primary color signals And a fourth processing circuit that performs a second inverse matrix transformation process using a second coefficient group including a plurality of coefficients having a smaller second number of bits, and the drive device includes a third processing circuit. First The panel is driven based on the video signal subjected to the inverse matrix conversion process, and the second processing circuit is for one field of the video signal subjected to the second inverse matrix conversion process by the fourth processing circuit. You may perform the process which each multiplies the signal level of several pixel data, and information.

In this case, the first inverse matrix conversion process of the video signal using the first coefficient group including a plurality of coefficients of the first number of bits is performed by the third processing circuit, and the second smaller than the first bit. The fourth processing circuit performs the second inverse matrix conversion processing of the video signal using the second coefficient group including a plurality of coefficients of the number of bits . These processes are performed without using a storage device.
The second processing circuit multiplies the signal level and information of a plurality of pixel data for one field of the video signal subjected to the second inverse matrix conversion processing by the fourth processing circuit. The average signal level calculation unit calculates the average value of the multiplication results of the second processing circuit as the average signal level.

Thus, as compared with the first coefficient of the number of bits used for the first inverse matrix conversion processing, the coefficient of the second number of bits used in the second inverse matrix conversion processing is small, the second reverse The circuit configuration of the fourth processing circuit that performs the matrix conversion processing is simplified, the circuit scale is reduced, and the cost is reduced and the manufacturing is facilitated. In addition, since the first inverse matrix conversion process is performed on the video signal that has been processed by the first processing circuit, processing of a desired video signal based on a plurality of processes is realized.
The second processing circuit is provided at the subsequent stage of the fourth processing circuit. In this case, the input video signal is subjected to the second inverse matrix conversion process by the fourth processing circuit, and then the process by the second processing circuit. As a result, the processing by the second processing circuit is performed after the second inverse matrix conversion processing by the fourth processing circuit, so that the average signal level calculation unit performs the processing by the first processing circuit and the third processing by the third processing circuit. A video signal equivalent to the video signal that has been subjected to the first inverse matrix conversion processing by the processing circuit can be obtained.

The video display device uses a first coefficient group that includes a first number of coefficients in the video signal generated by the first processing circuit without using a storage device, and adjusts the hue of the video. The second processing circuit uses a third processing circuit that performs linear arithmetic processing, and a second coefficient group that includes a second number of coefficients smaller than the first number in a video signal input without using a storage device. A fourth processing circuit for performing linear arithmetic processing, wherein the first and second linear arithmetic processing include addition processing and multiplication processing using the first coefficient group and the second coefficient group, respectively. The apparatus drives the panel based on the video signal on which the first linear arithmetic processing has been performed by the third processing circuit, and the second processing circuit performs the second linear arithmetic processing by the fourth processing circuit. Multiple pixel data for one field of the received video signal The level and information processing may be performed for multiplying respectively.

In this case, the first linear operation processing of the video signal using the first coefficient group including the first number of coefficients is performed by the third processing circuit, and the second number smaller than the first number is performed. The fourth processing circuit performs the second linear arithmetic processing of the video signal using the second coefficient group including the coefficients . These processes are performed without using a storage device.
The second processing circuit multiplies the signal level and information of a plurality of pixel data for one field of the video signal on which the second linear arithmetic processing has been performed by the fourth processing circuit. The average signal level calculation unit calculates the average value of the multiplication results of the second processing circuit as the average signal level.

As described above, since the second number of coefficients used in the second linear arithmetic processing is smaller than the first number of coefficients used in the first linear arithmetic processing , the second linear arithmetic processing is performed. The circuit configuration of the processing circuit 4 is simplified, the circuit scale is reduced, and the cost is reduced and the manufacturing is facilitated. In addition, since the first linear arithmetic processing is performed on the video signal that has been processed by the first processing circuit, processing of a desired video signal based on a plurality of processing is realized.
The second processing circuit is provided at the subsequent stage of the fourth processing circuit. In this case, the input video signal is subjected to the second linear arithmetic processing by the fourth processing circuit and then the second processing circuit. Thus, the processing by the second processing circuit is performed after the second linear arithmetic processing by the fourth processing circuit, so that the average signal level calculation unit performs the processing by the first processing circuit and the third processing by the average signal level calculation unit. A video signal equivalent to the video signal that has been subjected to the first linear arithmetic processing by the circuit can be obtained.

The video display device determines in advance a video signal generated by the first processing circuit without using a storage device in order to perform gamma correction of the video, adjustment of the dynamic range of the luminance of the video, or adjustment of the hue of the video. A third processing circuit that performs a first nonlinear arithmetic processing based on the second relationship, and a second processing approximation that uses an approximate expression of a second relationship that is predetermined for a video signal input without using a storage device. And a fourth processing circuit that performs the second non-linear arithmetic processing, and the predetermined second relationship is that each pixel of the video signal generated by the first processing circuit that is input to the third processing circuit The relationship between the signal level of data and the signal level of each pixel data of the video signal generated by the first processing circuit output from the third processing circuit. First nonlinear The panel is driven based on the video signal on which the arithmetic processing has been performed, and the second processing circuit has a plurality of pixel data for one field of the video signal on which the second nonlinear arithmetic processing has been performed by the fourth processing circuit. The signal level may be multiplied by the information.

In this case, the signal level of each pixel data of the video signal generated by the first processing circuit input to the third processing circuit and the video generated by the first processing circuit output from the third processing circuit. The first non-linear operation processing of the video signal based on the predetermined relationship between the signal level of each pixel data of the signal is performed by the third processing circuit, and the video using the approximate expression of the predetermined relationship The second nonlinear arithmetic processing of the signal is performed by the fourth processing circuit. These processes are performed without using a storage device.
The second processing circuit multiplies the signal level and information of a plurality of pixel data for one field of the video signal subjected to the second nonlinear arithmetic processing by the fourth processing circuit. The average signal level calculation unit calculates the average value of the multiplication results of the second processing circuit as the average signal level.

As a result, the first nonlinear arithmetic processing of the video signal based on the predetermined second relationship is performed on the video signal processed by the first processing circuit , thereby processing the desired video signal. Is realized.

Further, the second nonlinear calculation process is simpler than the first nonlinear calculation process . Thereby, the circuit configuration of the fourth processing circuit is simplified, and the circuit scale can be reduced from the circuit scale of the third processing circuit. As a result, circuitry scale is reduced, cost and ease of manufacture is achieved.
The second processing circuit is provided at the subsequent stage of the fourth processing circuit. In this case, the input video signal is subjected to the second nonlinear arithmetic processing by the fourth processing circuit, and then the second processing circuit. As a result, the processing by the second processing circuit is performed after the second nonlinear arithmetic processing by the fourth processing circuit, so that the average signal level calculation unit performs the processing by the first processing circuit and the third processing by the average signal level calculation unit. A video signal equivalent to the video signal subjected to the first nonlinear arithmetic processing by the circuit can be obtained.

Each pixel data of the input video signal is composed of one luminance signal and two color difference signals, and the video display device is generated by the first processing circuit without using a storage device in order to adjust the hue of the video. The obtained video signal is subjected to linear calculation processing including addition processing and multiplication processing using a plurality of coefficients, and each pixel data of the video signal generated by the first processing circuit is converted into pixel data composed of three primary color signals. In order to perform the conversion, a third inverse matrix conversion process using a first coefficient group including a plurality of coefficients of the first number of bits is performed on the video signal that has been subjected to the linear calculation process without using a storage device. In order to convert each pixel data of the input video signal into pixel data consisting of three primary color signals, the first bit is added to the input video signal without using a storage device. And a fourth processing circuit that performs a second inverse matrix conversion process using a second coefficient group that includes a plurality of coefficients having a smaller second number of bits, and the drive device is linear with the third processing circuit. The panel is driven based on the video signal on which the arithmetic processing and the first inverse matrix conversion processing are performed, and the second processing circuit is a video signal on which the second inverse matrix conversion processing is performed by the fourth processing circuit. A process of multiplying the signal level and information of a plurality of pixel data for one field may be performed.
In this case, the linear processing of the video signal using a plurality of coefficients and the first inverse matrix conversion processing of the video signal using the first coefficient group including a plurality of coefficients of the first number of bits are the third processing circuit. And the second inverse matrix transformation process of the video signal using the second coefficient group including a plurality of coefficients having the second number of bits smaller than the first bit is performed by the fourth processing circuit. These processes are performed without using a storage device.
The second processing circuit multiplies the signal level and information of a plurality of pixel data for one field of the video signal subjected to the second inverse matrix conversion processing by the fourth processing circuit. The average signal level calculation unit calculates the average value of the multiplication results of the second processing circuit as the average signal level.
The panel may be a plasma display panel . In this case, since the driving conditions of the plasma display panel are adjusted based on the video signal that has been processed equivalent to the processing by the first processing circuit , power discharge of the discharge cells of the plasma display panel does not occur. , Reliability is maintained. Thereby, the lifetime of the plasma display panel is extended.

According to the video display apparatus according to the present invention, based on the first processing process equivalent made the video signals processing by the circuit, the driving condition of the panel is adjusted, output from the first processing circuit The panel drive conditions corresponding to the video signal to be adjusted are adjusted. Thereby, processing of a desired video signal based on the processing by the first processing circuit is realized.

The input video signal is stored for one field by the storage device . Thereby, the video signal processed by the first processing circuit can be delayed by one field with respect to the video signal processed by the second processing circuit . Thereby, since the adjustment circuit adjusts the operation of the drive device based on the video signal of the same field as the field of a video signal used for adjusting the drive condition, the driving condition of the panel is adjusted optimally. As a result, processing of a desired video signal based on the processing by the first processing circuit is realized.

Furthermore, since the second processing circuit performs processing equivalent to the processing by the first processing circuit without using a storage device, it is not necessary to provide a storage device corresponding to the second processing circuit . As a result, the circuit scale is reduced, and cost reduction and ease of manufacture are realized.

  Hereinafter, a video display device according to an embodiment of the present invention will be described. FIG. 1 is a block diagram showing a basic configuration of a video display apparatus according to the present invention.

  1 includes an analog / digital (hereinafter abbreviated as A / D) converter 1, a video format conversion circuit 2, a field memory 3, a first video signal processing circuit 4, a drive control circuit 5, A second video signal processing circuit 6, an average signal level calculation circuit 7, a display device 8 and a timing signal generation circuit 9 are included.

  The A / D converter 1 is supplied with an analog video signal AVD. The A / D converter 1 converts the supplied video signal AVD into a digital format and supplies the converted video signal VD to the video format conversion circuit 2.

  The video format conversion circuit 2 performs, for example, interlace-progressive conversion (hereinafter abbreviated as IP conversion) on the video signal VD. The video format conversion circuit 2 writes the video signal VD supplied from the A / D converter 1 to the field memory 3 and reads the video signal VD written to the field memory 3 at the time of IP conversion. Is generated. The generated video signal n1 is supplied to the first video signal processing circuit 4 and the second video signal processing circuit 6.

  The field memory 3 includes a nonvolatile memory such as a flash memory or a volatile memory such as SRAM (Static Random Access Memory) and a data holding power source for holding the data, or for storing other data. It is equipped with the means.

  The first video signal processing circuit 4 performs predetermined processing on the video signal n1 given from the video format conversion circuit 2. This predetermined process includes, for example, a video display area changing process using the field memory 3. Further, the predetermined process may include a process in which a linear display process or a non-linear calculation process is combined with a video display area changing process. Note that the predetermined processing is not limited to these, and it is sufficient that at least processing using the field memory 3 is included as will be described later. Details will be described later.

  Thus, the first video signal processing circuit 4 performs a predetermined process using the field memory 3. In this case, the first video signal processing circuit 4 writes the supplied video signal n1 into the field memory 3, generates the video signal o1 based on the video signal n2 read from the field memory 3, and drives and controls the video signal o1. This is given to the circuit 5.

  The second video signal processing circuit 6 performs predetermined processing on the video signal n1 given from the video format conversion circuit 2, generates a video signal p1, and gives the video signal p1 to the average signal level calculation circuit 7. This predetermined process is simpler and equivalent to the predetermined process performed by the first video signal processing circuit 4. The second video signal processing circuit 6 does not perform processing using the field memory 3.

  The predetermined processing performed by the second video signal processing circuit 6 is equivalent to the processing performed by the first video signal processing circuit 4. Thereby, the signal level (value) of the video signal p1 generated by the second video signal processing circuit 6 and the signal level (value) of the video signal o1 generated by the first video signal processing circuit 4 are substantially the same. Will be equal. Details will be described later.

  The average signal level calculation circuit 7 calculates an average of signal levels (hereinafter referred to as an average signal level) based on the video signal p1 given from the second video signal processing circuit 6, and generates an average signal level p2. Then, the average signal level p2 is given to the drive control circuit 5. Details of the average signal level calculation circuit 7 will be described later.

  As described above, the first video signal processing circuit 4 performs a predetermined process using the field memory 3, and the second video signal processing circuit 6 performs a process not using the field memory 3.

  Thereby, in the drive control circuit 5, the video signal o <b> 1 given from the first video signal processing circuit 4 is delayed with respect to the average signal level p <b> 2 given from the average signal level calculation circuit 7. This delay amount is, for example, one field.

  Thereby, the drive control circuit 5 can obtain the average signal level p2 corresponding to the video signal o1 of the one field before the video signal o1 of the specific one field is given. As a result, the drive control circuit 5 can adjust the driving condition of the display device 8 based on the average signal level p2 corresponding to the video signal o1 given the video signal o1.

  The drive control circuit 5 generates a drive signal q1 based on the adjusted drive condition, and drives the display device 8. Thereby, the video is displayed on the display device 8.

  As the adjustment of the drive condition by the drive control circuit 5, for example, there is a video brightness adjustment. In this case, the average signal level p2 obtained by the average signal level calculation circuit 7 is an average luminance level signal.

  The timing signal generating circuit 9 is supplied with a horizontal synchronizing signal HS and a vertical synchronizing signal VS corresponding to the video signal AVD. The timing signal generation circuit 9 generates predetermined timing signals HTS and VTS based on the horizontal synchronization signal HS and the vertical synchronization signal VS. The timing signals HTS and VTS are given to each component of the video display device 100 as necessary.

  The display device 8 will be described. In the basic configuration of the video display device 100 of the present invention, the display device 8 includes, for example, a plasma display panel (hereinafter abbreviated as PDP).

  FIG. 2 is a block diagram showing an example of a specific configuration of the display device 8 of FIG. 2 includes a PDP 80, a data driver 81, a scan driver 82, a sustain driver 83, a subfield processor 84, and a video signal-subfield correlator 85.

  The video signal / subfield correlator 85 is supplied with the drive signal q 1 from the drive control circuit 5. This drive signal q1 corresponds to image data. Since the video signal / subfield associating unit 85 divides one field into a plurality of subfields for display, the video signal / subfield associating unit 85 generates the image data SP of each subfield from the image data of one field and outputs it to the subfield processor 84 To do.

  In this example, it is assumed that an address / display period separation method (hereinafter abbreviated as ADS method) is used as the gradation display driving method. Details of the ADS method will be described later.

  The subfield processor 84 generates a data driver control signal DS, a scan driver control signal UP, and a sustain driver control signal CP from the image data SP of the subfield.

  The data driver control signal DS is given to the data driver 81. The scan driver control signal UP is given to the scan driver 82. The sustain driver control signal CP is given to the sustain driver 83.

  The PDP 80 includes a plurality of data electrodes 81a, a plurality of scan electrodes 82a, and a plurality of sustain electrodes 83a. The plurality of data electrodes 81a are arranged in the vertical direction of the screen, and the plurality of scan electrodes 82a and the plurality of sustain electrodes 83a are arranged in the horizontal direction of the screen. The plurality of sustain electrodes 83a are connected in common.

  A discharge cell is formed at each intersection of the data electrode 81a, the scan electrode 82a, and the sustain electrode 83a, and each discharge cell constitutes a pixel on the screen. The plurality of data electrodes 81 a are connected to the data driver 81, the plurality of scan electrodes 82 a are connected to the scan driver 82, and the plurality of sustain electrodes 83 a are connected to the sustain driver 83.

  The data driver 81 applies a data pulse to any of the plurality of data electrodes 81a in accordance with the data driver control signal DS. The scan driver 82 applies an initialization pulse and a sustain pulse to the plurality of scan electrodes 82a in accordance with the scan driver control signal UP. The sustain driver 83 applies an initialization pulse and a sustain pulse to the plurality of sustain electrodes 83a in accordance with the sustain driver control signal CP.

  The ADS system will be described. FIG. 3 is a diagram for explaining an ADS method applied to the display device 8 shown in FIG. Note that FIG. 3 shows an example of a negative pulse that discharges at the fall of the drive pulse, but the basic operation is the same as the following even in the case of a positive pulse that discharges at the rise.

  In the ADS system, one field is temporally divided into a plurality of subfields. For example, one field is divided into five subfields SF1 to SF5. Further, each of the subfields SF1 to SF5 is divided into, for example, an initialization period R1 to R5, a writing period AD1 to AD5, and a sustain period SUS1 to SUS5.

  In the initialization periods R1 to R5, initialization processing of each subfield is performed. In the writing periods AD1 to AD5, address discharge for selecting the discharge cells to be lit is performed, and in the sustain periods SUS1 to SUS5. A sustain discharge for display is performed.

  In the initialization period R1 to R5, a single initialization pulse is applied to the sustain electrode 83a, and a single initialization pulse is also applied to the scan electrode 82a. Thereby, preliminary discharge is performed.

  In the write periods AD1 to AD5, the scan electrode 82a is sequentially scanned, and a predetermined write process is performed only on the discharge cells that have received the write pulse from the data electrode 81a. As a result, address discharge is performed.

  In sustain periods SUS1 to SUS5, sustain pulses corresponding to values weighted in subfields SF1 to SF5 are output to sustain electrode 83a and scan electrode 82a. For example, in the subfield SF1, in the initialization period R1, the sustain pulse is applied once to the sustain electrode 83a, the sustain pulse is applied once to the scan electrode 82a, and the discharge cell 14 selected in the write period AD1 is generated twice. Sustain discharge is performed. In the subfield SF2, the sustain pulse is applied twice to the sustain electrode 83a, the sustain pulse is applied twice to the scan electrode 82a, and the discharge cell 14 selected in the write period AD2 performs sustain discharge four times.

  As described above, in each of the subfields SF1 to SF5, the sustain pulse is applied to the sustain electrode 83a and the scan electrode 82a once, twice, four times, eight times, and 16 times, and brightness according to the number of pulses ( The discharge cell emits light. That is, the sustain periods SUS1 to SUS5 are periods in which the discharge cells selected in the write periods AD1 to AD5 are discharged at a number corresponding to the weighting amount of brightness.

  When the adjustment of the drive condition by the drive control circuit 5 relates to the luminance of the video, the following adjustment can be performed.

  When the ADS method is applied to the display device 8 of FIG. 2, the luminance of the video is determined according to the number of times of light emission of the discharge cells in the sustain periods SUS1 to SUS5 of FIG.

  Here, when the weighting amounts in the sustain periods SUS1 to SUS5 in FIG. 3 are 1, 2, 4, 8, and 16 in order, the number of times of light emission in each of the sustain periods SUS1 to SUS5 is a predetermined coefficient ( This coefficient is called a weighting constant).

  Therefore, the drive control circuit 5 can adjust the luminance of the video by adjusting the weighting constant. The drive control circuit 5 can also adjust the power consumption of the display device 8 by adjusting the weighting constant.

  In this case, the drive control circuit 5 may have a table for determining a weighting constant based on the average signal level p2 in advance.

  In the following description, it is assumed that the weighting constant is a multiplication value of a predetermined constant multiplication factor and a multiple for obtaining a desired sustain pulse (hereinafter referred to as a sustain pulse multiple). The drive control circuit 5 is assumed to have a table indicating the relationship between the sustain pulse multiple and the average signal level p2 in advance.

  FIG. 4 is a diagram illustrating an example of a table showing the relationship between the sustain pulse multiple of the drive control circuit 5 and the average signal level p2, and the relationship between the power consumption of the display device 8 and the magnitude of the average signal level p2.

  According to the table of FIG. 4, the sustain pulse constant is 4 when the average signal level p <b> 2 is equal to or less than a predetermined value (dotted line position). As the average signal level p2 becomes larger than a predetermined value, the sustain pulse multiple is gradually reduced.

  As a result, the drive control circuit 5 can decrease the number of times of light emission in the above-described sustain periods SUS1 to SUS5 as the average signal level p2 exceeds the predetermined value.

  As a result, the drive control circuit 5 can maintain the power consumption of the display device 8 at a constant power value Vc as shown in FIG. 4 even when the average signal level p2 exceeds a predetermined value. it can.

  As described above, the drive control circuit 5 can adjust the power consumption of the display device 8 based on the table as shown in FIG. By adjusting the power consumption as described above, the display device 8 is stably driven, and the reliability of the display device 8 is improved. In addition, the power consumption of the display device 8 is prevented from becoming excessively large, and a reduction in power consumption is realized.

  Next, the average signal level calculation circuit 7 in FIG. 1 will be described. In the basic configuration of the video display device 100 of the present invention, the average signal level calculation circuit 7 has the following configuration, for example.

  FIG. 5 is a block diagram showing an example of the configuration of the average signal level calculation circuit 7 of FIG. The average signal level calculation circuit 7 of FIG. 5 includes a signal addition circuit 71, a horizontal addition circuit 72, a vertical addition circuit 73, and a normalization circuit 74.

  In FIG. 5, the video signal p1 is given to the signal adding circuit 71 from the second video signal processing circuit 6 of FIG. As shown in FIG. 5, the video signal p1 may be composed of a red primary color signal (R signal), a green primary color signal (G signal), and a blue primary color signal (B signal), or may be composed of a luminance signal. Good.

  The signal addition circuit 71 adds a plurality of primary color signals constituting the video signal p1 in units of pixels. Thereby, the signal addition circuit 71 calculates the signal level of the video signal p1 in units of pixels. The signal addition circuit 71 gives the calculated signal level of the pixel unit to the horizontal addition circuit 72.

  The horizontal adder circuit 72 is supplied with the signal level of the pixel unit from the signal adder circuit 71 and the timing signal HTS based on the horizontal synchronizing signal HS from the timing signal generating circuit 9 of FIG.

  The horizontal addition circuit 72 cumulatively adds the signal level in units of pixels based on the timing signal HTS, and calculates the signal level in units of one line. The horizontal adder circuit 72 gives the calculated signal level of one line unit to the vertical adder circuit 73.

  The vertical adder circuit 73 is given a signal level in units of one line from the horizontal adder circuit 72, and is given a timing signal VTS based on the vertical synchronizing signal VS from the timing signal generating circuit 9 of FIG.

  The vertical adder circuit 73 cumulatively adds signal levels in units of one line based on the timing signal VTS to calculate signal levels in units of one field. The vertical adder circuit 73 gives the calculated signal level of one field unit to the normalization circuit 74.

  The normalization circuit 74 normalizes the given signal level by dividing it by a predetermined coefficient to calculate an average signal level p2.

  In the example of FIG. 5, the average signal level p2 is calculated based on the red primary color signal R, the blue primary color signal B, and the green primary color signal G, and the luminance signal is input to the signal addition circuit 71 as the average signal level signal p2. In this case, it may be calculated based on the luminance signal. In this case, the average signal level p2 is an average luminance level.

  As described above, the predetermined processing of the video signal p1 in the second video signal processing circuit 6 is simple and equivalent to the predetermined processing of the first video signal processing circuit 4.

  Therefore, when the average signal level calculation circuit 7 calculates the average signal level based on the video signal o1 output from the first video signal processing circuit 4, the average signal level is calculated from the second video signal processing circuit 6. It almost coincides with the average signal level p2 generated based on the output video signal p1.

  Thereby, the drive control circuit 5 can adjust the drive condition of the display device 8 by using the average signal level p2 that substantially matches the average signal level of the video signal o1. Thereby, high image quality by the first video signal processing circuit 4 is preferably realized.

  The above is the basic configuration of the video display device 100 of the present invention. According to the video display device 100 having this basic configuration, the drive conditions of the display device 8 are adjusted based on the video signal p1 that has been processed equivalent to the processing by the first video signal processing circuit 4. The drive condition of the display device 8 corresponding to the video signal o1 output from the first video signal processing circuit 4 is adjusted. Thereby, processing of a desired video signal based on the processing by the first video signal processing circuit 4 is realized.

The video signal n1 is stored in the field memory 3 for one field when processed by the first video signal processing circuit 4. As a result, the video signal o1 processed by the first video signal processing circuit 4 can be delayed by one field with respect to the video signal p1 processed by the second video signal processing circuit 6. Thereby, the drive control circuit 5 drives the display device 8 based on the video signal p1 in the same field as the field of the video signal p1 used by the average signal level calculation circuit 7 to adjust the drive condition . Driving conditions are adjusted optimally. As a result, processing of a desired video signal based on the processing by the first video signal processing circuit 4 is realized.

As described above, in the video display device 100 having this basic configuration, the drive control circuit is based on the field of the video signal p1 used by the average signal level calculation circuit 7 to adjust the drive conditions and the video signal o1 in the same field. 5 drives the display device 8, and the drive control circuit 5 adjusts the drive condition with an average signal level p 2 that substantially matches the average signal level of the video signal o 1.

  Here, when the display device 8 is configured to include the PDP 80 of FIG. 2, the power unlocking of each discharge cell of the PDP 80 that occurs due to the significantly different adjustment of the driving conditions is sufficiently prevented. Thereby, the reliability of each discharge cell is maintained, and the life of the PDP 80 is extended.

  Furthermore, since the second video signal processing circuit 6 performs processing equivalent to the processing by the first video signal processing circuit 4 without using the field memory 3, the field memory 3 corresponding to the second video signal processing circuit 6 is used. There is no need to provide. As a result, the circuit scale is reduced, and cost reduction and ease of manufacture are realized.

  In addition, although the structure containing PDP80 as the display apparatus 8 was shown above, the display apparatus 8 may be a structure containing a liquid crystal display panel or a cathode ray tube.

  The average signal level calculation circuit 7 calculates the average signal level for each field by the signal addition circuit 71, the horizontal addition circuit 72, the vertical addition circuit 73, and the normalization circuit 74. The configuration is not limited to this.

  The average signal level calculation circuit 7 adjusts driving conditions based on the average signal level for each field. As described above, when the average signal level is calculated based on the red primary color signal R, the blue primary color signal B, and the green primary color signal G, or when the average signal level is calculated based on the luminance signal, the image displayed on the display device 8 is displayed. The brightness is adjusted. Thereby, the user can obtain a desired image.

  Next, specific configuration examples of the first video signal processing circuit 4 and the second video signal processing circuit 6 will be described. Note that a video display device 100 described later has the same configuration and operation as the video display device 100 of FIG. 1 described above unless otherwise specified.

(First configuration example)
FIG. 6 is a block diagram of the video display apparatus 100 according to the first configuration example. As shown in FIG. 6, in the video display device 100 according to the first configuration example, the first video signal processing circuit 4 includes a resize processing circuit 401, and the second video signal processing circuit 6 includes a resize level calculation circuit 601. Is provided.

  Details of the resizing processing circuit 401 and the resizing level arithmetic circuit 601 will be described.

  The resizing processing circuit 401 performs a video display area changing process (hereinafter referred to as a resizing process) on the video signal n1 supplied from the video format conversion circuit 2. The resizing process is a process of changing the size of the display area to be displayed on the display device 8.

  For example, when the size of the display area is doubled in the horizontal direction and doubled in the vertical direction, the resizing processing circuit 401 doubles the number of each pixel data of the video signal n1 in the display area in the horizontal direction, Double in the vertical direction.

  The resizing processing circuit 401 stores predetermined information (hereinafter referred to as resizing information) used during the resizing process. This resize information is a scaling ratio of the display area.

  Further, as shown in FIG. 6, the resizing information r <b> 1 is appropriately given from the resizing processing circuit 401 to the resizing level calculation circuit 601. The resizing information r1 includes a horizontal resizing rate and a vertical resizing rate.

  The resizing processing circuit 401 performs the resizing process by writing the video signal n1 to the field memory 3 and reading the video signal n2 written to the field memory 3.

  The resize level calculation circuit 601 will be described. The resizing level calculation circuit 601 includes, for example, two multiplication circuits. FIG. 7 is a diagram showing an example of the configuration of the resize level arithmetic circuit 601 in FIG.

  The multiplication circuit 63 of the resize level calculation circuit 601 is supplied with the video signal n1 from the video format conversion circuit 2 and the horizontal resize ratio Hr from the resize processing circuit 401. As a result, the video signal n1 is multiplied by the horizontal resizing rate Hr.

  The multiplication circuit 64 of the resize level calculation circuit 601 is supplied with the multiplication result of the video signal n1 and the horizontal resize rate Hr and the vertical resize rate Vr from the resize processing circuit 401. As a result, the multiplication result of the video signal n1 and the horizontal resizing rate Hr is further multiplied by the vertical resizing rate Vr. Thereby, the video signal p1 is generated.

  The resize level calculation circuit 601 gives the generated video signal p1 to the average signal level calculation circuit 7 of FIG. The processing performed by the resizing level calculation circuit 601 is called resizing level calculation processing.

  Here, the video signal o1 obtained by the resizing process of the resizing processing circuit 401 and the signal level of the video signal p1 obtained by the resizing level computing process of the resizing level computing circuit 601 will be described with reference to FIG.

  FIG. 8 is a conceptual diagram for explaining the signal levels of the two video signals o1 and p1 generated by the resize processing circuit 401 and the resize level calculation circuit 601 in FIG.

  In FIG. 8, focusing on one pixel data g of the video signal n1, it is assumed that the video display area is doubled in the horizontal direction and doubled in the vertical direction. In this case, the resizing information r1 stored in the resizing processing circuit 401 has a horizontal resizing rate Hr of 2 and a vertical resizing rate Vr of 2.

  As shown in FIG. 8, in the resize processing circuit 401, the number of pixel data g of the video signal n1 is doubled in the horizontal direction and doubled in the vertical direction by the resize information r1.

  Accordingly, the resizing processing circuit 401 outputs the video signal o1 of the four pixel data g based on the single pixel data g of the video signal n1. In this case, if the signal level of one pixel data g of the video signal n1 is represented by g, the sum of the signal levels of the four pixel data g of the video signal o1 is 4g.

  On the other hand, in the resize level calculation circuit 601, one pixel data g of the video signal n1 is multiplied by using the resize information r1 provided from the resize processing circuit 401. That is, one pixel data g is multiplied by 2 of the horizontal resizing rate Hr and 2 of the vertical resizing rate Vr.

  Accordingly, the resize level calculation circuit 601 outputs a video signal p1 of pixel data whose signal level is quadrupled. In this case, if the signal level of one pixel data g of the video signal n1 is represented by g, the signal level of one pixel data of the video signal p1 is 4g.

  As described above, in the video display device 100 according to this configuration example, the sum of the signal levels of the four pixel data g of the video signal o1 after the resizing process of the resizing processing circuit 401 and the resizing level calculation of the resizing level calculation circuit 601 are performed. The signal level of one pixel data of the video signal p1 obtained by the processing matches.

  That is, it can be said that the resizing process performed in the resizing processing circuit 401 and the resizing level calculating process performed in the resizing level calculating circuit 601 are equivalent to each other.

  The resizing process performed in the resizing processing circuit 401 is a process using the field memory 3. On the other hand, the resize level calculation process performed in the resize level calculation circuit 601 is a process that does not use the field memory 3. The resizing level calculation process is simpler than the resizing process. Thereby, the configuration of the resizing level arithmetic circuit 601 is simpler than the configuration of the resizing processing circuit 401.

  As described above, according to the video display device 100 according to the first configuration example, the resizing processing using the field memory 3 is performed by the resizing processing circuit 401 in the first video signal processing circuit 4, and the second video signal. In the processing circuit 6, the resize level calculation circuit 601 performs a resize level calculation process that is equivalent to the resize process and does not use the field memory 3. As a result, the circuit scale of the second video signal processing circuit 6 is reduced, and cost reduction and easy manufacture are realized.

  Further, the resizing processing circuit 401 performs the resizing process based on the video signal n2 stored in the field memory 3 and the resizing information r1 regarding the display area of the display device 8. Further, the resize level calculation process is performed by the second linear calculation processing circuit 602 based on the resize information r1.

  The resize level calculation process of the resize level calculation circuit 601 is simpler and equivalent to the resize process. Thereby, the circuit configuration of the second video signal processing circuit 6 is simplified, the circuit scale is reduced, and the cost is reduced and the manufacturing is facilitated. Further, the display area changing process by the resizing process is preferably performed.

(Second configuration example)
FIG. 9 is a block diagram showing a configuration of the video display apparatus 100 according to the second configuration example. As shown in FIG. 9, in the video display device 100 according to the second configuration example, the first video signal processing circuit 4 in FIG. 1 includes a resizing processing circuit 401 and a first linear arithmetic processing circuit 402, and a second The video signal processing circuit 6 includes a resizing level arithmetic circuit 601 and a second linear arithmetic processing circuit 602.

  The resizing processing circuit 401 and the resizing level calculation circuit 601 have the same configuration and operation as the resizing processing circuit 401 and the resizing level calculation circuit 601 of the video display device 100 according to the first configuration example.

  The video display device 100 according to this configuration example includes a coefficient generation device 10 in addition to the basic configuration of FIG. The coefficient generator 10 is composed of, for example, a CPU (Central Processing Unit) or a microcomputer. The coefficient generator 10 provides a first coefficient group K1 described later to the first linear arithmetic processing circuit 402, and supplies a second coefficient group K2 described later to the second linear arithmetic processing circuit 602.

  In this example, the video signal AVD input to the A / D converter 1 will be described as being composed of a luminance signal and a color difference signal.

  In the first video signal processing circuit 4 in FIG. 9, the video signal n <b> 1 is supplied from the video format conversion circuit 2 to the resizing processing circuit 401. In the resizing processing circuit 401, the resizing process described in the first configuration example is performed on the video signal n1, and the video signal n3 is generated. The generated video signal n3 is given to the first linear arithmetic processing circuit 402, and predetermined processing using the first coefficient group K1 given from the coefficient generator 10 is performed by the first linear arithmetic processing circuit 402. .

  Thereby, the video signal o1 is generated, and the video signal o1 is given to the drive control circuit 5. The processing content of the first linear arithmetic processing circuit 402 for the video signal n3 will be described later.

  In the second video signal processing circuit 6 of FIG. 9, the video signal n1 is supplied from the video format conversion circuit 2 to the second linear arithmetic processing circuit 602, and the second coefficient group K2 is supplied from the coefficient generator 10. .

  In the second linear arithmetic processing circuit 602, predetermined processing using the second coefficient group K2 is performed on the video signal n1, and the video signal p10 is generated. The processing content of the second linear arithmetic processing circuit 602 for the video signal n1 will be described later.

  The generated video signal p10 is given to the resize level calculation circuit 601. In the resize level calculation circuit 601, the resize level calculation process described in the first configuration example is performed on the video signal p10. Thereby, the video signal p1 is generated, and the video signal p1 is given to the average signal level calculation circuit 7.

  The resizing process in the resizing processing circuit 401 and the resizing level computing process in the resizing level computing circuit 601 are equivalent to each other as described in the first configuration example.

  The first linear arithmetic processing circuit 402 and the second linear arithmetic processing circuit 602 are a first coefficient group K1 and a second coefficient group K2 given from the coefficient generator 10 to the input video signals n1 and p10. The same processing is performed based on

  In this configuration example, the process performed by the first linear arithmetic processing circuit 402 and the second linear arithmetic processing circuit 602 is an inverse matrix conversion process that is a linear arithmetic process.

  Inverse matrix transformation processing performed by the first linear arithmetic processing circuit 402 and the second linear arithmetic processing circuit 602, and details of the first coefficient group K1 and the second coefficient group K2 output from the coefficient generator 10 This will be described with reference to FIG.

  FIG. 10 is a diagram for explaining the inverse matrix transformation processing performed by the first linear arithmetic processing circuit 402 and the second linear arithmetic processing circuit 602 of FIG. 9, and the first coefficient group K1 and the second coefficient group K2. FIG.

  As shown in FIG. 10, the first linear arithmetic processing circuit 402 receives the video signal n3 from the resizing processing circuit 401 and the first coefficient group K1 from the coefficient generator 10. Here, in this configuration example, the video signal n3 includes one luminance signal Y1 and two color difference signals U1 and V1. The first coefficient group K1 includes a plurality of coefficients a1 to i1 for performing an inverse matrix conversion process.

  The first linear arithmetic processing circuit 402 performs an inverse matrix conversion process using a plurality of coefficients a1 to i1 on the luminance signal Y1 and the color difference signals U1 and V1. Accordingly, the first linear arithmetic processing circuit 402 generates a video signal o1 including the three red primary color signals R1, the blue primary color signal B1, and the green primary color signal G1, and supplies the generated video signal o1 to the drive control circuit 5. .

  On the other hand, the second linear arithmetic processing circuit 602 receives the video signal n1 from the video format conversion circuit 2 and the second coefficient group K2 from the coefficient generator 10. Similarly to the above, the video signal n1 includes one luminance signal Y2 and two color difference signals U2 and V2. The second coefficient group K2 includes a plurality of coefficients a2 to i2 for performing an inverse matrix conversion process.

  The second linear arithmetic processing circuit 602 performs inverse matrix conversion processing on the luminance signal Y2 and the color difference signals U2 and V2 using a plurality of coefficients a2 to i2. As a result, the second linear arithmetic processing circuit 602 generates a video signal p10 composed of the three red primary color signals R2, the blue primary color signal B2, and the green primary color signal G2, and the generated video signal p10 is sent to the resize level arithmetic circuit 601. give.

  The number of bits of each coefficient included in the first coefficient group K1 and the second coefficient group K2 output from the coefficient generator 10 is different. Specifically, if the number of bits of each coefficient included in the first coefficient group K1 is x and the number of bits of each coefficient included in the second coefficient group K2 is y, the number of bits included in the second coefficient group K2 is included in the second coefficient group K2. The number of bits y of each coefficient is smaller than the number of bits x of each coefficient included in the first coefficient group K1.

  As a result, the video signal p10 obtained by the inverse matrix transformation process performed by the second linear arithmetic processing circuit 602 with respect to the number of bits of the video signal o1 obtained by the inverse matrix transformation process performed by the first linear arithmetic processing circuit 402. The number of bits is reduced.

  As described above, the second linear arithmetic processing circuit 602 includes a plurality of coefficients having a number of bits smaller than the number of bits of each coefficient included in the first coefficient group K1 used in the first linear arithmetic processing circuit 402. Since the inverse matrix transformation process is performed with the second coefficient group K2, the configuration can be made simpler than the configuration of the first linear arithmetic processing circuit 402. In addition, since the second linear arithmetic processing circuit 602 has a smaller number of bits of data used for the inverse matrix conversion process than the first linear arithmetic processing circuit 402, the circuit scale can be reduced.

  According to the video display device 100 according to the second configuration example, the first linear arithmetic processing circuit 402 performs the inverse matrix transformation process without using the field memory 3, and the second linear arithmetic processing circuit 602 performs the field memory 3. Inverse matrix conversion processing without using is performed. As a result, the first linear arithmetic processing circuit 402 and the second linear arithmetic processing circuit 602 do not use the field memory 3, so that the circuit configuration is simplified, the circuit scale is reduced, the cost is reduced, and the manufacturing is facilitated. Realized.

  In addition, since the resizing process and the inverse matrix conversion process are performed in the first video signal processing circuit 4, processing of a desired video signal based on a plurality of processes is realized.

  Further, the inverse matrix transformation process using the first coefficient group K1 including a plurality of coefficients of the number of bits x is performed by the first linear arithmetic processing circuit 402, and the bits of each coefficient included in the first coefficient group K1. An inverse matrix transformation process using the second coefficient group K2 including a plurality of coefficients having a bit number y smaller than the number x is performed by the second linear arithmetic processing circuit 602.

  As described above, the inverse matrix of the second linear arithmetic processing circuit 602 is compared with the bit number x of each coefficient included in the first coefficient group K1 used for the inverse matrix conversion processing of the first linear arithmetic processing circuit 402. Since the number of bits y of each coefficient included in the second coefficient group K2 used for the conversion process is small, the circuit configuration of the second linear arithmetic processing circuit 602 that performs the inverse matrix conversion process is simplified, and the circuit scale is reduced. Thus, cost reduction and manufacturing ease are realized.

  In the above second configuration example, as shown in FIG. 9, the second linear arithmetic processing circuit 602 may be provided in the preceding stage of the resizing level calculating circuit 601 or in the subsequent stage of the resizing level calculating circuit 601. It may be provided.

(Third configuration example)
FIG. 11 is a block diagram showing a video display apparatus 100 according to the third configuration example. As shown in FIG. 11, in the video display device 100 according to the third configuration example, the first video signal processing circuit 4 in FIG. 1 includes a resizing processing circuit 401 and a third linear arithmetic processing circuit 403, and the second The video signal processing circuit 6 includes a resizing level arithmetic circuit 601 and a fourth linear arithmetic processing circuit 603.

  Here, the resizing processing circuit 401 and the resizing level calculation circuit 601 have the same configuration and operation as the resizing processing circuit 401 and the resizing level calculation circuit 601 of the video display apparatus 100 according to the first configuration example.

  In addition to the basic configuration of FIG. 1, the video display device 100 according to this configuration example includes an external arithmetic device 11. The external arithmetic unit 11 is composed of, for example, a CPU or a microcomputer. The external arithmetic unit 11 gives a third coefficient group K3, which will be described later, to the third linear arithmetic processing circuit 403, and gives a fourth coefficient group K4, which will be described later, to the fourth linear arithmetic processing circuit 603.

  In the first video signal processing circuit 4 of FIG. 11, the video signal n <b> 1 is supplied from the video format conversion circuit 2 to the resizing processing circuit 401. The resize processing circuit 401 performs the resize processing described in the first configuration example on the video signal n1 to generate the video signal n3. The generated video signal n3 is given to the third linear arithmetic processing circuit 403, and predetermined processing using the third coefficient group K3 given from the external arithmetic unit 11 is performed by the third linear arithmetic processing circuit 403. .

  Thus, the third linear arithmetic processing circuit 403 generates the video signal o1, and the generated video signal o1 is given to the drive control circuit 5. The processing content of the third linear arithmetic processing circuit 403 for the video signal n3 will be described later.

  In the second video signal processing circuit 6 of FIG. 11, the video signal n1 is supplied from the video format conversion circuit 2 to the fourth linear arithmetic processing circuit 603, and the fourth coefficient group K4 is supplied from the external arithmetic device 11. .

  The fourth linear arithmetic processing circuit 603 performs a predetermined process using the fourth coefficient group K4 on the video signal n1, and generates a video signal p11. The processing content of the fourth linear arithmetic processing circuit 603 for the video signal n1 will be described later.

  The generated video signal p11 is given to the resize level calculation circuit 601. Resizing information r 1 is given from the resizing processing circuit 401 to the resizing level arithmetic circuit 601. As a result, the resize level calculation circuit 601 performs the resize level calculation process described in the first configuration example on the video signal p11. Thereby, the video signal p1 is generated, and the generated video signal p1 is given to the average signal level calculation circuit 7.

  The resizing process in the resizing processing circuit 401 and the resizing level computing process in the resizing level computing circuit 601 are equivalent to each other as described in the first configuration example.

  Details of the third linear arithmetic processing circuit 403 and the fourth linear arithmetic processing circuit 603 will be described.

  As shown in FIG. 11, in this example, the third linear arithmetic processing circuit 403 includes an adder circuit 41, multiplier circuits 42 a, 42 b, 42 c, a selection circuit 43, and a control signal generation circuit 44. The fourth linear arithmetic processing circuit 603 includes an adder circuit 61 and a multiplier circuit 62.

  In this configuration example, the processing performed by the third linear arithmetic processing circuit 403 and the fourth linear arithmetic processing circuit 603 is linear arithmetic processing including addition processing and multiplication processing.

  The hue of the video is adjusted by the linear calculation processing of the third linear calculation processing circuit 403.

  FIG. 12 is a diagram for explaining the linear arithmetic processing by the third linear arithmetic processing circuit 403 and the fourth linear arithmetic processing circuit 603 of FIG. 11 and the third coefficient group K3 and the fourth coefficient group K4. . FIG. 13 is a diagram illustrating an example of an image display form in the third configuration example.

  The reason why the third linear arithmetic processing circuit 403 is provided in the subsequent stage of the resizing processing circuit 401 and the fourth linear arithmetic processing circuit 603 is provided in the previous stage of the resizing level arithmetic circuit 601 will be described later.

  In this example, as shown in FIG. 13, a main screen area MS and a sub screen area SS are formed on the screen of the PDP 80, and an image is displayed in each of the main screen area MS and the sub screen area SS.

  For example, the external arithmetic unit 11 performs the third coefficient group K3 and the third coefficient group K3 to be given to the third linear arithmetic processing circuit 403 and the fourth linear arithmetic processing circuit 603 based on the operation of a remote controller (not shown) by the user. A coefficient group K4 of 4 is determined.

  According to FIG. 12, the third coefficient group K3 includes five coefficients a31, a32, b3, c3, and d3, and the fourth coefficient group K4 includes two coefficients a4 and b4. The coefficient a31 of the third coefficient group K3 is a coefficient for the main screen area MS, and the coefficient a32 is a coefficient for the sub-screen area SS.

  Both of the two coefficients a31 and a32 are given to the selection circuit 43 of the third linear arithmetic processing circuit 403. The two coefficients a31 and a32 are different from each other but have substantially the same value.

  The coefficients b3 and c3 of the third coefficient group K3 are given to the multiplication circuit 42b of the third linear arithmetic processing circuit 403, and the coefficient d3 is given to the multiplication circuit 42c.

  In the third linear arithmetic processing circuit 403, the selection circuit 43 is supplied with the coefficients a31 and a32 and the control signal generation circuit 44 is supplied with a switching control signal CS for selecting one of the coefficients a31 and a32. It is done.

  As shown in FIG. 13, when the main screen area MS and the sub screen area SS are formed in the PDP 80, the control signal generation circuit 44 includes an area flag CS1 indicating the horizontal range of the main screen area MS, the sub screen area A region flag CS2 indicating the horizontal range of SS, a region flag CS3 indicating the vertical range of the main screen region MS, and a region flag CS4 indicating the vertical range of the sub-screen region SS are provided.

  The region flag CS1 becomes logic “1” within the horizontal range of the main screen region MS, and becomes logic “0” outside the horizontal range of the main screen region MS.

  The area flag CS2 becomes logic “1” within the horizontal range of the sub-screen area SS, and becomes logic “0” outside the horizontal range of the sub-screen area SS.

  The area flag CS3 becomes logic “1” within the vertical range of the main screen area MS, and becomes logic “0” outside the horizontal range of the main screen area MS.

  The area flag CS2 becomes logic “1” within the vertical range of the sub-screen area SS, and becomes logic “0” outside the horizontal range of the sub-screen area SS.

  These area flags CS 1, CS 2, CS 3 and CS 4 are created by the resizing processing circuit 401.

  The control signal generation circuit 44 generates the switching control signal CS based on the region flags CS1, CS2, CS3, CS4 and the timing signals HTS, VTS output from the timing signal generation circuit 9 of FIG.

  The selection circuit 43 selects one of the coefficients a31 and a32 given by the external arithmetic unit 11 based on the switching control signal CS, and gives the selected coefficient to the multiplication circuit 42a as the coefficient a3.

  The multiplication circuit 42a is supplied with the pixel data g of the video signal n3 from the resizing processing circuit 401 in FIG. The multiplication circuit 42a multiplies the pixel data g by the coefficient a3 from the selection circuit 43. In this case, when the signal level of the pixel data g is represented by g, the output value of the multiplication circuit 42a is a3g.

  The multiplication circuit 42b multiplies the coefficient b3 from the external arithmetic unit 11 and the coefficient c3. The output value of the multiplier circuit 42b is b3c3.

  The adder circuit 41 adds the output value a3g of the multiplier circuit 42a and the output value b3c3 of the multiplier circuit 42b. The output value of the adder circuit 41 is (a3g + b3c3).

  The multiplier circuit 42c multiplies the output value (a3g + b3c3) of the adder circuit 41 and the coefficient d3. The output value of the multiplier circuit 42c is d3 (a3g + b3c3). The output value (d3 (a3g + b3c3)) of the multiplier circuit 42c is given to the drive control circuit 5 as pixel data of the video signal o1.

  As shown in FIG. 12, the fourth coefficient group K4 includes a coefficient a4 and a coefficient b4. The external arithmetic unit 11 determines the fourth coefficient group K4 based on the third coefficient group K3. Specifically, the external arithmetic unit 11 determines the multiplication result of either the coefficient a31 or the coefficient a32 and the coefficient d3 as the coefficient a4. Further, the external arithmetic unit 11 determines the multiplication result of the coefficients b3, c3, d3 as the coefficient b4.

  In this example, the external arithmetic unit 11 determines the multiplication result of the coefficient a31 and the coefficient d3 as the coefficient a4.

  The coefficient a4 is given to the multiplier circuit 62, and the coefficient b4 is given to the adder circuit 61. The multiplication circuit 62 is supplied with the video signal n1 from the video format conversion circuit 2 of FIG. The multiplication circuit 62 multiplies the pixel data g of the video signal n1 and the coefficient a4. When the signal level of the pixel data g of the video signal n1 is represented by g which is the same as the pixel data of the video signal n3, the output value of the multiplication circuit 62 is a4g.

  The adder circuit 61 adds the output value a4g of the multiplier circuit 62 and the coefficient b4. The output value of the adder circuit 61 is (a4g + b4). The output value (a4g + b4) of the adder circuit 61 is given to the resize level calculation circuit 601 as pixel data of the video signal p11.

  The third linear arithmetic processing circuit 403 performs processing using different coefficients a31 and a32 on the video signal n3 of the main screen area MS and the video signal n3 of the sub-screen area SS.

  On the other hand, the fourth linear arithmetic processing circuit 603 performs processing using a common coefficient a4 for the video signal n3 in the main screen area MS and the video signal n3 in the sub-screen area SS.

  In this case, the coefficient a31 is equal to the coefficient a4, and the coefficient a32 is different from the coefficient a4 but has a close value.

  Further, the coefficient used for the addition process by the third linear arithmetic processing circuit 403 and the coefficient used for the addition process by the fourth linear arithmetic processing circuit 603 coincide with each other.

  Thereby, when the video signal n3 of the main screen area MS is processed, the output value of the video signal o1 output from the third linear arithmetic processing circuit 403 and the output of the video signal p11 output from the fourth linear arithmetic processing circuit 603 are output. When the video signal n3 of the sub-screen area SS is processed, the output value of the video signal o1 output from the third linear arithmetic processing circuit 403 and the video signal output from the fourth linear arithmetic processing circuit 603 are equal to each other. The output value of p11 is an approximate value.

  In other words, the third linear arithmetic processing circuit 403 and the fourth linear arithmetic processing circuit 603 are different in circuit configuration from each other, but perform equivalent processing on the input video signal.

  As shown in FIG. 12, the circuit configuration and linear arithmetic processing of the fourth linear arithmetic processing circuit 603 are simpler than the circuit configuration and linear arithmetic processing of the third linear arithmetic processing circuit 403. As a result, the circuit scale of the third linear arithmetic processing circuit 403 is reduced, and cost reduction and easy manufacture are realized.

  The external arithmetic unit 11 may generate coefficients for the main screen area MS and the sub screen area SS corresponding to the coefficients b3, c3, and d3, respectively, and selectively supply them to the third linear arithmetic processing circuit 403. .

  Incidentally, as described above, the resize processing circuit 401 of the first video signal processing circuit 4 corresponds to the resize level calculation circuit 601 of the second video signal processing circuit 6. The third linear arithmetic processing circuit 403 of the first video signal processing circuit 4 corresponds to the fourth linear arithmetic processing circuit 603 of the second video signal processing circuit 6. In addition, equivalent processing is performed between corresponding circuits.

  However, in this configuration example, the resize level arithmetic circuit 601 of the second video signal processing circuit 6 is a fourth linear arithmetic processing circuit in order to realize processing equivalent to the processing performed by the first video signal processing circuit 4. It is necessary to be provided in the subsequent stage of 603. Hereinafter, this reason will be described.

  14 and 15 show the relationship between the arrangement of the resizing level arithmetic circuit 601 and the fourth linear arithmetic processing circuit 603 in FIG. 11 and the signal level of the video signal p1 generated by the second video signal processing circuit 6. FIG. It is a conceptual diagram for demonstrating.

  14 and 15, the resizing processing circuit 401 of the first video signal processing circuit 4 is provided in the preceding stage of the third linear arithmetic processing circuit 403.

  Here, the resizing processing circuit 401 doubles the video display area in the horizontal direction and doubles in the vertical direction. The third linear arithmetic processing circuit 403 performs predetermined linear arithmetic processing on the video signal n3 given from the resizing processing circuit 401.

  The processing contents of the resizing processing circuit 401 and the third linear arithmetic processing circuit 403 will be described by focusing on one pixel data g of the video signal n1. In the following description, the signal level of the pixel data g is represented by g.

  14 and 15, the resizing processing circuit 401 stores resizing information r1 indicating that the video display area is doubled in the horizontal direction and doubled in the vertical direction.

  In the resize processing circuit 401, the number of pixel data g of the video signal n1 is doubled in the horizontal direction and doubled in the vertical direction based on the resize information r1.

  Thereby, the resizing processing circuit 401 gives the video signal n3 including the four pixel data g to the third linear arithmetic processing circuit 403 based on the one pixel data g of the video signal n1. The third linear arithmetic processing circuit 403 performs linear arithmetic processing on each of the four pixel data g of the video signal n3 based on the coefficients α and β given from the external arithmetic device 11.

  Here, in order to facilitate the following description, it is assumed that the external arithmetic unit 11 gives the same coefficients α and β to the third linear arithmetic processing circuit 403 and the fourth linear arithmetic processing circuit 603.

  As shown in FIGS. 14 and 15, the linear calculation processing of the third linear calculation processing circuit 403 is a process of multiplying each of the pixel data g of the video signal n3 by the coefficient α and then adding the coefficient β. is there. As a result, the third linear arithmetic processing circuit 403 outputs a video signal o1 including four pixel data with a signal level of αg + β. In this case, the sum of the signal levels of the four pixel data is 4αg + 4β.

  In FIG. 14, the resizing level calculation circuit 601 is arranged at the subsequent stage of the fourth linear calculation processing circuit 603 as shown in FIG. 11. In this case, the video signal n1 is given to the fourth linear arithmetic processing circuit 603. The fourth linear arithmetic processing circuit 603 performs linear arithmetic processing on one pixel data g of the video signal n1 based on the two coefficients α and β given from the external arithmetic unit 11.

  As shown in FIG. 14, the linear calculation processing of the fourth linear calculation processing circuit 603 is a process of multiplying one pixel data g of the video signal n1 by a coefficient α and then adding a coefficient β.

  As a result, the fourth linear arithmetic processing circuit 603 provides the resize level arithmetic circuit 601 with the video signal p11 including one pixel data with a signal level of αg + β. In the resizing level calculation circuit 601, one pixel data of the video signal p11 is multiplied by 2 of the horizontal resizing rate Hr and 2 of the vertical resizing rate Vr.

  Thus, the resizing level calculation circuit 601 outputs the video signal p1 including one pixel data in which the signal level of αg + β is quadrupled and becomes 4αg + 4β.

  As described above, in the second video signal processing circuit 6, when the resize level calculation circuit 601 is provided at the subsequent stage of the fourth linear calculation processing circuit 603, the signal level of one pixel data of the output video signal p 1 is 4αg + 4β. And coincides with 4αg + 4β which is the sum of the signal levels of the four pixel data of the video signal o1 output from the third linear arithmetic processing circuit 403.

  Therefore, in FIG. 14, the processing by the first video signal processing circuit 4 and the processing by the second video signal processing circuit 6 are equivalent.

  On the other hand, in FIG. 15, the resizing level arithmetic circuit 601 is arranged in front of the fourth linear arithmetic processing circuit 603. In this case, the video signal n1 is supplied to the resize level calculation circuit 601.

  In the resizing level calculation circuit 601, one pixel data g of the video signal n1 is multiplied by 2 of the horizontal resizing rate Hr and 2 of the vertical resizing rate Vr.

  As a result, the resize level calculation circuit 601 provides the fourth linear calculation processing circuit 603 with the video signal p11 of one pixel data whose signal level is quadrupled.

  The fourth linear arithmetic processing circuit 603 performs linear arithmetic processing on one pixel data of the video signal p11 based on the two coefficients α and β given from the external arithmetic device 11.

  As described above, this linear calculation process is a process of multiplying one pixel data of the video signal p11 by the coefficient α and then adding the coefficient β. As a result, the fourth linear arithmetic processing circuit 603 outputs a video signal p1 including one pixel data. In this case, the signal level of one pixel data of the video signal p1 is 4αg + β.

  As described above, in the second video signal processing circuit 6, when the resize level calculation circuit 601 is provided before the fourth linear calculation processing circuit 603, a signal of one pixel data included in the output video signal p 1. The level is 4αg + β, which does not match 4αg + 4β, which is the sum of the signal levels of the four pixel data included in the video signal o1 output from the third linear arithmetic processing circuit 403.

  Therefore, in FIG. 15, the processing by the first video signal processing circuit 4 and the processing by the second video signal processing circuit 6 are not equivalent.

  As described above, in the present configuration example, in order to make the processing by the first video signal processing circuit 4 and the processing by the second video signal processing circuit 6 equivalent, The resizing level arithmetic circuit 601 needs to be provided at a stage after the fourth linear arithmetic processing circuit 603.

  In the video display device 100 according to the third configuration example, the number of the fourth coefficient group K4 (coefficients a4 and b4) that the external arithmetic unit 11 gives to the fourth linear arithmetic processing circuit 603 is the third linear arithmetic. The number is smaller than the number of third coefficient groups K3 (coefficients a31, a32, b3, c3, d3) given to the processing circuit 403.

  Accordingly, the fourth coefficient group used for the linear arithmetic processing of the fourth linear arithmetic processing circuit 603 is compared with the number of the third coefficient group K3 used for the linear arithmetic processing of the third linear arithmetic processing circuit 403. Since the number of K4 is small, the fourth linear arithmetic processing circuit 603 is simplified, the circuit scale is reduced, and low cost and easy manufacture are realized.

  Further, in the video display device 100 according to the present configuration example, since the linear arithmetic processing is performed on the video signal o1 that has been subjected to the resizing processing by the resizing processing circuit 401, processing of a desired video signal based on a plurality of processing is realized. The

  Further, in the second video signal processing circuit 6, the resize level calculation process of the resize level calculation circuit 601 is performed after the linear calculation process of the fourth linear calculation processing circuit 603 for the video signal n1, A video signal p1 equivalent to the video signal o1 that has been subjected to the resizing processing of the resizing processing circuit 401 and the linear arithmetic processing of the third linear arithmetic processing circuit 403 can be obtained.

(Fourth configuration example)
FIG. 16 is a block diagram showing a video display apparatus 100 according to the fourth configuration example. As shown in FIG. 16, in the video display device 100 according to the fourth configuration example, the first video signal processing circuit 4 of FIG. 1 includes a resizing processing circuit 401 and a fifth linear arithmetic processing circuit 404, and the second The video signal processing circuit 6 includes a resizing level arithmetic circuit 601 and a sixth linear arithmetic processing circuit 604.

  Here, the resizing processing circuit 401 and the resizing level calculation circuit 601 have the same configuration and operation as the resizing processing circuit 401 and the resizing level calculation circuit 601 of the video display apparatus 100 according to the first configuration example.

  In addition to the basic configuration of FIG. 1, the video display device 100 according to the present configuration example includes the external arithmetic device 11 described in the third configuration example. In the description of this configuration example, the external arithmetic unit 11 gives the first coefficient group K1 and the third coefficient group K3 to the fifth linear arithmetic processing circuit 404, and supplies the fifth coefficient group K5 described later to the sixth coefficient group K5. This is given to the linear arithmetic processing circuit 604.

  In this example, it is assumed that the video signal AVD input to the A / D converter 1 is composed of a luminance signal and a color difference signal.

  In the first video signal processing circuit 4 of FIG. 16, the resize processing circuit 401 is supplied with the video signal n1 from the video format conversion circuit 2. The resize processing circuit 401 performs the resize processing described in the first configuration example on the video signal n1 to generate the video signal n3. The generated video signal n3 is given to the fifth linear arithmetic processing circuit 404, and the first coefficient group K1 and the third coefficient group K3 given from the external arithmetic unit 11 by the fifth linear arithmetic processing circuit 404 are used. The predetermined processing is performed.

  Thus, the fifth linear arithmetic processing circuit 404 generates the video signal o1, and the generated video signal o1 is supplied to the drive control circuit 5. The processing content of the fifth linear arithmetic processing circuit 404 for the video signal n3 will be described later.

  In the second video signal processing circuit 6 of FIG. 16, the sixth linear arithmetic processing circuit 604 is supplied with the video signal n1 from the video format conversion circuit 2 and the fifth coefficient group K5 from the external arithmetic unit 11. It is done.

  The sixth linear arithmetic processing circuit 604 performs a predetermined process using the fifth coefficient group K5 on the video signal n1, and generates a video signal p11. The processing content of the sixth linear arithmetic processing circuit 604 for the video signal n1 will be described later.

  The generated video signal p11 is given to the resize level calculation circuit 601. Resizing information r <b> 1 is given from the resizing processing circuit 401 to the resizing level arithmetic circuit 601. As a result, the resize level calculation circuit 601 performs the resize level calculation process described in the first configuration example on the video signal p11. Thereby, the video signal p1 is generated, and the generated video signal p1 is given to the average signal level calculation circuit 7.

  The resizing process in the resizing processing circuit 401 and the resizing level computing process in the resizing level computing circuit 601 are equivalent to each other as described in the first configuration example.

  Details of the fifth linear arithmetic processing circuit 404 and the sixth linear arithmetic processing circuit 604 will be described.

  As shown in FIG. 16, in this example, the fifth linear arithmetic processing circuit 404 includes a control signal generation circuit 44, a hue adjustment circuit 45, a color adjustment circuit 46, and an inverse matrix conversion circuit 47.

  In this configuration example, the processing performed by the fifth linear arithmetic processing circuit 404 and the sixth linear arithmetic processing circuit 604 is linear arithmetic processing including inverse matrix conversion processing, addition processing, and multiplication processing.

  By the linear arithmetic processing of the fifth linear arithmetic processing circuit 404, hue adjustment and color adjustment of the video, inverse matrix conversion processing, and the like are performed.

  FIG. 17 shows the linear arithmetic processing by the fifth linear arithmetic processing circuit 404 and the sixth linear arithmetic processing circuit 604 of FIG. 16, and the first coefficient group K1, the third coefficient group K3, and the fifth coefficient group K5. It is a figure for demonstrating.

  For example, the external arithmetic unit 11 is configured to supply the first coefficient group K1 and the first coefficient group K1 to be given to the fifth linear arithmetic processing circuit 404 and the sixth linear arithmetic processing circuit 604 based on the operation of a remote controller (not shown) by the user. The third coefficient group K3 and the fifth coefficient group K5 are determined.

  According to FIG. 17, the third coefficient group K3 includes seven coefficients t11, t12, t2, u1, u2, u3, u4, and the first coefficient group K1 includes a plurality of coefficients for performing the inverse matrix transformation process. a1 to i1 are included. The fifth coefficient group K5 includes a plurality of coefficients a5 to i5 for performing the inverse matrix conversion process. The coefficient t11 of the third coefficient group K3 is a coefficient for the main screen area MS, and the coefficient t12 is a coefficient for the sub-screen area SS.

  As shown in FIG. 17, one luminance signal Y 1 of the video signal n 1 is given to the inverse matrix conversion circuit 47. On the other hand, the two color difference signals U 1 and V 1 are supplied to the hue adjustment circuit 45.

  The hue adjustment circuit 45 includes two multiplication circuits 45 a and 45 b and a selection circuit 43. The color difference signal U1 of the video signal n1 is supplied to the multiplication circuit 45a, and the color difference signal V1 is supplied to the multiplication circuit 45b. Also, the coefficients t11 and t12 are given from the external arithmetic unit 11 to the selection circuit 43. Further, the coefficient t2 is given from the external arithmetic unit 11 to the multiplication circuit 45b.

  Note that as described in the third configuration example, the selection control circuit 43 is supplied with the switching control signal CS from the control signal generation circuit 44. The selection circuit 43 gives one of the coefficients t11 and t12 to the multiplication circuit 45a based on the switching control signal CS.

  As described above, the hue adjustment circuit 45 performs the multiplication processing based on the coefficients t11, t12, and t2, that is, the hue adjustment of the video, for each of the color difference signals U1 and V1 of the video signal n1.

  As a result, the color difference signal U12 is supplied from the multiplication circuit 45a to the color adjustment circuit 46, and the color difference signal V12 is supplied from the multiplication circuit 45b to the color adjustment circuit 46.

  The color adjustment circuit 46 includes four multiplication circuits 46a to 46d and two addition circuits 46e and 46f. The color difference signal U12 is supplied to multiplication circuits 46a and 46b, and the color difference signal V12 is supplied to multiplication circuits 46c and 46d.

  Further, the coefficient u1 is given from the external arithmetic unit 11 to the multiplication circuit 46a, and the coefficient u2 is given to the multiplication circuit 46b. Further, the coefficient u3 is given from the external arithmetic unit 11 to the multiplication circuit 46c, and the coefficient u4 is given to the multiplication circuit 46d.

  In the multiplication circuit 46a, the color difference signal U12 and the coefficient u1 are multiplied, and the multiplication result is given to the addition circuit 46e. In the multiplication circuit 46c, the color difference signal V12 and the coefficient u3 are multiplied, and the multiplication result is given to the addition circuit 46e. As a result, the adder circuit 46e performs an addition process based on the two given multiplication results. The obtained addition result is given to the inverse matrix conversion circuit 47 as the color difference signal U13.

  In the multiplication circuit 46b, the color difference signal U12 and the coefficient u2 are multiplied, and the multiplication result is given to the addition circuit 46f. In the multiplication circuit 46d, the color difference signal V12 and the coefficient u4 are multiplied, and the multiplication result is given to the addition circuit 46f. As a result, the adder circuit 46f performs an addition process based on the two given multiplication results. The obtained addition result is given to the inverse matrix conversion circuit 47 as the color difference signal V13.

  As described above, the color adjustment circuit 46 performs multiplication processing and addition processing based on the coefficients u1, u2, u3, and u4 for each of the color difference signals U12 and V12, that is, video color adjustment.

  In the inverse matrix conversion circuit 47, an inverse matrix conversion process is performed based on the input luminance signal Y1 and color difference signals U13 and V13 and the first coefficient group K1 described in the first configuration example. As a result, a video signal o1 including the red primary color signal R1, the blue primary color signal B1, and the green primary color signal G1 is generated, and the generated video signal o1 is supplied to the drive control circuit 5.

  On the other hand, in the sixth linear arithmetic processing circuit 604, the inverse matrix transformation process based on the fifth coefficient group K5 given from the external arithmetic unit 11 is performed on the luminance signals Y2, U2, V2 of the video signal n1. . As a result, a video signal p11 including the red primary color signal R2, the blue primary color signal B2, and the green primary color signal G2 is generated, and the generated video signal p11 is supplied to the resize level calculation circuit 601.

  Here, the external arithmetic unit 11 determines the signal level of the video signal output from the inverse matrix conversion circuit 47 and the sixth linear arithmetic processing circuit based on the first coefficient group K1 and the third coefficient group K3. The plurality of coefficients a5 to i5 of the fifth coefficient group K5 are determined so that the signal level K of the video signal output from 604 is equivalent.

  The sixth linear arithmetic processing circuit 604 performs an inverse matrix conversion process on the video signal n1 based on the fifth coefficient group K5, thereby being equivalent to the video signal o1 output from the fifth linear arithmetic processing circuit 404. A video signal p11 can be generated.

  Also in this configuration example, as described in the third configuration example, the resize level calculation circuit 601 of the second video signal processing circuit 6 may be provided at the subsequent stage of the sixth linear calculation processing circuit 604. preferable.

  In the video display device 100 according to the fourth configuration example, the first video signal processing circuit 4 performs the resize processing by the resizing processing circuit 401 on the video signal n1, the hue adjustment by the hue adjustment circuit 45, and the color adjustment circuit. The color adjustment and inverse matrix conversion processing by 46 are performed.

  Further, the second video signal processing circuit 6 makes the signal level of the processed video signal p11 for the video signal n1 equivalent to the signal level of the video signal o1 processed by the first video signal processing circuit 4. Inverse matrix transformation processing is performed.

  Thereby, processing of a desired video signal based on the processing by the first video signal processing circuit 4 is realized.

  Further, since the second video signal processing circuit 6 is a single circuit that performs only inverse matrix transformation, the circuit scale is reduced as compared with the first video signal processing circuit 4, and the cost is reduced and manufacturing is facilitated. Is realized.

(Fifth configuration example)
FIG. 18 is a block diagram showing a video display apparatus 100 according to the fifth configuration example. As shown in FIG. 18, in the video display device 100 according to the fifth configuration example, the first video signal processing circuit 4 in FIG. 1 includes a resizing processing circuit 401 and a first nonlinear arithmetic processing circuit 405, and the second The video signal processing circuit 6 includes a resizing level calculation circuit 601 and a second nonlinear calculation processing circuit 605.

  Here, the resizing processing circuit 401 and the resizing level calculation circuit 601 have the same configuration and operation as the resizing processing circuit 401 and the resizing level calculation circuit 601 of the video display apparatus 100 according to the first configuration example.

  The first nonlinear arithmetic processing circuit 405 has a lookup table (hereinafter abbreviated as LUT) described later.

  In addition to the basic configuration of FIG. 1, the video display device 100 according to this configuration example includes an external arithmetic device 11. In the present configuration example, the external arithmetic device 11 gives arithmetic processing information LT described later to the second nonlinear arithmetic processing circuit 605.

  In the first video signal processing circuit 4 of FIG. 18, the resize processing circuit 401 is supplied with the video signal n1 from the video format conversion circuit 2. The resize processing circuit 401 performs the resize processing described in the first configuration example on the video signal n1 to generate the video signal n3. The generated video signal n3 is supplied to the first nonlinear arithmetic processing circuit 405, and the first nonlinear arithmetic processing circuit 405 performs predetermined nonlinear arithmetic processing using the LUT.

  Thus, the first nonlinear arithmetic processing circuit 405 generates the video signal o1, and the generated video signal o1 is supplied to the drive control circuit 5. The processing content of the first nonlinear arithmetic processing circuit 405 for the video signal n3 will be described later.

  In the second video signal processing circuit 6 of FIG. 18, the second nonlinear arithmetic processing circuit 605 is supplied with the video signal n1 from the video format conversion circuit 2 and the arithmetic processing information LT from the external arithmetic device 11.

  The second nonlinear arithmetic processing circuit 605 performs predetermined processing using the arithmetic processing information LT on the video signal n1, and generates a video signal p11. The processing content of the second nonlinear arithmetic processing circuit 605 for the video signal n1 will be described later.

  The generated video signal p11 is given to the resize level calculation circuit 601. Resizing information r <b> 1 is given from the resizing processing circuit 401 to the resizing level arithmetic circuit 601. In the resize level calculation circuit 601, the resize level calculation process described in the first configuration example is performed on the video signal p11. Thereby, the video signal p1 is generated, and the generated video signal p1 is given to the average signal level calculation circuit 7.

  The resizing process in the resizing processing circuit 401 and the resizing level computing process in the resizing level computing circuit 601 are equivalent to each other as described in the first configuration example.

  As described above, the first nonlinear arithmetic processing circuit 405 uses the LUT to perform predetermined nonlinear arithmetic processing on the video signal n3, and the second nonlinear arithmetic processing circuit 605 uses the arithmetic processing information LT to generate the video signal. A predetermined process is performed for n1.

  The LUT and the calculation processing information LT will be described. FIG. 19A is a diagram showing the relationship between the input video signal and the output video signal in the first nonlinear arithmetic processing circuit 405. FIG. 19B is a diagram showing the relationship between the input video signal and the output video signal in the second nonlinear arithmetic processing circuit 605.

  As shown in FIG. 19A, the relationship between the output video signal and the input video signal in the first nonlinear arithmetic processing circuit 405 is represented by a curve. Therefore, it is necessary to store a lot of data in the LUT of the first nonlinear arithmetic processing circuit 405. Therefore, an LUT having a large storage capacity is required.

  As shown in FIG. 19B, the relationship between the output video signal and the input video signal in the second nonlinear arithmetic processing circuit 605 is approximated by a broken line.

  In this case, the external arithmetic unit 11 sets a plurality of points (0 to 6) of the input video signal, and supplies the second nonlinear arithmetic processing circuit 605 with the inclination of the broken line between the points as the arithmetic processing information LT.

  Accordingly, the second nonlinear arithmetic processing circuit 605 can perform processing substantially equivalent to the nonlinear arithmetic processing of the first nonlinear arithmetic processing circuit 405 based on the arithmetic processing information LT without using the LUT. Therefore, the circuit scale of the second nonlinear arithmetic processing circuit 605 is reduced.

  As described above, the processing by the second nonlinear arithmetic processing circuit 605 is simpler than the processing by the first nonlinear arithmetic processing circuit 405. Accordingly, the circuit configuration of the second nonlinear arithmetic processing circuit 605 is simplified, and the circuit scale can be reduced more than the circuit scale of the first nonlinear arithmetic processing circuit 405. As a result, the circuit configuration of the second nonlinear arithmetic processing circuit 605 is simplified, the circuit scale is reduced, and the cost is reduced and the manufacturing is facilitated.

  Non-linear calculation processing includes, for example, γ correction processing used in accordance with the configuration of the display device 8, luminance dynamic range adjustment processing, or hue adjustment processing.

(Sixth configuration example)
FIG. 20 is a block diagram showing a video display apparatus 100 according to the sixth configuration example. As shown in FIG. 20, in the video display device 100 according to the sixth configuration example, a memory control circuit 31 is disposed between the first video signal processing circuit 4 and the field memory 3 in FIG. 1.

  The first video signal processing circuit 4 and the second video signal processing circuit 6 have the same configurations as the first video signal processing circuit 4 and the second video signal processing circuit 6 in the first to fifth configuration examples, respectively. And have action.

  In the sixth configuration example, the memory control circuit 31 gives the video signal n1 given from the first video signal processing circuit 4 to the field memory 3, and the video signal n2 read from the field memory 3 becomes the first video signal processing circuit. Give to 4.

  In addition, the memory control circuit 31 gives an average signal level holding signal ms 1 described later to the average signal level calculation circuit 7. The memory control circuit 31 is supplied with a level calculation end signal ms 2 described later from the average signal level calculation circuit 7.

  In the field memory 3 of the video display device 100 according to the sixth configuration example, when the writing cycle of the video signal n1 and the reading cycle of the video signal n2 are different, that is, the field frequency of the video signal n1 and the field of the video signal n2. When the frequency is different, there is a difference between the field used for calculating the drive condition of the drive control circuit 5 and the field used for calculating the average signal level p2 output from the average signal level calculation circuit 7.

  Therefore, the memory control circuit 31 matches the field of the video signal o1 input to the drive control circuit 5 with the field of the video signal p1 used to calculate the average signal level p2 input from the average signal level calculation circuit 7. Thus, the average signal level calculation circuit 7 is controlled. This operation of the memory control circuit 31 is called field synchronization processing.

  Details of the memory control circuit 31 will be described. FIG. 21 is a block diagram showing the configuration of the memory control circuit 31 of FIG. 20, and FIG. 22 shows the memory control circuit 31 during field synchronization processing when the writing cycle of the video signal n1 and the reading cycle of the video signal n2 are different. 4 is a time chart of various signals used in the other circuits.

  As shown in FIG. 21, the memory control circuit 31 includes a write head address generation circuit 211, a read head address generation circuit 212, a front edge detection circuit 213, a rear edge detection circuit 214, a control signal generation circuit 215, and a phase comparator 216. .

  In FIG. 22, a write enable signal WEN is generated based on the write vertical synchronization signal WVS. The video signal n1 for one field is written into the field memory 3 while the write enable signal WEN is at a high level. In FIG. 22, the video signals n1 of the fields F1, F2, and F3 are written in the field memory 3 in order.

  The front edge detection circuit 213 in FIG. 21 detects the front edge of the write enable signal WEN and generates a write front edge signal WENE. An example of the pre-write edge signal WENE is shown in FIG.

  The write head address generation circuit 211 generates a write head address WADRT based on the write address WADR and the pre-write edge signal WENE. An example of the write start address WADRT is shown in FIG.

  As shown in FIG. 22, the write head address WADRT is held in the write head address generation circuit 211 continuously from the start of writing of the video signal n1 of the first field until the start of writing of the video signal n1 of the next field. Is output.

  In FIG. 22, the write head address WADRT represented by the symbols ADR1, ADR2, and ADR3 is sequentially held in the write head address generation circuit 211 in correspondence with the writing period of the video signal n1 in the fields F1, F2, and F3.

  The control signal generation circuit 215 shown in FIG. 21 is given a signal level calculation end signal ms2 from the average signal level calculation circuit 7 shown in FIG. 20 together with the pre-write edge signal WENE. The signal level calculation end signal ms2 is a signal indicating when the average signal level calculation circuit 7 finishes calculating the average signal level for each field. An example of the signal level calculation end signal ms2 is shown in FIG.

  The control signal generation circuit 215 generates the average signal level calculation period signal CLT based on the pre-write edge signal WENE and the calculation end signal ms2.

  The average signal level calculation period signal CALT is a signal indicating the calculation period of the average signal level in the average signal level calculation circuit 7. An example of the average signal level calculation period signal CALT is shown in FIG.

  In FIG. 22, the average signal level calculation period signal CALT indicates that the average signal level calculation circuit 7 is calculating the average signal level when the signal is high, and the average signal level calculation circuit 7 is the average when the signal level is low. Indicates that the signal level is not calculated.

  As shown in FIG. 22, when the average signal level calculation for each field of the average signal level calculation circuit 7 is finished, it coincides with the time when the writing of the video signal n1 in the fields F1, F2, F3 is finished.

  That is, the average signal level calculation circuit 7 ends the calculation of the average signal level when the writing of the video signal n1 in the fields F1, F2, and F3 is completed.

  In FIG. 22, the average signal level AST calculated by the average signal level calculation circuit 7 for each of the fields F0, F1, F2, and F3 is shown in the order of symbols P0, P1, P2, and P3.

  The trailing edge detection circuit 214 detects the trailing edge of the read enable signal REN and generates an average signal level holding signal ms1. An example of the read enable signal REN is shown in FIG. This average signal level holding signal ms1 is also applied to the average signal level calculation circuit 7 of FIG. Thus, the average signal level calculation circuit 7 holds the average signal level AST for each field calculated by itself based on the average signal level holding signal ms1.

  That is, the average signal level calculation circuit 7 holds the average signal level AST in response to the rising edge of the average signal level holding signal ms1. In this case, the average signal level calculation circuit 7 updates the average signal level held for one field period each time the average signal level holding signal ms1 rises. An example of the average signal level holding signal ms1 is shown in FIG.

  The phase comparator 216 compares the average signal level calculation period signal CALT and the average signal level holding signal ms 1, and reads the phase comparison result CON and gives it to the head address generation circuit 212.

  The phase comparison result CON is a signal indicating whether the average signal level calculation period signal CALT is at a high level or a low level at each rising edge of the average signal level holding signal ms1. In FIG. 22, this comparison timing is indicated by broken lines DL1 and DL2.

  The read head address generation circuit 212 determines and holds the read head address RADRT based on the write head address WADRT, the phase comparison result CON, and the average signal level holding signal ms1.

  As a result, the video signal n2 in the field corresponding to the read head address RADRT is read from the field memory 3 based on the read vertical synchronization signal RVS and the read enable signal REN. An example of the read vertical synchronization signal RVS is shown in FIG.

  Details of the operation of the read head address generation circuit 212 will be described.

  When the phase comparison result CON indicates that the average signal level calculation period signal CALT is at a high level at each rising edge of the average signal level holding signal ms1 as indicated by a broken line DL1 in FIG. The write head address WADRT corresponding to the field F0 immediately before the write head address WADRT (symbol ADR1) at that timing is held as the read head address RADRT (symbol ADR0).

  Further, the read head address generation circuit 212 indicates that the average signal level calculation period signal CALT is at the low level at each rising edge of the average signal level holding signal ms1, as indicated by the broken line DL2 in FIG. In this case, the write start address WADRT (symbol ADR2) of the field F2 at that timing is held as the read start address RADRT (symbol ADR2).

  Based on the read head address RADRT held in the read head address generation circuit 212, the video signal n2 of the corresponding field is read from the field memory 3 when the read enable signal REN is at a high level.

  The drive control circuit 5 drives the drive conditions for each field to be displayed on the display device 8 based on the video signal o1 given by the operation of the series of memory control circuits 31 and the average signal level p2 given from the average signal level calculation circuit 7. To decide.

  FIG. 22 shows a drive condition determination period DVT for each field. As shown in FIG. 22, the drive control circuit 5 determines the drive condition for each field to be displayed on the display device 8 based on the average signal level AST of the average signal level calculation circuit 7 as indicated by the one-dot chain line arrow. To do.

  In the example of FIG. 22, after the driving condition is determined using the average signal level AST of the field F0, the driving condition is determined using the average signal level AST of the field F2.

  Thereby, the drive control circuit 5 can determine and adjust the drive condition based on the average signal level p2 corresponding to the video signal o1 of each field.

  The memory control circuit 31 performs the same field synchronization processing as described above even when the video signal n1 writing cycle and the video signal n2 reading cycle are the same.

  FIG. 23 is a time chart of various signals used in the memory control circuit 31 and other circuits at the time of field synchronization processing when the writing cycle of the video signal n1 and the reading cycle of the video signal n2 are the same.

  In FIG. 23, the timings of the write vertical synchronization signal WVS and the read vertical synchronization signal RVS match. Thereby, the rising timings of the average signal level holding signal ms1 and the level calculation end signal ms2 coincide.

  In this case, the driving conditions are determined in order using the ASTs of the fields F1, F2, and F3.

  According to the video display device 100 according to this configuration example, even when the field frequency of the video signal o1 given to the drive control circuit 5 and the field frequency of the video signal p1 given to the average signal level calculation circuit 7 are different, the average The average signal level calculation circuit 7 controls the memory so that the drive control circuit 5 drives the display device 8 based on the video signal p1 in the same field as the field of the video signal o1 used by the signal level calculation circuit 7 to adjust the driving conditions. Controlled by circuit 31. Thereby, the drive conditions of the display device 8 are optimally adjusted.

As described above, in the video display device 100 according to the embodiment of the present invention, the video display device 100 corresponds to the video display device, the PDP 80 corresponds to the panel , the field memory 3 corresponds to the storage device, and the data driver 81. , The scan driver 82, the sustain driver 83, the subfield processor 84, and the video signal-subfield correlator 85 correspond to a driving device, the average signal level calculation circuit 7 corresponds to an average signal level calculation unit , and a drive control circuit. 5 corresponds to the adjustment circuit.

The resizing processing circuit 401 corresponds to the first processing circuit, the resizing level calculation circuit 601 corresponds to the second processing circuit, and the resizing information corresponds to information indicating the enlargement / reduction ratio of the size of the video display area. Resize level calculation processing corresponding to processing for changing the number of a plurality of pixel data for one field of the input video signal based on the information and generating a video signal including the changed number of pixel data 4 corresponds to a process of multiplying the signal level of a plurality of pixel data for one field of the input video signal and information, the weighting constant corresponds to a constant for adjusting the luminance of the video, and the table of FIG. Corresponds to the first relationship.
Further, the first linear arithmetic processing circuit 402, the third linear arithmetic processing circuit 403, the fifth linear arithmetic processing circuit 404, and the first nonlinear arithmetic processing circuit 405 correspond to the third processing circuit, and the second The linear arithmetic processing circuit 602, the fourth linear arithmetic processing circuit 603, the sixth linear arithmetic processing circuit 604, and the second nonlinear arithmetic processing circuit 605 correspond to a fourth processing circuit.
Further, the inverse matrix transformation process by the first linear arithmetic processing circuit 402 corresponds to the first inverse matrix transformation process, and the inverse matrix transformation process by the second linear arithmetic processing circuit 602 corresponds to the second inverse matrix transformation process. The linear operation processing by the third linear operation processing circuit 403 corresponds to the first linear operation processing, the linear operation processing by the fourth linear operation processing circuit 603 corresponds to the second linear operation processing, and the fifth The inverse matrix transformation process and the linear computation process by the linear computation processing circuit 404 correspond to the first inverse matrix transformation process and the linear computation process, respectively, and the inverse matrix transformation process by the sixth linear computation processing circuit 604 is the second inverse matrix. This corresponds to matrix conversion processing, and the non-linear operation processing by the first non-linear operation processing circuit 405 corresponds to the first non-linear operation processing. Non-linear operation processing by the second nonlinear processing circuit 605 corresponds to the second nonlinear processing.

Furthermore, the coefficients a1 to i1 of the first coefficient group K1 correspond to coefficients of the first number of bits, the coefficients a2 to i2 of the second coefficient group K2 correspond to coefficients of the second number of bits, and the third The coefficient group K3 of FIG. 19 corresponds to the first number of coefficients, the fourth coefficient group K4 corresponds to the second number of coefficients, and the LUT in FIG. 19A corresponds to the second relationship. The relationship (arithmetic processing information LT) between the output video signal and the input video signal approximated by the broken line in (b) corresponds to the approximate expression of the second relationship, and PDP 80 corresponds to the plasma display panel.

  The luminance signal Y1 and the two color difference signals U1 and V1 correspond to one luminance signal and two color difference signals, respectively, and the red primary color signal R1, the blue primary color signal B1 and the green primary color signal G1 correspond to three primary color signals and are averaged. The luminance level corresponds to the average signal level.

  The present invention can be used for an image display device that displays an image on a CRT (cathode ray tube), a liquid crystal display panel, a plasma display panel or the like based on an image signal.

The block diagram which shows the basic composition of the video display apparatus of this invention 1 is a block diagram illustrating an example of a specific configuration of the display device in FIG. The figure for demonstrating the ADS system applied to the display apparatus shown in FIG. 7 is a diagram illustrating an example of a table indicating the relationship between the sustain pulse multiple and the average signal level of the drive control circuit, and a diagram illustrating the relationship between the power consumption of the display device and the average signal level. 1 is a block diagram showing an example of the configuration of the average signal level calculation circuit of FIG. Block diagram of a video display device according to a first configuration example The figure which shows an example of a structure of the resize level arithmetic circuit of FIG. FIG. 6 is a conceptual diagram for explaining signal levels of two video signals generated by the resizing processing circuit and the resizing level calculation circuit of FIG. The block diagram which shows the structure of the video display apparatus which concerns on a 2nd structural example. The figure for demonstrating the inverse matrix transformation process which the 1st linear arithmetic processing circuit of FIG. 9 and a 2nd linear arithmetic processing circuit perform, and a 1st coefficient group and a 2nd coefficient group The block diagram which shows the video display apparatus which concerns on a 3rd structural example. FIG. 11 is a diagram for explaining linear arithmetic processing by the third linear arithmetic processing circuit and the fourth linear arithmetic processing circuit of FIG. 11 and the third coefficient group and the fourth coefficient group; The figure which shows an example of the display form of the image in a 3rd structural example. FIG. 11 is a conceptual diagram for explaining the relationship between the arrangement of the resizing level arithmetic circuit and the fourth linear arithmetic processing circuit in FIG. 11 and the signal level of the video signal generated by the second video signal processing circuit. FIG. 11 is a conceptual diagram for explaining the relationship between the arrangement of the resizing level arithmetic circuit and the fourth linear arithmetic processing circuit in FIG. 11 and the signal level of the video signal generated by the second video signal processing circuit. The block diagram which shows the video display apparatus which concerns on a 4th structural example. The figure for demonstrating the linear arithmetic processing by the 5th linear arithmetic processing circuit of FIG. 16, and the 6th linear arithmetic processing circuit, and the 1st coefficient group, the 3rd coefficient group, and the 5th coefficient group The block diagram which shows the video display apparatus which concerns on a 5th structural example. (A) is a figure which shows the relationship between the input video signal and output video signal in a 1st nonlinear arithmetic processing circuit, (b) shows the relationship between the input video signal and output video signal in a 2nd nonlinear arithmetic processing circuit. Figure The block diagram which shows the video display apparatus which concerns on a 6th structural example. 20 is a block diagram showing the configuration of the memory control circuit of FIG. Time chart of various signals used in the memory control circuit and other circuits during field synchronization processing when the video signal write cycle and video signal read cycle are different Time chart of various signals used in the memory control circuit and other circuits during field synchronization processing when the video signal write cycle and video signal read cycle are the same

Explanation of symbols

3 Field Memory 4 First Video Signal Processing Circuit 5 Drive Control Circuit 6 Second Video Signal Processing Circuit 7 Average Signal Level Calculation Circuit 8 Display Device 31 Memory Control Circuit 80 PDP
DESCRIPTION OF SYMBOLS 100 Image display apparatus 401 Resize processing circuit 402 1st linear arithmetic processing circuit 403 3rd linear arithmetic processing circuit 404 5th linear arithmetic processing circuit 405 1st nonlinear arithmetic processing circuit 601 Resize level arithmetic circuit 602 2nd linearity Arithmetic processing circuit 603 Fourth linear arithmetic processing circuit 604 Sixth linear arithmetic processing circuit 605 Second nonlinear arithmetic processing circuit a1, b1, c1, d1, e1, f1, g1, h1, i1, a2, b2, c2 , D2, e2, f2, g2, h2, i2 coefficient K1 first coefficient group K2 second coefficient group K3 third coefficient group K4 fourth coefficient group

Claims (6)

A video display device for displaying video based on an input video signal,
A panel for displaying images,
A storage device capable of storing a video signal for one field including a plurality of pixel data ;
Storing information indicating the enlargement / reduction ratio of the size of the display area of the video, and using the storage device, changing the number of pixel data for one field of the input video signal based on the information; A first processing circuit that performs processing for generating a video signal including the changed number of pixel data ;
A second processing circuit for performing a process of multiplying a signal level of a plurality of pixel data for one field of the input video signal and the information ;
A driving device for driving the panel based on a video signal output from the first processing circuit ;
An average signal level calculation unit for calculating an average value of multiplication results of the second processing circuit as an average signal level;
Storing a first predetermined relationship between a constant for adjusting an operation of the driving device and adjusting a luminance of an image displayed on the panel and the average signal level; And an adjustment circuit that determines a constant corresponding to the average signal level calculated by the average signal level calculation unit based on the average signal level and adjusts the operation of the driving device based on the determined constant. Display device. Each pixel data of the input video signal is composed of one luminance signal and two color difference signals,
  Video signal generated by the first processing circuit without using the storage device to convert each pixel data of the video signal generated by the first processing circuit into pixel data composed of three primary color signals A third processing circuit for performing a first inverse matrix conversion process using a first coefficient group including a plurality of coefficients of the first number of bits;
  In order to convert each pixel data of the input video signal into pixel data consisting of three primary color signals, a second smaller than the first bit is added to the input video signal without using the storage device. And a fourth processing circuit for performing a second inverse matrix transformation process using a second coefficient group including a plurality of coefficients of the number of bits.
  The driving device drives the panel based on the video signal on which the first inverse matrix transformation processing has been performed by the third processing circuit,
  The second processing circuit multiplies the information by the signal level of a plurality of pixel data for one field of the video signal subjected to the second inverse matrix conversion processing by the fourth processing circuit, respectively. The video display device according to claim 1, wherein:   First linear arithmetic processing for adjusting the hue of a video by using a first coefficient group including a first number of coefficients in a video signal generated by the first processing circuit without using the storage device A third processing circuit for performing
  A fourth process for performing a second linear operation process using a second coefficient group including a second number of coefficients smaller than the first number in the input video signal without using the storage device. And further comprising a circuit,
  The first and second linear arithmetic processes include an adding process and a multiplying process using the first coefficient group and the second coefficient group, respectively.
  The driving device drives the panel based on the video signal on which the first linear arithmetic processing has been performed by the third processing circuit,
  The second processing circuit multiplies the information by the signal level of a plurality of pixel data for one field of the video signal subjected to the second linear arithmetic processing by the fourth processing circuit, respectively. The video display device according to claim 1, wherein the video display device is performed.   In order to perform gamma correction of the image, adjustment of the dynamic range of the luminance of the image, or adjustment of the hue of the image, a predetermined first signal is generated in the video signal generated by the first processing circuit without using the storage device. A third processing circuit that performs a first nonlinear arithmetic processing based on the relationship of 2;
  A fourth processing circuit that performs a second non-linear operation process using the approximate expression of the second relationship that is predetermined for the input video signal without using the storage device;
  The predetermined second relationship is output from the third processing circuit and the signal level of each pixel data of the video signal generated by the first processing circuit that is input to the third processing circuit. A relationship between the signal level of each pixel data of the video signal generated by the first processing circuit,
  The driving device drives the panel based on the video signal on which the first nonlinear arithmetic processing has been performed by the third processing circuit,
  The second processing circuit performs a process of multiplying the information by the signal level of a plurality of pixel data for one field of the video signal subjected to the second nonlinear arithmetic processing by the fourth processing circuit, respectively. The video display device according to claim 1, wherein the video display device is performed. Each pixel data of the input video signal is composed of one luminance signal and two color difference signals,
  In order to adjust the hue of the video, linear processing including addition processing and multiplication processing using a plurality of coefficients is performed on the video signal generated by the first processing circuit without using the storage device, and In order to convert each pixel data of the video signal generated by the first processing circuit into pixel data composed of three primary color signals, the first video signal is subjected to the linear operation processing without using the storage device. A third processing circuit for performing a first inverse matrix transformation process using a first coefficient group including a plurality of coefficients of the number of bits of
  In order to convert each pixel data of the input video signal into pixel data composed of three primary color signals, a second smaller than the first bit is added to the input video signal without using the storage device. And a fourth processing circuit for performing a second inverse matrix transformation process using a second coefficient group including a plurality of coefficients of the number of bits.
  The driving device drives the panel based on the video signal on which the linear arithmetic processing and the first inverse matrix transformation processing are performed by the third processing circuit,
  The second processing circuit multiplies the information by the signal level of a plurality of pixel data for one field of the video signal subjected to the second inverse matrix conversion processing by the fourth processing circuit, respectively. The video display device according to claim 1, wherein: Video display according to any one of claims 1 to 5, wherein the panel is a plasma display panel.

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