JP4641775B2 - Semiconductor integrated circuit for magnetic detection and electronic component mounted therewith - Google Patents

Description

  The present invention relates to a technology that is effective when applied to a magnetic sensor using a Hall element. For example, a semiconductor integrated circuit for magnetic detection in which a Hall element and a current detection circuit that detects a current flowing through the Hall element are formed on one semiconductor chip. (Hall IC) Related to effective technology.

  Conventionally, Hall elements having magnetic-electrical conversion characteristics have been used as sensors in various measuring instruments and control systems. Since the Hall element is a non-contact switch and excellent in durability, it is used as a sensor in various fields by utilizing its characteristics. As an example of a control system using a Hall element as a sensor, an automobile engine control system that controls an engine by detecting an angle of a crankshaft and a rotational speed of a mission is well known.

  By the way, in a sensor using a Hall element, there are an offset voltage possessed by the Hall element itself and an offset voltage possessed by a differential amplifier that detects a voltage generated by the Hall element as factors that lower the detection accuracy of the sensor. For example, Patent Documents 1 to 3 disclose an invention for improving the detection accuracy by canceling these offset voltages.

Hall elements with two orthogonal terminal pairs have the same Hall voltage due to the magnetic field when the current direction is changed by 90 degrees, but the offset voltage (non-equilibrium voltage at zero magnetic field) of the Hall element is the same. The polarity is reversed. The inventions described in Patent Documents 1 to 3 use this property of the Hall element to add the Hall voltage detected in the first phase and the Hall voltage detected in the second phase with the current direction changed by 90 degrees. The offset voltage of the Hall element is canceled and the differential input of the differential amplifier that amplifies the Hall voltage is switched between the first phase and the second phase, thereby canceling the offset voltage of the amplifier simultaneously. It is.
JP 08-204911 A JP 09-196699 A JP 2001-337147 A

  The inventions described in Patent Documents 1 and 2 have a problem that the number of constituent elements is large and the area occupied by the circuit and thus the Hall IC chip size is increased. On the other hand, the invention of Patent Document 3 has the advantage that the number of elements is small, the circuit is simple, and the occupied area is small, but only the output in the second phase is effective, and the output is obtained in the first phase. Therefore, there is a problem that a continuous output cannot be obtained and it is difficult to cope with a low power supply voltage of the circuit because a differential output amplifier is used.

SUMMARY OF THE INVENTION An object of the present invention is to reduce the number of constituent elements in a Hall IC incorporating a Hall element and a current detection differential amplifier so that the area occupied by the circuit and thus the chip size can be reduced.
Another object of the present invention is to make it possible to easily achieve a reduction in power supply voltage of a Hall IC incorporating a Hall element and a differential amplifier for detecting a voltage generated by the Hall element.

Still another object of the present invention is to provide a Hall IC that incorporates a Hall element and a Hall voltage detection differential amplifier that can obtain a continuous output with a relatively simple configuration.
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
That is, a Hall element having two pairs of opposing terminal pairs, a voltage input-current output type differential amplifier circuit (Gm amplifier) that amplifies a change in voltage of the Hall element, and a predetermined bias voltage to switch the Hall element In the semiconductor integrated circuit for magnetic detection provided with a switching circuit that alternately applies to one terminal pair or the other terminal pair, a differential input having a pair of differential input terminals and one output terminal as the Gm amplifier A single-end output amplifier, a current-voltage conversion resistance element connected between the output terminal of the amplifier and a predetermined constant potential point, and a capacitance element provided in parallel with the resistance element; A switching element connected in series with the capacitive element, the switching element is turned on in a first phase period, and the voltage across the terminals of the resistive element is sampled in the capacitive element; It is configured to output a signal corresponding to a potential difference by comparing an inter-terminal voltage held in the capacitor element and an inter-terminal voltage of the resistance element in an off state during a phase period.

  According to the above-described means, the bias voltage applied to the Hall element is switched by the switching circuit, and the output current of the amplifier in the first phase period is converted into a voltage by the resistance element and sampled in the capacitive element, Hall element by outputting a signal corresponding to the potential difference by comparing the voltage obtained by converting the output current of the amplifier in the phase period of 2 with the resistance element with the voltage of the first phase period held in the capacitive element It is possible to output a signal in which the offset of is canceled. In addition, since a differential input-single-end output Gm amplifier is used, the circuit scale can be reduced, and the circuit can be easily adapted to lower power supply voltage.

  A second capacitor element provided in parallel with the resistor element; and a second switch element connected in series with the second capacitor element, wherein the switch element is turned on during the first phase period. The capacitor element samples the voltage across the resistor element, the second switch element is turned on during a second phase period, the second capacitor element samples the voltage across the resistor element, The inter-terminal voltage held in the capacitive element and the inter-terminal voltage held in the second capacitive element are compared in the phase period and the second phase period, and a signal corresponding to the potential difference is output. Constitute. Thereby, the detection output of the voltage generated by the Hall element can be obtained in each of the first phase period and the second phase period.

  More preferably, there is provided a second switching circuit for switching the voltage of one terminal pair of the Hall element or the voltage of the other terminal pair to alternately input to the Gm amplifier during the first phase period and the second phase period. . Thereby, the signal which canceled the offset which Gm amplifier has can be output.

  Further, the semiconductor integrated circuit for magnetic interface having the semiconductor integrated circuit for magnetic detection, a power supply circuit for supplying a driving voltage to the semiconductor integrated circuit for magnetic detection, and an interface circuit for receiving the magnetic detection signal and outputting it to an external control circuit (controller). A circuit is mounted on one insulating substrate to constitute a module. As a result, when a system having a plurality of Hall elements is configured, the number of parts can be reduced and the entire system can be downsized.

  Further, the interface circuit is provided with a parallel-serial conversion circuit for outputting detection results of a plurality of magnetic detection circuits as serial data or a bus interface corresponding to a general-purpose communication protocol. As a result, it is possible to allow the controller to input a detection signal corresponding to the state of the Hall element regardless of the specification of the Hall element to be used or the controller.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, according to the present invention, in a Hall IC incorporating a Hall element and a differential amplifier for current detection, the number of constituent elements can be reduced to reduce the occupied area of the circuit and thus the chip size.

Preferred embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows a first embodiment of a Hall IC according to the present invention. The elements shown in FIG. 1 and the elements constituting each circuit block are formed as a semiconductor integrated circuit on a single semiconductor substrate such as single crystal silicon.

  In FIG. 1, reference numeral 11 denotes a Hall element, which is formed by a substantially rectangular region surrounded by a P-type region on an N-type epitaxial layer grown on a P-type silicon substrate. A hall plate portion is configured. An orthogonal bias type that can change the direction of a current flowing by 90 degrees when a bias voltage is applied to each set of electrodes by two sets of electrodes formed so as to be in contact with the vicinity of the opposing sides of the rectangular region. It functions as a Hall element. The Hall element 11 generates a voltage VH proportional to the strength of the magnetic field applied to the Hall plate portion, and the voltage VH is more conspicuous when a current is applied by applying a bias voltage. Since the Hall plate portion is formed of an epitaxial layer, a Hall element having a higher uniformity of impurity concentration and less variation in characteristics than that of a diffusion layer can be obtained.

  The Hall IC of this embodiment includes a temperature compensation circuit 12 that generates a temperature-dependent bias voltage Vb that compensates for the magnetic-electrical conversion characteristics that change according to the ambient temperature of the Hall element 11, and the temperature compensation circuit 12. There are provided switch elements SW1 to SW4 that can apply a bias voltage Vb generated by the compensation circuit 12 and a ground potential GND as a reference potential between opposing electrodes of the Hall element 11.

  Of these switch elements SW1 to SW4, SW1 and SW3 are on / off controlled by the same clock signal φ1, and SW2 and SW4 are on / off controlled by a clock signal φ2 that is 180 ° out of phase with φ1, SW2 and SW4 When is turned on, a current that is 90 degrees different from the current flowing through the Hall element 11 when SW1 and SW3 are turned on flows. As the temperature compensation circuit 12, an arbitrary circuit such as the one described in Japanese Patent Application No. 2004-82165 previously filed by the present inventor or the one described in Japanese Patent Application Laid-Open No. 10-071927 can be used. Since the temperature compensation circuit 12 is not directly related to the present invention, a specific circuit illustration and description are omitted.

  Reference numeral 13 denotes a voltage input-current output type amplifier (Gm amplifier) for detecting a potential difference generated in a direction orthogonal to the current when a current is passed through the Hall element 11. The Gm amplifier 13 and the Hall element 11, switch elements SW <b> 5 to SW <b> 8 that switch the potential generated when a current flows through the Hall element 11 and input the current to the Gm amplifier 13 are provided. Of the switch elements SW5 to SW8, SW6 and SW8 are ON / OFF controlled by the clock φ1, and SW5 and SW7 are ON / OFF controlled complementarily to SW6 and SW8 by the clock φ2.

  In addition, in this embodiment, the switch elements SW6 and SW8 are input to the Gm amplifier 13 when they are on / off controlled by the clock signal φ1 and when SW5 and SW7 are on / off controlled by the clock signal φ2. The switch elements SW5 to SW8 are arranged so that the polarity of the Hall element output is reversed. Specifically, the potential generated at the left terminal when the current I1 flowing from the top to the bottom of FIG. 1 is passed through the Hall element 11 is input to the inverting input terminal (−) of the Gm amplifier 13, and the Hall element 11 The switch elements SW5 to SW8 are arranged so that the potential generated at the right terminal when the current I2 from the left to the right in FIG. 1 flows is input to the inverting input terminal (−) of the Gm amplifier 13. Thereby, the offset voltage of the Hall element 11 and the offset voltage of the Gm amplifier 13 can be canceled simultaneously.

  Further, in the Hall IC of the present embodiment, a differential input-single-ended output amplifier is used as the Gm amplifier 13, and the constant voltage circuit 14 for generating the reference constant voltage VDC and the output voltage thereof are impedance. A voltage follower 15 for conversion is provided. A resistor RL for converting the output current of the Gm amplifier 13 into a voltage is connected between the constant potential point Nc to which the output voltage of the voltage follower 15 is applied and the output terminal of the Gm amplifier 13. In addition, a capacitor C1 is provided in parallel with the resistor RL, and a switch element SW11 is connected in series with the capacitor C1. This switch element SW11 is controlled to be turned on / off by the same clock as the clock signal φ1 for turning on / off SW1 and SW3 among the input selector switches SW1 to SW4 of the Hall element. Although the constant voltage VDC can be set to an arbitrary potential, 1.2 V is selected in this embodiment as a voltage having good matching with other circuits.

  The resistor RL can be constituted by a diffusion layer or a polysilicon layer formed on a semiconductor chip, or an external resistor element may be used. Further, instead of a general resistance element, a hole plate portion as a dummy Hall element made of an epitaxial layer having substantially the same size is formed on a silicon substrate in the same process as the Hall element 11, and this dummy is formed. The Hall element may be used as the resistor RL. By using a dummy Hall element as the resistor RL, there is an advantage that it is not necessary to provide a circuit for compensating the temperature dependence of the Hall element.

  Furthermore, the Hall IC of this embodiment has a hysteresis circuit for comparing the potential of the connection node N0 between the output terminal of the Gm amplifier 13 and the resistor RL and the potential of the connection node N1 between the capacitor C1 and the switch element SW11. A comparator 16, a latch circuit 17 that holds the output of the comparator 16, and an external terminal 18 that outputs the output of the latch circuit 17 to the outside of the chip are provided. A linear amplifier may be provided in place of the hysteresis comparator 16 and a voltage proportional to the output current of the Gm amplifier 13 may be output. In that case, it is desirable to provide a sample hold circuit instead of the latch circuit 17. Further, the latch circuit 17 and the sample hold circuit may be omitted, and the output voltage of the comparator 16 or the linear amplifier may be directly output from the external terminal 18 to the outside of the chip.

  Next, the operation of the Hall IC of this embodiment will be described with reference to FIGS. 2A shows a state in which the clock signal φ1 is at a high level (first phase), and FIG. 2B shows a state in which the clock signal φ2 is at a high level (second phase).

  When the clock signal φ1 is set to the high level, as shown in FIG. 2A, the switch element SW11 is turned on, and the resistance RL is caused by the output current of the Gm amplifier 13 according to the voltage VH generated by the Hall element 11. The generated voltage VO2 is charged to the capacitor C1. At this time, assuming that the gain of the Gm amplifier 13 is Gm, the output current is Gm · VH, but since the offset voltage of the Gm amplifier 13 is included in the potential VO1 of the node N1, the input conversion offset of the Gm amplifier 13 is included. Is set to Voff, VO1 = VDC + RL · Gm · (VH1 + Voff). Further, the potential VO0 of the node N0 is equal to the potential VO1 of the node N1, and the potential difference VO between N1 and N0 is 0V.

Next, when the clock signal φ1 is set to the low level, as shown in FIG. 2B, the direction of the current of the Hall element 11 is changed and the input of the Gm amplifier 13 is switched, and the switch element SW11 is turned off. . As a result, the potential VO2 of the node N0, including the offset voltage Voff of the Gm amplifier 13, becomes VO2 = VDC−RL · Gm · (VH2−Voff). Further, since the potential VO1 of the node N1 holds the potential (VDC + RL · Gm · VH1 + RL · Gm · Voff) during the period when φ1 is at a high level by the capacitor C1, the potential difference VO between N1 and N0 is
VO = {VDC + RL.Gm (VH1 + Voff)}-{VDC-RL.Gm (VH2-Voff)}
= RL · Gm (VH1 + VH2)
It becomes. Therefore, it can be seen that the offset of the Gm amplifier is offset.

Here, if the offset voltage included in the voltage VH generated by the Hall element 11 is VHO, the offset voltage when the current flows in the direction of FIG. 2A and the offset when the current flows in the direction of FIG. Since the voltages are opposite, VH1 = VH + VHO, VH2 = VH-VHO,
VO = 2 ・ RL ・ Gm ・ VH
Thus, the offset during the period when φ1 is at the high level and the offset during the period when φ1 is at the low level cancel each other, and the potential difference VO between the nodes N1 and N0 does not include the offset of the Hall element 11.

4 to 6 show a second embodiment of the Hall IC according to the present invention.
In this embodiment, in addition to the capacitor C1 and the switch SW11 in parallel with the resistor RL, another set of the capacitor C2 and the switch element SW12 is provided between the output terminal of the Gm amplifier 13 and the constant potential point Nc in the first embodiment. The switch element SW12 is configured to be turned on and off complementarily with the switch element SW11 by a clock φ2 having a phase opposite to that of the clock φ1. Although not shown in FIG. 4, a constant voltage circuit 14, a voltage follower 15, a hysteresis comparator 16, and a latch circuit 17 are provided as in the embodiment of FIG. Similar to the first embodiment, a linear amplifier instead of the hysteresis comparator 16 and a sample hold circuit instead of the latch circuit 17 may be provided.

  In the first embodiment, a correct detection output can be obtained only during a period in which the clock φ1 is at a low level, whereas in the second embodiment, the offset of the Hall element 11 is reduced as in the first embodiment. In addition to obtaining an output in which the offset of the Gm amplifier 13 is canceled, it is possible to obtain a correct detection output during a period when the clock φ1 is at a low level and a period when the clock φ1 is at a high level. Therefore, there is an advantage that a result equivalent to that operated at a double speed can be obtained without increasing the frequency of the clock φ1.

  FIG. 7 shows a specific circuit example of the Gm amplifier 13, the voltage follower 15, and the hysteresis comparator 16 in the Hall IC of the second embodiment. Although not shown in FIG. 1, the Hall IC according to the embodiment includes constant current transistors Q5, Q6, Q7, Q15, Q16, Q18 in the Gm amplifier 13, the voltage follower 15, and the hysteresis comparator 16. A bias voltage generation circuit 19 for generating the gate bias voltage Vcs of Q25 and Q27 is provided.

  The Gm amplifier 13 is connected between the differential input transistors Q1 and Q2, which are bipolar transistors to which the output VH of the Hall element is input via the switch elements SW5 to SW8, and between the collectors of the Q1 and Q2 and the power supply voltage terminal. Active load MOS transistors Q3 and Q4, an emitter resistor Re connected between the emitter terminals of Q1 and Q2, and a constant current MOS transistor Q5 connected between the emitter terminals of Q1 and Q2 and the ground point. Q6. By using bipolar transistors for the differential input transistors Q1 and Q2, the amplification factor of the amplifier can be increased. Further, since the amplifier 13 for amplifying the output VH of the Hall element may be a single-ended output amplifier, a Gm amplifier can be used, and this can widen the output dynamic range with a simple circuit as shown in FIG. In addition, the Gm (transfer conductance) of the amplifier can be easily controlled.

  When a differential output amplifier is required as in the invention of Patent Document 3 described above, an amplifier having an active load MOS transistor (a voltage output type amplifier that is not a Gm amplifier) is used in order to cope with a low power supply voltage. Since an amplifier that amplifies the signal on the positive phase side and an amplifier that amplifies the signal on the negative phase side are required, the circuit scale becomes large, but when a single-end output amplifier is sufficient as in the present invention, Even if the amplifier is simplified as in this embodiment, the power supply voltage can be reduced. In other words, if a type of amplifier that uses a resistor instead of a transistor as a load of a differential input transistor is sufficient, a differential output can be taken out from one amplifier, but an amplifier using a resistor as a load has a narrow output dynamic range. As a result, a sufficient output dynamic range cannot be obtained when the power supply voltage of the IC is lowered. However, with a Gm amplifier as in this embodiment, a simple amplifier is sufficient and even a low power supply voltage is compared. A wide output dynamic range can be obtained.

  The hysteresis comparator 16 includes an impedance converter VF including a voltage follower and a comparator CMP. MOS transistors are used as the differential input transistors Q11 and Q12 constituting the voltage follower of the impedance converter VF. This is because when the bipolar transistor is used, the input impedance is lowered, the charges of the capacitors C1 and C2 are extracted, and the voltages at the nodes N1 and N2 are lowered.

  The impedance converter VF including a voltage follower is provided in the hysteresis comparator 16 because when the potential of the node N1 is directly input to the comparator CMP, the hysteresis comparator 16 is connected to the gate terminal of the differential input transistor Q21 of the comparator CMP. This is because the charge of the capacitor C1 is extracted by the MOS transistors Q16 to Q18 for changing the threshold value provided between the points. On the other hand, since there is no MOS transistor for changing the threshold value on the gate terminal side of the differential input transistor Q22, the potential of the node N3 is directly input to the gate terminal of the differential input transistor Q22 of the comparator CMP. .

  Comparator CMP comprises a differential amplifier stage composed of MOS transistors Q21 to Q25, a common source output stage composed of MOS transistors Q26 and Q27, and a CMOS inverter type final output stage composed of MOS transistors Q28 and Q29. Yes. An input resistor R1 is provided between the output node of the impedance converter VF and the gate terminal of the differential input transistor Q21, and a constant current MOS transistor Q16 is provided between the gate terminal of the differential input transistor Q21 and the ground point. Further, MOS transistors Q17 and Q18 in series are connected in parallel with Q16, the output potential of the common source output stage is fed back to the gate terminal of Q17, and the voltage from the bias generation circuit 19 is fed to the gate terminal of Q18. By operating as a constant current source when Vcs is applied, it has a hysteresis characteristic in which the threshold voltage changes according to the level of the output potential.

  That is, when the output potential of the comparator 16 is high level (the output potential of the common source output stage is low level), the MOS transistor Q17 is turned off to reduce the voltage drop at the input resistor R1, and the output potential of the comparator 16 is reduced. When the level is low (the output potential of the common-source output stage is high), the MOS transistor Q17 is turned on to increase the voltage drop across the input resistor R1. As a result, when the input changes from the low level to the high level, the apparent threshold voltage increases, and when the input changes from the high level to the low level, the apparent threshold voltage decreases. .

  FIG. 8 shows a first modification of the Hall IC of the second embodiment. In the embodiment of FIG. 7, the temperature compensation circuit 12 that generates a voltage that compensates for the temperature characteristics of the Hall element is used in the circuit that generates the bias voltage Vb to be applied to the Hall element 11, but in this modification, The Gm amplifier 13 is provided with a temperature compensation unit 13a including a differential amplifier stage for controlling the output current so as to compensate the temperature characteristic of the Hall element and a current control circuit. Since the voltage follower 15 and the hysteresis comparator 16 may be the same as those of the embodiment of FIG. 7, illustration and description of specific circuits are omitted.

  In this modification, so-called diode-connected bipolar transistors Q3 and Q4 in which a base and a collector are coupled to the loads of the differential input transistors Q1 and Q2 of the Gm amplifier 13 are used, and the differential amplification stage of the temperature compensation unit 13a is used. The differential input transistors Q31 and Q32 are connected in common to the load transistors Q3 and Q4 of the Gm amplifier 13 so as to form current mirrors, and currents that are the same as or proportional to the currents flowing through Q3 and Q4 are supplied to Q31 and Q32. It is made to flow. A constant-current MOS transistor Q35 connected between the common emitter of the transistors Q31 and Q32 and the power supply voltage terminal and a diode-connected MOS transistor Q36 which is connected in common to the gate and constitutes a current mirror are provided. The transistor Q36 Is connected in series with a temperature compensation current source CS1 for supplying a current having a temperature characteristic that compensates for the temperature dependence of the Hall element 11, and an output current is taken out from the collector of the differential input transistor Q32 of the differential amplifier. It is configured as follows.

  In the Hall IC of this modified example, the current compensated for the temperature dependence of the Hall element 11 by the temperature compensation unit 13a can be output to the subsequent resistor RL. At the same time, the current of the temperature compensation current source CS1 is turned back by the current mirrors of Q35 and Q36 and passed to the differential amplification stage of the temperature compensation unit 13a, and the differential input transistors Q31, Q32 and Gm of the differential amplification stage are supplied. The load transistors Q3 and Q4 of the amplifier 13 constitute a current mirror. Therefore, if the input is fixed and the current of the temperature compensation current source CS1 is increased, the output current is increased, and if the current of CS1 is decreased, the output current is decreased, that is, the current of the temperature compensation current source CS1 is large. The gain of the amplifier is determined according to. Therefore, by configuring the temperature compensation current source CS1 so that the current can be controlled by the control signal CNT from the outside, it is possible to realize a circuit that can easily adjust the gain of the amplifier. There is.

  FIG. 9 shows a second modification of the Hall IC of the second embodiment. In this modification, instead of providing the temperature compensation circuit 12 that generates the bias voltage Vb that compensates the temperature characteristic of the Hall element 11, the threshold voltage of the hysteresis comparator 16 is changed according to the temperature to thereby change the Hall voltage. The temperature dependence of the element 11 is compensated.

  Specifically, a temperature compensating current source CS2 having a predetermined temperature characteristic and a MOS transistor Q19 provided in series with the current source CS2 are provided, and the transistor Q19 and the two-stage threshold value are generated. MOS transistors Q16 and Q18 are connected in common to form a current mirror. The transistor Q19 has a diode connection in which a gate and a drain are coupled, and converts a current flowing from the current source CS2 into a voltage and supplies the voltage to the gates of Q16 and Q18, whereby the size ratio between Q19 and Q16 and Q18 ( A current corresponding to the ratio of the gate width is supplied to Q16 and Q18. Accordingly, when the current of the current source CS2 changes according to the temperature, the current flowing through Q16 and Q18 changes, and the voltage drop amount at the resistor R1 changes according to the temperature, so that the threshold voltage of the hysteresis comparator 16 is changed. It can be changed according to the temperature.

  The case where the present invention is configured as a three-terminal Hall IC having the power supply voltage terminal VCC, the ground terminal GND, and the detection signal output terminal 18 has been described above. The output terminal 18 is omitted, and a resistor Ro is connected between the power supply voltage terminal VCC and the comparator 16 or the output terminal of the linear amplifier, as shown in FIG. 10A, or as shown in FIG. A series resistor Ro and an output transistor Qo (or only Qo) connected between the power supply voltage terminal VCC and the ground terminal GND are provided, and the output transistor Qo is turned on / off by the output of the comparator 16 or the linear amplifier. It is also possible to configure as a two-terminal Hall IC. By configuring as a two-terminal Hall IC, a system using a large number of Hall ICs has the advantage that the wire harness connecting the Hall IC and the controller can be reduced by combining with an interface circuit as described below. .

  In a conventional magnetic detection system using a two-terminal Hall IC, a load resistor 40 is provided on the power supply line L1 of the Hall IC 10 as shown in FIG. The current flowing through the load resistor 40 is changed by being turned on and off. A comparator 70 is provided on the control unit 20 side, and the comparator 70 compares the voltage at one terminal of the load resistor 40 with the reference voltage Vref to detect a change in the voltage between the terminals of the resistor, thereby controlling the control unit. 20 is configured to input.

  A detection system using a three-terminal Hall IC requires a signal line for transmitting a detection signal in addition to two power lines, whereas a detection system using a two-terminal Hall IC has two power lines. Only L1 and L2 are sufficient. For example, when a Hall IC is provided in a position where the Hall element is provided at a position away from the control unit, such as an automobile control system, and the number tends to increase, the control unit and the Hall IC are connected to each other. There are problems such as an increase in the number of wire harnesses to be connected, which increases costs and makes it difficult to perform maintenance inspections and find faulty parts when a failure occurs.

  On the other hand, the system using the two-terminal Hall IC has an advantage that the wire harness can be reduced, but the reference voltage Vref of the comparator 70 depends on the insertion position of the load resistor 40 and the resistance value of the load resistor 40 to be inserted. Is difficult to set, and if the specification or system configuration of the Hall IC to be used is different, the optimum setting value of the reference voltage Vref is different, which makes the setting more complicated. As described above, since the set value of the reference voltage Vref of the comparator 70 varies, conventionally, an interface IC for performing input / output between the plurality of Hall ICs and the control unit has not been provided.

FIG. 11 shows a first embodiment of an interface circuit suitable for a system using a plurality of Hall ICs, and a configuration example of a control system using the interface circuit.
In FIG. 11, reference numeral 10 denotes a Hall IC, 20 denotes a control unit including a microcomputer, and 30 denotes an interface circuit according to the present invention. For example, in an engine control system, the control unit 20 controls ignition timing of the spark plug based on a detection signal from a Hall IC (sensor) that detects a crank angle provided on the crankshaft. The Hall IC 10 includes a Hall element 11 having magnetic-electrical conversion characteristics, and an output transistor Qo that is turned on and off according to the state of the Hall element 11.

  Although not particularly limited, in this embodiment, the Hall IC 10 uses a two-terminal element having only a power supply terminal to which the drive voltage Vcc is applied and a ground terminal to which the ground potential GND is applied. Although not shown, the Hall IC 10 may be provided with a temperature compensation circuit for guaranteeing a stable output regardless of the temperature variation of the chip. Such a temperature compensation circuit is well known in Patent Document 1 and the like, and is not directly related to the present invention, so that the description thereof is omitted.

  The interface circuit 30 of this embodiment receives a DC power source Vcc from the battery 50 and generates a drive voltage Vbias to be applied to the Hall IC 10, and a power source for connecting the interface circuit 30 and the Hall IC 10. And a current detection circuit 32 that detects a current flowing to the Hall IC 10 via the line L1. Although not particularly limited, the series regulator 31 and the current detection circuit 32 constituting the interface circuit 30 are formed as a semiconductor integrated circuit on one semiconductor chip such as single crystal silicon by a known CMOS manufacturing process.

  The series regulator 31 includes a voltage control MOS transistor Q10 provided between a voltage input terminal P1 connected to the positive terminal of the battery 50 and a voltage output terminal P2 to which a power supply line L1 for supplying power to the Hall IC 10 is connected. And an operational amplifier (operational amplifier circuit) OP1 to which the drain side voltage of the transistor Q10, that is, the output drive voltage Vbias is applied to the inverting input terminal and the reference voltage Vb is applied to the non-inverting input terminal. An output voltage is applied to the gate terminal of the voltage control MOS transistor Q10.

  As a result, the voltage control MOS transistor Q10 is feedback-controlled by the operational amplifier OP1 so that the output drive voltage Vbias matches the reference voltage Vb. In this embodiment, by setting the reference voltage Vb to a value such as 2.5V, the series regulator 31 converts the 12V DC power source from the battery 50 into a 2.5V drive voltage Vbias and outputs it. It is configured. By providing an external terminal that can adjust the reference voltage Vb or set the reference voltage Vb from the outside, the output drive voltage Vbias can be set according to the specifications of the Hall IC to be used.

  The current detection circuit 32 is provided in parallel with the voltage control MOS transistor Q10. Similarly to Q10, the MOS transistor Q20 having the gate terminal applied with the output voltage of the operational amplifier OP1, the voltage input terminal P1, and the ground potential applied. A current-voltage conversion resistor Rs connected in series with the MOS transistor Q20 between the ground terminal P3 and a comparator CMP for comparing the voltage converted by the resistor Rs with a predetermined comparison potential Vc. It is composed of Bipolar transistors may be used in place of the MOS transistors Q10 and Q20.

  The voltage control MOS transistor Q10 is preferably an element having a small on-resistance, that is, a large size so that a sufficient current can flow through the Hall IC 10. On the other hand, the MOS transistor Q20 is used to reduce the current consumption of the interface circuit 30 as much as possible. A small size is desirable. Specifically, the size ratio (gate width ratio) between the transistors Q10 and Q20 is set to a value such as 100: 1 to 1000: 1. Even if the current flowing through Q20 is reduced by setting such a size ratio, a voltage necessary for detection can be generated by increasing the resistance value of the resistor Rs.

  Further, it is desirable to use a comparator having a hysteresis characteristic for the comparator CMP. By using the comparator CMP having hysteresis characteristics, an accurate detection output that ignores the detected current even when noise is applied to the power supply line or the detection current changes due to temperature fluctuation or the like can be obtained.

  In this embodiment, an on-chip element is used as the resistance element Rs. However, an external terminal may be provided in the interface circuit 30 so that it can be connected as an external element. The resistance value of the resistance element Rs is selected such that a voltage of about 0.1 to 1 V is generated due to a voltage drop. In this embodiment, a comparator is used to output a binarized detection result to the control unit 20. However, instead of the comparator, a linear amplifier is provided and the current flowing through the Hall IC 10, that is, the magnetic field of the Hall IC 10 is provided. You may comprise so that it may output as an analog voltage according to detection amount.

  In the system using the interface circuit 30 of this embodiment, since the drive voltage Vbias supplied to the Hall IC 10 is 2.5 V, the current consumption when the Hall IC 10 is off is 5 mA, and the current consumption when the Hall IC 10 is on is 15 mA. Assuming that the thermal resistance is 200 ° C./W to 300 ° C./W, the power consumption when the Hall IC is off is 12.5 mW, the temperature rise due to heat generation is 2.5 ° C. to 3.8 ° C., and when it is on The power consumption is 37.5 mW, and the temperature rise due to heat generation is only 7.5 ° C to 11.3 ° C.

  Therefore, even if the ambient temperature is 150 ° C., the temperature of the Hall IC 10 does not reach 165 ° C., and it is easy to keep it below the operation compensation temperature. Further, in the system using the interface circuit 30 of the present embodiment, since the impedance of the power supply line is reduced, there is an advantage that noise is hardly applied to the power supply line.

Next, a second embodiment of the interface circuit of the Hall IC according to the present invention and a configuration example of a control system using the same will be described with reference to FIG.
The interface circuit 30 of this embodiment is provided with a plurality of sets of a power supply circuit 31 and a current detection circuit 32 formed of a series regulator as shown in FIG. 11, and between the plurality of Hall ICs 10 and the control unit 20. Can be connected by a single interface circuit 30. In a control system such as an automobile, a plurality of Hall ICs are often used as sensors. By using the interface circuit 30 of this embodiment, it is possible to reduce the size of the control device and reduce the cost of the entire system. Can be lowered. In the interface circuit 30 of this embodiment, one or several of the current detection circuits 32 are provided with linear amplifiers, and the remaining current detection circuits 32 are provided with comparators, so that they can be used in accordance with the use location of the sensor. Thus, it can be configured to output a binarized output and an analog value.

  13 and 14 show a modification of the interface circuit 30 of the second embodiment. Among these, FIG. 13 is provided with a parallel-serial conversion circuit 33 for converting the detection outputs of a plurality of current detection circuits 32 into serial data, and the detection result can be output to the control unit as serial data. Since many general-purpose microcomputers have a serial communication port, the use of the interface circuit of this modification has an advantage that it is easy to configure a control system using the general-purpose microcomputer as a control unit.

  In addition, a large-scale system using several tens of Hall ICs cannot be supported by one interface circuit having the configuration shown in FIG. Use of the modified interface circuit facilitates connection to the control unit. For a channel provided with a linear amplifier instead of a comparator in the interface circuit, an AD conversion circuit for converting the analog output of the linear amplifier into a digital signal is provided, and the output of the AD conversion circuit is converted into a parallel-serial signal. Variations can be applied.

  The modification of FIG. 14 shows a configuration of an interface circuit suitable for configuring an in-vehicle control system. In recent years, a LAN (local area network) standard called LIN or CAN has been proposed for an in-vehicle control system. In this modification, an interface 34 corresponding to LIN or CAN is incorporated. Thereby, it becomes easy to apply to the control system which employ | adopted vehicle-mounted LAN.

Next, a third embodiment of the Hall IC interface circuit according to the present invention will be described with reference to FIG.
In this embodiment, the current detection circuit 32 of the interface circuit is configured by a logic circuit. Specifically, the voltage signal converted by the resistor Rs is discriminated by a predetermined threshold value Vth and latched in synchronization with the clock CLK, and the output of the first latch circuit LT1 is latched. And a determination circuit JDG that compares the outputs Vt (n−1) and Vt (n) of the two latch circuits LT1 and LT2 to determine whether or not the signal has changed. ing. The determination circuit JDG can be configured by a logic gate circuit such as an exclusive OR gate.

  FIG. 16 shows the signal timing of each part of the current detection circuit 32 in the interface circuit of this embodiment. 16, (a) is the current flowing through the Hall IC, (b) is the current detection output detected by the resistor Rs, etc., (c) and (d) are the outputs Vt (n-1) of the latch circuits LT1 and LT2. , Vt (n), (e) are the exclusive logical ring of Vt (n-1) and Vt (n), and (f) is the determination output DTC of the determination circuit JDG. The determination circuit JDG is configured so that the output is switched when the output result of (e) is switched from the low level to the high level. In the interface circuit of this embodiment, as shown in FIGS. 16A and 16B, there is an advantage that no noise appears in the output even if the current flowing in the Hall IC or the current detection output has noise. .

  Note that latch means (sample hold means) capable of holding an analog voltage is used as the first latch circuit LT1 and the second latch circuit LT2 shown in FIG. 15, and the latch means is held in the subsequent stage. The subtracting means that takes the difference Vt (n-1) -Vt (n) of the voltage being applied, and the hysteresis that compares the difference output (see FIG. 16 (g)) of the subtracting means with the predetermined threshold values Vth1 and Vth2. An attached comparator or the like may be provided to determine the detected current.

FIG. 17 shows a fourth embodiment of the interface circuit 30.
In the interface circuit of the present embodiment, the current detection circuit 32 is configured by the comparator CMP that determines the detection output from the current detection means 60 that detects the current of the power supply line L1 provided outside by comparing with the comparison voltage Vc. It is a thing. According to this embodiment, the transistor Q20 and the resistor Rs are not required as compared with the embodiment of FIG. 11, and there is an advantage that the interface circuit can be simplified and reduced in size.

  Also in the present embodiment, a modified example in which a linear amplifier is used instead of the comparator CMP and an analog voltage is output can be considered. The current detection means 60 for detecting the current of the power supply line L1 includes a ring-shaped magnetic body 61 that is disposed around the power supply line L1 and has a partially cut portion, and a magnetic body that is disposed at the cut portion of the magnetic body 61. For example, a sensor including a Hall element 62 that detects a magnetic field generated in the sensor can be considered. A load resistor may be provided in the interface circuit 30 in preparation for using a sensor having the Hall element 62.

  According to this embodiment, a Hall element interface circuit capable of accurately detecting magnetism regardless of the specifications of the Hall element used, reducing the amount of heat generated by the Hall element, and improving the reliability, and a system using the same Can be realized.

  Furthermore, a highly versatile Hall element interface circuit capable of outputting detection results to a controller having a serial communication function or an interface connectable to a bus constituting a LAN, and a system using the same are realized. There is an effect that can be done.

Next, an embodiment of a module in which the Hall IC 10 and the interface circuit 30 of the above embodiment are mounted on one printed wiring board will be described with reference to FIGS.
The module 80 of the embodiment shown in FIG. 18 has a plurality of Hall ICs 10 arranged in a row and mounted on a printed wiring board 81, and held by a yoke 82 made of a magnetic material so as to face each Hall IC 10. It is fixed on the substrate 81 with holders 85a and 85b so that the counter substrate 84 on which the magnets 83 are arranged faces each other at a predetermined interval. In this module 80, a triangular magnetic plate 86 as shown in FIG. 19 is slidably inserted in the interval between the printed circuit board 81 and the counter substrate 84, and the position or movement amount of the plate 86 is detected. Functions as a position detection device.

  In place of using the magnetic plate 86 shown in FIG. 19, a plurality of magnets 83 on the counter substrate 84 can be opposed to a plate 87 made of a rectangular nonmagnetic material as shown in FIG. The magnetic piece 88 provided in a predetermined pattern may be used. When the plate of FIG. 20 is used, a detection signal in which position information is encoded is obtained from the Hall IC 10 on the printed circuit board 81. Therefore, the number of Hall ICs 10 can be reduced as compared with the case of using the magnetic plate 86 shown in FIG. There is an advantage that you can. For example, in the case of FIG. 19, if eight Hall ICs 10 are required, three Hall ICs 10 are sufficient in the case of FIG. 20, and in the case of FIG. 19, 256 Hall ICs 10 are required in the case of FIG. Requires 8 Hall ICs 10. That is, 2 n Hall ICs can be substituted with n Hall ICs.

  FIG. 21 shows a configuration example of a detection system using the Hall IC, the interface circuit 30 shown in FIG. 13, and the module 80 shown in FIG. When the positions where the sensors are provided are different but relatively close to the control unit 20 composed of a microcomputer, the Hall ICs 10 are individually connected to the control unit 20 as indicated by reference signs A to X. The signal is detected in parallel. When the position where the sensor is provided is far from the control unit 20 but a plurality of sensors are arranged together, a common interface circuit 18 is assigned to the integrated Hall ICs 10a to 10h, and a detection signal is sent from each IC. The detected data may be transferred to the control unit 20 by serial communication.

  By applying the module 80 shown in FIG. 18 to a portion where a position detection device is required, the interface circuit 18 in the module sucks a detection signal from each Hall IC 10 in the module, and the detection data is sent to the control unit 20 by serial communication. Can be transferred. Further, the module 80 may be provided with one or several ports or terminals 89 to which a detection signal from a single Hall IC 10 other than the position detection Hall IC 10 can be input. As a result, it is possible to collect the detection signals of the Hall IC 10 that is separated from the control unit 20 but close to the position detection module 80 without providing an extra wire.

  According to the embodiment of the present invention, it is possible to easily achieve a low power supply voltage of a Hall IC incorporating a Hall element and a differential amplifier that detects a voltage generated by the Hall element. Furthermore, it is possible to realize a Hall IC incorporating a Hall element and a Hall voltage detection differential amplifier capable of obtaining a continuous output with a relatively simple configuration.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above embodiment, a system using a two-terminal Hall IC is shown. However, the interface circuit of this embodiment can also be applied to a case where the Hall IC to be used has three terminals. In that case, an external resistor may be connected between the output terminal of the three-terminal Hall IC and the power supply voltage terminal.

  In the above embodiment, the example of the interface circuit configured as a monolithic IC in which the elements constituting the power supply circuit 31 and the current detection circuit 32 are formed on one semiconductor chip has been described. However, the present invention is not limited thereto. However, the present invention can be applied to a case where a plurality of ICs and electronic components such as discrete resistance elements are mounted on a single insulating substrate as a hybrid module. In the above embodiment, the power supply circuit provided in the interface circuit uses a series regulator. However, a switching regulator or a shunt regulator may be used.

  The present invention is most effective when applied to a control system having a Hall IC used as a sensor, such as a vehicle speed sensor, a wheel speed sensor, a crank angle sensor, etc. Control system using Hall IC as a position sensor represented by the above, and Hall IC as a sensor for detecting the position of a rotor of a brushless motor such as a washing machine or an air conditioner, or detecting the open / closed state of a door. It can also be used as a control system for household electrical appliances using the.

It is a circuit block diagram which shows the 1st Example of Hall IC which concerns on this invention. (A) is operation | movement explanatory drawing which shows the state of the 1st phase of Hall IC of an Example, (B) is operation | movement explanatory drawing which shows the state of the 2nd phase of Hall IC of an Example. It is a timing chart which shows the change of the voltage of each part of Hall IC of an example. It is a circuit block diagram which shows the 2nd Example of Hall IC which concerns on this invention. (A) is operation explanatory drawing which shows the state of the 1st phase of Hall IC of the 2nd example, and (B) is operation explanatory drawing which shows the state of the 2nd phase of Hall IC of the 2nd example. . It is a timing chart which shows the change of the voltage of each part of Hall IC of the 2nd example. It is a circuit diagram which shows the specific circuit example of Hall IC of a 2nd Example. It is a circuit diagram which shows the 1st modification of Hall IC of a 2nd Example. It is a circuit diagram which shows the 2nd modification of Hall IC of a 2nd Example. (A), (B) is a schematic explanatory drawing which shows the modification of Hall IC of this invention, (C) is a block diagram which shows the structural example of the magnetic detection system which uses Hall IC of 2 terminals. 1 is a block diagram showing a first example of a Hall element interface circuit according to the present invention and a configuration example of a control system using the interface circuit; FIG. It is a block diagram which shows the 2nd Example of the interface circuit of the Hall element based on this invention, and the structural example of the control system using this interface circuit. It is a block diagram which shows the modification of the interface circuit of a 2nd Example. It is a block diagram which shows the other modification of the interface circuit of a 2nd Example. It is a block diagram which shows the 3rd Example of the interface circuit of the Hall element based on this invention. It is a timing chart which shows the timing of the signal of each part of the current detection circuit in the interface circuit of a 3rd Example. It is a block diagram which shows the 4th Example of the interface circuit of the Hall element based on this invention. It is a side view which shows the Example of the module for position detection which mounted the Hall IC and the interface circuit of the Example on one printed wiring board. It is front explanatory drawing which shows the use condition which abbreviate | omitted the opposing board | substrate of the position detection module of the Example which mounted the Hall IC and the interface circuit on one printed wiring board. It is front explanatory drawing which shows the other structural example of the magnetic body plate used for the module for position detection of an Example. It is a block diagram which shows the structural example of the detection system using Hall IC, an interface circuit, and the position detection module.

Explanation of symbols

10 Hall IC
11 Hall element 12 Temperature compensation circuit 13 Gm amplifier 14 Constant voltage circuit 15 Voltage follower 16 Hysteresis comparator 17 Latch circuit (sample hold circuit)
18 Output Terminal 19 Bias Voltage Generation Circuit 20 Control Unit 30 Interface Circuit 31 Power Supply Circuit (Series Regulator)
32 current detection circuit 50 battery 80 position detection module 81 printed wiring board 82 yoke 83 magnet 84 counter substrate 86 magnetic plate RL current-voltage conversion resistance CMP comparator VF voltage follower Qo output transistor

Claims (10)

Hall element having two pairs of opposing terminal pairs positioned on intersecting lines, and a voltage change that occurs between the other terminal pair when a predetermined bias voltage is applied between one terminal pair of the Hall element and a current flows A voltage input-current output type differential amplifying circuit, and switching the predetermined bias voltage applied to the Hall element in a first phase period and a second phase period to switch one terminal pair of the Hall element Alternatively, a first switching circuit that alternately applies to the other terminal pair, and a voltage generated between one terminal pair of the Hall element during the first phase period and the other terminal pair of the Hall element during the second phase period. A magnetic switching semiconductor integrated circuit comprising: a second switching circuit that alternately applies a voltage generated between the differential input terminals of the differential amplifier circuit;
The differential amplifier circuit comprises a differential input-single phase output differential amplifier circuit having a pair of differential input terminals and one output terminal, and a predetermined potential is applied to the output terminal of the differential amplifier circuit. A resistance element that is connected between the constant potential point and converts the current output from the differential amplifier circuit into a voltage, and one terminal is connected to the constant potential point and provided in parallel with the resistance element. A capacitive element and a switching element connected in series with the capacitive element and present between the output terminal and the other terminal of the capacitive element, the switching element being in the first phase period The output is obtained by sampling the voltage between the terminals of the resistance element in the capacitive element in the on state and holding the voltage held in the capacitive element by turning off the switch element in the second phase period. Terminal and said Magnetic sensing semiconductor integrated circuit, characterized in that is configured to output a signal corresponding to a potential difference by comparing the voltage between the other terminal of the quantity elements. Hall element having two pairs of opposing terminal pairs positioned on intersecting lines, and a voltage change that occurs between the other terminal pair when a predetermined bias voltage is applied between one terminal pair of the Hall element and a current flows A voltage input-current output type differential amplifying circuit, and switching the predetermined bias voltage applied to the Hall element in a first phase period and a second phase period to switch one terminal pair of the Hall element Alternatively, a first switching circuit that alternately applies to the other terminal pair, and a voltage generated between one terminal pair of the Hall element during the first phase period and the other terminal pair of the Hall element during the second phase period. A magnetic switching semiconductor integrated circuit comprising: a second switching circuit that alternately applies a voltage generated between the differential input terminals of the differential amplifier circuit;
The differential amplifier circuit comprises a differential input-single phase output differential amplifier circuit having a pair of differential input terminals and one output terminal, and a predetermined potential is applied to the output terminal of the differential amplifier circuit. A resistance element that is connected between the constant potential point and converts the current output from the differential amplifier circuit into a voltage, and one terminal is connected to the constant potential point and provided in parallel with the resistance element. And a first switch element connected in series with the first capacitor element and present between the output terminal and the other terminal of the first capacitor element, A second capacitive element connected to the constant potential point and provided in parallel with the resistive element, and connected in series with the second capacitive element, the output terminal and the second capacitive element A second switch element existing between the other terminal and the front terminal The first switch element is turned on during the first phase period, the terminal voltage of the resistance element is sampled in the first capacitor element, and the second switch element is turned on during the second phase period. The voltage between the terminals of the resistance element is sampled in the second capacitor element, and the voltage applied to the other terminal of the first capacitor in the first phase period and the second phase period, respectively, A magnetic detection semiconductor integrated circuit which compares a voltage applied to the other terminal of the second capacitor and outputs a signal corresponding to the potential difference.   The second switching circuit is configured such that the polarity of the voltage input to the differential amplifier circuit during the first phase period is opposite to the polarity of the voltage input to the differential amplifier circuit during the second phase period. The semiconductor integrated circuit for magnetic detection according to claim 1, wherein the input is switched.   4. The semiconductor integrated circuit for magnetic detection according to claim 1, further comprising a temperature compensation circuit that compensates for temperature dependence of the Hall element.   5. The magnetic detection according to claim 4, wherein the temperature compensation circuit gives a temperature characteristic that compensates for temperature dependence of the Hall element to the predetermined bias voltage applied between the pair of terminals of the Hall element. Semiconductor integrated circuit.   2. The semiconductor integrated circuit for magnetic detection according to claim 1, further comprising a voltage comparison circuit that has a hysteresis characteristic and compares a voltage between the output terminal and the other terminal of the capacitive element.   7. The semiconductor integrated circuit for magnetic detection according to claim 6, further comprising an impedance conversion circuit provided between the other terminal or the output terminal of the capacitive element and the voltage comparison circuit.   8. A semiconductor integrated circuit for magnetic detection according to claim 1, a power supply circuit for generating a voltage to be applied to the semiconductor integrated circuit for magnetic detection by stepping down a power supply voltage supplied from a power supply, and the magnetic detection An electronic component comprising: an interface semiconductor integrated circuit having an interface circuit that receives a detection signal output from the semiconductor integrated circuit and outputs the detection signal to an external control circuit; .   The magnetic detection semiconductor integrated circuit is a two-terminal semiconductor integrated circuit having a power supply voltage terminal to which a drive voltage from the power supply circuit is applied and a ground terminal to which a reference potential is applied, and the interface semiconductor integrated circuit is 9. The electronic component according to claim 8, further comprising a current detection circuit that detects a current flowing from the power supply circuit to the magnetic detection semiconductor integrated circuit.   A semiconductor integrated circuit for magnetic detection according to any one of claims 1 to 7, a magnet opposed to the semiconductor integrated circuit for magnetic detection at a predetermined interval, and a power supply voltage supplied from a power supply is stepped down. Interface semiconductor integrated circuit comprising a power supply circuit that generates a voltage to be applied to the magnetic detection semiconductor integrated circuit and an interface circuit that receives a detection signal output from the magnetic detection semiconductor integrated circuit and outputs the detection signal to an external control circuit Are mounted on a single insulating substrate.

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