JP4640274B2 - Class D amplifier - Google Patents

Description

  The present invention relates to a class D amplifier, and more particularly to a technique for detecting a DC output.

  Conventionally, a class D amplifier that converts an analog input signal such as an audio signal into a pulse signal and amplifies the power is known. According to this class D amplifier, a pulse signal whose power is amplified with the amplitude (information component) of the input signal reflected in the pulse width is output. The pulse signal is converted into an analog signal by passing through an external low-pass filter, and this signal drives the speaker. Since the class D amplifier can be formed on a silicon chip, the class D amplifier can be realized in a small size and at a low cost, and is widely used in portable terminals and personal computers that require low power consumption.

  FIG. 12 shows an example of a conventional class D amplifier. In this example, analog input signals AIN (+) and AIN (−) having opposite polarities are applied to the input terminals T11 and T12 of the class D amplifier from an external signal source, and the analog input signals AIN (+), AIN (−) is input to the integrating circuit 110 via the input resistors R11 and R12. The pulse width modulation circuit 120 compares the output signal of the integration circuit 110 with the triangular wave signal from the triangular wave generation circuit 140 to output a pulse width modulated signal.

The drive circuit 130 outputs complementary pulse signals OUTP and OUTM based on the output signal of the pulse width modulation circuit 120. The pulse signals OUTP and OUTM are fed back to the input side of the integration circuit 110 via feedback resistors R21 and R22, thereby correcting the waveform distortion of the pulse signal. The pulse signals OUTP and OUTM are output to the outside via the output terminals T21 and T22, and become analog signals that drive the speaker SP through a low-pass filter including the inductors L1 and L2 and the capacitor C.
Japanese Patent Publication No.56-27001

  By the way, generally, when a DC output is applied to the speaker from the amplifier and the cone paper of the speaker is driven in a DC manner, the speaker may be damaged. As an example of a measure for preventing such breakage of the speaker, for example, when a DA converter or the like is connected in front of the input section of the amplifier, input is performed by digital processing on the front side of the DA converter. There is a method of previously removing a DC component from a signal.

  However, according to this method, it is impossible to prevent a DC output due to a failure of the amplifier itself. Therefore, in order to cope with such a failure of the amplifier itself, a method of monitoring the output of the amplifier is necessary. As this technique, for example, there is a technique in which a low-pass filter (R = 220 kΩ, C = 10 μF) having a cutoff frequency of about 0.07 Hz is connected to the output section of the amplifier, and the DC output is extracted by the low-pass filter.

  However, according to the above-described method using each low-pass filter, there is a problem that the device configuration is complicated. That is, as shown in FIG. 12, when the output format of the amplifier is a BTL (Bridged Transformer Less) format, it is necessary to connect a low pass filter for DC output extraction to each of the two output terminals T21 and T22. A circuit for calculating the difference between the outputs of the low-pass filter is required. Moreover, since the chemical capacitor generally used for a low-pass filter is expensive, it also causes an increase in apparatus cost.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a class D amplifier having a function of detecting the DC output of an amplifier with a simple configuration.

The present invention is a class D amplifier configured to generate a first pulse signal and a second pulse signal whose duty changes in a complementary manner according to the signal level of the analog input signal by performing pulse width modulation on the analog input signal. Then, the first and second pulse signals are converted into first and second signals according to the polarity of the signal level of the analog input signal, and one of the first and second signals is converted during the conversion. Is a signal of a predetermined level, the other is a pulse signal modulated by pulse width, and the level of the first and second signals is complementarily set to the predetermined level, and any one of the first and second signals And a timer unit for detecting that the predetermined level has been maintained for a predetermined time.

In the class D amplifier, for example, the signal conversion unit includes a first logic circuit unit and a second logic circuit unit, and the polarity of the signal level of the analog input signal is either positive or negative, When the first pulse signal is at a level complementary to the predetermined level and the first input condition that the second pulse signal is at the predetermined level is satisfied, the second logic circuit unit is 2 signals are output as signals of the predetermined level, and the first logic circuit unit outputs the first signals as pulse width modulated pulse signals , and the polarity of the signal level of the analog input signal is positive or negative A first polarity complementary to the first input condition of the other polarity, wherein the first pulse signal is at the predetermined level and the second pulse signal is at a level complementary to the predetermined level . 2 input conditions If the plus, the first logic circuit unit outputs the first signal as the predetermined level of the signal, the second logic circuit outputs the second signal as a pulse width modulated pulse signal It is characterized by that.

In the class D amplifier, for example, the timing unit includes a first shift register that starts an operation based on a predetermined clock signal when the signal level of the first signal reaches the predetermined level, and the signal of the second signal A second shift register that starts an operation based on a predetermined clock signal when the level reaches a predetermined level; and a logical sum circuit that calculates a logical sum of the output signals of the first and second shift registers. It is characterized by.
In the class D amplifier, for example, the signal conversion unit further includes a delay unit that delays one of the first and second pulse signals by a predetermined time.

The class D amplifier according to the present invention outputs a signal having a predetermined level from one of the first and second output terminals when the polarity of the signal level of the analog input signal is positive, and a pulse whose width is modulated from the other. A class D amplifier configured to output a signal and output a signal of a predetermined level from the other and a pulse width modulated pulse signal from the other when the polarity of the signal level of the analog signal is negative And a class D amplifier having a timer unit for detecting that the predetermined level is maintained for a predetermined time.

  In the class D amplifier, for example, the timing unit includes a shift register that starts an operation based on a clock signal when a signal output from one of the first and second output terminals reaches the predetermined level. It is characterized by that.

  According to the present invention, since a state in which a signal having a predetermined level according to the polarity of the analog input signal is maintained at the predetermined level for a predetermined time is detected, the state in which the polarity of the analog input signal does not change is grasped. Therefore, the DC output can be detected with a simple configuration.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 shows an example of a class D amplifier according to the first embodiment of the present invention. The class D amplifier shown in FIG. 1 performs pulse width modulation on an analog input signal AIN from an external signal source SIG, and generates pulse signals OUTP and OUTM whose duty changes complementarily according to the signal level of the analog input signal AIN. It is configured to generate and output, and further includes a DC detection unit 150 as compared with the configuration of the conventional class D amplifier shown in FIG.

  That is, the class D amplifier according to this embodiment shown in FIG. 1 includes input terminals T11 and T12, input resistors R11 and R12, feedback resistors R21 and R22, an integration circuit 110, a pulse width modulation circuit 120, a drive circuit 130, and a triangular wave generation. The circuit 140, the DC detection unit 150, and the output terminals T21, T22, and T23 are configured. Analog input signals AIN (+) and AIN (−) having opposite polarities are applied to the input terminals T11 and T12 from the signal source SIG. The

  Here, the integration circuit 110 includes a differential operational amplifier 111 and capacitors 112 and 113. An input resistor R11 is connected between the inverting input portion of the differential operational amplifier 111 and the input terminal T11, and an input is provided between the non-inverting input portion of the differential operational amplifier 111 and the input terminal T12. Resistor R12 is connected. A capacitor 112 is connected between the inverting input unit and the non-inverting output unit of the differential operational amplifier 111, and a capacitor 113 is connected between the non-inverting input unit and the inverting output unit.

  The pulse width modulation circuit 120 includes comparators 121 and 122. Among these, the non-inverting input part of the comparator 121 is connected to the non-inverting output part of the differential operational amplifier 111, and the non-inverting input part of the comparator 122 is connected to the inverting output part of the differential operational amplifier 111. A triangular wave signal T (a triangular wave signal having a constant period and peak value) is commonly input from the triangular wave generating circuit 140 to each inverting input unit of the comparators 121 and 122.

  The drive circuit 130 includes an inverter 132 and CMOS driver inverters 131 and 133. The input part of the driver inverter 131 is connected to the output part of the comparator 121. The output part of the driver inverter 131 is connected to the output terminal T21, and the inverting input of the differential operational amplifier 111 via the feedback resistor R21. Connected to the part. The input part of the inverter 132 is connected to the output part of the comparator 121, the input part of the driver inverter 133 is connected to the output part of the inverter 132, and the output part of the driver inverter 133 is connected to the output terminal T22. And connected to the non-inverting input portion of the differential operational amplifier 111 via a feedback resistor R22.

  One output terminal T21 is connected to one end of an inductor L1, and the other end of the inductor L1 is connected to one input terminal of the speaker SP. One end of the inductor L2 is connected to the other output terminal T22, and the other end of the inductor L2 is connected to the other input terminal of the speaker SP. A capacitor C is connected between the other end of the inductor L1 and the other end of the inductor L2. The inductors L1 and L2 and the capacitor C constitute a low-pass filter for removing a carrier frequency component in pulse width modulation from the output signal of the class D amplifier.

The output units of the comparators 121 and 122 of the pulse width modulation circuit 120 are connected to the input unit of the DC detection unit 150 according to the feature of the class D amplifier, and the output unit of the DC detection unit 150 is an output terminal. Connected to T23.
Note that VDD is a power supply voltage, and GND is a ground voltage (0 V). In this embodiment, it is assumed that the power supply voltage VDD is 12 V, and the class D amplifier operates with a single power supply.

The detailed configuration of the DC detection unit 150 will be described with reference to FIG.
As shown in the figure, the DC detection unit 150 includes a signal conversion unit 151 and a timer unit 152. Among these, the signal conversion unit 151 includes inverters 151A, 151B, 151D, 151F, 151G, and 151J, a delay unit 151E, negative AND gates 151C and 151H, and the timing unit 152 includes a D-type flip-flop 152A. , 152B, 152C, 152D and an OR gate 152E.

  Here, the pulse signal SC output from the comparator 121 of the pulse width modulation circuit 120 described above is given to the input portion of the inverter 151A constituting the signal converter 151, and the output portion of the inverter 151A is the input of the inverter 151B. Connected to the part. The output part of the inverter 151B is connected to one input part of the negative AND gate 151C, and the output part of the negative AND gate 151C is connected to the input part of the inverter 151D. The output signal of the inverter 151D is a signal P.

In addition, the pulse signal SD output from the comparator 122 of the pulse width modulation circuit 120 is given to the input unit of the delay unit 151E, and the output unit of the delay unit 151E is connected to the input unit of the inverter 151F. The output part of the inverter 151F is connected to the input part of the inverter 151G. The output part of the inverter 151G is connected to one input part of the negative AND gate 151H, and the output part of the negative AND gate 151H is connected to the input part of the inverter 151J. The output signal of the inverter 151J is a signal M. The other input part of the negative AND gate 151C is connected to the output part of the inverter 151F, and the other input part of the negative AND gate 151H is connected to the output part of the inverter 151A.

Asynchronous reset terminals of the D-type flip-flops 152A and 152B constituting the timer unit 152 are connected to the output part of the inverter 151D constituting the signal converter 151 described above. Among these flip-flops, the data input portion of the D-type flip-flop 152A is connected to the power source, and the data output portion is connected to the data input portion of the D-type flip-flop 152B. The output part of the D-type flip-flop 152B is connected to one input part of the OR gate 152E.

Further, the asynchronous reset terminals of the D-type flip-flops 152C and 152D constituting the timer unit 152 are connected to the output part of the inverter 151J constituting the signal converter 151. Among these flip-flops, the data input portion of the D-type flip-flop 152C is connected to the power supply, and the data output portion is connected to the data input portion of the D-type flip-flop 152D. The output portion of the D-type flip-flop 152D is connected to the other input portion of the OR gate 152E.

  A clock signal CLK having a constant frequency is input to each clock terminal of the D-type flip-flops 152A to 152D. The D-type flip-flops 152A and 152B constitute a first shift register that operates based on the clock signal CLK, and the D-type flip-flops 152C and 152D constitute a second shift register that operates based on the clock signal CLK. To do. In this embodiment, the clock signal CLK is generated inside the class D amplifier and has a frequency of 40 Hz. As will be described later, this frequency defines the time measured by the time measuring unit 152 when detecting the DC output.

Next, the operation of the class D amplifier according to this embodiment will be described.
(1) Amplification Operation First, a normal amplification operation (power amplification operation) will be described with reference to the waveform diagram of FIG.
An analog input signal AIN (+) from the signal source SIG is applied to the input terminal T11 shown in FIG. (-) Is applied. These analog input signals AIN (+) and AIN (−) are input to the integrating circuit 110 via input resistors R11 and R12.

  The integrating circuit 110 integrates the difference between the analog signal AIN (+) and the analog input signal AIN (−), and outputs the positive phase signal (output signal from the non-inverting output unit) SA of the difference from the non-inverting output unit. At the same time, the opposite phase signal (output signal from the inverted output unit) SB of the difference is output from the inverted output unit. The normal phase signal SA and the negative phase signal SB are input to the pulse width modulation circuit 120.

  The comparators 121 and 122 of the pulse width modulator 120 compare the positive phase signal SA and the negative phase signal SB output from the integration circuit 110 with the triangular wave signal T output from the triangular wave generation circuit 140, thereby comparing the pulse width. Modulated pulse signals SC and SD are output. Among these, the pulse signal SC is output as complementary output pulse signals OUTP and OUTM from the drive circuit 130 via the output terminals T21 and T22, and these output pulse signals OUTP and OUTM are supplied via the feedback resistors R21 and R22. Thus, the output waveform distortion is reduced by feeding back to the differential operational amplifier 111 of the integrating circuit 110.

  3A to 3E show the signal waveforms. 3A to 3C show signal waveforms when the analog input signal AIN has a signal level of 0 V, that is, no signal input state. FIG. 3A shows a triangular wave generation. Each waveform of the triangular wave signal T generated by the circuit 140 and the positive phase signal SA and the negative phase signal SB output from the integrating circuit 110 are shown. FIG. 3B shows the waveforms of the pulse signals SC and SD. FIG. 3C shows the waveforms of the output pulse signals OUTP and OUTM. FIG. 3D shows the case where the signal level of the analog input signal AIN (+) increases and becomes positive (that is, the signal level of the analog input signal AIN (−) decreases and becomes negative). FIG. 3 (e) shows signal waveforms of the output pulse signals OUTP and OUTM of FIG. 3, and FIG. 3 (e) shows a case where the signal level of the analog input signal AIN (+) decreases and becomes negative (that is, the analog input signal AIN (−)). Each signal waveform of the output pulse signals OUTP and OUTM when the signal level increases and becomes positive) is shown.

  In the no-signal input state, the difference between the input signal of the inverting input section and the input signal of the non-inverting input section of the differential operational amplifier 111 is zero. Therefore, as shown in FIG. The waveform and the waveform of the negative phase signal SB match, that is, the difference between the positive phase signal SA and the negative phase signal SB becomes zero. In the no-signal input state, as shown in FIGS. 3B and 3C, the pulse signals SC and SD and the output pulse signal OUTP. The relationship between the triangular wave signal T, the positive phase signal SA, and the negative phase signal SB is set so that each duty of OUTM is 50%.

  Here, as understood from FIGS. 3A and 3B, the high level period (pulse width) of the pulse signals SC and SD depends on the signal levels of the positive phase signal SA and the negative phase signal SB, The signal levels of the positive phase signal SA and the negative phase signal SB depend on the signal levels of the analog input signals AIN (+) and AIN (−). Therefore, the pulse widths of the pulse signals SC and SD depend on the signal levels of the analog input signals AIN (+) and AIN (−), thereby realizing pulse width modulation.

  In the no-signal input state, the duty of the output pulse signal OUTP is 50%. Therefore, when the signal level of the output pulse signal OUTP is integrated by the inductor L1 and the capacitor C, the integrated value (average value) becomes 6V. Further, since the duty of the output pulse signal OUTM is also 50%, its integrated value is 6V. Therefore, in the no-signal input state, 6 V is applied to both input terminals of the speaker SP, and the difference voltage becomes 0 V. Therefore, the speaker SP is not driven.

  When the signal level of the analog input signal AIN (+) increases and the signal level of the analog input signal AIN (−) having the opposite polarity decreases from the above-described no-signal input state, the positive phase signal output from the integrating circuit 110. The signal level of SA decreases, and therefore the high level period of the pulse signal SC decreases. As a result, as shown in FIG. 3D, the high level period of the output pulse signal OUTP, which is an inverted signal of the pulse signal SC, increases, and the low level of the output pulse signal OUTM that is in phase with the pulse signal SC. The period increases. That is, the duty of the output pulse signal OUTP increases and the duty of the output pulse signal OUTM decreases.

  In this case, the integrated value of the output pulse signal OUTP obtained by integrating with the inductor L1 and the capacitor C is, for example, 8V, which is higher than 6V at the time of no signal input, and is obtained by integrating with the inductor L2 and the capacitor C. The integrated value of the output pulse signal OUTM is, for example, 4V, which is lower than 6V when no signal is input. Therefore, the voltage difference between the input terminals of the speaker SP becomes, for example, 4V (= 8V-4V), and the cone paper of the speaker SP is driven forward, for example.

  Conversely, when the signal level of the analog input signal AIN (+) decreases and the analog input signal AIN (−) rises from the above-described no-signal input state, FIG. 3 (d) is reversed. As shown in (e), the duty of the output pulse signal OUTP decreases while the duty of the output pulse signal OUTM increases. Thereby, the voltage difference between the input terminals of the speaker SP becomes, for example, −4 V (= 4 V−8 V), and the cone paper of the speaker SP is driven rearward, for example.

  As described above, in the normal amplification operation, the duty ratios of the output pulse signal OUTP and the output pulse signal OUTM are complementarily controlled according to the signal level of the analog input signal AIN, so that the difference between the two terminals of the speaker P is achieved. The speaker SP is driven by generating a voltage.

(2) DC Output Detection Operation Next, the DC output detection operation by the DC detection unit 150 will be described.
Prior to the description of the operation, the definition of “DC output” will be described. In this embodiment, the output of the amplifier when the cone paper of the speaker continues to be driven forward or backward is defined as a DC output. This state corresponds to a state in which one of signals P and M output from the signal conversion unit 151 described later is fixed at a low level, but in this embodiment, one of the signals P and M is longer than a predetermined time. The output when the signal is maintained at a low level for a long time is regarded as a DC output. Here, the “predetermined time” can be arbitrarily set as a reference for considering the output of the class D amplifier as DC (direct current). As will be described later, this “predetermined time” is measured by the timer unit 152 and is set to 25 ms in the present embodiment.

(2-1) Operation of Signal Conversion Unit 151 Constructing DC Detection Unit 150 Next, the operation of the signal conversion unit 151 constituting the DC detection unit 150 will be described. Schematically, the signal converter 151 converts the pulse signals SC and SD into signals P and M (first and second) that are complementary to a low level (predetermined level) according to the signal level of the analog input signal AIN. Signal). Hereinafter, the operation of the signal conversion unit 151 will be described in detail by dividing into a no-signal input state, a state where the analog input signal is increased, and a state where the analog input signal is decreased.

(2-1-1) No-Signal Input State FIG. 4 shows the waveforms of the pulse signals SC and SD that are input signals of the signal converter 151 in the no-signal input state and the signals P and M that are output signals at that time. Indicates. As described above, in the no-signal input state, each duty of the pulse signals SC and SD is 50%, and the waveforms of the normal phase signal SC and the negative phase signal SD match.

Pulse signal SC is applied to one input part of negative AND gate 151C through inverters 151A and 151B, and is inverted by inverter 151A and supplied to the other input part of negative AND gate 151H . The pulse signal SD is delayed by a fixed time by the delay unit 151E and then output from the delay unit 151E as the pulse signal Sd. This pulse signal Sd is inverted by the inverter 151F and supplied to the other input portion of the negative AND gate 151C, and is also supplied to one input portion of the negative AND gate 151H through the inverters 151F and 151G. .

  When the first input condition in which the pulse signal SC is high level and the pulse signal Sd is low level is satisfied, the negative AND gate 151C outputs a low level to the inverter 151D. A high level (a level complementary to the predetermined low level) is output. On the other hand, when the negative AND gate 151H satisfies the second input condition in which the pulse signal SC is at a low level and the pulse signal Sd is at a high level (that is, an input condition complementary to the first input condition). The low level is output to the inverter 151J, and the inverter 151J outputs a high level (a level complementary to the low level which is the predetermined level) as the signal M.

Here, in the present embodiment, the first input condition is to specify the signal levels of the pulse signal SC and the pulse signal Sd that are pulse width modulated when the polarity of the signal level of the analog input signal AIN (+) is negative. The second input condition is a specific combination of signal levels of the pulse signal SC and the pulse signal Sd that are pulse width modulated when the polarity of the signal level of the analog input signal AIN (+) is positive. Is set as

  In this way, by setting the first and second input conditions that are complementary to each other, the pulse width-modulated pulse signals SC and SD are converted into signals P and M that are complementarily fixed at a low level. It is possible to do. However, the present invention is not limited to this example, and any combination of signal levels corresponding to changes in the pulse widths of the pulse signal SC and the pulse signal Sd by pulse width modulation can be arbitrarily set.

  Here, as can be understood from the waveforms of the signals shown in FIG. 4, in the no-signal input state, the pulse signal Sd after the pulse signal SC transits to the high level during the period in which the first input condition is satisfied. Is a fixed period until the transition to high level, and this period corresponds to the delay time tD in the delay unit 151E. The period in which the second input condition is satisfied is a fixed period from when the pulse signal SC changes to the low level until the pulse signal Sd changes to the low level, and this period is also the time at the delay unit 151E. This corresponds to the delay time tD. After all, at the time of no signal input, the signal conversion unit 151 converts the pulse signals SC and SD into pulse signals having a predetermined pulse width corresponding to the delay time tD, and intermittently outputs them with the period of the triangular wave signal T.

(2-1-2) When the analog input signal rises from the no-signal input state (0 V) FIG. 5 shows the input signal of the signal converter 151 when the analog input signal AIN rises from the no-signal input state (0 V). The respective waveforms of the pulse signals SC and SD and the signals P and M which are output signals at that time are shown. In FIG. 5, the waveform indicated by the dotted line indicates the waveform when no signal is input.

  In this case, as indicated by a solid line in FIG. 5, the duty of the pulse signal SC decreases and the duty of the pulse signals SD and Sd increases compared to when no signal is input. As a result, the first input condition is not satisfied, and the signal P is fixed at a low level. On the other hand, the period during which the above-described second input condition is satisfied is increased compared to when no signal is input, so that the signal M includes a pulse whose width is modulated. This signal state corresponds to the state in which the cone paper of the speaker SP is driven forward. Therefore, if this signal state continues, that is, if the state where the signal P is maintained at a low level, it can be considered that a positive polarity DC output is supplied from the class D amplifier to the speaker SP.

(2-1-3) When the analog input signal drops from the no-signal input state (0 V) FIG. 6 shows the input signal of the signal converter 151 when the analog input signal AIN drops from the no-signal input state (0 V). The respective waveforms of the pulse signals SC and SD and the signals P and M which are output signals at that time are shown. In FIG. 6, the waveform indicated by the dotted line indicates the waveform when no signal is input.

  In this case, as indicated by a solid line in FIG. 6, the duty of the pulse signal SC increases and the duty of the pulse signals SD and Sd decreases compared to when no signal is input. As a result, the period during which the first input condition described above is satisfied increases, so that the signal P includes a pulse whose width is modulated. On the other hand, since the second input condition is not satisfied, the signal M is fixed at a low level. This signal state corresponds to the state in which the cone paper of the speaker SP is driven backward. Therefore, if this signal state continues, that is, if the signal M is kept at a low level, it can be considered that a negative polarity DC output is supplied from the class D amplifier to the speaker SP. Therefore, in order to detect the DC output, it is important to measure the time during which the low level of the signals P and M continues.

(2-2) Operation of the timer unit 152 constituting the DC detector 150 Next, the operation of the timer unit 152 will be described.
Schematically, the time measuring unit 152 detects a DC output by detecting that either the signal P or the signal M from the signal converting unit 151 has maintained a low level (predetermined level) for a predetermined time. .

  This will be described in detail with reference to FIG. If the signals P and M are at a high level in the initial state, the D-type flip-flops 152A to 152D that input the signals P and M to the asynchronous reset terminal are set to a reset state, and the output signal of each D-type flip-flop is set to a low level. The OR gate 152E outputs a low level as the signal D.

  From this initial state, at time t1, for example, when the signal P transitions to a low level (predetermined level) indicating reset release, a first shift register including D-type flip-flops 152A and 152B that inputs this to the asynchronous reset terminal Starts data capture and data transfer operations in synchronization with the clock signal CLK.

  At time t2, the D-type flip-flop 152A takes in the power supply level (high level) at the rising edge of the first clock signal CLK after the signal P becomes low level, and outputs a high level signal. The D-type flip-flop 152B takes in the high-level signal output from the D-type flip-flop 152A at the rising edge of the second clock signal CLK at the next time t3, and inputs the high-level signal to the OR gate 152E. Output to. The OR gate 152E outputs a high level as the signal D in response to the high level signal input from the D-type flip-flop 152B.

Similarly, for the signal M, when the signal M becomes low level, the second shift register including the D-type flip-flops 152C and 152D that inputs the signal M to the asynchronous reset terminal synchronizes with the predetermined clock signal CLK. Start capture and transfer operations. Then, after the signal M becomes low level, the OR gate 152E outputs a high level as the signal D at the rising edge of the second clock signal CLK.
In this way, after either of the signals P and M becomes low level and a time corresponding to one clock of the clock signal CLK has elapsed, a high level is output as the signal D from the OR gate 152E, and the DC output from this signal D The detection is grasped.

In this embodiment, since the frequency of the clock signal CLK is 40 Hz, the time between the first rising edge and the second rising edge of the clock signal CLK is 25 ms. Therefore, in this case, at the time when the signal D output from the time measuring unit 152 transits to the high level, 25 ms has elapsed since the signal P or the signal M transited to the low level. It is understood that the signal state shown in FIG. 5 or FIG. 6 is maintained for 25 ms or more, and the DC output is detected.
Therefore, the user of the class D amplifier can grasp the DC output from the signal D, and can appropriately take measures to prevent the speaker from being damaged by the DC output.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS.
FIG. 8 shows the configuration of the class D amplifier according to this embodiment. The class D amplifier according to this embodiment shown in the figure outputs a signal of a predetermined level from one of the two output terminals according to the signal level of the analog input signal, and obtains a pulse width modulation of the analog input signal from the other. This is a so-called filterless class D amplifier that outputs a pulse signal, and includes a timer 1520 for detecting that the predetermined level is maintained for a predetermined time.

  In other words, the class D amplifier according to the present embodiment further includes a signal conversion circuit 1510 in addition to the configuration of the class D amplifier according to the first embodiment shown in FIG. And a timer 1520 instead of the DC detector 150. Here, the signal conversion circuit 1510 is the same as the configuration in which the inverters 151D and 151J are omitted from the signal conversion unit 151 according to the first embodiment shown in FIG. 2, and the time measurement unit 1520 is the same as that shown in FIG. It is the same as the timing unit 152 according to the first embodiment shown in FIG.

The amplification operation of the class D amplifier is roughly equivalent to the pulse signal P, M converted to the output pulse signal OUTP, OUTM in the class D amplifier of the first embodiment described above.
This will be specifically described. In the no-signal input state, as shown in FIG. The relationship between the triangular wave signal T, the positive phase signal SA, and the negative phase signal SB is set so that each duty of OUTM is 50%.

  In this no-signal input state, as described above, as the output pulse signals OUTP and OUTM, a pulse having a short pulse width (for example, a duty of 10 percent) corresponding to the delay time tD of the delay unit 151E of the signal conversion circuit 1510 is a triangular wave. It is intermittently output at the period of the signal T. Therefore, since the period during which the output pulse signal is at the high level when no signal is input is extremely short, the power loss when no signal is input can be greatly reduced compared to the conventional one, with a simple configuration. Since the output pulse signals OUTP and OUTM always have a carrier frequency component, the analog input signal is caused by the appearance / disappearance of the carrier frequency component when transitioning between the no-signal input state and other states. Generation of noise can be prevented.

  Subsequently, in a state where the signal level AIN (+) of the analog input signal is increased and the signal level AIN (−) of the analog input signal having the opposite polarity is decreased, the signal is output from the integrating circuit 110 as shown in FIG. The signal level of the positive phase signal SA decreases and the signal level of the negative phase signal SB increases, and the signal level of the negative phase signal SB exceeds the signal level of the positive phase signal SA. In FIG. 10, the delay time of the delay unit 151E is ignored.

  As a result, the duty of the pulse signal SC output from the pulse width modulation circuit 120 decreases and the duty of the pulse signal SD increases. Accordingly, since the first input condition described above is not satisfied, the output pulse signal OUTP is fixed at a low level. The pulse width of the output pulse signal OUTM is a pulse width modulated according to the signal level of the analog input signal AIN.

  Subsequently, in a state where the signal level AIN (+) of the analog input signal is decreased and the signal level AIN (−) of the analog input signal having the opposite polarity is increased, as shown in FIG. As the signal level of the positive phase signal SA increases, the signal level of the negative phase signal SB decreases, and the signal level of the positive phase signal SA exceeds the signal level of the negative phase signal SB. In FIG. 11, the delay time of the delay unit 151E is ignored.

  As a result, the duty of the pulse signal SC increases and the duty of the pulse signal SD decreases. Therefore, since the second input condition described above is not satisfied, the output pulse signal OUTM is fixed at a low level. The pulse width of the output pulse signal OUTP is a pulse width modulated according to the signal level of the analog input signal AIN.

  As described above, in a normal amplification operation, one of the output pulse signals OUTP and OUTM is fixed at a low level according to an analog input signal, and the other includes a pulse width-modulated pulse. When such output pulse signals OUTP and OUTM are supplied to the speaker SP, a differential voltage is generated between the input terminals of the speaker, and the speaker is driven.

Next, the DC detection operation by the timer unit 1520 will be described.
The operation of the timer unit 1520 is the same as the operation of the timer unit 152 of the DC detector 150 according to the first embodiment described above, and the output pulse signals OUTP and OUTM corresponding to the signals P and M of the first embodiment are the same. The DC output is detected by timing the low level duration. That is, the timer unit 1520 detects the DC output by detecting that the low level (predetermined level) of the output pulse signals OUTP and OUTM is maintained for a predetermined time.

  Specifically, the shift register including the D-type flip-flops 152A to 152D shown in FIG. 2 constituting the DC detector 1520 has a low level (predetermined level) in which the output pulse signals OUTP and OUTM indicate reset release. Then, the operation starts based on the predetermined clock signal CLK, and the logical sum gate 152E becomes the signal D at the second rising edge of the clock signal CLK after either of the output pulse signals OUTP and OUTM becomes low level. Output high level. Therefore, the DC output can be detected as in the first embodiment.

  The class D amplifier according to the present embodiment is a so-called filterless type that can drive the speaker SP without using a low-pass filter connected to the output terminals T21 and T22 of the class D amplifier according to the first embodiment. Can function as a type of amplifier. Further, according to the present embodiment, it is possible to detect the DC output in this type of amplifier only by adding a very simple configuration (timer 1520).

  As mentioned above, although embodiment of this invention was described, this invention is not limited to the above-mentioned embodiment, A deformation | transformation is possible in the range which does not deviate from the summary of this invention. For example, in the above-described embodiment, the frequency of the clock signal CLK is 40 Hz, but is not limited to this. In the above-described embodiment, the signal conversion unit 151 includes the delay unit 151E. However, the delay unit 151 may be omitted if it is not necessary to leave a carrier frequency component when no signal is input. Moreover, the logic level of each signal is an example and is not limited to the above example. For example, the signals P and M of the first embodiment are set to a low level in accordance with the input level of the analog input signal, but this is set to a high level, and the time during which the high level is maintained is elapsed. A DC output may be detected.

1 is a circuit diagram showing a configuration of a class D amplifier according to a first embodiment of the present invention. It is a circuit diagram which shows the structure of the DC detection part with which the class D amplifier which concerns on 1st Embodiment of this invention was provided. It is a wave form diagram for demonstrating the amplification operation | movement of the class D amplifier which concerns on 1st Embodiment of this invention. It is a wave form diagram for demonstrating operation | movement (at the time of no signal input) of the signal conversion part of the class D amplifier which concerns on 1st Embodiment of this invention. It is a wave form diagram for demonstrating operation | movement (at the time of an input signal level rise) of the signal conversion part of the class D amplifier which concerns on 1st Embodiment of this invention. It is a wave form diagram for demonstrating operation | movement (at the time of an input signal level fall) of the signal converter of the class D amplifier which concerns on 1st Embodiment of this invention. It is a wave form diagram for demonstrating operation | movement of the time measuring part of the class D amplifier which concerns on 1st Embodiment of this invention. It is a circuit diagram which shows the structure of the class D amplifier which concerns on 2nd Embodiment of this invention. It is a wave form chart for explaining operation (at the time of no signal input) of a class D amplifier concerning a 2nd embodiment of the present invention. It is a wave form diagram for explaining operation (at the time of an input signal level rise) of a class D amplifier concerning a 2nd embodiment of the present invention. It is a wave form chart for explaining operation (at the time of input signal level fall) of a class D amplifier concerning a 2nd embodiment of the present invention. It is a circuit diagram which shows the structural example of the class D amplifier which concerns on a prior art.

Explanation of symbols

  R11, R12; input resistors, R21, R22; feedback resistors, 110; integration circuit, 120; pulse width modulation circuit, 130; drive circuit, 140; triangular wave generation circuit, 150; DC detection unit, 151; ; Timer unit 1300; Drive circuit 1510; Signal conversion circuit 1520; Timer unit.

Claims (6)

A class D amplifier configured to generate a first pulse signal and a second pulse signal whose pulses are modulated in a pulse-width manner in accordance with a signal level of the analog input signal, and the duty changes complementarily.
The first and second pulse signals are converted into first and second signals according to the polarity of the signal level of the analog input signal, and one of the first and second signals is predetermined during the conversion. A signal conversion unit that sets the level of the first and second signals to the predetermined level as a level signal and the other as a pulse signal subjected to pulse width modulation,
A class D amplifier comprising: a timer for detecting that one of the first and second signals has maintained the predetermined level for a predetermined time. The signal converter is
A first logic circuit portion and a second logic circuit portion;
The polarity of the signal level of the analog input signal is one of positive or negative polarity, the first pulse signal is a level complementary to the predetermined level, and the second pulse signal is the predetermined level. If the first input condition is satisfied is,
The second logic circuit unit outputs the second signal as the signal of the predetermined level,
The first logic circuit unit outputs the first signal as a pulse signal subjected to pulse width modulation ,
The polarity of the signal level of the analog input signal is the other polarity, positive or negative, the first pulse signal is the predetermined level, and the second pulse signal is a level complementary to the predetermined level. When the second input condition that is complementary to the first input condition is satisfied,
The first logic circuit unit outputs the first signal as the signal of the predetermined level,
2. The class D amplifier according to claim 1, wherein the second logic circuit unit outputs the second signal as a pulse signal subjected to pulse width modulation . The timekeeping section is
A first shift register that starts an operation based on a predetermined clock signal when the signal level of the first signal reaches the predetermined level;
A second shift register that starts operation based on a predetermined clock signal when the signal level of the second signal reaches a predetermined level;
3. The class D amplifier according to claim 1, further comprising a logical sum circuit that calculates a logical sum of the output signals of the first and second shift registers. The signal converter is
It said first and claims 1 to 3 according to any one of the class-D amplifier and further comprising a delay unit for delaying either a certain time of the second pulse signal. When the polarity of the signal level of the analog input signal is positive, a signal of a predetermined level is output from one of the first and second output terminals, and a pulse signal that has been subjected to pulse width modulation is output from the other. A class D amplifier configured to output a signal of a predetermined level from the other when the polarity of the level is negative and to output a pulse width modulated pulse signal from the one;
A class D amplifier comprising a timer for detecting that the predetermined level is maintained for a predetermined time. The timing unit includes a shift register that starts an operation based on a clock signal when a signal output from one of the first and second output terminals reaches the predetermined level. 5. A class D amplifier according to 5 .

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