JP4635727B2 - Method of manufacturing epitaxial wafer for nitride semiconductor light emitting diode, epitaxial wafer for nitride semiconductor light emitting diode, and nitride semiconductor light emitting diode - Google Patents

Description

  The present invention relates to a method for manufacturing a nitride semiconductor light emitting diode (LED) epitaxial wafer, and an epitaxial wafer for nitride semiconductor light emitting diode and a nitride semiconductor light emitting diode obtained by the method.

  Nitride semiconductor materials have a large band gap and are also directly transitional between band transitions, so that they are actively applied to short wavelength light emitting devices. Nitride semiconductor devices are epitaxially grown on an underlying substrate using vapor phase growth methods such as metal organic chemical vapor deposition (MOVPE), molecular beam vapor deposition (MBE), and hydride vapor phase epitaxy (HVPE). Is obtained.

FIG. 8 shows a structural example of a conventional nitride semiconductor light emitting diode.
This nitride semiconductor light-emitting diode is formed on a sapphire substrate 1 by a MOVPE method in order, a GaN low-temperature growth buffer layer 2 having a thickness of 22 nm, an undoped GaN layer 3 having a thickness of 2 μm, and an Si-doped n-type GaN layer having a thickness of 4 μm. 4 (electron concentration = 4 × 10 ¹⁸ cm ⁻³ ), 6 periods of InGaN / GaN multiple quantum well layer 5, 35 nm-thick Mg-doped p-type Al _0.15 Ga _0.85 N layer 6 (hole concentration = 5 × 10 ¹⁷ cm ⁻³ ) and a 200 nm-thick Mg-doped p-type GaN contact layer 7 (hole concentration = 1 × 10 ¹⁸ cm ⁻³ ) are formed, and n is formed by a reactive ion etching (RIE) apparatus. Etching to expose the p-type GaN layer 4 is performed to form an n-type electrode 10 thereon, while a transparent electrode 9 also serving as a p-type electrode is formed on the p-type GaN contact layer 7 Form and has a surface emission type the LED.

  As described above, a plurality of semiconductor layers including the light emitting layer of the InGaN / GaN multiple quantum well layer 5 are stacked on the sapphire substrate 1 by crystal growth, and light generated in the light emitting layer is emitted from a part of the device surface. The most important figure of merit for LEDs is efficiency. That is, in an LED, it is desired that a high light output can be obtained with as little current as possible, and that it should be highly efficient.

  In general, efficiency is determined by internal quantum efficiency and light extraction efficiency. Here, the internal quantum efficiency is the electro-optical conversion efficiency inside the device, and is the efficiency at which the injected current is converted into photons in the light emitting layer. The light extraction efficiency is the efficiency with which light generated in the light emitting layer is extracted outside the device. As for the internal quantum efficiency, a value of 50% or more has already been obtained in almost all of the LEDs that are generally marketed, and some examples have achieved an internal quantum efficiency of almost 100%. is there.

  On the other hand, it is known that the light extraction efficiency depends on the ratio of the refractive index inside and outside the light emitting element on the light extraction surface and the surface properties. That is, the refractive index of a compound semiconductor generally used for LEDs (n≈2.2 to 3.8, for example, 3.5 for GaAs), which is very large compared to the value of air (vacuum) n = 1. . Therefore, according to Snell's law, the light that can be emitted from the light emitting element to the outside is limited to a light incident angle from the inside of the light emitting element to the surface that is less than a critical angle (θc), and most of the generated light is reduced. It becomes a situation that cannot be taken out of the element. For example, in the case of GaAs, the critical angle is θc = 16.6 degrees, and only about 2% of the total light emission can be extracted outside the device.

  Thus, for example, it has been proposed to improve the efficiency by performing an etching process on the light extraction surface to moderately roughen the light extraction surface, thereby reducing the rate of incidence on the light extraction surface at an angle greater than the critical angle. . In fact, in GaAs-based and GaP-based LEDs, a moderately rough surface can be formed by wet etching at a relatively low temperature (<100 ° C.) for a short time, and some of them have already been put into practical use. However, the situation is different in nitride semiconductors that are materials for blue LEDs and ultraviolet LEDs. That is, a nitride semiconductor such as gallium nitride (GaN) is a chemically very stable substance, and in order to roughen its surface, for example, phosphoric acid, sulfuric acid, KOH or the like is heated to 200 ° C. or more, and the time is 1 hour. It is necessary to perform the etching for a long time as described above. Therefore, if such an etching process is added, the manufacturing process and manufacturing cost of LED will increase, and manufacturing efficiency will fall.

On the other hand, there is a method disclosed in Patent Document 1 as a method of performing uneven processing on the surface of a p-type GaN layer crystal-grown on a substrate.
In this method, first, a resist is applied to the surface of the p-type GaN layer, patterned by a PEP (photo-engraving process) method to form a plurality of parallel stripe-shaped resist patterns, and then subjected to heat treatment to form a stripe shape. By softening the resist to deform into a “kamaboko shape” having a semicircular cross section, and further etching from above the resist pattern by a method such as RlE (reactive ion etching) or ion milling (ion milling), In this method, the resist pattern is sequentially etched, and the underlying p-type GaN layer is sequentially etched to form irregularities similar to the cross-sectional shape of the resist pattern on the surface of the p-type GaN layer.
JP 2000-196152 A

  However, even in the method of forming irregularities using such a resist pattern, there still remains a problem that the manufacturing process and the manufacturing cost increase.

Accordingly, an object of the present invention is to provide a nitride semiconductor having a moderately rough surface with high light extraction efficiency without causing an increase in manufacturing process and manufacturing cost as in a method using long-time wet etching or a resist pattern. An object of the present invention is to provide a method for manufacturing an epitaxial wafer for a light emitting diode.
Another object of the present invention is to provide an epitaxial wafer and a nitride semiconductor for a nitride semiconductor light-emitting diode having a moderately rough surface with high light extraction efficiency by the above-described method that does not increase the manufacturing process and manufacturing cost. It is to provide a light emitting diode.

  As a result of intensive studies to solve the above-mentioned problems, the present inventor has moderately roughened by appropriately controlling the epitaxial growth conditions of the nitride semiconductor crystal when manufacturing an epitaxial wafer for nitride semiconductor light-emitting diodes. The inventors have obtained the knowledge that an epitaxial wafer for a nitride semiconductor light-emitting diode having a rough surface can be produced, and have completed the present invention based on this knowledge.

That is, the method for manufacturing an epitaxial wafer for a nitride semiconductor light emitting diode according to the present invention includes a step of growing a low-temperature buffer layer on a C-plane sapphire substrate, an undoped nitride semiconductor layer on the buffer layer, and an n-type impurity. Epitaxially growing a nitride semiconductor layer including the nitride semiconductor layer at a temperature of 1075 ° C., epitaxially growing a multiple quantum well layer on the nitride semiconductor layer including the n-type impurity at a temperature of 750 ° C., and on the multiple quantum well layer In addition, a nitride semiconductor layer containing a p-type impurity is epitaxially grown at a temperature of 1075 ° C. and a molar ratio of the supply amount of the group V raw material and the group III raw material being epitaxially grown to 8000, and contains the p-type impurity. On the nitride semiconductor layer, a temperature of 1075 ° C. and a molar ratio of the supply amount of the Group V raw material and the Group III raw material is 200 or more And a step of epitaxially growing a contact layer containing p-type impurities.

The undoped nitride semiconductor layer is epitaxially grown with a molar ratio of the supply amount of the group V source and the group III source being 2000, and the nitride semiconductor layer containing the n-type impurity is supplied with the group V source and the group III source. It may be epitaxially grown with a molar ratio of the amount of 800.

A p-type impurity delta-doped layer may be further formed between the p-type impurity-containing nitride semiconductor layer and the p-type impurity-containing contact layer or in the p-type impurity-containing contact layer. An n-type impurity delta-doped layer may be further formed between the undoped nitride semiconductor layer and the n-type impurity-containing nitride semiconductor layer or in the n-type impurity-containing nitride semiconductor layer .

  The p-type impurity may be magnesium, zinc, or carbon, and the n-type impurity may be silicon, oxygen, or selenium.

The method may further comprise etching the surface of the contact layer containing the p-type impurity . The etching can be wet etching using an acid solution or an alkali solution, or electrochemical etching using an acid solution or an alkali solution. The acid solution or the alkali solution preferably contains at least one of H ₂ SO ₄ , H ₃ PO ₄ , HCl, KOH, and NaOH.

An epitaxial wafer for a nitride semiconductor light-emitting diode according to the present invention includes a C-plane sapphire substrate, a low-temperature buffer layer provided on the C-plane sapphire substrate, an undoped nitride semiconductor layer provided on the buffer layer, A nitride semiconductor layer including an n-type impurity provided on the undoped nitride semiconductor layer, a multiple quantum well layer provided on the nitride semiconductor layer including the n-type impurity, and on the multiple quantum well layer A nitride semiconductor layer including a p-type impurity and a nitride semiconductor layer including the p-type impurity, the surface including a concavo-convex surface having a step of 50 nm , and a flat portion on the concavo-convex surface The area ratio is 20% , and a contact layer containing a p-type impurity is provided.

A p-type impurity delta doped layer may be further provided between the nitride semiconductor layer containing the p-type impurity and the contact layer containing the p-type impurity, or in the contact layer containing the p-type impurity .

An n-type impurity delta-doped layer may be further formed between the undoped nitride semiconductor layer and the n-type impurity-containing nitride semiconductor layer or in the n-type impurity-containing nitride semiconductor layer .

The nitride semiconductor light-emitting diode according to the present invention includes a C-plane sapphire substrate, a low-temperature buffer layer provided on the C-plane sapphire substrate, an undoped nitride semiconductor layer provided on the buffer layer, and the undoped nitride semiconductor light-emitting diode . A nitride semiconductor layer including an n-type impurity provided on the nitride semiconductor layer, a multiple quantum well layer provided on the nitride semiconductor layer including the n-type impurity, and provided on the multiple quantum well layer; A nitride semiconductor layer including a p-type impurity and a nitride semiconductor layer including the p-type impurity, the surface includes a concavo-convex surface having a step difference of 50 nm , and a ratio of a flat portion in the concavo-convex surface is A contact layer having an area ratio of 20% and containing a p-type impurity; and a transparent electrode made of a metal or an oxide provided on the contact layer containing the p-type impurity ;
Is provided.

  The transparent electrode may include at least one of Ni, Pd, Au, ITO, ZnO, and Ag.

The nitride semiconductor light-emitting diode according to the present invention includes a C-plane sapphire substrate, a low-temperature buffer layer provided on the C-plane sapphire substrate, an undoped nitride semiconductor layer provided on the buffer layer, and the undoped nitride semiconductor light-emitting diode . A nitride semiconductor layer including an n-type impurity provided on the nitride semiconductor layer, a multiple quantum well layer provided on the nitride semiconductor layer including the n-type impurity, and provided on the multiple quantum well layer; A nitride semiconductor layer including a p-type impurity and a nitride semiconductor layer including the p-type impurity, the surface includes a concavo-convex surface having a step difference of 50 nm , and a ratio of a flat portion in the concavo-convex surface is It is 20% in the area ratio, comprises a contact layer including a p-type impurity, and a metal collector electrode provided on the contact layer including the p-type impurity.

  The nitride semiconductor is preferably InxAlyGazN (x ≧ 0, y ≧ 0, z ≧ 0, x + y + z = 1).

  According to the manufacturing method of the present invention, it is possible to provide a nitride semiconductor light emitting diode epitaxial wafer and a nitride semiconductor light emitting diode having a moderately rough surface by a normal epitaxial growth process. For this reason, the manufacturing cost and the manufacturing process are not increased unlike the conventional method using wet etching and the method using photoresist.

  In addition, according to the epitaxial wafer for nitride semiconductor light emitting diode and the nitride semiconductor light emitting diode of the present invention, by appropriately roughening the light extraction surface, the ratio of incidence on the light extraction surface at an angle greater than the critical angle can be reduced. Efficiency can be improved.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a cross-sectional view showing a structural example of a nitride semiconductor light emitting diode according to an embodiment of the present invention.
This nitride semiconductor light-emitting diode is different from the conventional nitride semiconductor light-emitting diode shown in FIG. 8 in that an uneven surface 8 having a flat portion 8a and a hole portion 8b is formed on the surface of the p-type GaN contact layer 7. ing.

  The level difference between the flat portion 8a and the hole portion 8b on the uneven surface 8 is 50 nm or more, preferably 200 nm or more. Further, in the surface light extraction type LED, it is preferable that the ratio of the flat portion 8a in the uneven surface 8 is 20% or more in terms of area ratio. If the ratio of the flat portion 8a is less than 20%, the region of the hole 8b is excessively widened and the flat portion 8a is reduced. This is because only the part is energized.

The uneven surface 8 can be formed by the following method.
(1) At the time of growth of the p-type GaN contact layer 7, as a growth condition, the molar ratio of the source gas ammonia and trimethylgallium (TMG) is set to 1000 or less, preferably 200 to 1000.
(2) During the growth of the p-type GaN contact layer 7, the growth temperature is set to 700 to 1000 ° C. as a growth condition.
(3) When the p-type GaN contact layer 7 is grown, the concentration of the p-type impurity in the crystal is set to 1 × 10 ¹⁹ / cm ³ or more as a growth condition.
(4) A p-type impurity delta doped layer is inserted in the p-type GaN contact layer 7 or adjacent to the GaN contact layer 7.
(5) During the growth of the n-type GaN layer 4, as a growth condition, the molar ratio of the source gas ammonia to trimethylgallium (TMG) is set to 1000 or less, preferably 200 to 1000.
(6) During the growth of the n-type GaN layer 4, the growth temperature is set to 700 to 1000 ° C. as a growth condition.
(7) When the n-type GaN layer 4 is grown, the concentration of the n-type impurity in the crystal is set to 5 × 10 ¹⁸ / cm ³ or more as a growth condition.
(8) An n-type impurity delta doped layer is inserted inside or adjacent to the n-type GaN layer 4.
(9) During the growth of the undoped GaN layer 3 and the n-type GaN layer 4, as a growth condition, the molar ratio of the source gas ammonia to trimethylgallium (TMG) is set to 1000 or less, preferably 200 to 1000.
(10) A plurality of methods (1) to (9) are combined.
(11) Etching is further performed on the methods (1) to (10).

  The crystal growth described above is preferably performed in a vapor phase growth apparatus, for example, in a metal organic vapor phase growth (MOVPE) apparatus or a hydride vapor phase growth (HVPE) apparatus.

  According to the above-described method, it is possible to provide a nitride semiconductor light emitting diode having a moderately rough surface using a normal epitaxial growth process. In addition, the nitride semiconductor light-emitting diode having the uneven surface 8 obtained by the above-described method can improve the efficiency by reducing the rate of incidence on the light extraction surface at an angle greater than the critical angle.

A nitride semiconductor light emitting diode having a structure as shown in FIG. 1 was manufactured by the following method.
First, an LED structure that emits blue light was grown on a 2-inch diameter C-plane sapphire substrate 1 by the MOVPE method. Specifically, after introducing the sapphire substrate 1 into the MOVPE apparatus, the sapphire substrate is heated at 1135 ° C. for 10 minutes in a hydrogen / nitrogen mixed gas atmosphere of 760 Torr (total flow rate = 150 slm, nitrogen / hydrogen = 2). One surface oxide and the like were removed (thermal cleaning). Thereafter, the substrate temperature is lowered to 515 ° C., the carrier gas flow rate is 140 slm, the volume ratio of nitrogen / hydrogen in the carrier gas is 1.5, and the growth apparatus for ammonia (NH ₃ ) gas, which is a nitrogen raw material, at a flow rate of 10 slm Introduced. Further, trimethylgallium (TMG) was introduced into the growth apparatus as a Ga raw material, and the GaN low-temperature buffer layer 2 was grown on the sapphire substrate 1 at a growth rate of 1.6 μm / hour to 22 nm.

Thereafter, the carrier gas flow rate is 80 slm, the volume ratio of nitrogen / hydrogen in the carrier gas is 1, the ammonia gas flow rate is 20 slm, the substrate temperature is 1075 ° C., and the undoped GaN layer 3 is grown by 2 μm at a growth rate of 4 μm / hour. It was. In this case, the molar flow rate ratio between the Group V raw material (ammonia) and TMG was 2000. Further, an Si-doped n-type GaN layer 4 having an electron concentration of 4 × 10 ¹⁸ cm ⁻³ was grown thereon by 4 μm at an ammonia / TMG molar ratio = 2000. Thereafter, the substrate temperature was lowered to 750 ° C., and six-cycle InGaN / GaN multiple quantum well layers 5 were formed.

Next, the substrate temperature is again 1075 ° C., the ammonia / TMG molar ratio = 8000, and the Mg-doped p-type Al _0.15 Ga _0.85 N layer 6 (hole concentration = 5 × 10 ¹⁷ cm ⁻³ ) is 35 nm. After the growth, only the ammonia / TMG molar ratio was changed between 200 and 1000, and the Mg-doped p-type GaN contact layer 7 (hole concentration = 1 × 10 ¹⁸ cm ⁻³ ) was 200 nm by a growth process similar to the above. Grown up.

By setting the ammonia / TMG molar ratio during growth of the p-type GaN contact layer 7 to 1000 or less, an uneven surface 8 having a flat portion 8a and a hole 8b was formed on the surface of the p-type GaN contact layer 7. The size of the hole 8b generated on the surface increased with a decrease in the ammonia / TMG molar ratio.
FIG. 2 shows an electron micrograph of the surface of the p-type GaN contact layer 7 when the ammonia / TMG molar ratio is set to a predetermined value. From this, it can be seen that the step on the surface is formed to be 50 nm or more.

After growing the p-type GaN contact layer 7, the wafer was heated to 600 ° C. in oxygen and heat-treated for 20 minutes to reduce the resistance of the p-type GaN contact layer 7.
The blue LED epitaxial wafer thus obtained is etched to expose the n-type GaN layer 4 by a reactive ion etching (RIE) apparatus, and the n-type electrode 10 and the SiO ₂ film are exposed. A transparent electrode 9 (Ni 2 nm / Au 6 nm) that also serves as a p-type electrode was formed to produce a surface light extraction type LED structure shown in FIG. 1, and the light output of the LED was measured.

  As a comparative example, a surface light extraction type LED structure was manufactured under the same conditions as described above except that only the ammonia / TMG molar ratio during growth of the p-type GaN contact layer 7 was grown under a condition exceeding 1000. The light output was measured. In this case, the surface of the p-type GaN contact layer 7 was flat as in the conventional case.

FIG. 3 shows the relationship between the ammonia / TMG molar ratio during the growth of the p-type GaN contact layer 7 and the light output during 20 mA energization.
The light output increased with increasing ammonia / TMG molar ratio. When the ammonia / TMG molar ratio was 800, the light output reached a maximum of 8.2 mW. In this case, the depth of the hole of the p-type GaN contact layer 7 in FIG. 2 (corresponding to the hole 8b schematically shown in FIG. 1) is 200 nm, which is the same as the thickness of the p-type GaN contact layer 7. .
When the ammonia / TMG molar ratio is 500 or less, the light output is reduced when the molar ratio is small because the region of the hole 8b is too wide and the flat portion 8a is reduced, so that the transparent electrode formed thereon It is considered that 9 was disconnected and only a part of the light emitting region of the LED was energized.

  On the other hand, the light output of the LED in the comparative example when energized with 20 mA was 6.2 mW. In FIG. 3, among the LEDs having a light output higher than 6.2 mW, the lowest V / III ratio during the growth of p-type GaN is when the ammonia / TMG molar ratio is 500. In this case, the ratio of the flat portion 8a and the hole 8b on the surface of the p-type GaN contact layer 7 of the LED was 2: 8. This indicates that when the area ratio of the flat portion 8a on the LED surface is 20% or more, the light output can be improved by applying to the surface light extraction type LED.

  Using the same method as in Example 1, a backside light extraction type LED was manufactured using an LED epitaxial wafer grown by changing the ammonia / TMG molar ratio during growth of the p-type GaN contact layer 7.

FIG. 4 shows an element structure of a backside light extraction type LED.
The basic element structure of the backside light extraction type LED is the same as that shown in FIG. 1 except that a p-type electrode 12 made of an Ag electrode (300 nm thick) having a high reflectance is formed on the surface of the p-type GaN contact layer 7. Is different from the surface light extraction type LED shown in FIG. After forming the chip by the same method as in Example 1, mounting was performed with the back side of the LED facing up, an LED lamp was formed, and the light output was measured.

FIG. 5 shows the relationship between the ammonia / TMG molar ratio during growth of the p-type GaN contact layer 7 and the light output of the backside light extraction type LED.
Unlike the results of the surface light extraction type LED, in this case, the lower the ammonia / TMG molar ratio, the higher the light output. When the ammonia / TMG molar ratio was 100, the highest light output of 38 mW was obtained.
This is because, in the case of the back light extraction type, the p-type electrode 12 is formed thick, so that the electrode disconnection does not occur as in Example 1, and the ammonia / TMG molar ratio is low and the surface hole 8b is large. It is considered that the light extraction efficiency is improved.

In the growth of the LED of Example 1, an LED epitaxial wafer was grown with only the n-type GaN layer 4 having an ammonia / TMG molar ratio = 800.
Also in this case, the surface of the epitaxial wafer is rough as in the case of Example 1, and the light output of the surface light extraction type LED manufactured using this epitaxial wafer is 7.5 mW when energized with 20 mA. It became larger than the light output.

In the growth of the LED of Example 1, an epitaxial wafer for LED was grown with the carrier concentration of the n-type GaN layer 4 set to 5 × 10 ^{18 to} 3 × 10 ¹⁹ / cm ³ .
Also in this case, the surface of the epitaxial wafer is rough as in Example 1, and the light output of the surface light extraction type LED manufactured using this epitaxial wafer is 7 to 8.2 mW when energized with 20 mA, which is a comparative LED. It became larger than the light output.

  As shown in FIG. 6, in the growth of the LED of Example 1, a Si delta doped layer 14 was formed at the interface between the undoped GaN layer 3 and the 4 μm thick n-type GaN layer 4 to grow an LED epitaxial wafer. In this case, as in Example 1, the surface of the epitaxial wafer was rough, and the light output of the surface light extraction type LED fabricated using this epitaxial wafer was 7.3 mW when energized with 20 mA, which is based on the light output of the LED of the comparative example. Also became larger.

  Further, when an epitaxial wafer for LED in which the Si delta doped layer 14 is formed in the same manner at a position 2 μm from the interface of the undoped GaN layer 3 in the n-type GaN layer 4 is grown, the surface of the epitaxial wafer is similarly roughened. The light output of the surface light extraction type LED manufactured using this epitaxial wafer was 6.8 mW when energized with 20 mA, which was larger than the light output of the LED of the comparative example.

In the growth of the LED of Example 1, an epitaxial wafer for LED was grown by setting the Mg concentration of the p-type GaN layer to 1 × 10 ^{19 to} 3 × 10 ²⁰ / cm ³ .
Also in this case, the surface of the epitaxial wafer is rough as in Example 1, and the light output of the surface light extraction type LED manufactured using this epitaxial wafer is 7.4 to 8.2 mW when energized with 20 mA, which is a comparative example. It became larger than the light output of the LED.

  As shown in FIG. 7, in the growth of the LED of Example 1, an Mg delta doped layer 16 was formed at the interface between the p-type AlGaN layer 6 and the p-type GaN contact layer 7 to grow an LED epitaxial wafer. In this case, the surface of the epitaxial wafer is rough as in Example 1, and the light output of the surface light extraction type LED manufactured using this epitaxial wafer is 7 mW when energized with 20 mA, which is larger than the light output of the LED of the comparative example. became.

  Further, when an epitaxial wafer for LED in which the Mg delta doped layer 16 is similarly formed at a position 100 nm from the p-type AlGaN layer 6 in the p-type GaN contact layer 7 is grown, the surface of the epitaxial wafer is similarly roughened. The light output of the surface light extraction type LED fabricated using this epitaxial wafer was 8 mW when energized with 20 mA, which was larger than the light output of the LED of the comparative example.

  In the growth of the LED of Example 1, an epitaxial wafer for LED was grown at a growth temperature of 600 to 1075 ° C. during the growth of the p-type GaN contact layer 7. When the growth temperature is 1000 ° C. or lower, the surface of the epitaxial wafer becomes rough as in Example 1, and the surface light extraction type LED manufactured using these epitaxial wafers in the growth temperature range of 700 to 1000 ° C. The light output was larger than that of a normal LED. However, when the growth temperature was less than 700 ° C., the crystallinity was significantly lowered, and the light output was smaller than the light output of the LED of the comparative example.

In the growth of the LED of Example 1, an epitaxial wafer for LED was grown at a growth temperature during growth of the p-type GaN contact layer 7 of 950 ° C. and an ammonia / TMG molar ratio of 800.
The light output of the surface light extraction type LED fabricated using this epitaxial wafer was 9.2 mW when energized with 20 mA, which was larger than the light output of the LED of the comparative example.

In the growth of the LED of Example 1, an epitaxial wafer for LED was grown at a growth temperature of 800 ° C. during growth of the p-type GaN contact layer 7 and an Mg concentration of 1 × 10 ²⁰ / cm ³ in the p-type GaN layer.
The light output of the surface light extraction type LED manufactured using this epitaxial wafer was 10 mW when energized with 20 mA, which was larger than the light output of the LED of the comparative example.

The same experiment as in Example 4 was performed using n-type impurities as oxygen or selenium.
Also in this case, the surface of the epitaxial wafer is rough as in Example 4, and the light output of the surface light extraction type LED manufactured using this epitaxial wafer is 8 to 8.5 mW when energized with 20 mA, which is a comparative LED. It became larger than the light output.

The same experiment as in Example 6 was performed using zinc or carbon as the p-type impurity.
Also in this case, the surface of the epitaxial wafer is rough as in Example 6, and the light output of the surface light extraction type LED manufactured using this epitaxial wafer is 8.2 to 9 mW when energized with 20 mA, which is a comparative LED. It became larger than the light output.

After growing the epitaxial wafer for LED described in Example 9, (1) in H ₂ SO ₄ at 150 ° C., (2) in H ₃ PO ₄ at 180 ° C., and (3) HCl and H ₃ PO _{4 at} 180 ° C. (5) Etching for 20 minutes in an ethylene glycol solution of KOH at 200 ° C., (5) in an ethylene glycol solution of NaOH at 250 ° C. Thereafter, a surface light extraction type LED was manufactured using this epitaxial wafer.
The light output of the LED was 10.1 to 12.2 mW when energized with 20 mA, which was larger than that in Example 9. This is because the hole on the wafer surface formed by the growth is enlarged by etching, and the light extraction efficiency is increased.

After growing the epitaxial wafer for LED described in Example 9, (1) in H ₂ SO ₄ , (2) in H ₃ PO ₄ , (3) in a mixed solution of HCl and H ₃ PO ₄ , (4) KOH Electrochemical etching was performed in an aqueous solution for 10 minutes in (5) NaOH aqueous solution or the like. Thereafter, a surface light extraction type LED was manufactured using this epitaxial wafer.
The light output of the LED was 11 to 13.2 mW when energized with 20 mA, which was larger than that in Example 9. This is also because the holes on the wafer surface formed by the growth were enlarged by etching and the light extraction efficiency increased as in the case of Example 13.

Experiments similar to those in Example 9 were performed using (1) SiC substrate, (2) Si substrate, (3) GaN substrate, (4) AlN substrate, (5) ZnO substrate, and (6) ZrB ₂ substrate. . In any case, the light output of the LED having a rough surface was larger than that of the LED of the comparative example.

  In Example 1, the same result as in Example 1 was obtained even in the sample in which the part of the p-type GaN contact layer 7 having a thickness of 200 nm was a laminated structure of undoped GaN layer 100 nm / p-type GaN 100 nm.

In Example 1, the same results as in Example 1 were obtained when the transparent electrode 9 was Pd 2 nm / Au 8 nm, ITO 300 nm, ZnO 200 nm, or Ag 5 nm.
From this, it became clear that the present invention is applicable regardless of the material of the transparent electrode.

1 is a cross-sectional view showing the structure of a nitride semiconductor light-emitting diode obtained by Example 1. FIG. 2 is an electron micrograph of the surface of a p-type GaN contact layer obtained in the manufacturing stage of Example 1. FIG. It is a graph which shows the relationship between the ammonia / TMG molar ratio at the time of p-type GaN contact layer growth, and the light output of surface light extraction type | mold LED. 6 is a cross-sectional view showing the structure of a nitride semiconductor light-emitting diode obtained in Example 2. FIG. It is a graph which shows the relationship between the ammonia / TMG molar ratio at the time of p-type GaN contact layer growth, and the optical output of a back light extraction type LED. 6 is a cross-sectional view showing the structure of a nitride semiconductor light-emitting diode obtained by Example 5. FIG. 7 is a cross-sectional view showing the structure of a nitride semiconductor light-emitting diode obtained by Example 7. FIG. It is sectional drawing which shows the structure of the nitride semiconductor light-emitting diode obtained by the method of a prior art example.

Explanation of symbols

1 Sapphire substrate 2 Low temperature growth buffer layer 3 Undoped GaN layer 4 n-type GaN layer 5 InGaN / GaN multiple quantum well layer 6 p-type AlGaN layer 7 p-type GaN contact layer 8 uneven surface 9 transparent electrode 10 n-type electrode 12 p-type electrode 14 Si delta doped layer 16 Mg delta doped layer

Claims (16)

Growing a low temperature buffer layer on the C-plane sapphire substrate;
Epitaxially growing an undoped nitride semiconductor layer and a nitride semiconductor layer containing an n-type impurity on the buffer layer at a temperature of 1075 ° C .;
Epitaxially growing a multiple quantum well layer on the nitride semiconductor layer containing the n-type impurity at a temperature of 750 ° C .;
A nitride semiconductor layer containing a p-type impurity is epitaxially grown on the multiple quantum well layer at a temperature of 1075 ° C. and a molar ratio of the supply amount of the Group V material and the Group III material during epitaxial growth is 8000, A contact layer containing a p-type impurity is epitaxially grown on a nitride semiconductor layer containing a p-type impurity at a temperature of 1075 ° C. and a molar ratio of the supply amount of the group V material and the group III material being 200 to 1000. And an epitaxial wafer manufacturing method for a nitride semiconductor light emitting diode. The undoped nitride semiconductor layer is epitaxially grown with a molar ratio of the supply amount of the Group V material and the Group III material being 2000,
2. The method for manufacturing an epitaxial wafer for a nitride semiconductor light-emitting diode according to claim 1, wherein the nitride semiconductor layer containing an n-type impurity is epitaxially grown with a molar ratio of a supply amount of a group V material and a group III material being 800. 3. The p-type impurity delta doped layer is further formed between the nitride semiconductor layer containing the p-type impurity and the contact layer containing the p-type impurity, or in the contact layer containing the p-type impurity. 2. A method for producing an epitaxial wafer for nitride semiconductor light-emitting diodes according to 1 . Between the nitride semiconductor layer including the n-type impurity and the nitride semiconductor layer of the undoped, or in claim 1, delta-doped layer of n-type impurity is further formed on the nitride semiconductor layer including the n-type impurity The manufacturing method of the epitaxial wafer for nitride semiconductor light-emitting diodes of description. The p-type impurity, magnesium, zinc, method of manufacturing the nitride semiconductor light emitting diode epitaxial wafer according to any one of 請 Motomeko 1-4 Ru der either carbon. The n-type impurity, silicon, oxygen, method of manufacturing the nitride semiconductor light emitting diode epitaxial wafer according to any one of 請 Motomeko 1-5 Ru der either selenium. The manufacturing method of the epitaxial wafer for nitride semiconductor light-emitting diodes of any one of Claims 1-6 further equipped with the process of etching the surface of the contact layer containing the said p-type impurity . The etching, an acid solution, or a nitride semiconductor light emitting diode epitaxial wafer manufacturing method according to the wet etching der Ru請 Motomeko 7 using an alkaline solution. The etching, an acid solution or an alkali solution electrochemical etching der Ru請 Motomeko 7 nitride semiconductor light emitting diode epitaxial wafer manufacturing method according to using. The acid solution or alkali _{solution, H 2 SO 4, H 3} PO 4, HCl, KOH, manufacture of the nitride semiconductor light emitting diode epitaxial wafer according to at least one of NaOH in including請 Motomeko 8 or 9 Method. A C-plane sapphire substrate;
A low-temperature buffer layer provided on the C-plane sapphire substrate;
An undoped nitride semiconductor layer provided on the buffer layer;
A nitride semiconductor layer provided on the undoped nitride semiconductor layer and including an n-type impurity;
A multiple quantum well layer provided on the nitride semiconductor layer containing the n-type impurity;
A nitride semiconductor layer provided on the multiple quantum well layer and containing a p-type impurity;
The p-type impurity is provided on the nitride semiconductor layer containing the p-type impurity, has a concavo-convex surface with a step of 50 nm on the surface , and the ratio of the flat portion on the concavo-convex surface is 20% in area ratio. Including contact layer and
The nitride semiconductor light emitting diode epitaxial wafer comprising a. The p-type impurity delta doped layer is further provided between the nitride semiconductor layer containing the p-type impurity and the contact layer containing the p-type impurity, or in the contact layer containing the p-type impurity. An epitaxial wafer for nitride semiconductor light-emitting diodes as described in 1 above. Between the nitride semiconductor layer including the n-type impurity and the nitride semiconductor layer of the undoped, or to claim 11, delta-doped layer of n-type impurity is further formed on the nitride semiconductor layer including the n-type impurity The epitaxial wafer for nitride semiconductor light-emitting diodes as described. A C-plane sapphire substrate;
A low-temperature buffer layer provided on the C-plane sapphire substrate;
An undoped nitride semiconductor layer provided on the buffer layer;
A nitride semiconductor layer provided on the undoped nitride semiconductor layer and including an n-type impurity;
A multiple quantum well layer provided on the nitride semiconductor layer containing the n-type impurity;
A nitride semiconductor layer provided on the multiple quantum well layer and containing a p-type impurity;
The p-type impurity is provided on the nitride semiconductor layer containing the p-type impurity, has a concavo-convex surface with a step of 50 nm on the surface , and the ratio of the flat portion on the concavo-convex surface is 20% in area ratio. A contact layer comprising:
A transparent electrode made of metal or oxide provided on the contact layer containing the p-type impurity ;
The front surface emission type nitride semiconductor light emitting diode comprising a. The transparent electrode, Ni, Pd, Au, ITO , ZnO, at least one of the described including請 Motomeko 14 nitride semiconductor light emitting diode of Ag. A C-plane sapphire substrate;
A low-temperature buffer layer provided on the C-plane sapphire substrate;
An undoped nitride semiconductor layer provided on the buffer layer;
A nitride semiconductor layer provided on the undoped nitride semiconductor layer and including an n-type impurity;
A multiple quantum well layer provided on the nitride semiconductor layer containing the n-type impurity;
A nitride semiconductor layer provided on the multiple quantum well layer and containing a p-type impurity;
The p-type impurity is provided on the nitride semiconductor layer containing the p-type impurity, has a concavo-convex surface with a step of 50 nm on the surface , and the ratio of the flat portion on the concavo-convex surface is 20% in area ratio. A contact layer comprising:
Backside emission type nitride semiconductor light emitting diode comprising a <br/> metal electrodes provided on the contact layer including the p-type impurity.

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