JP4632038B2 - Copper wiring board manufacturing method - Google Patents
Copper wiring board manufacturing method Download PDFInfo
- Publication number
- JP4632038B2 JP4632038B2 JP2005112157A JP2005112157A JP4632038B2 JP 4632038 B2 JP4632038 B2 JP 4632038B2 JP 2005112157 A JP2005112157 A JP 2005112157A JP 2005112157 A JP2005112157 A JP 2005112157A JP 4632038 B2 JP4632038 B2 JP 4632038B2
- Authority
- JP
- Japan
- Prior art keywords
- copper
- weight
- etching
- copper wiring
- etching solution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
- H05K3/16—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation by cathodic sputtering
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- ing And Chemical Polishing (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Description
本発明は、セミアディティブ法での銅配線基板製造におけるシード層のエッチング除去方法に関する。 The present invention relates to a method for removing a seed layer by etching in the production of a copper wiring board by a semi-additive method.
近年電子機器用配線基板の分野において、高密度実装化に伴い銅配線の細線化が急速に進み配線幅および配線間が著しく狭くなりつつある。銅配線の細線化に対応するため、高密度配線基板製造では、セミアディティブ法による銅配線形成が主流である。セミアディティブ法では、絶縁層上に金属薄膜層(シード層)を無電解メッキまたはスパッタリング法等の物理的な方法で設け、その上にフォトリソによりパターンレジストを形成しさらに電気銅メッキを施し、最後にレジストを剥離し不要となるシード層をエッチング除去して銅配線が形成される。本発明者らは、このセミアディティブ法でのシード層の銅エッチング液として、過酸化水素−硫酸にアゾール類を添加した系を提案している(特許文献1参照)。該エッチング液は、シード層が無電解銅メッキである場合は良好なエッチングが出来るが、シード層がスパッタリング法で形成された銅(スパッタ銅)の場合は完全にエッチング除去出来ない。スパッタ銅は、絶縁層上に微粒子の状態で緻密に物理的に形成されるため、無電解銅メッキよりもエッチング除去するのが困難である。そのため、完全にエッチング除去させるためオーバーエッチングすると銅配線幅が減少する。また、銅配線側面または表面に銅以外の金属皮膜を形成してシード層の銅をエッチングする方法も提案されているが、上述の薬液と同様にシード層がスパッタ銅の場合は完全にエッチング除去が出来ない(特許文献2、3参照)。セミアディティブ法でのシード層のニッケルエッチング液に関しては、過酸化物−硝酸−硫酸系が提案されているが、シード層がスパッタリング法で形成されたニッケル(スパッタニッケル)の場合はエッチング除去が完全に出来ない(特許文献4参照)。従って、セミアディティブ法での細線銅配線形成において、銅配線の配線幅減少を抑制して、シード層のスパッタ銅またはスパッタニッケルをエッチング除去する方法の実用化が求められている。
本発明は、セミアディティブ法での細線銅配線形成において、シード層のスパッタ銅またはスパッタニッケルをエッチング除去する際に、銅配線の配線幅の減少を抑制して、断線、短絡等の不具合の無い信頼性の高い基板の製造方法を提供することである。 The present invention suppresses a decrease in the wiring width of the copper wiring when etching and removing the sputtered copper or sputtered nickel in the seed layer in the formation of the thin-wire copper wiring by the semi-additive method, and there is no problem such as disconnection or short circuit. It is to provide a method for manufacturing a highly reliable substrate.
本発明者らは上記課題を解決するため鋭意検討を重ねた結果、セミアディティブ法での細線銅配線形成において、シード層のスパッタ銅またはスパッタニッケルをエッチング除去する際に、過酸化水素−リン酸のエッチング液で処理することで、銅配線の配線幅減少を抑制出来ることを見出し、本発明を完成させるに至った。 As a result of intensive studies to solve the above-mentioned problems, the inventors of the present invention have formed a hydrogen peroxide-phosphoric acid when etching away sputtered copper or sputtered nickel in the seed layer in forming a thin copper wiring by the semi-additive method. It has been found that the reduction of the wiring width of the copper wiring can be suppressed by treating with this etching solution, and the present invention has been completed.
すなわち、本発明は、セミアディティブ法における銅配線基板製造において、金属薄膜層(シード層)のエッチング液として、過酸化水素 0.1〜10重量%とリン酸 0.5〜50重量%を含有し、かつ過酸化水素/リン酸の重量比が 0.02〜0.2であるエッチング液を使用する銅配線基板製造方法である。 That is, the present invention contains 0.1 to 10% by weight of hydrogen peroxide and 0.5 to 50% by weight of phosphoric acid as an etching solution for a metal thin film layer (seed layer) in the production of a copper wiring board by a semi-additive method. And a copper wiring board manufacturing method using an etching solution having a weight ratio of hydrogen peroxide / phosphoric acid of 0.02 to 0.2.
本発明のエッチング方法により、セミアディティブ法での細線銅配線形成において、銅配線の配線幅減少を抑制して、シード層のスパッタ銅またはスパッタニッケルをエッチング除去することが可能となり、半導体製品、プリント配線基板等の電子部品の製造に有用である。 With the etching method of the present invention, it is possible to suppress the reduction of the wiring width of the copper wiring and to remove the sputtered copper or sputtered nickel of the seed layer in the semi-additive thin-film copper wiring formation. This is useful for manufacturing electronic components such as wiring boards.
本発明の銅配線基板製造方法のエッチング液に使用する過酸化水素濃度は、0.1〜10重量%であり、好ましくは0.5〜5重量%である。過酸化水素濃度が、0.1重量%未満では十分なエッチング速度が得られず、10重量%を超えると銅配線の配線幅減少が顕著になるため好ましくない。 The hydrogen peroxide concentration used in the etching solution of the copper wiring board manufacturing method of the present invention is 0.1 to 10% by weight, preferably 0.5 to 5% by weight. When the hydrogen peroxide concentration is less than 0.1% by weight, a sufficient etching rate cannot be obtained.
本発明の銅配線基板製造方法のエッチング液に使用するリン酸濃度は、0.5〜50重量%であり、好ましくは2.5〜25重量%である。リン酸濃度が、0.5重量%未満では十分なエッチング速度が得られず、50重量%を超えてもそれ以上の効果が得られないため経済上好ましくない。 The phosphoric acid concentration used in the etching solution of the copper wiring board manufacturing method of the present invention is 0.5 to 50% by weight, preferably 2.5 to 25% by weight. When the phosphoric acid concentration is less than 0.5% by weight, a sufficient etching rate cannot be obtained.
本発明で使用するエッチング液における過酸化水素とリン酸の重量比(過酸化水素/リン酸)は、0.02〜0.2である。過酸化水素とリン酸の重量比が、0.02未満ではシード層のエッチング除去性が十分ではなく、0.2を超えると銅配線の配線幅減少が顕著になるため好ましくない。 The weight ratio of hydrogen peroxide to phosphoric acid (hydrogen peroxide / phosphoric acid) in the etching solution used in the present invention is 0.02 to 0.2. If the weight ratio of hydrogen peroxide to phosphoric acid is less than 0.02, the seed layer etching removability is not sufficient, and if it exceeds 0.2, the reduction in the wiring width of the copper wiring becomes remarkable.
本発明で使用するエッチング液中に塩素イオンが微量でも混在すると、シード層のエッチング除去性を著しく阻害するので、本発明の濃度に調整する際は純水またはイオン交換水を用いて調整を行い、本発明で使用するエッチング液中の塩素イオン濃度を1ppm未満にすることが好ましい。 If even a small amount of chlorine ions is mixed in the etching solution used in the present invention, the etching removability of the seed layer is significantly inhibited. Therefore, when adjusting to the concentration of the present invention, adjustment is performed using pure water or ion-exchanged water. The chlorine ion concentration in the etching solution used in the present invention is preferably less than 1 ppm.
本発明におけるエッチングの対象となる金属は、スパッタリング法、真空蒸着法、イオンプレーティング法、化学蒸着法等の物理的な方法により形成された銅またはニッケルである。特に、スパッタリング法にて形成された銅またはニッケルに対して好適である。 The metal to be etched in the present invention is copper or nickel formed by a physical method such as sputtering, vacuum deposition, ion plating, or chemical vapor deposition. In particular, it is suitable for copper or nickel formed by sputtering.
本発明におけるエッチング液と対象物との接触方法は、特に制限はなく、浸漬処理、スプレー処理等で行うことができる。エッチング処理温度は、20〜60℃が好ましい。処理温度が60℃を越えると、過酸化水素の分解が促進されるため好ましくない。エッチング処理時間に関しては、対象物の表面状態や形状に合わせて最適な時間を選択するが、実用的には30秒〜120秒が好ましい。エッチング処理後エッチング液が対象物に付着したままで放置すると銅表面が酸化変色してムラになるので、エッチング処理後は速やかに水洗を行うことが好ましい。 The contact method between the etching solution and the object in the present invention is not particularly limited, and can be performed by immersion treatment, spray treatment, or the like. The etching treatment temperature is preferably 20 to 60 ° C. When the treatment temperature exceeds 60 ° C., decomposition of hydrogen peroxide is accelerated, which is not preferable. As for the etching processing time, an optimal time is selected in accordance with the surface state and shape of the object, but practically 30 seconds to 120 seconds are preferable. If the etching solution is left as it is attached to the object after the etching process, the copper surface is oxidized and discolored, so that it is preferable to immediately wash with water after the etching process.
本発明で使用されるエッチング液の管理は、金属の溶解に伴い各成分濃度が低下するので、各成分濃度を分析により算出し不足分を補充する。また、金属溶解量が増加するにつれて、エッチング速度が低下するので、金属溶解量が15g/Lを超えた段階で液更新することが好ましい。 In the management of the etching solution used in the present invention, the concentration of each component decreases as the metal dissolves. Moreover, since the etching rate decreases as the amount of dissolved metal increases, it is preferable to renew the solution when the amount of dissolved metal exceeds 15 g / L.
以下に実施例及び比較例により、本発明を具体的に説明するが、本発明は以下の実施例に限定されるものではない。
実施例1
過酸化水素1重量%、リン酸10重量%を含有するエッチング液を調合した。次に、シリコンウェハ基材上に0.5μm厚みのスパッタ銅膜を形成して、その上にフォトリソによりパターンレジストを形成し、さらに電気銅メッキを施し、最後にレジストを剥離して、銅配線幅/配線スペースが15μm/10μmの試験基板を作成した。該基板を30℃のエッチング液にて浸漬処理して、配線スペース部分であるシード層のスパッタ銅が完全にエッチング除去されるまでの時間を測定した。さらに、エッチング処理前後の銅配線幅を、光学顕微鏡を用いて測定し、配線幅減少量を算出した。結果を表1に示す。
EXAMPLES The present invention will be specifically described below with reference to examples and comparative examples, but the present invention is not limited to the following examples.
Example 1
An etching solution containing 1% by weight of hydrogen peroxide and 10% by weight of phosphoric acid was prepared. Next, a 0.5 μm-thick sputtered copper film is formed on the silicon wafer substrate, a pattern resist is formed thereon by photolithography, electrolytic copper plating is applied, and finally the resist is peeled off to form a copper wiring. A test substrate having a width / wiring space of 15 μm / 10 μm was prepared. The substrate was immersed in an etching solution at 30 ° C., and the time until the sputtered copper in the seed layer, which is a wiring space portion, was completely removed by etching was measured. Furthermore, the copper wiring width before and after the etching treatment was measured using an optical microscope, and the wiring width reduction amount was calculated. The results are shown in Table 1.
実施例2
実施例1においてエッチング液として、過酸化水素0.5重量%、リン酸8重量%を含有するエッチング液を用いる以外は実施例1と同様に行い、除去時間と配線幅減少量を測定算出した。結果を表1に示す。
Example 2
The same procedure as in Example 1 was performed except that an etchant containing 0.5% by weight of hydrogen peroxide and 8% by weight of phosphoric acid was used as the etchant in Example 1, and the removal time and the reduction in wiring width were measured and calculated. . The results are shown in Table 1.
比較例1
実施例1においてエッチング液として、過酸化水素1重量%、硫酸4重量%、1H−テトラゾール0.01重量%を含有するエッチング液を用いる以外は実施例1と同様に行い、除去時間と配線幅減少量を測定算出した。結果を表1に示す。
Comparative Example 1
In Example 1, except that an etching solution containing 1% by weight of hydrogen peroxide, 4% by weight of sulfuric acid, and 0.01% by weight of 1H-tetrazole was used as the etching solution, the removal time and the wiring width were obtained. The amount of decrease was measured and calculated. The results are shown in Table 1.
比較例2
実施例1においてエッチング液として、過酸化水素3重量%、リン酸3重量%含有するエッチング液を用いる以外は実施例1と同様に行い、除去時間と配線幅減少量を測定算出した。結果を表1に示す。
Comparative Example 2
In Example 1, except that an etching solution containing 3% by weight of hydrogen peroxide and 3% by weight of phosphoric acid was used as the etching solution, the removal time and the amount of decrease in wiring width were measured and calculated. The results are shown in Table 1.
実施例3
過酸化水素1.5重量%、リン酸15重量%を含有するエッチング液を調合した。次に、ポリイミド基材上に0.3μm厚みのスパッタニッケル膜を形成して、その上にフォトリソによりパターンレジストを形成し、さらに電気銅メッキを施し、最後にレジストを剥離して、銅配線幅/配線スペースが15μm/10μmの試験基板を作成した。該基板を30℃のエッチング液にてスプレー処理(スプレー圧0.03MPa)して、配線スペース部分であるシード層のスパッタニッケルが完全にエッチング除去されるまでの時間を測定した。さらに、エッチング処理前後の銅配線幅を、光学顕微鏡を用いて測定し、配線幅減少量を算出した。結果を表1に示す。
Example 3
An etching solution containing 1.5% by weight of hydrogen peroxide and 15% by weight of phosphoric acid was prepared. Next, a sputtered nickel film having a thickness of 0.3 μm is formed on the polyimide substrate, a pattern resist is formed thereon by photolithography, electrolytic copper plating is performed, and finally the resist is peeled off to form a copper wiring width. / A test substrate having a wiring space of 15 μm / 10 μm was prepared. The substrate was sprayed with an etching solution at 30 ° C. (spray pressure 0.03 MPa), and the time until the sputtered nickel of the seed layer, which is a wiring space portion, was completely etched away was measured. Furthermore, the copper wiring width before and after the etching treatment was measured using an optical microscope, and the wiring width reduction amount was calculated. The results are shown in Table 1.
比較例3
実施例3においてエッチング液として、過酸化水素0.3重量%、硝酸30重量%、硫酸6重量%、塩化ナトリウム0.01重量%、2−クロロ−ピリジン1重量%含有するエッチング液を用いる以外は実施例3と同様に行い、除去時間と配線幅減少量を測定算出した。結果を表1に示す。
Comparative Example 3
In Example 3, an etching solution containing 0.3% by weight of hydrogen peroxide, 30% by weight of nitric acid, 6% by weight of sulfuric acid, 0.01% by weight of sodium chloride and 1% by weight of 2-chloro-pyridine was used as an etching solution. Was performed in the same manner as in Example 3, and the removal time and the amount of decrease in the wiring width were measured and calculated. The results are shown in Table 1.
比較例4
実施例1においてエッチング液として、過酸化水素1.5重量%、リン酸15重量%、塩素イオン2ppm含有するエッチング液を用いる以外は実施例3と同様に行い、除去時間と配線幅減少量を測定算出した。結果を表1に示す。
Comparative Example 4
In Example 1, except that an etching solution containing 1.5% by weight of hydrogen peroxide, 15% by weight of phosphoric acid and 2 ppm of chlorine ions was used as the etching solution, the removal time and the amount of reduction in wiring width were reduced. Measurement was calculated. The results are shown in Table 1.
表1に示されるように、本発明のエッチング方法によりセミアディティブ法での細線銅配線形成において、銅配線の配線幅減少を抑制して、シード層のスパッタ銅またはスパッタニッケルをエッチング除去出来る。 As shown in Table 1, in the thin additive copper wiring formation by the semi-additive method by the etching method of the present invention, the reduction of the wiring width of the copper wiring can be suppressed and the sputtered copper or sputtered nickel of the seed layer can be removed by etching.
Claims (1)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005112157A JP4632038B2 (en) | 2005-04-08 | 2005-04-08 | Copper wiring board manufacturing method |
KR1020060031037A KR20060107349A (en) | 2005-04-08 | 2006-04-05 | Method for manufacturing a substrate on which copper wiring or bumps are formed |
TW095112305A TWI380750B (en) | 2005-04-08 | 2006-04-07 | Method for producing substrate with copper wiring or bump |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005112157A JP4632038B2 (en) | 2005-04-08 | 2005-04-08 | Copper wiring board manufacturing method |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006294797A JP2006294797A (en) | 2006-10-26 |
JP4632038B2 true JP4632038B2 (en) | 2011-02-16 |
Family
ID=37415058
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005112157A Active JP4632038B2 (en) | 2005-04-08 | 2005-04-08 | Copper wiring board manufacturing method |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP4632038B2 (en) |
KR (1) | KR20060107349A (en) |
TW (1) | TWI380750B (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100936079B1 (en) * | 2008-04-01 | 2010-01-12 | 삼성전기주식회사 | Printed Circuit Board Manufacturing Method |
CN103491732B (en) * | 2013-10-08 | 2016-08-17 | 华进半导体封装先导技术研发中心有限公司 | A kind of manufacture method of circuit board layer reinforced structure |
CN103929890B (en) * | 2013-12-31 | 2017-08-29 | 中国科学院微电子研究所 | Method for manufacturing inner layer circuit of circuit board |
JP7443926B2 (en) | 2020-05-15 | 2024-03-06 | 株式会社デンソー | Semiconductor device and its manufacturing method |
CN112609189A (en) * | 2020-12-09 | 2021-04-06 | 四川富乐德科技发展有限公司 | Method for cleaning Open Mask surface magnesium-silver material of OLED Mask |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09288358A (en) * | 1996-04-22 | 1997-11-04 | Hitachi Ltd | Method of forming conductor circuit |
JPH1030194A (en) * | 1996-07-16 | 1998-02-03 | Nec Toyama Ltd | Surface treating agent for copper and copper alloy |
JPH116083A (en) * | 1997-06-13 | 1999-01-12 | Hitachi Ltd | Solution for copper or copper alloy, method for producing the same, method for etching copper or copper alloy, method for chemical polishing and method for forming, and method for producing printed wiring board |
JP2003003283A (en) * | 2001-06-25 | 2003-01-08 | Mitsubishi Gas Chem Co Inc | Surface treatment agent for copper and copper alloy |
JP2003138389A (en) * | 2001-10-30 | 2003-05-14 | Asahi Denka Kogyo Kk | Etching agent composition and pattern forming method |
-
2005
- 2005-04-08 JP JP2005112157A patent/JP4632038B2/en active Active
-
2006
- 2006-04-05 KR KR1020060031037A patent/KR20060107349A/en active Search and Examination
- 2006-04-07 TW TW095112305A patent/TWI380750B/en active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09288358A (en) * | 1996-04-22 | 1997-11-04 | Hitachi Ltd | Method of forming conductor circuit |
JPH1030194A (en) * | 1996-07-16 | 1998-02-03 | Nec Toyama Ltd | Surface treating agent for copper and copper alloy |
JPH116083A (en) * | 1997-06-13 | 1999-01-12 | Hitachi Ltd | Solution for copper or copper alloy, method for producing the same, method for etching copper or copper alloy, method for chemical polishing and method for forming, and method for producing printed wiring board |
JP2003003283A (en) * | 2001-06-25 | 2003-01-08 | Mitsubishi Gas Chem Co Inc | Surface treatment agent for copper and copper alloy |
JP2003138389A (en) * | 2001-10-30 | 2003-05-14 | Asahi Denka Kogyo Kk | Etching agent composition and pattern forming method |
Also Published As
Publication number | Publication date |
---|---|
KR20060107349A (en) | 2006-10-13 |
TW200642552A (en) | 2006-12-01 |
JP2006294797A (en) | 2006-10-26 |
TWI380750B (en) | 2012-12-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR102237844B1 (en) | Method for preparing printed circuit board | |
TWI630261B (en) | Etching composition and method of manufacturing printed circuit board using the same | |
JP2005023340A (en) | Etching method for printed circuit board and etching liquid | |
KR20200046001A (en) | Liquid composition for etching and preparing method of multilayer printed wiring board by using the same | |
CN103510089B (en) | Liquid composition for etching and preparing method of multilayer printed wiring board using same | |
JP4434632B2 (en) | Method for manufacturing printed wiring board | |
US8486281B2 (en) | Nickel-chromium alloy stripper for flexible wiring boards | |
JP4632038B2 (en) | Copper wiring board manufacturing method | |
KR101162370B1 (en) | Etching removing method and etching solution in manufacturing print wiring substrate using semi-additive process | |
JP2011166028A (en) | Method of manufacturing cof substrate | |
JP5576525B1 (en) | Copper etchant | |
WO2021210458A1 (en) | Etching liquid for titanium and/or titanium alloy, method for etching titanium and/or titanium alloy with use of said etching liquid, and method for producing substrate with use of said etching liquid | |
JP2010196119A (en) | Metal surface treating agent | |
JP2624068B2 (en) | Manufacturing method of printed wiring board | |
CN114032548A (en) | Copper foil etching solution for printed circuit board | |
JP2011080131A (en) | Metal surface treatment method and method for manufacturing wiring board |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080312 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100609 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100706 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20101020 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20101102 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 4632038 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131126 Year of fee payment: 3 |