JP4618839B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device including an internal clock and control signal generation circuit, such as a clock synchronous DRAM (dynamic random access memory).
[0002]
[Prior art]
FIG. 10 shows a configuration of an internal clock and control signal generation circuit for a conventional clock synchronous DRAM. 2. Description of the Related Art In a conventional clock synchronous DRAM, a semiconductor memory device in which an internal clock signal generation circuit that generates a clock signal inside a chip in accordance with the specifications of an external circuit with respect to an external clock signal is installed in recent years as the frequency increases. Many have been developed. Typical examples of the internal clock signal generation circuit include a PLL (Phase Locked Loop) circuit, a DLL (Delay Locked Loop) circuit, and the like. For example, a clock synchronous semiconductor device such as a clock synchronous DRAM is generally used. in use. In the clock synchronous semiconductor memory device having the internal clock signal generation circuit, as a technique for reducing power consumption, several circuit groups having different activation timings in the semiconductor device are synchronized with the activation timing. A technique for controlling a clock signal supplied to the circuit group has been proposed.
[0003]
As an explanation of this control method, a clock synchronous DRAM will be described as an example with reference to FIG. In FIG. 10, an external clock signal supplied from an external circuit is input to the internal clock generator 1, and the internal clock generator 1 inputs an external clock signal having a predetermined external signal level to a predetermined internal signal level. Each of the first input terminals of the local buffer amplifiers 51-1 to 51-3 with AND gates after being converted into an internal clock signal having the same high level as the operating power supply voltage of the DRAM (referred to as a so-called CMOS level). Output to. On the other hand, a column activation signal for activating the column-related control signal generation circuit 4 of the memory cell array 7 of the DRAM is input to the second input terminal of the local buffer amplifier 51-1 with AND gate. A row activation signal for activating the row-related control signal generation circuit 5 of the memory cell array 7 of the DRAM is inputted to the second input terminal of the gated local buffer amplifier 51-2. A data input activation signal for activating the data system control signal generation circuit 6 of the memory cell array 7 of the DRAM is input to the second input terminal of the buffer amplifier 51-3. Here, these three activation signals are activated at different timings.
[0004]
Here, each of the local buffer amplifiers 51-1 to 51-3 with AND gates has an AND gate that receives the internal clock signal and any one of the active signals, and, for example, a two-stage inverter connected to the subsequent stage. And the logical product operation of the internal clock signal and any one of the active signals is performed, and the internal clock signals CLKR, CLKC, and CLKD having the calculation result are respectively converted into the column-related control signal generating circuit 4 and the row system. The data is output to the control signal generation circuit 5 and the data system control signal generation circuit 6. In response to this, the column-related control signal generating circuit 4, the row-related control signal generating circuit 5, and the data-related control signal generating circuit 6 each receive various control signals for controlling the operation of the memory cell array 7 of each system. Generated and output to the memory cell array 7.
[0005]
In the above-described clock synchronous DRAM, there are roughly three circuit groups as several circuit groups having different activation timings as shown in FIG. That is, a column-related control signal generation circuit 4 that generates various column-related control signals in synchronization with the column activation signal, and a row-related control signal generation circuit 5 that generates various row-related control signals in synchronization with the row activation signal. And a data system control signal generating circuit 6 for generating various data system control signals in synchronization with the data input activation signal.
[0006]
[Problems to be solved by the invention]
In the conventional example, the clock signals for these circuit groups are collectively generated in the internal clock signal generation circuit and supplied to each circuit group. In this case, since the load of each clock signal in each circuit group is large, the local buffer amplifiers 51-1 to 51-3 having a considerably large size are necessary. Due to layout limitations, the local buffer amplifiers 51-1 to 51-3 Three or more fanouts are set. When the fan-out of the local buffer amplifiers 51-1 to 1-3 is large, jitter is likely to occur in the internal clock signal due to fluctuations in the power supply voltage supplied to the local buffer amplifiers 51-1 to 51-3. It tends to affect the phase difference (skew) of each internal clock signal. As a result, there is a problem in that the setup characteristics and hold characteristics of various control signals are deteriorated.
[0007]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device that can solve the above-described problems and can reduce the skew by preventing jitter in the internal clock signal.
[0010]
[Means for Solving the Problems]
  First of this applicationAccording to another aspect of the present invention, there is provided a semiconductor memory device that converts an internal clock signal into an internal clock signal and outputs the internal clock signal, the internal clock signal, and first and second activation signals that are activated at different timings. Generating first and second control signals for each memory cell array based onvesselA semiconductor memory device in which the second activation signal may be activated only when the first activation signal is activated,
  A main buffer amplifying means which is provided at a subsequent stage of the internal clock generating means, performs a logical product operation of the internal clock signal and the first activation signal, and performs buffer amplification and outputs;
  The internal clock signal output from the main buffer amplifying means generates the first and second control signals.vesselSignal wiring means for transmitting to the circuit of
  First control signal generationvesselA plurality of first local buffer amplifying means for buffering and outputting an internal clock signal transmitted by the signal wiring means;
  First control signal generationvesselThe first control signal is generated by converting each signal output from the plurality of first local buffer amplifiers into its complementary signal.vesselA plurality of first complementary conversion means for outputting to
  Second control signal generationvesselA plurality of second local buffer amplifying means for performing an AND operation between the internal clock signal transmitted by the signal wiring means and the second active signal, and buffering and amplifying the output. ,
  Second control signal generationvesselThe second control signal is generated by converting each signal output from the plurality of second local buffer amplifiers into its complementary signal.vesselAnd a plurality of second complementary conversion means for outputting to,
  The first activation signal is a column activation signal for activating a column-related control signal generator, and the second activation signal is a row activation signal for activating a row-related control signal generator; This is a data input activation signal for activating the data system control signal generator.It is characterized by
[0011]
  AlsoSecond of this applicationAccording to another aspect of the present invention, there is provided a semiconductor memory device that converts an internal clock signal into an internal clock signal and outputs the internal clock signal, the internal clock signal, and first and second activation signals that are activated at different timings. Generating first and second control signals for each memory cell array based onvesselA semiconductor memory device in which the second activation signal may be activated only when the first activation signal is activated,
  The internal clock generation means includes a complementary conversion means, converts an external clock signal into a complementary internal clock signal, and outputs it.
  The semiconductor memory device is
  A main buffer amplifying means which is provided at a subsequent stage of the internal clock generating means, performs a logical product operation of the complementary internal clock signal and the first activation signal, and performs buffer amplification and outputs;
  The complementary internal clock signal output from the main buffer amplifier means generates the first and second control signals.vesselSignal wiring means for transmitting to the circuit of
  First control signal generationvesselAnd generating a first control signal by buffering and amplifying a complementary internal clock signal transmitted by the signal wiring means.vesselA plurality of first local buffer amplifying means for outputting to
  Second control signal generationvesselThe second control signal is generated by performing AND operation on the complementary internal clock signal transmitted by the signal wiring means and the second active signal, and buffering and amplifying it.vesselAnd a plurality of second local buffer amplification means for outputting to,
  The first activation signal is a column activation signal for activating a column-related control signal generator, and the second activation signal is a row activation signal for activating a row-related control signal generator; This is a data input activation signal for activating the data system control signal generator.It is characterized by that.
[0013]
  UpFirstAnd 2In the semiconductor memory device according to the invention, the fan-out of the main buffer amplifying means is preferably set to 3 or more.
[0014]
  Also,The firstAnd 2In the semiconductor memory device according to the present invention, the fan-out of each of the local buffer amplification means is preferably set to 3 or less.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same symbols are attached to the same components.
[0016]
Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of an internal clock and control signal generation circuit for a clock synchronous DRAM according to the first embodiment of the present invention. The internal clock and control signal generation circuit according to the first embodiment includes an internal clock generator 1 that converts an external clock signal into an internal clock signal and outputs it, an internal clock signal, and an external circuit that are generated at different timings. In a clock synchronous DRAM including three control signal generation circuits 4a, 5a, 6a for generating respective control signals of the memory cell array 7 based on a column activation signal to be activated, a matrix activation signal, and a data input column activation signal As shown in FIG. 1, a main buffer amplifier 2 and a signal wiring 3 are provided between the internal clock generator 1 and the control signal generation circuits 4a, 5a, 6a, and the control signal generation circuits 4a, 5a, 6a are provided. Inside, local buffer amplifiers 11-1 to 11-N with AND gates and complementary converters 12-1 to 12-N are provided. There.
[0017]
In FIG. 1, an external clock signal supplied from an external circuit is input to an internal clock generator 1, and the internal clock generator 1 receives an external clock signal having a predetermined external signal level as a predetermined internal signal level. Is converted to an internal clock signal having a signal output to the main buffer amplifier 2. The main buffer amplifier 2 is provided in a subsequent stage immediately after the internal clock generator 1, buffers and amplifies the internal clock signal, and generates a column-related control signal generation circuit 4a and a row-related control signal through one signal wiring 3. The signal is output to each of the first input terminals of the plurality N of local buffer amplifiers 11-1 to 11-N with AND gates in the circuit 5a and the data system control signal generation circuit 6a.
[0018]
Here, as shown in FIG. 5, the main buffer amplifier 2 is configured to include four inverters INV1, INV2, INV3, and INV4 that are cascade-connected to each other. To do. Here, the fan-out of the main buffer amplifier 2 is preferably set to 3 or more. Thereby, the load capacity of the main buffer amplifier 2 can be set relatively large. The signal wiring 3 is routed from the output terminal of the main buffer amplifier 2 to the vicinity of each control signal generating circuit 4a, 5a, 6a and then branched into three branches. The column related control signal generating circuit 4a and the row related control signal generating circuit 5a. And a plurality of N local buffer amplifiers 11-1 to 11-N with AND gates in the data system control signal generation circuit 6a are connected to the first input terminals. In the drawings such as FIG. 1 to FIG. 4, the numbers shown in the vicinity of the signal wiring represent the number or logarithm of the signal wiring, and one signal wiring 3 in FIG. 1 or a ground conductor (not shown). Is a pair of signal wirings. In addition, since the signal wiring from each complementary converter 12-1 thru | or 12-N mentioned later to the control signal generator 13 is a signal wiring of a complementary signal, it is two pairs.
[0019]
The column-related control signal generation circuit 4a includes a plurality of N local buffer amplifiers 11-1 to 11-N with AND gates, a plurality of N complementary converters 12-1 to 12-N, a control signal generator 13, and the like. It is configured with. As shown in FIG. 6, the local buffer amplifiers 11-1 to 11-N with AND gates (generally referred to by reference numeral 11) have an AND gate AND1 and two inverters INV5 and INV6 connected in cascade. And an AND operation of the internal clock signal transmitted by the signal wiring 3 and the column activation signal generated by the external circuit, and buffered and amplified to output to each of the complementary converters 12-1 to 12-N To do. Here, the fan-out of the local buffer amplifiers 11-1 to 11-N is preferably set to 3 or less. Thereby, the load capacity of the main buffer amplifier 2 can be set relatively small, and the power consumption can be reduced.
[0020]
Further, the complementary converters 12-1 to 12-N (generally, denoted by reference numeral 12) are configured to include five inverters INV11 to INV15 and a noise removing capacitor C1 as shown in FIG. Here, one end of the capacitor C1 is connected to a connection point between the output terminal of the inverter INV11 and the input terminal of the inverter INV12, while the other end of the capacitor C1 is grounded. In FIG. 7, the input internal clock signal is output as a non-inverted internal clock signal via two inverters INV11 and INV12, and as an inverted internal clock signal via three inverters INV13 to INV15. Is output. Therefore, in the complementary converter 12 configured as described above, as shown in FIG. 8, the non-inverted internal clock signal synchronized with the input internal clock signal and the input internal clock signal A complementary internal clock signal including an inverted internal clock signal synchronized with each other is generated and output to the control signal generator 13. Further, the control signal generation circuit 13 generates various column related control signals for the column related control circuit of the memory cell array 7 based on the complementary internal clock signal and outputs them to the memory cell array 7.
[0021]
Similarly to the column-related control signal generating circuit 4a, the row-related control signal generating circuit 5a includes a plurality of local buffer amplifiers with AND gates, a plurality of complementary converters, and a control signal generator. Then, a complementary internal clock signal is generated based on the internal clock signal transmitted by the signal wiring 3 and the row activation signal, and in response thereto, various column system controls for the row system control circuit of the memory cell array 7 are generated. A signal is generated and output to the memory cell array 7.
[0022]
Further, like the column-related control signal generating circuit 4a, the data-related control signal generating circuit 6a includes a plurality of local buffer amplifiers with AND gates, a plurality of complementary converters, and a control signal generator. The complementary internal clock signal is generated based on the internal clock signal transmitted by the signal wiring 3 and the data input activation signal, and various column systems for the data system control circuit of the memory cell array 7 are generated in response thereto. A control signal is generated and output to the memory cell array 7.
[0023]
As described above, according to the present embodiment, a plurality of control signals are generated from one internal clock signal by one signal line 3 from one internal buffer signal generator 1 through one main buffer amplifier 2. A column activation signal, a row activation signal and a data input activation signal which are transmitted to the circuits 4a, 5a and 6a and activate the control signal generation circuits 4a, 5a and 6a in the control signal generation circuits 4a, 5a and 6a. , The activation is controlled by the converters, and one internal clock signal is converted into a complementary internal clock signal by the complementary converters 12-1 to 12-N, and then various controls for these control signal generation circuits 4a, 5a, 6a are performed. Generate a signal.
[0024]
Here, it is necessary to create complementary internal clock signals in each local control signal generation circuit 4a, 5a, 6a in recent years. External data information is chipped with respect to the rising edge and the falling edge with respect to the clock signal. This is because an internal transfer configuration (referred to as a so-called DDR (DDR) configuration) has begun to be used as a technology for improving the data transfer rate.
[0025]
According to this embodiment, there is one main buffer amplifier 2 with a relatively large fan-out, and there are a plurality of main buffer amplifiers with a relatively large fan-out (for example, three in the conventional example of FIG. 10). Thus, the skew between the clock signals can be reduced. Further, the power consumption during the worst operation in which all the clock signals operate is reduced because the number of signal wirings 3 for the clock signal is changed from three in the conventional example to one in this embodiment. Also, the number of main buffer amplifiers is reduced from three in the conventional example to one in this embodiment, and the layout area of the DRAM can be greatly reduced. Further, the local buffer amplifiers 11-1 to 11-N arranged in the control signal generation circuits 4a, 5a, and 6a can have a smaller fan-out than the local arrangement of the conventional example, and each local buffer amplifier 11-1 to 11-N. The skew in the internal clock signal output from 11-N can be suppressed and reduced.
[0026]
Embodiment 2. FIG.
FIG. 2 is a block diagram showing a configuration of an internal clock and control signal generation circuit for the clock synchronous DRAM according to the second embodiment of the present invention. The internal clock and control signal generation circuit of this embodiment is different from that of the first embodiment of FIG. 1 in that the internal clock generator 1 replaces the internal clock generator 1a incorporating a complementary converter and generates an internal clock. Complementary internal clock signal processing and signal wiring from the output terminal of the device 1a to each input terminal of the control signal generator 13 in each control signal generating circuit 4b, 5b, 6b. Hereinafter, the difference will be described in detail.
[0027]
In FIG. 2, the internal clock generator 1a includes a complementary converter, and includes an external clock signal having a predetermined external signal level, and two internal clock signals having a predetermined internal signal level and inverted and non-inverted. After being converted to a complementary internal clock signal, it is output to the main buffer amplifier 2c. The main buffer amplifier 2c is provided in the subsequent stage immediately after the internal clock generator 1a, buffers and amplifies the complementary internal clock signal, and via the two signal wirings 3a, the column-related control signal generating circuit 4b and the row-related control signal. The data is output to the first input terminals of the plurality of N AND-gate local buffer amplifiers 11c-1 to 11c-N in the generation circuit 5b and the data system control signal generation circuit 6b. Here, the signal wiring 3a is routed from the output terminal of the main buffer amplifier 2c to the vicinity of each control signal generation circuit 4b, 5b, 6b and then branched into three branches, and the column-related control signal generation circuit 4b and the row-related control signal generation circuit. 5b and a plurality of N local buffer amplifiers 11c-1 to 11c-N with AND gates in the data system control signal generation circuit 6b.
[0028]
The column-related control signal generation circuit 4b includes a plurality of N local buffer amplifiers 11c-1 to 11c-N with AND gates and a control signal generator 13. Here, the local buffer amplifiers 11c-1 to 11c-N perform the logical product operation of the complementary internal clock signal transmitted by the signal wiring 3a and the column activation signal generated by the external circuit, and control by buffer amplification. Output to the signal generator 13.
[0029]
Similarly to the column-related control signal generating circuit 4b, the row-related control signal generating circuit 5b includes a plurality of AND gate-attached local buffer amplifiers and a control signal generator, and is transmitted by the signal wiring 3a. The complementary internal clock signal is generated based on the complementary internal clock signal and the row activation signal, and various column related control signals for the row related control circuit of the memory cell array 7 are generated in response to the generated internal clock signal. 7 is output.
[0030]
Further, like the column-related control signal generating circuit 4b, the data-related control signal generating circuit 6b includes a plurality of local buffer amplifiers with AND gates and a control signal generator, and is transmitted by the signal wiring 3a. The complementary internal clock signal is generated based on the complementary internal clock signal and the data input activation signal, and various column system control signals for the data system control circuit of the memory cell array 7 are generated in response to the generated internal clock signal. Output to the cell array 7.
[0031]
As described above, according to the present embodiment, a complementary internal clock signal is transmitted to each control signal generation circuit 4b, 5b, 6b through two signal wirings 3a via one main buffer amplifier 2c. These control signal generation circuits 4b, 5b, 6b are controlled by respective activation signals for activating these control signal generation circuits 4b, 5b, 6b, and various control signals for the memory cell array 7 are generated.
[0032]
According to this embodiment, there is one main buffer amplifier 2c having a relatively large fan-out, and there is a plurality of main buffer amplifiers having a relatively large fan-out (three in the conventional example). Skew can be reduced. Further, the power consumption during the worst operation in which all the clock signals are operating is reduced because the number of signal wirings 3a for the clock signal is two from three in the conventional example. Also, the number of main buffer amplifiers 2c is increased from three in the conventional example to one, and the layout area can be greatly reduced.
[0033]
Since the complementary clock signal is generated by the internal clock signal generator 1a in addition to the effect of the first embodiment, the complementary converter 12 does not exist in each local control signal generation circuit 4b, 5b, 6b. The jitter and skew caused by the complementary converter 12 can be reduced, and the layout area and power consumption of the circuit of the complementary converter 12 can be reduced.
[0034]
Embodiment 3 FIG.
FIG. 3 is a block diagram showing a configuration of an internal clock and control signal generation circuit for the clock synchronous DRAM according to the third embodiment of the present invention. The internal clock and control signal generation circuit of this embodiment replaces the main buffer amplifier 8 with an AND gate in which the main buffer amplifier 2 is activated by the column activation signal, as compared with the first embodiment of FIG. The local buffer amplifiers 11-1 to 11-N with AND gates in the column-related control signal generation circuit 4a replace the local buffer amplifiers 11b-1 to 11b-N in the column-related control signal generation circuit 4c. Row related control signal generating circuit 5c has the same configuration as column related control signal generating circuit 4a in FIG. Hereinafter, the difference will be described.
[0035]
In the third and fourth embodiments, as shown in FIG. 9, when the column activation signal is inactive, the row activation signal and the data input activation signal are not necessarily activated during that period, but when the column activation signal is active, the row activation signal is not activated. The activation signal and the data input activation signal have a circuit configuration that is limited to the case where the activation signal and the data input activation signal may be activated at any timing during the period.
[0036]
In FIG. 3, the internal clock generator 1 converts an input external clock signal having a predetermined external signal level into an internal clock signal having a predetermined internal signal level. 1 to the input terminal. On the other hand, a column activation signal generated by an external circuit is inputted to the second input terminal of the main buffer amplifier 8 with AND gate. The main buffer amplifier 8 with an AND gate is provided at a subsequent stage immediately after the internal clock generator 1, performs an AND operation between the internal clock signal and the column activation signal, performs buffer amplification, and passes through one signal wiring 3. Output to the plurality of N local buffer amplifiers 11b-1 to 11b-N in the column-related control signal generating circuit 4c, and a plurality of M in the row-related control signal generating circuit 5c and the data-related control signal generating circuit 6c. And output to the first input terminals of the local buffer amplifiers 15-1 to 15-M with AND gates.
[0037]
Here, the main buffer amplifier 8 with an AND gate is constituted by, for example, one AND gate and four inverters connected in cascade, and the fanout is preferably set to 3 or more. Each of the local buffer amplifiers 11b-1 to 11b-N is configured by, for example, two inverters connected in cascade, and the fanout is preferably set to 3 or less. The signal wiring 3 is wired from the output terminal of the main buffer amplifier 8 with AND gate to the vicinity of each control signal generating circuit 4c, 5c, 6c and then branched into three branches, and the local buffer amplifier 11b of the column related control signal generating circuit 4c. -1 to 11b-N are connected to the first input terminals, and a plurality of M AND-gate-attached local buffer amplifiers 15-1 to 15- 1 in the row-related control signal generating circuit 5c and the data-related control signal generating circuit 6c. Connected to each 15-M first input terminal.
[0038]
The column-related control signal generation circuit 4c includes a plurality of N local buffer amplifiers 11b-1 to 11b-N, a plurality of N complementary converters 12-1 to 12-N, and a control signal generator 13. Composed. The local buffer amplifiers 11b-1 to 11b-N buffer-amplify the internal clock signal transmitted through the signal wiring 3 and output the buffered signals to the complementary converters 12-1 to 12-N. The operations of complementary converters 12-1 to 12-N and control signal generator 13 are the same as those in the first embodiment.
[0039]
Similarly to the column-related control signal generator 4a of the first embodiment, the row-related control signal generating circuit 5c includes a plurality of M local buffer amplifiers 15-1 to 15-M with AND gates and a plurality of M pieces of local buffer amplifiers 15a to 15-M. Complementary converters 16-1 to 16-M and a control signal generator 14 are configured to generate a complementary internal clock signal based on the internal clock signal transmitted by the signal wiring 3 and the row activation signal. In response to this, various column related control signals for the row related control circuit of the memory cell array 7 are generated and output to the memory cell array 7.
[0040]
Further, like the column-related control signal generating circuit 4c, the data-related control signal generating circuit 6c includes a plurality of AND gate-attached local buffer amplifiers, a plurality of complementary converters, and a control signal generator. The complementary internal clock signal is generated based on the internal clock signal transmitted by the signal wiring 3 and the data input activation signal, and various column systems for the data system control circuit of the memory cell array 7 are generated in response thereto. A control signal is generated and output to the memory cell array 7.
[0041]
As described above, according to the third embodiment, the internal clock signal output from the internal clock signal generator 1 is transmitted to the signal wiring 3 via the main buffer amplifier 8 with an AND gate activated by the column activation signal. Is transmitted to each control signal generation circuit 4c, 5c, 6c, and is controlled by a row activation signal and a data input activation signal for activating each control signal generation circuit 5c, 6c in each control signal generation circuit 5c, 6c. Various control signals for the cell array 7 are generated.
[0042]
According to this embodiment, there is one main buffer amplifier 8 having a relatively large fan-out, and each clock signal resulting from the presence of a plurality of main buffer amplifiers having a relatively large fan-out (three in the conventional example). The skew between them can be reduced. Furthermore, the power consumption during the worst operation in which all the clock signals are operating is reduced because the number of signal wirings 3 for the internal clock signal is reduced from three in the conventional example to one. Further, the number of main buffer amplifiers 8 is one, and the layout area can be greatly reduced. In addition to the effect of the first embodiment, when the column-related control signal generation circuit 4c is not activated, it is not necessary to activate the signal wiring 3 of the internal clock signal, and therefore when the DRAM is not operating. There is a specific effect that the power consumption can be greatly reduced.
[0043]
Embodiment 4 FIG.
FIG. 4 is a block diagram showing a configuration of an internal clock and control signal generation circuit for the clock synchronous DRAM according to the fourth embodiment of the present invention. In the internal clock and control signal generation circuit of this embodiment, the internal clock generator 1 replaces the internal clock generator 1a with a built-in complementary converter, as compared with the third embodiment of FIG. Complementary internal clock signal processing and signal wiring from the output terminal of the device 1a to each input terminal of the control signal generator 13 in each control signal generation circuit 4d, 5d, 6d. In the fourth embodiment, similarly to the third embodiment, when the column activation signal is inactive, the row activation signal and the data input activation signal are not necessarily activated during that period. However, when the column activation signal is activated, the row activation signal is not activated. The activation signal and the data input activation signal have a circuit configuration that is limited to the case where the activation signal and the data input activation signal may be activated at any timing during the period. Hereinafter, the difference will be described in detail.
[0044]
In FIG. 4, an internal clock generator 1a includes a complementary converter, and includes an external clock signal having a predetermined external signal level and two internal clock signals having a predetermined internal signal level and inverted and non-inverted. After being converted into a complementary internal clock signal, it is output to the main buffer amplifier 8c with AND gate. The main buffer amplifier 8c with an AND gate is provided in the subsequent stage immediately after the internal clock generator 1a, performs an AND operation between the complementary internal clock signal and the column activation signal, and buffers and amplifies the two signal wirings 3a. To the plurality of N local buffer amplifiers 11bc-1 to 11bc-N in the column related control signal generating circuit 4d, and a plurality of M in the row related control signal generating circuit 5d and the data related control signal generating circuit 6d. The data are output to the first input terminals of the local buffer amplifiers 15c-1 to 15c-M with AND gates. Here, the signal wiring 3a is routed from the output terminal of the main buffer amplifier 8c with AND gate to the vicinity of each of the control signal generation circuits 4d, 5d, 6d and then branched into three, and a plurality of N in the column-related control signal generation circuit 4d. The local buffer amplifiers 11c-1 to 11bc-1 to 11c-1 to 11bc-1 to 11bc-N, and a plurality of M AND-gate-attached local buffer amplifiers 11c-1 to 11c in the row-related control signal generating circuit 5d and the data-related control signal generating circuit 6d. 11c-M is connected to each first input terminal.
[0045]
The column-related control signal generation circuit 4d includes a plurality of N local buffer amplifiers 11bc-1 to 11bc-N and a control signal generator 13. Here, the local buffer amplifiers 11bc-1 to 11bc-N buffer-amplify the complementary internal clock signal transmitted through the signal wiring 3a and output the buffered signal to the control signal generator 13.
[0046]
Similarly to the column-related control signal generating circuit 4b, the row-related control signal generating circuit 5d includes a plurality of M local buffer amplifiers 15c-1 to 15c-M with AND gates and a control signal generator 14. A complementary internal clock signal is generated based on the complementary internal clock signal transmitted through the signal wiring 3a and the row activation signal, and various columns for the row-related control circuit of the memory cell array 7 in response thereto. A system control signal is generated and output to the memory cell array 7.
[0047]
Further, like the column-related control signal generating circuit 5d, the data-related control signal generating circuit 6d comprises a plurality of local buffer amplifiers with AND gates and a control signal generator, and is transmitted by the signal wiring 3a. The complementary internal clock signal is generated based on the complementary internal clock signal and the data input activation signal, and various column system control signals for the data system control circuit of the memory cell array 7 are generated in response to the generated internal clock signal. Output to the cell array 7.
[0048]
As described above, according to the present embodiment, the complementary internal clock signal output from the internal clock signal generator 1a is routed through the main buffer amplifier 8c with an AND gate activated by the column activation signal. 3 is transmitted to each control signal generation circuit 4d, 5d, 6d, and is controlled by a row activation signal and a data input activation signal for activating each control signal generation circuit 5d, 6d in each control signal generation circuit 5d, 6d, Various control signals for the memory cell array 7 are generated.
[0049]
According to this embodiment, there is one main buffer amplifier 8c having a relatively large fan-out, and each clock signal resulting from the presence of a plurality of main buffer amplifiers having a relatively large fan-out (three in the conventional example). The skew between them can be reduced. Further, the power consumption during the worst operation in which all the clock signals are operating is reduced because the number of signal wirings 3a for the internal clock signal is two from three in the conventional example. Further, the number of main buffer amplifiers 8c is one, and the layout area can be greatly reduced.
[0050]
Since the complementary clock signal is generated by the internal clock signal generator 1a in addition to the effect of the first embodiment, there is no complementary converter 12 in each local control signal generation circuit 4d, 5d, 6d. The jitter and skew caused by the complementary converter 12 can be reduced, and the layout area and power consumption of the circuit of the complementary converter 12 can be reduced.
[0051]
In addition to the effect of the third embodiment, when the column-related control signal generation circuit 4d is not activated, the signal wiring 3a for the internal clock signal does not need to be activated, so that the DRAM is not operating. There is a specific effect that the power consumption can be greatly reduced.
[0052]
Modified example.
Although the case where the three control signal generation circuits are provided has been described in the above embodiment, the present invention is not limited to this, and a plurality of control signal generation circuits may be provided. The number of local buffer amplifiers and local buffer amplifiers with AND gates in each control signal generation circuit may be changed as necessary.
[0055]
【The invention's effect】
  As detailed above, the first of the present application.According to the semiconductor memory device of the present invention, the internal clock generating means for converting the external clock signal into the internal clock signal and outputting it, and the internal clock signal and the first and second activations activated at different timings. First and second control signal generation for generating each control signal of the memory cell array based on the signalvesselA semiconductor memory device in which the second activation signal may be activated only when the first activation signal is activated,
  A main buffer amplifying means which is provided at a subsequent stage of the internal clock generating means, performs a logical product operation of the internal clock signal and the first activation signal, and performs buffer amplification and outputs;
  The internal clock signal output from the main buffer amplifying means generates the first and second control signals.vesselSignal wiring means for transmitting to the circuit of
  First control signal generationvesselA plurality of first local buffer amplifying means for buffering and outputting an internal clock signal transmitted by the signal wiring means;
  First control signal generationvesselThe first control signal is generated by converting each signal output from the plurality of first local buffer amplifiers into its complementary signal.vesselA plurality of first complementary conversion means for outputting to
  Second control signal generationvesselA plurality of second local buffer amplifying means for performing an AND operation between the internal clock signal transmitted by the signal wiring means and the second active signal, and buffering and amplifying the output. ,
  Second control signal generationvesselThe second control signal is generated by converting each signal output from the plurality of second local buffer amplifiers into its complementary signal.vesselAnd a plurality of second complementary conversion means for outputting to,
  The first activation signal is a column activation signal for activating a column-related control signal generator, and the second activation signal is a row activation signal for activating a row-related control signal generator; This is a data input activation signal for activating the control signal generator of the data system.
  Therefore, there is only one main buffer amplifying means having a relatively large fanout, and the skew between clock signals due to the presence of a plurality of main buffer amplifying means having a relatively large fanout (three in the conventional example) is reduced. Can be made. Further, the power consumption during the worst operation in which all the clock signals are operating is reduced because the number of signal wiring means for the internal clock signal is reduced from three in the conventional example to one. Further, the number of main buffer amplification means 8 is one, and the layout area can be greatly reduced.
  In addition to the effects described above, the first control signal is generated.vesselWhen the semiconductor memory device is not activated, it is not necessary to activate the signal wiring means for the internal clock signal, so that there is a specific effect that power consumption can be significantly reduced when the semiconductor memory device is not operating.
  Here, the first activation signal is a column activation signal for activating a column-related control signal generator, and the second activation signal is a row for activating a row-related control signal generator. A data input activation signal for activating an activation signal and a control signal generator of a data system. As a result, when the first control signal generator is not activated, the signal wiring means for the internal clock signal does not need to be activated, so that the power consumption is greatly reduced when the semiconductor memory device is not operating. There is a specific effect that it can be reduced.
[0056]
  AlsoSecond of this applicationAccording to the semiconductor memory device of the present invention, the internal clock generating means for converting the external clock signal into the internal clock signal and outputting it, and the internal clock signal and the first and second activations activated at different timings. First and second control signal generation for generating each control signal of the memory cell array based on the signalvesselA semiconductor memory device in which the second activation signal may be activated only when the first activation signal is activated,
  The internal clock generation means includes a complementary conversion means, converts an external clock signal into a complementary internal clock signal, and outputs it.
  The semiconductor memory device is
  A main buffer amplifying means which is provided at a subsequent stage of the internal clock generating means, performs a logical product operation of the complementary internal clock signal and the first activation signal, and performs buffer amplification and outputs;
  The complementary internal clock signal output from the main buffer amplifier means generates the first and second control signals.vesselSignal wiring means for transmitting to the circuit of
  First control signal generationvesselAnd generating a first control signal by buffering and amplifying a complementary internal clock signal transmitted by the signal wiring means.vesselA plurality of first local buffer amplifying means for outputting to
  Second control signal generationvesselThe second control signal is generated by performing AND operation on the complementary internal clock signal transmitted by the signal wiring means and the second active signal, and buffering and amplifying it.vesselAnd a plurality of second local buffer amplification means for outputting to,
  The first activation signal is a column activation signal for activating a column-related control signal generator, and the second activation signal is a row activation signal for activating a row-related control signal generator; This is a data input activation signal for activating the control signal generator of the data system.
  Therefore, there is only one main buffer amplifying means having a relatively large fanout, and the skew between clock signals due to the presence of a plurality of main buffer amplifying means having a relatively large fanout (three in the conventional example) is reduced. Can be made. Furthermore, the power consumption during the worst operation in which all the clock signals are operating is reduced because the number of signal wiring means for the internal clock signal is two from three in the conventional example. Further, the number of main buffer amplification means is one, and the layout area can be greatly reduced.
  In addition to the above effects, the internal clock signal generating means generates a complementary clock signal, so that each local control signal is generated.vesselHowever, since there is no complementary conversion means, the jitter and skew caused by the complementary conversion means can be reduced, and the layout area and power consumption of the circuit of the complementary conversion means can be reduced.
  Furthermore, in addition to the above-described effects, the first control signal generationvesselWhen the semiconductor memory device is not activated, it is not necessary to activate the signal wiring means for the internal clock signal, so that there is a specific effect that power consumption can be significantly reduced when the semiconductor memory device is not operating.
  Here, the first activation signal is a column activation signal for activating a column-related control signal generator, and the second activation signal is a row for activating a row-related control signal generator. A data input activation signal for activating an activation signal and a control signal generator of a data system. As a result, when the first control signal generator is not activated, the signal wiring means for the internal clock signal does not need to be activated, so that the power consumption is greatly reduced when the semiconductor memory device is not operating. There is a specific effect that it can be reduced.
[0058]
  First and second aboveIn the semiconductor memory device according to the invention, the fan-out of the main buffer amplifying means is preferably set to 3 or more. As a result, the load capacity of the main buffer amplification means can be increased, and a plurality of control signals can be generated.vesselIt can correspond to.
[0059]
  Also, 1 and 2 aboveIn the semiconductor memory device according to the present invention, the fan-out of each of the local buffer amplification means is preferably set to 3 or less. As a result, the load capacity of the main buffer amplification means can be reduced, and the power consumption can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an internal clock and control signal generation circuit for a clock synchronous DRAM according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of an internal clock and control signal generation circuit for a clock synchronous DRAM according to a second embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of an internal clock and control signal generation circuit for a clock synchronous DRAM according to a third embodiment of the present invention.
FIG. 4 is a block diagram showing a configuration of an internal clock and control signal generation circuit for a clock synchronous DRAM according to a fourth embodiment of the present invention.
FIG. 5 is a block diagram showing a configuration of a main buffer amplifier 2 used in the embodiment.
FIG. 6 is a block diagram showing a configuration of an AND gated local buffer amplifier 11 used in the embodiment.
FIG. 7 is a block diagram showing a configuration of a complementary converter 12 used in the embodiment.
8 is a timing chart of an input clock signal and an output clock signal showing the operation of the complementary converter 12 of FIG.
FIG. 9 is a timing chart of a column activation signal and a row activation signal or a data system activation signal showing operations in the third and fourth embodiments.
FIG. 10 is a block diagram showing a configuration of an internal clock and control signal generation circuit for a conventional clock synchronous DRAM.
[Explanation of symbols]
1, 1a internal clock generator, 2, 2c main buffer amplifier, 3, 3a signal wiring, 4a, 4b, 4c, 4d column system control signal generation circuit, 5a, 5b, 5c, 5d row system control signal generation circuit, 6a , 6b, 6c, 6d Data system control signal generating circuit, 7 Memory cell array, 8, 8c Main buffer amplifier with AND gate, 11, 11-1 to 11-N, 11c-1 to 11c-N Local buffer amplifier with AND gate 11b-1 to 11b-N, 11bc-1 to 11bc-N local buffer amplifiers, 12, 12-1 to 12-N, 16-1 to 16-M complementary converters, 13, 14 control signal generators, 15 -1 to 15-M, 15c-1 to 15c-M Local buffer amplifiers with AND gates.

Claims (4)

Each control of the memory cell array is based on internal clock generation means for converting an external clock signal into an internal clock signal and outputting the internal clock signal, and the first and second activation signals activated at different timings. and first and second control signal generator for generating a signal, a semiconductor memory device viewed the second active signal when said first activation signal becomes active there is a case to be the active state And
A main buffer amplifying means which is provided at a subsequent stage of the internal clock generating means, performs a logical product operation of the internal clock signal and the first activation signal, and performs buffer amplification and outputs;
And the signal line means for transmitting an internal clock signal output from the main buffer amplifier means to the circuit of the first and second control signal generators described above,
A plurality of first local buffer amplifying means provided in the circuit of the first control signal generator , for buffering and outputting an internal clock signal transmitted by the signal wiring means;
Provided in the circuit of the first control signal generator, and outputs the first control signal generator above converts the signals output from said plurality of first local buffer amplifier means to its complementary signal A plurality of first complementary conversion means;
Provided in the circuit of the second control signal generator, the signal and the internal clock signal transmitted by the routing unit, a plurality of outputs to perform and buffer amplifying a logical AND operation between the second active signal Second local buffer amplification means;
Provided in the circuit of the second control signal generator, and outputs to the second control signal generator converts the signals output from said plurality of second local buffer amplifier means to its complementary signal A plurality of second complementary conversion means ,
The first activation signal is a column activation signal for activating a column-related control signal generator, and the second activation signal is a row activation signal for activating a row-related control signal generator; A semiconductor memory device characterized by being a data input activation signal for activating a control signal generator of a data system. Each control of the memory cell array is based on internal clock generation means for converting an external clock signal into an internal clock signal and outputting the internal clock signal, and the first and second activation signals activated at different timings. and first and second control signal generator for generating a signal, a semiconductor memory device viewed the second active signal when said first activation signal becomes active there is a case to be the active state And
The internal clock generation means includes a complementary conversion means, converts an external clock signal into a complementary internal clock signal, and outputs it.
The semiconductor memory device is
A main buffer amplifying means which is provided at a subsequent stage of the internal clock generating means, performs a logical product operation of the complementary internal clock signal and the first activation signal, and performs buffer amplification and outputs;
And the signal line means for transmitting complementary internal clock signal output from the main buffer amplifier means to the circuit of the first and second control signal generators described above,
Provided in the circuit of the first control signal generator, a plurality of first local buffer to the complementary internal clock signal transmitted by the signal line means and a buffer amplifier outputs the first control signal generator the Amplifying means;
The second control signal generator is provided in the circuit, performs a logical AND operation between the complementary internal clock signal transmitted by the signal wiring means and the second active signal, and buffers and amplifies the second control signal generator . and a plurality of second local buffer amplifying means for outputting a control signal generator,
The first activation signal is a column activation signal for activating a column-related control signal generator, and the second activation signal is a row activation signal for activating a row-related control signal generator; A semiconductor memory device characterized by being a data input activation signal for activating a control signal generator of a data system. The semiconductor memory device according to claim 1 or 2, wherein the fan-out of the main buffer amplifying means is set to 3 or higher. The semiconductor memory device according to any one of claims 1 to 3, characterized in that the fan-out of each local buffer amplifying means is set to 3 or less.

Images