JP4615290B2 - Plasma etching method - Google Patents

Description

The present invention, an etching gas into plasma, relates a SiC layer formed on the object to be processed by the plasma in the plasma etching how to etch.

Conventionally, plasma etching has been frequently used in the manufacturing process of semiconductor devices. Among such plasma etchings, CHF ₃ and N ₂ are used for plasma etching in which the SiC layer formed on the object to be processed is selectively etched with respect to the oxide film layer (SiO ₂ layer) constituting the insulating layer. It is known to use an etching gas comprising a mixed gas of (see, for example, Patent Document 1).
JP 2004-140025 A

In recent years, in the field of manufacturing semiconductor devices, for example, SiOC (CDO (Carbon-doped oxide) is used as a so-called Low-k film having a lower dielectric constant than an SiO ₂ layer conventionally used as an oxide film layer constituting an insulating layer. )) Etc. are used.

However, when the etching gas comprising the above-mentioned mixed gas of CHF ₃ and N ₂ is used, when the SiC layer is etched, sufficient selectivity for the SiOC layer cannot be obtained, and the selectivity (etching of the SiC layer) is not possible. (Rate / etching rate of SiOC layer) was less than 2.

The present invention has been made to address the conventional circumstances described above, it is intended to provide a plasma etching how that can be selectively etched with high SiC layer with respect SiOC layer.

In order to achieve the above object, a plasma etching method according to claim 1 is a plasma etching method in which an etching gas is turned into plasma and an SiC layer formed on an object to be processed is etched by the plasma. , it looks containing at least NF ₃ gas and He gas and Ar gas, and the SiOC layer to be treated is formed, with respect to the SiOC layer, characterized by selectively etching the SiC layer .

The plasma etching method of claim 2, in plasma etching method according to claim 2, wherein the SiOC layer is formed on the upper side of the SiC layer, the etching the SiC layer the SiOC layer as a mask Features.

The plasma etching method of claim 3, wherein, in the plasma etching method according to claim 1 or 2, characterized in that plasma etching is performed while cooling the object to be processed 30 ° C. or less.

The plasma etching method according to claim 4 is the plasma etching method according to any one of claims 1 to 3 , wherein the object to be processed is accommodated in a processing container, and the etching gas is resident in the etching gas. It introduce | transduces in the said processing container so that time may be set to 0.36 milliseconds-1.44 milliseconds.

The plasma etching method according to claim 5 is the plasma etching method according to any one of claims 1 to 4 , wherein the object to be processed is accommodated in a processing container, and the pressure in the processing container is 2 Pa to The pressure is reduced to 6 Pa.

The plasma etching method according to claim 6 is the plasma etching method according to any one of claims 1 to 5 , wherein the etching gas is a CF-based gas or CHF at a flow rate ratio of 1/2 or less to NF ₃ gas. System gas is included.

The plasma etching method of claim 7, wherein, in the plasma etching method according to any one of claims 1 to 6, the object to be processed is placed on the lower electrode, at a position opposed to the lower electrode A first high frequency power having a first frequency is supplied to the upper electrode disposed, and a second high frequency power having a second frequency lower than the first high frequency power is applied to the lower electrode. And performing plasma etching.

The plasma etching method according to claim 8 is the plasma etching method according to claim 7 , wherein a power density of the first high-frequency power applied to the upper electrode is 0.07 W / cm ^{2 to} 0.7 W. / Cm ² .

The plasma etching method according to claim 9 is the plasma etching method according to claim 7 , wherein the power density of the second high-frequency power applied to the lower electrode is 0.07 W / cm ^{2 to} 0.21 W. / Cm ² .

According to the present invention, it is possible to provide a plasma etching how that can be selectively etched with high SiC layer with respect SiOC layer.

  The details of the present invention will be described below with reference to the drawings.

  FIG. 1 shows an enlarged cross-sectional configuration of a semiconductor wafer W according to the present embodiment, and FIG. 2 shows a configuration of a plasma etching apparatus according to the present embodiment. First, the configuration of the plasma etching apparatus will be described with reference to FIG. The plasma etching apparatus 1 is configured as a capacitively coupled parallel plate etching apparatus in which electrode plates are opposed in parallel in the vertical direction, and a plasma forming power source is connected to one of them.

  The plasma etching apparatus 1 has a chamber (processing container) 2 made of, for example, aluminum whose surface is sprayed with yttria and formed in a cylindrical shape, and the chamber 2 is grounded. A substantially cylindrical susceptor support 4 for placing an object to be processed, for example, a semiconductor wafer W, is provided on the bottom of the chamber 2 via an insulating plate 3 such as ceramic. Further, a susceptor 5 constituting a lower electrode is provided on the susceptor support 4. A high pass filter (HPF) 6 is connected to the susceptor 5.

  A refrigerant chamber 7 is provided inside the susceptor support 4, and the refrigerant is introduced into the refrigerant chamber 7 through a refrigerant introduction pipe 8 and circulated, and the cold heat is transmitted through the susceptor 5 to the semiconductor wafer. Heat is transferred to W, whereby the semiconductor wafer W is controlled to a desired temperature.

  The upper center portion of the susceptor 5 is formed in a convex disk shape, and an electrostatic chuck 11 having substantially the same shape as the semiconductor wafer W is provided thereon. The electrostatic chuck 11 is configured by disposing an electrode 12 between insulating materials. Then, when a DC voltage of, for example, 1.5 kV is applied from the DC power source 13 connected to the electrode 12, the semiconductor wafer W is electrostatically attracted by, for example, Coulomb force.

  The insulating plate 3, the susceptor support 4, the susceptor 5, and the electrostatic chuck 11 are formed with gas passages 14 for supplying a heat transfer medium (for example, He gas) on the back surface of the semiconductor wafer W. The cold heat of the susceptor 5 is transmitted to the semiconductor wafer W via the heat transfer medium so that the semiconductor wafer W is maintained at a predetermined temperature.

  An annular focus ring 15 is disposed at the upper peripheral edge of the susceptor 5 so as to surround the semiconductor wafer W placed on the electrostatic chuck 11. The focus ring 15 is made of, for example, a conductive material such as silicon, and has an effect of improving etching uniformity.

  An upper electrode 21 is provided above the susceptor 5 so as to face the susceptor 5 in parallel. The upper electrode 21 is supported on the upper part of the chamber 2 via an insulating material 22 and forms a surface facing the susceptor 5 and has a large number of discharge holes 23. For example, the surface is anodized (anodized) The electrode plate 24 is formed by providing a quartz cover on the treated aluminum, and an electrode support 25 made of a conductive material that supports the electrode 24. The distance between the susceptor 5 and the upper electrode 21 can be changed.

A gas inlet 26 is provided in the center of the electrode support 25 in the upper electrode 21, and a gas supply pipe 27 is connected to the gas inlet 26. Further, a processing gas supply source 30 is connected to the gas supply pipe 27 via a valve 28 and a mass flow controller 29. An etching gas for plasma etching is supplied from the processing gas supply source 30. In the present embodiment, an etching gas containing at least NF ₃ , He, and Ar is supplied from the processing gas supply source 30.

  An exhaust pipe 31 is connected to the bottom of the chamber 2, and an exhaust device 35 is connected to the exhaust pipe 31. The exhaust device 35 includes a vacuum pump such as a turbo molecular pump, and is configured to be able to evacuate the chamber 2 to a predetermined reduced pressure atmosphere, for example, a predetermined pressure of 1 Pa or less. Further, a gate valve 32 is provided on the side wall of the chamber 2 so that the semiconductor wafer W is transferred to and from an adjacent load lock chamber (not shown) with the gate valve 32 opened. It has become.

  A first high frequency power supply 40 is connected to the upper electrode 21, and a matching device 41 is inserted in the feeder line. Further, a low pass filter (LPF) 42 is connected to the upper electrode 21. The first high frequency power supply 40 has a frequency in the range of 50 to 150 MHz. By applying such a high frequency, it is possible to form a high-density plasma in a preferable dissociated state in the chamber 2. The frequency of the first high-frequency power supply 40 is preferably 50 to 80 MHz, and typically the illustrated condition of 60 MHz or the vicinity thereof is adopted.

  A second high-frequency power source 50 is connected to the susceptor 5 serving as a lower electrode, and a matching unit 51 is interposed in the power supply line. The second high-frequency power supply 50 has a frequency in a range of frequencies lower than that of the first high-frequency power supply 40. By applying a frequency in such a range, the second high-frequency power supply 50 is applied to the semiconductor wafer W that is the object to be processed. Therefore, it is possible to give an appropriate ion action without damaging it. The frequency of the second high-frequency power supply 50 is preferably in the range of 1 to 20 MHz, and typically the conditions shown in the figure, 13.56 MHz or in the vicinity thereof, are employed.

  The operation of the plasma etching apparatus 1 having the above configuration is controlled by the control unit 60. The control unit 60 is provided with a recording medium in which a program indicating a control procedure is recorded. The control unit 60 controls the following etching processing operation in accordance with the program read from the recording medium. . Below, the case where the SiC layer formed in the semiconductor wafer W by the plasma etching apparatus 1 of the said structure is etched is demonstrated.

  First, after the gate valve 32 is opened, the semiconductor wafer W is loaded into the chamber 2 from a load lock chamber (not shown) and placed on the electrostatic chuck 11. The semiconductor wafer W is electrostatically attracted onto the electrostatic chuck 11 by applying a DC voltage from the high-voltage DC power supply 13. Next, the gate valve 32 is closed, and the inside of the chamber 2 is evacuated to a predetermined degree of vacuum by the exhaust device 35.

Thereafter, the valve 28 is opened, and an etching gas, for example, a mixed gas of NF ₃ / He / Ar, is supplied from the processing gas supply source 30 while the flow rate of the mixed gas is adjusted by the mass flow controller 29. The liquid is introduced into the hollow portion of the upper electrode 21 through the opening 26, and further uniformly discharged onto the semiconductor wafer W through the discharge holes 23 of the electrode plate 24 as indicated by the arrows in FIG.

  Then, the pressure in the chamber 2 is maintained at a predetermined pressure. Thereafter, high frequency power having a predetermined frequency is applied to the upper electrode 21 from the first high frequency power supply 40. As a result, a high-frequency electric field is generated between the upper electrode 21 and the susceptor 5 as the lower electrode, and the etching gas is dissociated into plasma.

  On the other hand, high frequency power having a frequency lower than that of the first high frequency power supply 40 is applied from the second high frequency power supply 50 to the susceptor 5 serving as the lower electrode. Thereby, ions in the plasma are drawn to the susceptor 5 side, and the anisotropy of etching is enhanced by ion assist.

  Then, when the predetermined etching process is completed, the supply of the high frequency power and the supply of the etching gas are stopped, and the semiconductor wafer W is unloaded from the chamber 2 by a procedure reverse to the procedure described above.

Next, the plasma etching method according to this embodiment will be described with reference to FIG.
As shown in FIG. 1A, an SiOC layer 101 is formed on the surface of a semiconductor wafer W as an object to be processed, and an SiC layer 102 is formed below the SiOC layer 101. A Cu wiring layer 103 is formed on the lower side.

Further, the SiOC layer 101 is formed with a trench 110 in which the SiOC layer 101 is linearly recessed along the horizontal direction in the figure, and an opening 111 for forming a via is formed at the bottom of the trench 110. Is formed. The opening 111 is formed by, for example, plasma etching using a resist as a mask and a mixed gas of CF-based gas, Ar gas, and O ₂ gas or the like as an etching gas, and then removing the resist by ashing using O ₂ gas. Thus, the state shown in FIG.

Then, from the state shown in FIG. 1A, as shown in FIG. 1B, plasma etching of the SiC layer 102 is performed using the SiOC layer 101 as a mask and a mixed gas of NF ₃ / He / Ar as an etching gas. Then, an opening 112 continuous to the opening 111 is formed, and a via 113 reaching the Cu wiring layer 103 is formed.

At this time, the etching selectivity of the SiC layer 102 with respect to the SiOC layer 101 can be increased by using a gas containing at least NF ₃ , He, and Ar as an etching gas.

As Example 1, the following etching conditions, NF ₃ / He / Ar = 4/240/200 sccm, pressure 6 Pa (45 mTorr), power (upper / lower) = 400/150 W, temperature (upper / side wall / lower) = Plasma etching was actually performed at 80/60/0 ° C., cooling helium pressure (center portion / peripheral portion) = 1330/1330 Pa (10/10 Torr), and electrode distance = 170 mm. As a result, the etching rate of SiC was 148 nm / min, the etching rate of SiOC was 9.0 nm / min, and the selectivity was 16.4.

  Next, the results of investigation on usable etching conditions in addition to the above etching conditions will be described. Under the above etching conditions, since the pressure is 6 Pa (45 mTorr), the total flow rate of the etching gas is 444 sccm, and the volume of the chamber 2 is 90 l, the residence time is 0.72 milliseconds.

When the total flow rate of the etching gas is halved (222 sccm), that is, when NF ₃ / He / Ar = 2/120/100 sccm, the residence time is 1.44 milliseconds. Etching was performed under the same flow rate of the etching gas as in Example 1 except that the etching rate of SiC was 108 nm / min, the etching rate of SiOC was 8.9 nm / min, and the selectivity was 12. 1

Further, when the total flow rate of the etching gas is doubled (888 sccm), that is, when NF ₃ / He / Ar = 8/480/400 sccm, the residence time is 0.36 milliseconds. In this case, the etching rate of SiC is Was 132 nm / min, the etching rate of SiOC was 30.0 nm / min, and the selectivity was 4.40.

  As described above, when the total flow rate increased and the residence time decreased, the etching rate of SiOC increased and the selectivity decreased. Moreover, when the total flow rate decreased and the residence time increased, the SiC etching rate tended to decrease. Therefore, the residence time is preferably about 0.72 milliseconds to 1.44 milliseconds, and preferably at least in the range of 0.36 milliseconds to 1.44 milliseconds.

Next, regarding the flow rate ratio of the etching gas, when the flow rate of Ar is decreased from the conditions of Example 1 to NF ₃ / He / Ar = 4/240/50 sccm, the flow rate of He is further increased from here. In the case of NF ₃ / He / Ar = 4/480/50 sccm, substantially the same selection ratio as in Example 1 was obtained. Therefore, the range of such a flow rate ratio is a usable range.

On the other hand, when the flow rate of Ar is 0 and NF ₃ / He / Ar = 6/120/0 sccm, the etching rate of SiC is 82 nm / min, the etching rate of SiOC is 62 nm / min, and the selection ratio is 1. 32. For this reason, addition of Ar is indispensable in order to ensure the selection ratio.

  Regarding the pressure, even when the pressure was 2 Pa (15 mTorr), a selection ratio substantially similar to that in Example 1 could be obtained. Therefore, the pressure can be used in the range of at least 2 to 6 Pa.

In addition, regarding the power applied to the upper electrode 21, when it was set to 50W, it was possible to obtain substantially the same selection ratio as in the case of Example 1 (in the case of 400W) when it was set to 500W. Therefore, the power applied to the upper electrode 21 can be at least in the range of 50W to 500W. In this case, since the diameter of the semiconductor wafer W is 300 mm, the power density is in the range of 0.07 W / cm ^{2 to} 0.7 W / cm ² .

On the other hand, regarding the power applied to the lower electrode (susceptor 5), when the power was 50W and 100W, a selection ratio substantially similar to that in Example 1 (150W) could be obtained. . Therefore, the power applied to the lower electrode (susceptor 5) can be in the range of at least 50W to 150W. In this case, since the diameter of the semiconductor wafer W is 300 mm, the power density is in the range of 0.07 W / cm ^{2 to} 0.21 W / cm ² .

  Next, the influence of the lower temperature (temperature of the susceptor 5) on the etching state will be described. When the lower temperature (the temperature of the susceptor 5) was 70 ° C. and 30 ° C., substantially the same selection ratio as in the case of 0 ° C. in Example 1 could be obtained. However, in the case of 70 ° C., as shown in FIG. 3, the shape of the side wall 112a of the opening 112 of the SiC layer 102 was not linear but curved outward. As described above, when the shape of the inner wall portion of the via 113 is curved outward, there arises a problem that a void is generated when a conductor such as copper is embedded thereafter.

  As for the shape of the side wall part 112a, the degree of bending was reduced at 30 ° C. than at 70 ° C., and the degree of bending was reduced at 0 ° C. than at 30 ° C. Thus, when the lower temperature (the temperature of the susceptor 5) is high, the shape of the side wall 112a of the opening 112 tends to be curved, and this tendency can be reduced by lowering the temperature. For this reason, in order to make the shape of the inner wall portion of the via 113 linear, the lower temperature (the temperature of the susceptor 5) is preferably 30 ° C. or less, and more preferably 0 ° C. or less.

In order to make the shape of the inner wall of the via 113 linear, it is preferable to add a CHF-based gas or a CF-based gas such as CH ₂ F ₂ to the etching gas. Actually, the etching gas was set to NF ₃ / He / Ar / CH ₂ F ₂ = 4/240/200/2 sccm, and the other etching conditions were the same as in Example 1. As a result, the shape of the side wall portion 112a was A linear via 113 could be obtained. However, in this case, the etching rate of SiC was 124 nm / min, the etching rate of SiOC was 54.9 nm / min, and the selection ratio was 2.26.

As described above, when CH ₂ F ₂ or the like is added to the etching gas, the shape of the side wall portion 112a can be made linear, but the etching rate of SiOC increases and the selection ratio decreases. For example, if the CH ₂ F ₂ additive is increased from ₂ sccm to 4 sccm and the flow rate is the same as the flow rate of NF ₃ , the selection ratio is. 1.90 and less than 2. For this reason, it is preferable that the CHF-based gas or the CF-based gas has a flow rate of ½ or less of the flow rate of NF ₃ .

The figure which expands and shows the principal part structure of the semiconductor wafer which concerns on one Embodiment of this invention. The figure which shows schematic structure of the plasma etching apparatus used for embodiment of this invention. The figure for demonstrating the shape of the side wall part of an opening part.

Explanation of symbols

  W ... Semiconductor wafer, 101 ... SiOC layer, 102 ... SiC layer, 103 ... Copper wiring layer, 110 ... Trench, 111 ... Opening of SiOC layer, 112 ... Opening of SiC layer, 113 ... Via.

Claims (9)

A plasma etching method for converting an etching gas into a plasma and etching a SiC layer formed on a workpiece by the plasma,
The etching gas, see contains at least NF ₃ gas and He gas and Ar gas,
And the SiOC layer is formed in the said to-be-processed object, The said SiC layer is selectively etched with respect to the said SiOC layer, The plasma etching method characterized by the above-mentioned . The plasma etching method according to claim 1 , wherein
A plasma etching method, wherein the SiOC layer is formed on the SiC layer, and the SiC layer is etched using the SiOC layer as a mask. In the plasma etching method according to claim 1 or 2 ,
A plasma etching method comprising performing plasma etching while cooling the object to be processed at 30 ° C. or lower. In the plasma etching method according to any one of claims 1 to 3 ,
The plasma is characterized in that the object to be processed is accommodated in a processing container, and the etching gas is introduced into the processing container so that a residence time of the etching gas is 0.36 milliseconds to 1.44 milliseconds. Etching method. In the plasma etching method according to any one of claims 1 to 4 ,
A plasma etching method, wherein the object to be processed is accommodated in a processing container, and the pressure in the processing container is reduced to 2 Pa to 6 Pa. In the plasma etching method according to any one of claims 1 to 5 ,
The plasma etching method, wherein the etching gas contains a CF-based gas or a CHF-based gas at a flow rate ratio of 1/2 or less with respect to the NF ₃ gas. In the plasma etching method according to any one of claims 1 to 6 ,
The object to be processed is placed on the lower electrode, a first high-frequency power having a first frequency is supplied to the upper electrode disposed at a position facing the lower electrode, and the first electrode is supplied to the lower electrode. A plasma etching method comprising performing plasma etching by applying a second high frequency power having a second frequency lower than that of the high frequency power. The plasma etching method according to claim 7 , wherein
A plasma etching method, wherein a power density of the first high-frequency power applied to the upper electrode is 0.07 W / cm ^{2 to} 0.7 W / cm ² . The plasma etching method according to claim 7 , wherein
A plasma etching method, wherein a power density of the second high-frequency power applied to the lower electrode is 0.07 W / cm ^{2 to} 0.21 W / cm ² .

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