JP4610426B2 - 回路装置の製造方法 - Google Patents
回路装置の製造方法 Download PDFInfo
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- JP4610426B2 JP4610426B2 JP2005189223A JP2005189223A JP4610426B2 JP 4610426 B2 JP4610426 B2 JP 4610426B2 JP 2005189223 A JP2005189223 A JP 2005189223A JP 2005189223 A JP2005189223 A JP 2005189223A JP 4610426 B2 JP4610426 B2 JP 4610426B2
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- circuit board
- lead
- circuit
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
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- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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Description
本形態では、回路装置の一例として混成集積回路装置10の構造を説明する。
本形態では、図4から図6を参照して、混成集積回路装置10の製造方法を説明する。本形態の製造方法では、多数個のリード25が設けられたリードフレーム40を用いて、混成集積回路装置10を製造する。また、製造工程の途中段階に於いては、リード25Aが機械的に回路基板11に接続することにより、回路基板11はリードフレーム40に保持されている。
本形態では、図7から図9を参照して、混成集積回路装置10の他の製造方法を説明する。本形態の概略は上述した第2の実施の形態と同様であり、相違点はリードフレーム40にランド45を設けた点にある。このランド45は、回路基板11の裏面に貼着される。回路基板11の裏面にランド45が貼着されることにより、封止樹脂を形成する工程に於いて、回路基板11の下方にボイドが発生することが抑制される。更には、図3に示すような、外部に露出する金属基板16(ランド45)が回路基板11の裏面に形成された混成集積回路装置10を製造することができる。
11 回路基板
12A 第1の絶縁層
12B 第2の絶縁層
13 導電パターン
13A パッド
14 封止樹脂
15A 半導体素子
15B チップ素子
16 金属基板
17 金属細線
18 固定部
19 メッキ膜
21 放熱フィン
22A 上金型
22B 下金型
23 キャビティ
24 メッキ膜
25 リード
25A リード
31 突起部
40 リードフレーム
41 外枠
42A、42B 接続部
43 吊りリード
44 タイバー
45 ランド
46 ユニット
Claims (4)
- 吊りリードにより外枠と連結されたランドと、前記ランドに一端が近接して配置された複数個のリードとを有するリードフレームに、導電パターン、前記導電パターンから成るパッドおよび前記導電パターンと接続された回路素子が表面に形成された回路基板を前記ランドに載置し、
少なくとも2つの前記リードを、前記回路基板を厚み方向に部分的に突出して設けた突起部にかしめ、
前記回路基板の周辺部に対応する領域の前記吊りリードを部分的に除去し、
前記突起部を介して前記回路基板を前記リードフレームに対して固定した状態で、前記回路基板の少なくとも表面を絶縁性樹脂により封止する事を具備することを特徴とする回路装置の製造方法。 - 前記吊りリードを除去した後、前記突起部にかしめられた前記リードを介して、前記回路基板を支持することを特徴とする請求項1に記載の回路装置の製造方法。
- 前記ランドは前記基板よりも小さく形成され、
前記ランドにより被覆されない前記回路基板の裏面を前記封止樹脂により被覆することを特徴とする請求項1に記載の回路装置の製造方法。 - 前記ランドの裏面を下金型に当接させ、前記ランドにより被覆されない前記回路基板の裏面を前記封止樹脂により被覆することを特徴とする請求項3に記載の回路装置の製造方法。
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JP2005189223A JP4610426B2 (ja) | 2005-06-29 | 2005-06-29 | 回路装置の製造方法 |
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JP2005189223A JP4610426B2 (ja) | 2005-06-29 | 2005-06-29 | 回路装置の製造方法 |
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JP2007012731A JP2007012731A (ja) | 2007-01-18 |
JP4610426B2 true JP4610426B2 (ja) | 2011-01-12 |
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JP2005189223A Expired - Fee Related JP4610426B2 (ja) | 2005-06-29 | 2005-06-29 | 回路装置の製造方法 |
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Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2016181536A (ja) * | 2015-03-23 | 2016-10-13 | 住友ベークライト株式会社 | パワー半導体装置 |
AU2020284538B2 (en) | 2019-05-28 | 2022-03-24 | PAIGE.AI, Inc. | Systems and methods for processing images to prepare slides for processed images for digital pathology |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS564243A (en) * | 1979-06-25 | 1981-01-17 | Hitachi Ltd | Semiconductor device and assembly method thereof |
JPH05326808A (ja) * | 1992-05-15 | 1993-12-10 | Ibiden Co Ltd | 電子部品搭載用基板およびこれを用いた半導体装置 |
JPH06132457A (ja) * | 1992-10-15 | 1994-05-13 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JPH06295972A (ja) * | 1993-04-07 | 1994-10-21 | Nippondenso Co Ltd | ハイブリッドicのリードフレームの位置決め構造及びハイブリッドicの製造方法 |
JPH1074880A (ja) * | 1996-06-28 | 1998-03-17 | Goto Seisakusho:Kk | ヒートシンクを備えた樹脂封止型半導体装置及びその製造方法 |
-
2005
- 2005-06-29 JP JP2005189223A patent/JP4610426B2/ja not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS564243A (en) * | 1979-06-25 | 1981-01-17 | Hitachi Ltd | Semiconductor device and assembly method thereof |
JPH05326808A (ja) * | 1992-05-15 | 1993-12-10 | Ibiden Co Ltd | 電子部品搭載用基板およびこれを用いた半導体装置 |
JPH06132457A (ja) * | 1992-10-15 | 1994-05-13 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JPH06295972A (ja) * | 1993-04-07 | 1994-10-21 | Nippondenso Co Ltd | ハイブリッドicのリードフレームの位置決め構造及びハイブリッドicの製造方法 |
JPH1074880A (ja) * | 1996-06-28 | 1998-03-17 | Goto Seisakusho:Kk | ヒートシンクを備えた樹脂封止型半導体装置及びその製造方法 |
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