JP4597627B2 - Wiring board manufacturing method - Google Patents

Description

  The present invention relates to a wiring substrate using a droplet discharge method, a manufacturing method thereof, a thin film transistor, and a manufacturing method thereof.

In recent years, the droplet discharge method has been applied to the field of flat panel displays and has been actively developed. The droplet discharge method has many advantages such as no need for a mask for direct drawing, easy application to a large substrate, and high material utilization efficiency, and is applied to the production of electrodes for color filters and plasma displays. (For example, refer nonpatent literature 1).
T.Shimoda, Ink-jet Technology for Fabrication Processes of Flat Panel Displays, SID 03 DIGEST, p1178-p1181

  When forming a wiring board by the droplet discharge method, a composition in which the particles are made in nano order is used, but the thin film formed by the above composition has low adhesion to the lower layer thin film. Its peelability is high. For this reason, when a wet process such as a cleaning process that is essential for a semiconductor process is performed, the formed pattern may be peeled off.

  Further, when the composition is discharged from the tip of the nozzle, a phenomenon called a Leonard phenomenon occurs. This phenomenon is a phenomenon in which the composition to be discharged is positively charged due to a bias in charge. As described above, it is considered that the thin film to which the composition adheres may be damaged or destroyed by the electric charge charged in the composition.

  In view of the above circumstances, an object of the present invention is to provide a wiring board with improved adhesion and peel resistance and a method for manufacturing the wiring board. It is another object of the present invention to provide a wiring board that prevents damage and destruction of a thin film to which the composition adheres and a method for manufacturing the wiring board. It is another object of the present invention to provide a thin film transistor having improved adhesion and peel resistance and a method for manufacturing the same, by using the wiring board and the method for manufacturing the wiring substrate.

  In order to solve the above-described problems of the prior art, the following measures are taken in the present invention.

  In the method for manufacturing a wiring board of the present invention, the first step of forming a first conductive layer in contact with the insulating layer and made of a refractory metal, and discharging the composition containing a conductive material, It has the 2nd step of forming the 2nd conductive layer which touches a conductive layer, It is characterized by the above-mentioned. In the present invention, the first conductive layer is formed before the second conductive layer is formed by a droplet discharge method, thereby improving the adhesion and peeling resistance of the second conductive layer. Furthermore, since the insulating layer is covered with the first conductive layer, the insulating layer is prevented from being damaged or broken.

  In the method for manufacturing a wiring board according to the present invention, a first step of forming a first conductive layer made of a refractory metal in contact with an insulating layer provided with an opening, and a composition containing a conductive material are discharged. And a second step of forming a second conductive layer filling the opening. This feature improves the adhesion and peel resistance of the second conductive layer. In addition, damage and destruction of the insulating layer are prevented. Further, according to this structure, the first conductive layer functions as a barrier layer and prevents intrusion of impurities from the insulating layer.

  The present invention is characterized in that a first conductive layer made of a refractory metal is formed between an insulating layer and a second conductive layer, and the refractory metal includes Ti (titanium) and W (tungsten). Cr (chromium), Al (aluminum), Ta (tantalum), Ni (nickel), Zr (zirconium), Hf (hafnium), V (vanadium), Ir (iridium), Nb (niobium), Pd (lead) , Pt (platinum), Mo (molybdenum), Co (cobalt), or Rh (rhodium). The first conductive layer is formed by a known method such as a sputtering method, a vapor deposition method, an ion implantation method, a CVD method, a dip method, or a spin coating method. It forms by a method or a spin coat method. In addition, when the first conductive layer is insulated later, it is convenient and preferable that the first conductive layer is formed with a thickness of 0.01 to 10 nm and insulated by natural oxidation.

  In the present invention, the insulating layer is formed of a silicon oxide material or a nitride material. This is due to the fact that the dielectric constant of the thin film formed of the above material is suitable as a gate insulating film.

  In the present invention, the insulating layer provided with the opening is formed using an organic material or a material in which a skeleton structure is formed by a bond of silicon and oxygen. Since the organic material has excellent flatness, the film thickness is not extremely reduced at the step portion or disconnection occurs even when the conductor is formed later. Organic materials have a low dielectric constant. Therefore, when used as an interlayer insulator for a plurality of wirings, the wiring capacity is reduced, multilayer wiring can be formed, and high performance and high functionality are realized.

On the other hand, a typical example of a material in which a skeleton structure is formed by a bond of silicon and oxygen is a siloxane polymer. Specifically, a skeleton structure is formed by a bond of silicon and oxygen, and at least hydrogen is added to a substituent. Or a material having at least one of fluorine, an alkyl group, and an aromatic hydrocarbon as a substituent. This material is also excellent in flatness, has transparency and heat resistance, and can be subjected to heat treatment at a temperature of about 300 ° C. to 600 ° C. or less after forming an insulator made of a siloxane polymer. By this heat treatment, for example, hydrogenation and baking treatment can be performed simultaneously.
In the present invention, the insulating layer provided with the opening is formed to a thickness of 100 nm to 2 μm. This is because the insulating layer is provided with an opening for connecting the lower layer pattern and the upper layer pattern.

  In the present invention, the second conductive layer is formed of a composition containing silver, gold, copper, or indium tin oxide. These materials can process molecules in nano order, and if these particles are dispersed in a solvent, they can be drawn easily by a droplet discharge method.

  In the present invention, after the second step, there is a step of insulating the first conductive layer that is not in contact with the second conductive layer. Alternatively, the method includes a step of etching the first conductive layer that is not in contact with the second conductive layer. The above process is for preventing a short circuit of a plurality of elements and wirings, and is performed as necessary. In the case of using an insulating step, as described above, it is convenient and preferable that the first conductive layer is formed with a thickness of 0.01 to 10 nm and insulated by natural oxidation.

  In addition, the present invention is characterized in that a thin film transistor is formed using the second conductive layer completed through the above steps as a gate electrode and the insulating layer as a gate insulating film.

  The wiring substrate of the present invention is in contact with an insulating layer made of a silicon oxide material, a silicon nitride material, an organic material, a material in which a skeleton structure is formed by a bond of silicon and oxygen, and is made of a first refractory metal. And a second conductive layer made of silver, gold, copper, or indium tin oxide in contact with the first conductive layer. The first conductive layer is preferably formed with a thickness of 0.01 to 10 nm, and the refractory metal includes Ti, W, Cr, Al, Ta, Ni, Zr, Hf, V, Ir, Nb, Pd, Pt, Mo, Co, or Rh. Furthermore, the present invention provides a thin film transistor in which the insulating layer is a gate insulating film and the second conductive layer is a gate electrode. The wiring substrate and the thin film transistor having the above laminated structure have good adhesion and peeling resistance, and do not peel even after a wet process.

  The wiring board of the present invention includes an insulating layer provided on the substrate, a first conductive layer in contact with the insulating layer, and a second conductive layer in contact with the first conductive layer, The insulating layer includes an oxide or nitride material of silicon, the first conductive layer includes a refractory metal, and the second conductive layer includes silver, gold, copper, or indium tin oxide. It is characterized by that.

  The wiring board of the present invention includes an insulating layer provided on the substrate, a first conductive layer in contact with the insulating layer, and a second conductive layer in contact with the first conductive layer, The insulating layer includes an organic material or a material in which a skeleton structure is formed by a combination of silicon and oxygen, the first conductive layer includes a refractory metal, and the second conductive layer includes silver, gold, It has copper or indium tin oxide.

  Improves adhesion and peel resistance of a conductive layer formed by a droplet discharge method. In addition, damage and destruction of the underlying thin film are prevented.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in common in different drawings.
(Embodiment 1)

An embodiment of the present invention will be described with reference to FIG. As the substrate 10, a glass substrate made of barium borosilicate glass, alumino borosilicate glass, or the like, a quartz substrate, a silicon substrate, a metal substrate, a stainless steel substrate, or a plastic substrate having heat resistance that can withstand the processing temperature in this manufacturing process is used (see FIG. 1 (A)).
Next, the insulating layer 11 is formed on the substrate 10. The insulating layer 11 is formed as a single layer or a stacked layer using an oxide material or a nitride material containing silicon by a known method such as a CVD method, a plasma CVD method, a sputtering method, or a spin coating method.

Subsequently, a first conductive layer 12 is formed on the insulating layer 11. The first conductive layer 12 is formed by a known method such as a sputtering method or a vapor deposition method. The first conductive layer 12 is formed of a refractory metal material such as Ti, W, Cr, Al, Ta, Ni, Zr, Hf, V, Ir, Nb, Pd, Pt, Mo, Co, or Rh. It is characterized by.
Note that when the step of naturally oxidizing the first conductive layer 12 is performed later, the first conductive layer 12 is formed with a thickness of 0.01 to 10 nm. However, the thickness of 0.01 nm is very thin and may not take the form of a thin film. However, the first conductive layer 12 referred to here does not take the form of a thin film. It also includes the state. Moreover, in order to form the first conductive layer 12 thinner, it is preferable to form the first conductive layer 12 by a sputtering method.

  Next, the second conductive layer 13 is formed by discharging a composition containing a conductive material. The formation of the second conductive layer 13 is performed using the droplet discharge means 14. The droplet discharge means 14 is a general term for a device having means for discharging droplets such as a nozzle having a composition discharge port and a head having one or a plurality of nozzles. The nozzle diameter of the droplet discharge means 14 is set to 0.02 to 100 μm (preferably 30 μm or less), and the discharge amount of the composition discharged from the nozzle is 0.001 pl to 100 pl (preferably 10 pl or less). The discharge amount increases in proportion to the size of the nozzle diameter. In addition, the distance between the object to be processed and the nozzle outlet is preferably as close as possible in order to drop it at a desired location, preferably about 0.1 to 3 mm (preferably about 1 mm or less). Set.

  When the composition is discharged from the droplet discharge means 14, the composition of the composition tends to be positively charged due to the bias of the charge. The insulating layer 11 may be destroyed by the charged charge. is there. However, since the insulating layer 11 is covered with the first conductive layer 12, such damage and destruction can be prevented.

A composition in which a conductive material is dissolved or dispersed in a solvent is used as the composition discharged from the discharge port. Conductive materials include metals such as Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, and Al, metal sulfides of Cd, Zn, Fe, Ti, Si, Ge, Si, Zr, Ba It corresponds to oxides such as silver halide fine particles or dispersible nanoparticles. Further, it corresponds to indium tin oxide (ITO) used as a transparent conductive film, ITSO composed of indium tin oxide and silicon oxide, organic indium, organic tin, zinc oxide, titanium nitride, and the like.
However, it is preferable to use a composition in which any of gold, silver and copper is dissolved or dispersed in a solvent in consideration of the specific resistance value, more preferably the composition discharged from the discharge port. It is preferable to use low resistance silver or copper. However, when silver or copper is used, a barrier film may be provided as a countermeasure against impurities. As the solvent, esters such as butyl acetate and ethyl acetate, alcohols such as isopropyl alcohol and ethyl alcohol, organic solvents such as methyl ethyl ketone and acetone are used. The viscosity of the composition is preferably 50 cp or less, in order to prevent the drying from occurring or to smoothly discharge the composition from the discharge port. The surface tension of the composition is preferably 40 mN / m or less. However, the viscosity and the like of the composition may be appropriately adjusted according to the solvent to be used and the application. As an example, the viscosity of a composition in which ITO, organic indium, or organic tin is dissolved or dispersed in a solvent is 5 to 50 mPa · S, the viscosity of a composition in which silver is dissolved or dispersed in a solvent is 5 to 20 mPa · S, The viscosity of the composition in which gold is dissolved or dispersed in a solvent is preferably set to 10 to 20 mPa · S.

  Although depending on the diameter of each nozzle and the desired pattern shape, the diameter of the conductor particles is preferably as small as possible for preventing nozzle clogging and producing a high-definition pattern. 1 μm or less is preferable. The composition is formed by a known method such as an electrolytic method, an atomizing method, or a wet reduction method, and its particle size is generally about 0.01 to 10 μm. However, when formed in a gas evaporation method, the nanomolecules protected with the dispersant are as fine as about 7 nm. When the surface of each particle is covered with a coating agent, the nanoparticles are aggregated in the solvent. And stably disperse at room temperature and shows almost the same behavior as liquid. Therefore, it is preferable to use a coating agent.

  When the step of discharging the composition is performed under reduced pressure, the solvent of the composition is volatilized between the time of discharging the composition and landing on the object to be processed, and the subsequent drying and baking steps are omitted. be able to. Further, it is preferable to perform under reduced pressure because an oxide film or the like is not formed on the surface of the conductor. In addition, after discharging the composition, one or both steps of drying and baking are performed. The drying and baking steps are both heat treatment steps. For example, drying is performed at 100 degrees for 3 minutes, and baking is performed at 200 to 350 degrees for 15 minutes to 30 minutes. Time is different. The drying process and the firing process are performed under normal pressure or reduced pressure by laser light irradiation, rapid thermal annealing, a heating furnace, or the like. In addition, the timing which performs this heat processing is not specifically limited. In order to satisfactorily perform the drying and firing steps, the substrate may be heated, and the temperature at that time depends on the material of the substrate or the like, but is generally 100 to 800 degrees (preferably 200). ~ 350 degrees). By this step, the solvent in the composition is volatilized or the dispersant is chemically removed, and the surrounding resin is cured and contracted to bring the nanoparticles into contact with each other, thereby accelerating fusion and fusion.

For the laser light irradiation, a continuous wave or pulsed gas laser or solid-state laser may be used. Examples of the former gas laser include an excimer laser and a YAG laser, and examples of the latter solid laser include a laser using a crystal such as YAG or YVO ₄ doped with Cr, Nd, or the like. Note that it is preferable to use a continuous wave laser because of the absorption rate of the laser light. Alternatively, a hybrid laser irradiation method combining pulse oscillation and continuous oscillation may be used. However, depending on the heat resistance of the substrate 10, the heat treatment by laser light irradiation may be performed instantaneously within a few microseconds to several tens of seconds so that the substrate 10 is not destroyed.
Instantaneous thermal annealing (RTA) uses an infrared lamp or a halogen lamp that irradiates ultraviolet light or infrared light in an inert gas atmosphere, and rapidly raises the temperature for several minutes to several microseconds. This is done by applying heat instantaneously. Since this treatment is performed instantaneously, only the outermost thin film can be heated substantially without affecting the lower layer film. That is, it does not affect a substrate having low heat resistance such as a plastic substrate.

Through the above steps, the insulating layer 11, the first conductive layer 12, and the second conductive layer 13 are completed. If the first conductive layer 12 is still covered on the insulating layer 11 and there is a possibility that an element or wiring may be short-circuited, either of the following two steps is performed. Do.
One is a step of insulating the first conductive layer 12 that does not overlap with the second conductive layer 13 to form the insulating layer 16 (see FIG. 1C). More specifically, the first conductive layer 12 that does not overlap the second conductive layer 13 is oxidized and insulated. As described above, when the first conductive layer 12 is insulated, it is preferable to form the first conductive layer 12 with a thickness of 0.01 to 10 nm. It becomes an insulating layer. As a method of natural oxidation, a method of exposing to an oxygen atmosphere or a method of performing heat treatment may be used.
The other is a step of forming the conductive layer 17 by etching the first conductive layer 12 using the second conductive layer 13 as a mask (see FIG. 1D).

  The second conductive layer formed as described above may be used as a wiring, or the second conductive layer 13 may be used as a gate electrode and the insulating layer 11 may be used as a gate insulating film as one component of a thin film transistor. Good. Note that a protective film may be formed so as to cover the conductive layer completed through the above steps, and the protective film may be formed of a known material such as a silicon oxide material or a nitride material. Preferably, a silicon nitride film having a dense film quality is used.

As described above, the present invention in which the first conductive layer 12 is formed between the insulating layer 11 and the second conductive layer 13 formed by a droplet discharge method improves adhesion and peel resistance. In addition, damage and destruction of the underlying thin film can be prevented.
(Embodiment 2)

  An embodiment of the present invention will be described with reference to FIG. As the substrate 20, a glass substrate, a quartz substrate, or the like is used (FIG. 2A). Next, a conductor layer (also referred to as a conductor layer or a conductive layer) or a semiconductor layer 21 is formed over the substrate 20. Here, the semiconductor layer 21 is illustrated. Note that a base film may be formed over the substrate 20 in order to prevent impurities from entering from the substrate 20 as necessary.

  Next, the insulating layer 22 is formed on the substrate 20. The insulating layer 22 has a thickness of 50 nm to 5 μm (preferably 100 nm to 2 μm) using a known method such as plasma CVD, sputtering, SOG (Spin On Glass), spin coating, or droplet discharge. It will be formed. Examples of the material for the insulating layer 22 include silicon-containing materials such as a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, and a silicon oxynitride film, and organic materials such as acrylic, benzocyclobutene, parylene, flare, and transparent polyimide. A material, a compound material obtained by polymerization of a siloxane polymer, a composition containing a water-soluble homopolymer and a water-soluble copolymer, or the like is used.

Since the organic material has excellent flatness, the film thickness is not extremely reduced at the step portion or disconnection occurs even when the conductor is formed later. Organic materials have a low dielectric constant. Therefore, when used as an interlayer insulator for a plurality of wirings, the wiring capacity is reduced, multilayer wiring can be formed, and high performance and high functionality are realized. However, the organic material is preferably formed of a thin film of an inorganic material containing silicon in the lower layer and the upper layer in order to prevent outgassing. Specifically, a silicon nitride oxide film or a silicon nitride film is preferably formed by a plasma CVD method or a sputtering method.
A siloxane-based polymer is a material having a skeleton structure formed of a bond of silicon and oxygen and containing at least hydrogen as a substituent, or a material having at least one of fluorine, an alkyl group, or an aromatic hydrocarbon as a substituent. These are given as representative examples, and various materials within the above conditions can be used. This siloxane-based polymer is excellent in flatness, has transparency and heat resistance, and can be heat-treated at a temperature of about 300 ° C. to 600 ° C. or less after forming an insulator made of a siloxane polymer. . By this heat treatment, for example, hydrogenation and baking treatment can be performed simultaneously.

  Next, the insulating layer 22 is patterned using a photolithography technique to form an opening (contact hole) 23. Either wet etching or dry etching may be used, but when dry etching is used, the opening 23 having a high aspect ratio (3 or more) can be formed. The method should be used. The mask used when forming the opening 23 may be formed by a droplet discharge method using an organic material such as polyimide or acrylic.

  Note that the opening 23 may be formed by a droplet discharge method instead of a photolithography technique. In this case, the wet etching solution is discharged from a nozzle. However, in order to control the aspect ratio of the opening 23, a step of appropriately washing with a solvent such as water may be added. Of course, this cleaning process can also be performed continuously using the same device by replacing the droplets discharged from the nozzles with water or replacing the head filled with the solution using the droplet discharge method. From the viewpoint of processing time, it is preferable. After forming the opening 23 by any of the above methods, the lower semiconductor layer 21 is exposed.

Subsequently, a first conductive layer 24 is formed on the insulating layer 22. The first conductive layer 24 is formed by a known method such as a sputtering method, a vapor deposition method, or a spin coating method. The first conductive layer 24 is formed of a material of Ti, W, Cr, Al, Ta, Ni, Zr, Hf, V, Ir, Nb, Pd, Pt, Mo, Co, or Rh. .
Note that when the step of naturally oxidizing the first conductive layer 24 is performed later, the first conductive layer 24 is formed with a thickness of 0.01 to 10 nm. However, the thickness of 0.01 nm is very thin and may not take the form of a thin film. However, the first conductive layer 24 referred to here does not take the form of a thin film. It also includes the state. Further, in order to form the first conductive layer 24 thinner, it is preferable to form it by a sputtering method.

  The first conductive layer 24 not only improves adhesion between the second conductive layer 25 and the insulating layer 22 to be formed later, but also functions as a barrier layer, imparts embeddability, and further has contact resistance. Reduction and stabilization. In particular, when the second conductive layer 25 to be formed later is made of silver or copper, the formation of the first conductive layer 24 is effective as a countermeasure against impurities.

  Next, a composition containing a conductive material is discharged to form the second conductive layer 25. The formation of the second conductive layer 25 is performed using the droplet discharge means 26. When the composition is discharged from the droplet discharge means 26, the composition of the composition tends to be positively charged due to the bias of the charge, and the charged layer may destroy the insulating layer 22. is there. However, since the insulating layer 22 is covered with the first conductive layer 24, such damage and destruction can be prevented.

Through the above steps, the insulating layer 22, the first conductive layer 24, and the second conductive layer 25 are completed. If the first conductive layer 24 remains covered on the insulating layer 22 and there is a possibility that an element or wiring may be short-circuited, one of the following two steps is performed. Do.
One is a step of insulating the first conductive layer 24 that does not overlap with the second conductive layer 25 to form the insulating layer 27 (see FIG. 2C). Specifically, the first conductive layer 24 that does not overlap the second conductive layer 25 is oxidized and insulated. As described above, when the first conductive layer 24 is insulated, it is preferable to form the first conductive layer 24 with a thickness of 0.01 to 10 nm. It becomes an insulating layer. As a method of natural oxidation, a method of exposing to an oxygen atmosphere or a method of performing heat treatment may be used.
The other is a step of forming the conductive layer 28 by etching the first conductive layer 24 using the second conductive layer 25 as a mask (see FIG. 2D).

  The second conductive layer formed as described above is preferably used as a wiring connecting the upper layer and the lower layer. Although not shown in the drawing, a multilayer wiring can be formed by laminating conductive layers formed according to the present invention. The multilayer wiring is suitable for use in a functional circuit that needs to incorporate a large number of semiconductor elements such as a CPU (Central Processing Unit), enables high integration, realizes a large size reduction, and further leads the wiring. Since it is not necessary, high speed is realized. Note that a protective film may be formed so as to cover the conductive layer completed through the above steps, and the protective film may be formed of a known material such as a silicon oxide material or a nitride material. Preferably, a silicon nitride film having a dense film quality is used.

As described above, the present invention in which the first conductive layer 24 is formed between the insulating layer 22 and the second conductive layer 25 formed by a droplet discharge method improves adhesion and peel resistance. In addition, damage and destruction of the underlying thin film can be prevented. This embodiment mode can be freely combined with the above embodiment modes.
(Embodiment 3)

  An embodiment of the present invention will be described with reference to FIGS. More specifically, a method for manufacturing a thin film transistor to which the present invention is applied and a method for manufacturing a display device using the thin film transistor are described. First, a method for manufacturing a channel-etched thin film transistor and a method for manufacturing a display device using the thin film transistor, in which the present invention is applied to manufacturing a gate electrode and a source / drain wiring, are described with reference to FIGS. I will explain. The channel etch type transistor is a transistor using an amorphous semiconductor (amorphous silicon, a-Si) as a channel portion.

  A refractory metal material such as Ti, W, Cr, Al, Ta, Ni, Zr, Hf, V, Ir, Nb, Pd, Pt, Mo, Co, or Rh is formed on the substrate 200 by a known method. The layer 201 is formed (see FIG. 3A). Next, a conductive layer 202 which functions as a gate electrode later is formed by discharging a composition containing a conductive material. The conductive layer 202 is formed by using a droplet discharge unit. Next, the insulating layer 219 is formed by insulating a portion of the conductive layer 201 that does not overlap with the conductive layer 202. Note that when a process of naturally oxidizing the conductive layer 201 is performed later, the conductive layer 201 is formed with a thickness of 0.01 to 10 nm.

  Next, an insulating layer 203 functioning as a gate insulating film, an amorphous semiconductor layer 204, and an N-type amorphous semiconductor layer 205 are stacked (see FIG. 3B). Subsequently, a mask 206 made of an insulating material such as resist or polyimide is formed, and the amorphous semiconductor layer 204 and the N-type amorphous semiconductor layer 205 are simultaneously patterned using the mask 206 to form an amorphous material. A semiconductor layer 207 and an N-type amorphous semiconductor layer are formed. After removing the mask 206, a composition containing a conductive material is discharged to form conductive layers 210 and 211, and the N-type amorphous semiconductor layer is patterned using the conductive layers 210 and 211 as a mask. N-type amorphous semiconductor layers 208 and 209 are formed (see FIG. 3C). Note that although not shown, a conductive layer made of a refractory metal may be formed before forming the conductive layers 210 and 211, so that the peel resistance and adhesion of the conductive layers 210 and 211 are improved.

  Through the above steps, a channel etch type thin film transistor is completed. Next, the insulating layers 212, 213, and 214 are stacked, and openings are formed in these insulating layers using a photolithography technique (see FIG. 3D). The insulating layer 213 is preferably formed of a compound material made by polymerization of an organic material, a siloxane-based polymer, or the like. When an organic material is used, a thin film is preferably formed using an inorganic material containing silicon in the insulating layers 212 and 214 in order to prevent outgassing.

  After that, a conductive layer 215 is formed on the insulating layer 214 with a material of Ti, W, Cr, Al, Ta, Ni, Zr, Hf, V, Ir, Nb, Pd, Pt, Mo, Co, or Rh. Note that in the case where the step of naturally oxidizing the conductive layer 215 is performed later, the conductive layer 215 is formed with a thickness of 0.01 to 10 nm. Next, a conductive layer 225 is formed by discharging a composition containing a conductive material. The conductive layer 225 is also formed using a droplet discharge means. Next, the insulating layer 216 is formed by insulating a portion of the conductive layer 215 that does not overlap with the conductive layer 225.

  Next, a composition containing a conductive material is discharged so as to be in contact with the conductive layer 225 to form conductive layers 217 and 218 (see FIG. 5A). The conductive layers 217 and 218 are formed using a light-transmitting conductive material. Specifically, the conductive layers 217 and 218 are formed using ITSO including indium tin oxide, ITO, and silicon oxide. Subsequently, an insulating layer 223 serving as a bank is formed, and an electroluminescent layer 220, a conductive layer 221, and a shield 222 are stacked so as to be in contact with the conductive layer 218, and a display device having a display function using a light-emitting element Is completed. In the above structure, the transistor for driving the light-emitting element is an N-type transistor, the conductive layer 218 corresponds to a cathode, and the conductive layer 221 corresponds to an anode. Then, the light emitted from the light emitting element is emitted to the substrate 200 side, and a display device that performs bottom emission is completed. In the above manufacturing process, before the conductive layers 202 and 225 are formed by a droplet discharge method, the conductive layers 201 and 215 are formed, thereby improving the adhesion and peeling resistance of the conductive layers 202 and 225. It is possible to prevent damage and destruction of the underlying thin film. The conductive layer 215 also functions as a barrier film.

  Next, a method for manufacturing a channel protective thin film transistor in which the present invention is applied to manufacturing a gate electrode and a method for manufacturing a display device using the thin film transistor will be described with reference to FIGS. The channel protection type transistor is a transistor using an amorphous semiconductor as a channel portion.

  A conductive layer 251 is formed using a refractory metal material over the substrate 250 (see FIG. 4A). Next, a composition containing a conductive material is discharged, so that a conductive layer 252 that functions as a gate electrode later is formed. The conductive layer 252 is formed using a droplet discharge unit. Next, the insulating layer 262 is formed by oxidizing a portion of the conductive layer 251 that does not overlap with the conductive layer 252. Note that in the case where the step of naturally oxidizing the conductive layer 201 is performed later, the conductive layer 201 is formed with a thickness of 0.01 to 10 nm.

  Next, an insulating layer 253 functioning as a gate insulating film, an amorphous semiconductor layer 254, an insulating layer 256, and an N-type amorphous semiconductor layer 255 are stacked (see FIG. 4B). The insulating layer 256 may be formed using a photolithography technique after an insulating film is formed over the entire surface, or may be formed by a droplet discharge method. Note that in the case of using a photolithography technique, the back surface exposure is preferably performed using the conductive layer 252 functioning as a gate electrode. Then, the resist coating process can be omitted.

  Subsequently, a mask 257 made of an insulating material such as resist or polyimide is formed, and the amorphous semiconductor layer 254 and the N-type amorphous semiconductor layer 255 are simultaneously patterned using the mask 257 to form an amorphous material. A semiconductor layer 266 and an N-type amorphous semiconductor layer are formed (see FIG. 4C). Next, a composition containing a conductive material is discharged to form conductive layers 258 and 259. Using the conductive layers 258 and 259 as a mask, the N-type amorphous semiconductor layer is patterned to form an N-type amorphous material. Quality semiconductor layers 260 and 261 are formed.

  Through the above steps, a channel protective thin film transistor is completed. Next, a conductive layer 267 functioning as a pixel electrode is formed by discharging a composition containing a conductive material so as to be in contact with the conductive layer 259. Subsequently, an insulating layer 272 serving as a bank is formed, and an electroluminescent layer 270 and a conductive layer 271 are stacked so as to be in contact with the conductive layer 267, whereby a display device having a display function using a light-emitting element is completed ( (See FIG. 5B). In the above structure, the transistor for driving the light-emitting element is an N-type transistor, the conductive layer 267 corresponds to an anode, and the conductive layer 271 corresponds to a cathode. Then, the light emitted from the light emitting element is emitted to the side opposite to the substrate 200, and the display device that performs top emission is completed. In the above manufacturing process, the conductive layer 251 is formed before the conductive layer 252 is formed, whereby adhesion and peeling resistance of the conductive layer 252 can be improved.

Note that in the structure illustrated in FIG. 5B, since the light-emitting element emits light from the top surface, the conductive layer 267 is formed using a reflective material or the lower layer of the conductive layer 267 has reflectivity. A layer formed of the material having the above may be formed.

  FIG. 5C shows an equivalent circuit diagram of the structure shown in FIGS. 5A and 5B. More specifically, FIG. 5C shows an equivalent circuit diagram of the N-type driving transistor 230 and the light emitting element 231. Is shown.

Next, a method for manufacturing a forward staggered thin film transistor in which the present invention is applied to manufacturing a gate electrode will be described with reference to FIGS. This transistor is a transistor using an amorphous semiconductor as a channel portion.

  A conductive film 31 is formed with a thickness of 100 to 800 nm on a substrate 30 by a known method such as sputtering or CVD using a material such as W, Al, or Ta. The N-type amorphous semiconductor 32 is formed with a thickness of 50 to 200 nm by a known method (see FIG. 6A). Subsequently, masks 33 and 34 made of an insulator such as resist or polyimide are formed. Then, using the masks 33 and 34, the conductive film 31 and the N-type amorphous semiconductor 32 are simultaneously patterned to form conductive layers 35 and 36 and N-type amorphous semiconductor layers 37 and 38. At this time, it is formed to be as tapered as possible. Subsequently, the masks 33 and 34 are removed using an ashing device and a peeling device, and the semiconductor layer 40 is formed to a thickness of 50 to 200 nm by CVD or the like so as to be in contact with the N-type amorphous semiconductor layers 37 and 38. It is formed (see FIG. 6B). As the semiconductor layer 40, an amorphous semiconductor or a semi-amorphous semiconductor (hereinafter referred to as SAS) existing so that crystal grains are dispersed in the amorphous semiconductor may be used.

A transistor using SAS has a field effect mobility of 2 to 20 cm ² / V · sec, 2 to 20 times that of a transistor using an amorphous semiconductor, and has an amorphous and crystalline structure ( A semiconductor having an intermediate structure (including single crystal and polycrystal). This semiconductor is a semiconductor having a third state which is stable in terms of free energy, and is a crystalline material having a short-range order and lattice strain, and having a grain size of 0.5 to 20 nm. It can be dispersed in a semiconductor. Further, hydrogen or halogen is contained at least 1 atomic% or more as a neutralizing agent for dangling bonds. Further, by adding a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, stability is improved and a favorable SAS can be obtained.

Subsequently, a mask 39 is formed, and the semiconductor layer 40 is patterned using the mask 39 to form a semiconductor layer 45 (see FIG. 6C). After removing the mask 39, an insulating film 41 to be a gate insulating film is formed with a thickness of 40 to 200 nm by a known method such as a CVD method. Next, the conductive layer 43 is formed to a thickness of 0.5 to 10 nm by a known method such as a sputtering method or a CVD method. Subsequently, a conductive layer 44 is formed by discharging a composition containing a conductive material. Then, a baking process is performed as needed. Further, a region of the conductive layer 43 that does not overlap with the conductive layer 44 is insulated to form an insulating layer 46 (see FIG. 6D).
Through the above process, a thin film transistor is completed. In the above process, by forming the thin conductive layer 43 before the conductive layer 44 is manufactured, the adhesion and peel resistance of the conductive layer 44 can be improved.
Note that, as shown in the manufacturing steps of FIGS. 3 to 5 described above, a display element such as a light emitting element or a liquid crystal element may be formed on the thin film transistor, and a display device having a display function is completed. To do.

  Next, a method for manufacturing a top-gate thin film transistor in which the present invention is applied to manufacturing a gate electrode will be described with reference to FIGS. This transistor is a transistor using a polycrystalline semiconductor as a channel portion.

  An amorphous semiconductor is formed over the substrate 300 and crystallized using a known crystallization method such as laser crystallization to obtain a polycrystalline semiconductor. Subsequently, an insulating layer 304 is formed over the semiconductor (see FIG. 7A). Note that an insulating film serving as a base film may be formed over the substrate 300 as necessary to prevent impurities from entering from the substrate 300. Next, a conductive layer 305 is formed using a refractory metal material over the insulating layer 304. Note that when a process of naturally oxidizing the conductive layer 305 is performed later, the conductive layer 305 is formed with a thickness of 0.01 to 10 nm. Next, a composition containing a conductive material is discharged, so that a conductive layer 306 that functions as a gate electrode later is formed. The conductive layer 306 is formed using a droplet discharge unit. Next, the exposed region of the conductive layer 305 is insulated to form the insulating layer 320. Subsequently, using the conductive layer 306 as a mask, an impurity is added to the semiconductor, and impurity regions 302 and 303 to which the impurity is added and a channel formation region 301 are formed.

  Subsequently, after forming the insulating layer 307, an opening is formed in the insulating layer 307 by using a photolithography technique. Then, conductive layers 308 and 309 are formed by discharging a composition containing a conductive material so as to fill the opening. Next, a conductive layer 310 functioning as a pixel electrode is formed so as to be in contact with the conductive layer 308, and then an alignment film 311 is formed. Then, a substrate 316 on which the color filter 315, the counter electrode 314, and the alignment film 313 are formed is prepared, and the substrates 300 and 316 are bonded together by heat curing of a sealing material (not shown). After that, when the liquid crystal 312 is injected, a display device having a display function using a liquid crystal element is completed. Polarizing plates 317 and 318 are attached to the substrates 316 and 300, respectively. In the above process, a thin conductive layer is formed before the conductive layer 306 is formed, whereby adhesion and peeling resistance of the conductive layer 306 can be improved. This embodiment mode can be freely combined with the above embodiment modes.

  In this example, a result of an experiment in which adhesion of a conductive layer formed using the present invention was evaluated and a result of measuring the transmittance of the conductive layer will be described. First, a method for manufacturing a sample used in each experiment will be described. A thin film of titanium (Ti) was formed on a quartz substrate by sputtering at a thickness of 0.5 nm, 1.0 nm, 2.0 nm, and 5.0 nm. Next, a composition containing silver was discharged on titanium to form a wiring having a line width of 200 μm. Subsequently, baking was performed at 230 ° C. for 1 hour as the first heat treatment. Then, as a second heat treatment, a sample fired at 250 ° C. for 1 hour, a sample fired at 300 ° C. for 1 hour, a sample fired at 350 ° C. for 1 hour, and a sample fired at 410 ° C. for 1 hour were formed. In addition, a sample in which the titanium thin film was not formed and a sample in which the second heat treatment was not performed were formed. Two samples of a tape test and a hydrofluoric acid treatment test were performed on the samples (25 in total) formed as described above to evaluate the adhesion.

  First, the results of the tape test will be described. The tape test was evaluated by cutting the tape with physical means after cutting it with a cutter in the center of the wiring formed with the silver-containing composition, sticking the tape on the entire surface and making it adhere. Table 1 shows the results. As shown in Table 1, in the sample in which titanium was not formed, the wiring was peeled off at any temperature condition. On the other hand, in the sample in which titanium was formed, the wiring did not peel off under all temperature conditions. From the above results, it was found that the adhesion between the titanium and silver compositions was good, and that the adhesion was good even when the titanium film thickness (0.5 nm, 1.0 nm) was very thin. .

  Next, the results of the hydrofluoric acid treatment test will be described. In the hydrofluoric acid treatment test, each sample was immersed in hydrofluoric acid and then evaluated by inspecting the peeling of the wiring. Table 2 shows the results. Note that the hydrofluoric acid treatment was performed for 10 seconds, and when the wiring was not peeled off, the hydrofluoric acid treatment was repeated for 10 seconds. Table 2 shows the results. As shown in Table 2, in the sample in which titanium was formed, the wiring was not peeled off even after 9 hydrofluoric acid treatments, that is, hydrofluoric acid treatment for a total of 90 seconds. On the other hand, in the sample in which titanium was not formed, in the sample heated at 250 ° C. for 1 hour as the second heat treatment, the wiring was peeled after the eighth hydrofluoric acid treatment, that is, the hydrofluoric acid treatment for 80 seconds. Oops. In addition, after the sample heated at 300 ° C. for 1 hour was subjected to the sixth hydrofluoric acid treatment, that is, the hydrofluoric acid treatment for 60 seconds, the wiring was peeled off. From the above results, it was found that the adhesion between the titanium and silver compositions was good.

Although not shown in Table 2 above, after being immersed in a stripping solution for 6 minutes in an atmosphere at 80 ° C., the immersion in a isopropyl alcohol solution was performed for 6 minutes in an ambient temperature atmosphere. However, the titanium did not peel off.
Finally, the results of measuring the transmittance will be described. As a result of the measurement, the transmittance of the sample in which titanium was not formed was approximately 1, and the transmittance tended to decrease as the titanium film thickness increased. However, no significant difference was observed depending on the heat treatment conditions, and all the samples had translucency.

  A thin film transistor is formed by applying the present invention, and a display device can be formed using the thin film transistor. A light emitting element is used as a display element, and a P-type transistor is used as a transistor for driving the light emitting element. In such a case, the light emitted from the light emitting element performs any one of bottom emission, top emission, and double emission. Here, a stacked structure of light-emitting elements corresponding to either case will be described.

  First, a case where light is emitted to the substrate 450 side, that is, a case where bottom emission is performed will be described with reference to FIG. In this case, source / drain wirings 452 and 453, an anode 454, an electroluminescent layer 455, and a cathode 456 are stacked in this order so as to be electrically connected to the transistor 451. Next, a case where light is emitted to the side opposite to the substrate 450, that is, a case where top emission is performed will be described with reference to FIG. Source / drain wirings 461 and 462 electrically connected to the transistor 451, an anode 463, an electroluminescent layer 464, and a cathode 465 are sequentially stacked. With the above structure, even if light is transmitted through the anode 463, the light is reflected by the wiring 462 and emitted to the side opposite to the substrate 450. Note that in this structure, it is not necessary to use a light-transmitting material for the anode 463. Finally, the case where light is emitted to both the substrate 450 side and the opposite side, that is, the case where dual emission is performed will be described with reference to FIG. Source / drain wirings 470 and 471 electrically connected to the transistor 451, an anode 472, an electroluminescent layer 473, and a cathode 474 are sequentially stacked. At this time, when both the anode 472 and the cathode 474 are formed using a light-transmitting material or a thickness capable of transmitting light, dual emission is realized.

  In the above structure, the cathodes 456, 465, and 474 can be made of a material having a low work function. For example, Ca, Al, CaF, MgAg, and AlLi are preferable. The electroluminescent layers 455, 464, and 473 may be any of a single layer type, a stacked type, and a mixed type that does not have an interface between layers, a singlet material, a triplet material, a combination thereof, a low molecular material, a high Any of an organic material including a molecular material and a medium molecular material, an inorganic material typified by molybdenum oxide having excellent electron injecting property, and a composite material of an organic material and an inorganic material may be used. The anodes 454, 463, and 472 are formed using a transparent conductive film that transmits light. For example, in addition to ITO and ITSO, a transparent conductive film in which indium oxide is mixed with 2 to 20% zinc oxide (ZnO) is used. Note that plasma treatment in an oxygen atmosphere or heat treatment in a vacuum atmosphere is preferably performed before forming the anodes 454, 463, and 472. The partition walls 457, 466, and 475 are formed using a material containing silicon, an organic material, and a compound material. However, it is preferable to use a photosensitive or non-photosensitive material such as acrylic or polyimide because the side surface has a shape in which the radius of curvature continuously changes and the upper thin film is formed without being cut off. This embodiment can be freely combined with the above embodiment modes.

  The appearance of a panel which is one embodiment of a semiconductor device to which the present invention is applied will be described with reference to FIGS. 9A is a top view of the panel, FIG. 9B is a cross-sectional view taken along A-A ′ of FIG. 9A, and FIG. 9C is a cross-sectional view taken along B-B ′.

  As shown in FIGS. 9A and 9B, a pixel portion 4002, a scan line driver circuit 4004, and a protection circuit 4040 are provided over a first substrate 4001, and a sealant 4005 is provided so as to surround them. And the second substrate 4006 together with the liquid crystal layer 4007. A signal line driver circuit 4003 formed of a polycrystalline semiconductor is mounted on a separately prepared substrate in a region different from a region surrounded by the sealant 4005. The pixel portion 4002 and the scan line driver circuit 4004 each include a plurality of TFTs. FIG. 9B illustrates a TFT 4010 included in the pixel portion 4002 and an element group 4041 including a diode and a resistance element included in the protection circuit 4040. . The TFT 4010 is a TFT using an amorphous semiconductor as a channel portion, and a portion where the pixel electrode 4030 electrically connected to the TFT 4010, the counter electrode 4031 formed over the second substrate 4006, and the liquid crystal layer 4007 overlap is provided. It is a liquid crystal element. In addition, alignment films 4020 and 4021 are provided so as to be in contact with the pixel electrode 4030 and the counter electrode 4031. The spacer 4035 is provided to control the distance between the pixel electrode 4030 and the counter electrode 4031. FIG. 9B illustrates a TFT 4009 formed of a polycrystalline semiconductor, which is included in the signal line driver circuit 4003. Note that some configurations of the protection circuit 4040 will be described later with reference to FIG.

  In addition, as illustrated in FIG. 9C, various signals supplied to the signal line driver circuit 4003, the scan line driver circuit 4004, and the pixel portion 4002 which are separately formed are supplied from a connection terminal 4015. The connection terminal 4015 is connected to the FPC 4018 through an anisotropic conductor 4016. The above panel has a structure in which the signal line driver circuit 4003 having a TFT using a polycrystalline semiconductor is bonded to the first substrate 4001, but the panel is not a polycrystalline semiconductor but a TFT using a single crystal semiconductor. A driving circuit may be attached. Alternatively, the scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted. The above panel shows the case where the pixel portion 4002 and the scanning line driver circuit 4004 are integrally formed over a substrate 4001, and an element constituting them is a polycrystalline semiconductor or a semi-amorphous semiconductor (hereinafter referred to as SAS). It is preferable to use a TFT as a channel portion. A TFT having a channel portion of SAS has higher mobility than a TFT having a channel portion of an amorphous semiconductor), and the scan line driver circuit 4004 has sufficient characteristics. Although not shown, the panel may have a polarizing plate, a color filter, and a shielding film. Further, although the case where a liquid crystal element is included as a display element is illustrated, the present invention may be applied to a semiconductor device to which another display element such as a self-luminous element is applied.

  Next, the appearance of a panel which is one embodiment of a semiconductor device different from the above is described with reference to FIGS. FIG. 12A is a top view of the panel, and FIG. 12B is a cross-sectional view taken along line A-A ′ of FIG.

  12A and 12B, a sealant 5006 is provided over the first substrate 5001 so as to surround the pixel portion 5003 and the driver circuits 5004 and 5005. Further, the first substrate 5001 is provided. A resin film 5015 is formed over the upper element and then sealed with the second substrate 5002. FIG. 12B illustrates a CMOS circuit 5010 included in the signal line driver circuit 5005, a TFT 5011 included in the pixel portion 5003, and a light-emitting element 5012. Various signals supplied to each circuit formed over the first substrate 5001 are supplied from the FPC 5007.

  Note that the above panel shows a case where the light-emitting element 5012 is sealed with a glass substrate, but the sealing process is a process for protecting the light-emitting element from moisture, and is a method of mechanically sealing with a cover material. Either a method of encapsulating with a thermosetting resin or an ultraviolet light curable resin, or a method of encapsulating with a thin film having a high barrier ability such as a metal oxide or a nitride is used. As the cover material, glass, ceramics, plastic, or metal can be used. However, when light is emitted to the cover material side, it must be translucent. In addition, the cover material and the substrate on which the light emitting element is formed are bonded together using a sealing material such as a thermosetting resin or an ultraviolet light curable resin, and the resin is cured by heat treatment or ultraviolet light irradiation treatment to form a sealed space. Form. It is also effective to provide a hygroscopic material typified by barium oxide in this sealed space. Further, the space between the cover material and the substrate on which the light emitting element is formed can be filled with a thermosetting resin or an ultraviolet light curable resin. In this case, it is effective to add a moisture absorbing material typified by barium oxide in the thermosetting resin or the ultraviolet light curable resin.

  A structure of a semiconductor device of the present invention having a display function will be described with reference to FIGS. FIG. 13 is a top view for explaining the outline of the semiconductor device. A pixel portion (display portion) 6102 and protection circuits 6103 and 6104 are provided over a substrate 6100, and a driver IC 6107 on the signal line side through a lead wiring. , Connected to the driver IC 6104 on the scanning line side. In the case where an amorphous semiconductor or a microcrystalline semiconductor is used as an element included in the pixel portion 6102, driver ICs 6107 and 6108 are mounted by a known method such as a COG method or a TAB method as illustrated, and the driver ICs 6107, 6108 may be used as a driver circuit. Note that in the case where a microcrystalline semiconductor is used as an element included in the pixel portion 6102, a driver circuit on the scan line side may be formed using the microcrystalline semiconductor and a driver IC 6107 may be mounted on the signal line side. As a configuration different from the above, a configuration in which a part of the driving circuits on the scanning side and the signal line side is formed on the same substrate and a part is replaced with a driver IC may be used. In other words, the configuration of the driver IC varies, and the present invention may use any configuration.

  Next, a pixel circuit of the semiconductor device of the present invention having a display function will be described with reference to FIGS. FIG. 14A shows an equivalent circuit diagram of the pixel 6101. The pixel 6101 is provided in a region surrounded by wirings of the signal line 6114, the power supply lines 6115 and 6117, and the scan line 6116. A TFT 6110 for controlling input of a video signal to the TFT, a TFT 6111 for controlling a current value flowing between both electrodes of the light emitting element 6113, and a capacitor element 6112 for holding a gate-source voltage of the TFT 6111. Note that the capacitor 6112 is illustrated in FIG. 5B; however, the capacitor 6112 is not necessarily provided when it can be covered by the gate capacitance of the TFT 6111 or other parasitic capacitance.

  FIG. 14B illustrates a pixel circuit in which a TFT 6118 and a scan line 6119 are newly provided in the pixel 6101 illustrated in FIG. The arrangement of the TFT 6118 can forcibly create a state in which no current flows to the light-emitting element 6113. Therefore, the lighting period is started immediately after or immediately after the writing period without waiting for signal writing to all pixels. be able to. Therefore, the duty ratio is improved, and moving images can be displayed particularly well.

FIG. 14C illustrates a pixel circuit in which the TFT 6111 of the pixel 6101 illustrated in FIG. 14B is deleted and TFTs 6125 and 6126 and a wiring 6127 are newly provided. In this structure, the gate electrode of the TFT 6125 is connected to the wiring 6127 which is held at a constant potential, so that the potential of the gate electrode is fixed and the TFT 6125 is operated in the saturation region. In addition, a video signal that transmits information on lighting or non-lighting of the pixel is input to the gate electrode of the TFT 6126 that is connected in series with the TFT 6125 and operates in a linear region through the TFT 6110. Since the value of the voltage between the source and the drain of the TFT 6126 operating in the linear region is small, a slight variation in the voltage between the gate and the source of the TFT 6126 does not affect the value of the current flowing through the light emitting element 6113. Therefore, the value of current flowing through the light emitting element 6113 is determined by the TFT 6125 operating in the saturation region. In the present invention having the above structure, luminance unevenness of the light-emitting element 6113 due to variation in characteristics of the TFT 6125 can be improved and image quality can be improved. Note that the channel length L ₁ and channel width W _{1 of} the TFT 6125 and the channel length L ₂ and channel width W ₂ of the TFT 6126 are set so as to satisfy L ₁ / W ₁ : L ₂ / W ₂ = 5 to 6000: 1. Good. Further, it is preferable in the manufacturing process that both TFTs have the same conductivity type. Further, as the TFT 6125, not only an enhancement type but also a depletion type TFT may be used.

  FIG. 16 is a top view of the pixel circuit having the above structure. In FIGS. 16A and 16B, a region surrounded by the signal line 6703, the power supply line 6704, the scanning line 6705, and the power supply line 6706 is illustrated. , TFTs 6700, 6701, 6702, and a capacitor 6708, and a pixel electrode 6707 is connected to the source or drain of the TFT 6701.

  Note that either an analog video signal or a digital video signal may be used for the semiconductor device of the present invention having a display function. However, when a digital video signal is used, it differs depending on whether the video signal uses voltage or current. That is, when the light emitting element emits light, a video signal input to the pixel includes a constant voltage signal and a constant current signal. A video signal having a constant voltage includes a constant voltage applied to the light emitting element and a constant current flowing through the light emitting element. In addition, a video signal having a constant current includes a constant voltage applied to the light emitting element and a constant current flowing in the light emitting element. A constant voltage applied to the light emitting element is constant voltage driving, and a constant current flowing through the light emitting element is constant current driving. In constant current driving, a constant current flows regardless of the resistance change of the light emitting element. In the display device and the driving method thereof of the present invention, either a voltage video signal or a current video signal may be used, and either constant voltage driving or constant current driving may be used. This embodiment can be freely combined with the above embodiment modes and embodiments.

  An example of a protection circuit included in the semiconductor device of the present invention will be described. The protection circuit is composed of one or a plurality of elements selected from a TFT, a diode, a resistance element, a capacitance element, and the like, and the configurations and operations of some protection circuits will be described below. First, a configuration of an equivalent circuit diagram of a protection circuit arranged between an external circuit and an internal circuit and corresponding to one input terminal will be described with reference to FIG. The protection circuit illustrated in FIG. 15A includes P-type TFTs 7220 and 7230, capacitor elements 7210 and 7240, and a resistance element 7250. The resistance element 7250 is a two-terminal resistor, and an input voltage Vin (hereinafter referred to as Vin) is applied to one end, and a low potential voltage VSS (hereinafter referred to as VSS) is applied to the other end. The resistance element 7250 is provided to set the potential of the wiring to VSS when Vin is no longer applied to the input terminal, and the resistance value is set sufficiently larger than the wiring resistance of the wiring.

  When Vin is higher than a high potential voltage VDD (hereinafter referred to as VDD), the TFT 7220 is turned on and the TFT 7230 is turned off because of the gate-source voltage. Then, VDD is supplied to the wiring through the TFT 7220. Therefore, even if Vin becomes higher than VDD due to noise or the like, the voltage applied to the wiring does not become higher than VDD. On the other hand, when Vin is lower than VSS, the TFT 7220 is turned off and the TFT 7230 is turned on because of the gate-source voltage. Then, VSS is given to the wiring. Therefore, even if Vin is lower than VSS due to noise or the like, the voltage applied to the wiring does not become higher than VDD. Further, the capacitive elements 7210 and 7240 can damp pulsed noise to the voltage from the input terminal, and abrupt changes in voltage due to noise can be reduced to some extent.

  With the arrangement of the protection circuit having the above configuration, the voltage of the wiring is kept in a range between VSS and VDD, and is protected from application of an abnormally high or low voltage outside this range. Further, by providing a protection circuit at an input terminal to which a signal is input, the voltage of all wirings to which a signal is applied can be kept constant (here, VSS) when no signal is input. it can. In other words, when a signal is not input, it also has a function as a short ring that can make the wirings short-circuited. For this reason, electrostatic breakdown due to a voltage difference between the wirings can be prevented. Further, when a signal is being input, the resistance value of the resistor is sufficiently large, so that a signal applied to the wiring is not pulled by VSS.

  The protection circuit shown in FIG. 15B is an equivalent circuit diagram in which P-type TFTs 7220 and 7230 are substituted with diodes 7260 and 7270 having rectifying properties. The protection circuit shown in FIG. 15C is an equivalent circuit diagram in which P-type TFTs 7220 and 7230 are substituted with TFTs 7350, 7360, 7370, and 7380. Further, as a protection circuit having a structure different from the above, the protection circuit illustrated in FIG. 15D includes resistance elements 7280 and 7290 and an N-type TFT 7300. A protection circuit illustrated in FIG. 15E includes resistance elements 7280 and 7290, a P-type TFT 7310, and an N-type TFT 7320. 15D and 15E, a wiring or the like is connected to the terminal 7330, and the N-type TFT 7300 or the P-type TFT 7310 and the N-type TFT 7320 are turned on when the potential of the wiring or the like changes abruptly. As a result, current flows in the direction of terminals 7330 to 7340. Then, rapid fluctuations in the potential connected to the terminal 7330 can be reduced, and damage or destruction of the element can be prevented. Note that the element forming the protection circuit is preferably formed using an amorphous semiconductor with excellent withstand voltage. This embodiment can be freely combined with the above embodiment modes.

  As an example of an electronic device manufactured by applying the present invention, a digital camera, a sound reproducing device such as a car audio, a notebook personal computer, a game device, a portable information terminal (mobile phone, portable game machine, etc.), home use An image reproducing device including a recording medium such as a game machine may be used. Specific examples of these electronic devices are shown in FIGS.

  FIG. 10A illustrates a television receiver, which includes a housing 9501, a display portion 9502, and the like. FIG. 10B illustrates a monitor for a personal computer, which includes a housing 9601, a display portion 9602, and the like. FIG. 10C illustrates a laptop personal computer, which includes a housing 9801, a display portion 9802, and the like. The present invention is applied to manufacture of a display portion of the electronic device. Since the display unit of the electronic device is larger than a portable terminal, a large glass substrate of the fourth generation, the fifth generation or later is inevitably used. Therefore, the use of the present invention in which the wiring is formed by a droplet discharge method, which has a high material utilization efficiency and can reduce the number of steps compared to the case of using a photolithography process, can realize a reduction in cost. The In view of manufacturing process and cost, the transistor is preferably formed using a transistor including an amorphous semiconductor or a microcrystalline semiconductor as a channel portion.

  FIG. 11A illustrates a mobile phone of mobile terminals, which includes a housing 9101, a display portion 9102, and the like. FIG. 11B illustrates a PDA among portable terminals, which includes a housing 9201, a display portion 9202, and the like. FIG. 11C illustrates a video camera, which includes display portions 9701 and 9702 and the like. The present invention is applied to manufacture of a display portion of the electronic device. Since the electronic device is a portable terminal, its screen is relatively small. Therefore, it is preferable to reduce the size by mounting a driving circuit using a thin film transistor using a polycrystalline semiconductor channel, a functional circuit such as a CPU, and multilayer wiring on the same substrate as the display portion. In this case, the use of the present invention in which the wiring is formed by a droplet discharge method that can reduce the number of steps can reduce the cost. Further, since the electronic device is a mobile terminal, a display portion using a light-emitting element is preferably used in order to achieve added value in terms of thinness, lightness, and small size. This embodiment can be freely combined with the above embodiment modes and embodiments.

8A and 8B illustrate a method for manufacturing a wiring board of the present invention (Embodiment 1). 8A and 8B illustrate a method for manufacturing a wiring substrate of the present invention (Embodiment 2). 8A and 8B illustrate a method for manufacturing a channel-etched thin film transistor (Embodiment 3). 8A and 8B illustrate a method for manufacturing a channel protective thin film transistor (Embodiment 3). 4A and 4B illustrate a method for manufacturing a display device (Embodiment 3). 8A and 8B illustrate a method for manufacturing a forward staggered thin film transistor (Embodiment 3). 8A and 8B illustrate a method for manufacturing a forward staggered thin film transistor and a display device (Embodiment 3). 8A and 8B illustrate a stacked structure of a forward staggered thin film transistor and a light-emitting element connected to the thin film transistor (Example 2). The top view and sectional drawing of a panel which are one form of the semiconductor device to which this invention was applied (Example 3). FIG. 11 is a diagram showing an electronic apparatus to which the present invention is applied (Example 6). FIG. 11 is a diagram showing an electronic apparatus to which the present invention is applied (Example 6). The top view of the panel which is one form of the semiconductor device to which this invention was applied (Example 3). FIG. 11 illustrates a semiconductor device to which the present invention is applied (Example 4). FIG. 11 is a diagram illustrating a pixel circuit of a semiconductor device to which the present invention is applied (Example 4); FIG. 11 shows a protection circuit provided in a semiconductor device of the present invention (Example 5). FIG. 6 is a top view of a pixel circuit of a semiconductor device of the present invention (Example 4).

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Substrate 11 Insulating layer 12, 13 Conductive layer 14 Droplet discharge means 16 Insulating layer 17 Conductive layer 20 Substrate 21 Semiconductor layer 22, 27 Insulating layer 23 Openings 24, 25, 28 Conductive layer 26 Droplet discharge means

Claims (10)

Forming an insulating layer on the substrate;
Forming a first conductive layer made of titanium so as to be in contact with the insulating layer;
A composition containing silver is selectively discharged so as to be in contact with the first conductive layer to form a second conductive layer;
A method for manufacturing a wiring board, wherein the first conductive layer not in contact with the second conductive layer is insulated. Forming an insulating layer on the substrate;
Forming a first conductive layer made of titanium so as to be in contact with the insulating layer;
A composition containing silver is selectively discharged so as to be in contact with the first conductive layer to form a second conductive layer;
A method for manufacturing a wiring board, comprising: etching the first conductive layer that is not in contact with the second conductive layer. Forming an insulating layer with an opening on the substrate;
Forming a first conductive layer made of titanium so as to be in contact with the insulating layer;
A composition containing silver is selectively discharged so as to fill the opening through the first conductive layer, thereby forming a second conductive layer;
A method for manufacturing a wiring board, wherein the first conductive layer not in contact with the second conductive layer is insulated. Forming an insulating layer with an opening on the substrate;
Forming a first conductive layer made of titanium so as to be in contact with the insulating layer;
A composition containing silver is selectively discharged so as to fill the opening through the first conductive layer, thereby forming a second conductive layer;
A method for manufacturing a wiring board, comprising: etching the first conductive layer that is not in contact with the second conductive layer.   3. The method for manufacturing a wiring board according to claim 1, wherein the insulating layer is formed of a silicon oxide material or a nitride material.   5. The method for manufacturing a wiring substrate according to claim 3, wherein the insulating layer is formed using an organic material or a material in which a skeleton structure is formed by a bond of silicon and oxygen.   5. The method for manufacturing a wiring board according to claim 3, wherein the insulating layer is formed with a thickness of 100 nm to 2 [mu] m.   4. The method for manufacturing a wiring board according to claim 1, wherein the first conductive layer that is not in contact with the second conductive layer is insulated by natural oxidation.   9. The method for manufacturing a wiring board according to claim 1, wherein the first conductive layer is formed with a thickness of 0.01 to 10 nm.   10. The method for manufacturing a wiring board according to claim 1, wherein the first conductive layer is formed by a sputtering method, an evaporation method, a dip method, or a spin coating method.

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