JP4592649B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device having a MISFET using a silicide that forms a Schottky junction with a silicon substrate as a source and a drain.

  In order to apply a metal gate or a high dielectric gate insulating film to the MOSFET, a process using a dummy gate (Rep1acement gate process, Damascene gate process) has been proposed (see, for example, Non-Patent Documents 1 and 2).

  Here, the dummy gate process means that a disposable gate to be removed later is formed in a region where a gate is to be formed in the future, a source / drain is formed by self-alignment, a dummy gate is removed, and then a dummy gate is removed. In this process, the original gate is replaced with a damascene process in the groove formed.

  If the dummy gate process is used, the source / drain that requires high-temperature heat treatment is formed before the gate, so that the thermal process after forming the gate can be lowered to 450 ° C. or lower. Therefore, it becomes easy to apply a metal gate electrode or a high dielectric gate insulating film with poor heat resistance to the MOSFET.

The problem of a damascene gate (or replacement gate) transistor using a metal gate or high-k gate insulating film is
(1) The number of processes greatly increases for the formation and removal of dummy gates.
(2) The short channel effect is deteriorated by the fringe effect of the gate electric field (for example, see Non-Patent Document 3).
(3) Since the work function of many metal gates used is located in the vicinity of the silicon mid gap, the threshold voltage (absolute value) rises due to the influence.
It is.
A. Chatterjee et al., IEDM Tech. Dig., (1997), p.821 A. Yagishita et al., IEDM Tech Dig, (1998), p.785) Baohong Cheng et al., IEEE Transactions on ELECTRON DEVICES, Vol.46, No.7, (1999), p.1537)

  As described above, there is a problem in that the number of processes is greatly increased for forming and removing the dummy gate. Further, there is a problem that the short channel effect is deteriorated due to the fringe effect of the gate electric field.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing the number of steps of a MISFET using a high dielectric film and a metal for a gate insulating film and a gate electrode, respectively.

Another object of the present invention is to provide a semiconductor device manufacturing method capable of suppressing the short channel effect even when a high dielectric film is used as a gate insulating film.

[Constitution]
The present invention is configured as follows to achieve the above object.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming an interlayer insulating film on a silicon substrate, and selectively removing the interlayer insulating film between regions where the PMISFET and NMISET source and drain are to be formed, Forming a gate groove; forming a sidewall insulating film on a sidewall of the gate groove; exposing the silicon substrate to a bottom surface of the gate groove; and forming a gate insulating film on the exposed surface of the silicon substrate. And a step of embedding and forming a gate electrode in the gate trench, and removing the interlayer insulating film in a region where the source and drain of the PMISFET are to be formed, and exposing the surface of the silicon substrate at the bottom, the PMIS side source / drain Forming a trench, and embedding and forming a first metal film in the PMIS side source / drain trench, A step of forming an electrode and a drain electrode, and reacting the silicon substrate with the source electrode and the drain electrode of the PMISFET to form a silicide film that forms a Schottky junction with the substrate, thereby forming a source and a drain of the PMISFET. Removing the interlayer insulating film in the region where the source and drain of the NMISFET are to be formed, forming an NMIS side source / drain trench exposing the surface of the silicon substrate at the bottom, and the NMIS side source / drain A step of embedding and forming a second metal film made of a material different from the first metal film in the trench to form a source electrode and a drain electrode of the NMISFET, and a step of forming the silicon substrate and the source electrode and the drain electrode of the NMISFET React to form a silicide film that forms a Schottky junction with the substrate Te, and forming a source and a drain of NMISFET.

  In the semiconductor device manufacturing method, the gate electrode and the gate insulating film are formed of a metal material and a high dielectric material, and the reaction between the silicon substrate and the metal film is performed at a temperature of 450 ° C. or lower. preferable.

[Action]
The present invention has the following operations and effects by the above configuration.

  As described above, since the dummy gate need not be formed and removed, the number of steps can be greatly reduced as compared with the conventional damascene gate process. Further, since it is not necessary to perform a high-temperature heat process (usually about 1000 ° C.) for activating the source and drain, the manufacturing becomes easy. Furthermore, since the source and drain are not pn junctions but Schottky junctions, the short channel effect can be prevented even if a high dielectric film is used for the gate insulating film. If the short channel effect is suppressed, the channel concentration can be reduced, so that the effect of improving the S-factor and reducing the threshold voltage can be obtained.

  Further, since different metal materials are used for the NMOS and PMOS as the source / drain materials, the following merits arise. That is, in a transistor using a Schottky contact (junction) for the source and drain, a Schottky having a small work function for the N channel and a large work function for the P channel is used in order to avoid a decrease in current driving capability. Although a contact material is required, a material with a low work function can be used for NMOS, and a material with a high work function can be used for PMOS, so that the drive current for both NMOS and PMOS can be increased. Become. Further, by selecting a Schottky contact material, the threshold voltages of the NMOS and PMOS can be controlled separately.

  In addition, by applying a Schottky junction to the source / drain of the SOI-MOSFET, it is possible to make up for the defects of the SOI element by making use of the characteristics of the contact, and by using the SOI, the defects of the Schottky contact can be solved. It can be removed. That is, the substrate floating problem of SOI-MOSFET can be suppressed by the effect of the Schottky barrier in both the source and drain, and the leakage current at the drain contact can be suppressed by adopting the SOI structure, so that the transistor off-current ( (Power consumption) can be reduced.

  According to the present invention, since the gate and the source / drain can be formed by self-alignment without using a dummy gate, the number of steps can be greatly reduced. Further, it is not necessary to perform a high-temperature heat process for activating the source / drain, and the manufacturing is easy. Further, since the metal source and the metal drain by the Schottky junction are used, DIBL is suppressed and the short channel effect can be prevented.

  The details of the present invention will be described below with reference to the illustrated embodiments.

(First embodiment)
FIG. 1 is a sectional view showing the configuration of an NMOSFET according to the first embodiment of the present invention. FIG. 1 shows a cross section in the gate length direction.

  As shown in FIG. 1, an element isolation insulating film 102 is formed around the element region of the semiconductor silicon substrate 101. A sidewall insulating film 107 made of a silicon nitride film is formed on the silicon substrate 101 so as to cover the periphery of the channel region.

A Ta ₂ O ₅ film 108, a barrier metal TiN film 109, and an Al film 110 are embedded in a trench whose side wall is made of a side wall insulating film. The Ta ₂ O ₅ film 108 is a gate insulating film, and the barrier metal TiN film 109 and the Al film 110 are metal gate electrodes 111.

  An interlayer insulating film 104 is formed on the element isolation insulating film 102. A Schottky junction / source / drain 115 made of silicide is formed on the silicon substrate 101 at the bottom of the trench whose side wall is made of the side wall insulating film 107 and the interlayer insulating film. A source / drain electrode 114 is formed on the Schottky junction / source / drain 115.

  This NMOSFET is a transistor (Schottky barrier tunne1 transistor (SBTT)) in which the junction with the silicon substrate is not a pn junction but a Schottky junction. SBTT is a junction between the source and drain regions and has a small depletion layer width. In addition, the barrier height of the Schottky junction does not change with the electric field except for the mirror image effect, so that DIBL (Drain-Induced Barrier Lowering) can be avoided. Therefore, this transistor structure can suppress the short channel effect. By suppressing the short channel effect, the channel concentration can be reduced, so that the effects of S-factor improvement and threshold voltage reduction can also be obtained.

Next, a method for manufacturing this NMOSFET will be described with reference to FIGS. 2 to 5 are process cross-sectional views showing a manufacturing process of the NMOSFET shown in FIG. When described in the order of steps, first, as shown in FIG. 2A, a semiconductor silicon substrate 101 is prepared. Next, as shown in FIG. 2B, in order to perform element isolation by STI (Shallow-trench-iso1ation), a groove having a depth of about 200 nm is formed in the element isolation region, and a TEOS-SiO ₂ film is embedded in the groove. Then, an element isolation insulating film 102 is formed.

Next, as shown in FIG. 2C, after a SiO ₂ film 103 is formed on the surface of the silicon substrate 101 by thermal oxidation of about 5 nm, a TEOS-SiO ₂ film of about 150 nm is deposited by LPCVD to form an interlayer insulating film. 104 is formed. This interlayer insulating film is used as a stopper for CMP in a later process.

  Next, as shown in FIG. 2D, a resist film 105 having an opening in the channel formation region of the MISFET is formed by EB direct drawing or lithography, and then the region between the source and drain formation scheduled regions is formed using the resist film 105 as a mask. The interlayer insulating film 104 is etched to form a gate groove 106.

  Next, as shown in FIG. 3E, after removing the resist film 105, a silicon nitride film is deposited and etched by the RIE method to form a sidewall insulating film 107 inside the gate groove 106. Here, ion implantation for adjusting the threshold voltage of the transistor is performed in the channel region (not shown). This gate groove 106 becomes a gate formation scheduled region.

In the transistor of the present invention, since the source / drain is scheduled to be formed at a low temperature (for example, at 450 ° C. or lower) by a Schottky junction, there is no high-temperature heat treatment step at 450 ° C. or higher after the gate formation. Therefore, a high dielectric constant film or a ferroelectric film (Ta ₂ O ₅ film, TiO ₂ film, Si ₃ N ₄ film, (Ba, Sr) TiO ₃ , HfO ₂ , ZrO ₂ , La ₂ O ₃ , Gd ₂ O _3, Y2O _3, used for _{CaF 2, CaSnF 2, CeO 2} , YttriaStabi1ized Zirconia, Al 2 O 3, ZrSiO 4, HfSiO 4, Gd 2 SiO 5, 2La 2 O 3 · 3SiO 2, etc.) of the gate insulating film In addition, a metal material (TiN, WN, Al, W, Ru, etc.) can be used for the gate electrode.

  If a high-temperature process of about 800 to 1000 ° C. exists after the gate is formed, the metal gate atoms diffuse into the gate insulating film to deteriorate the gate breakdown voltage, or the dielectric constant is low at the interface between the high-k film and silicon. A thin film layer is formed, and the effective gate insulating film thickness is significantly increased.

Here, a case where a Ta ₂ O ₅ film is used as the gate insulating film material and a laminated structure of barrier metal TiN and Al is used as the metal gate material will be described. The manufacturing method will be described in detail. As shown in FIG. 3F, for example, the silicon substrate 101 is exposed at the bottom of the gate groove 106 to form a silicon nitride film (NO nitride oxynitride film) of 1 nm or less. A Ta ₂ O ₅ film (gate insulating film) 108 is formed thereon by a CVD method with a thickness of about 4 nm. At this time, the equivalent oxide thickness of the gate insulating film is 2 nm or less. Thereafter, a barrier metal TiN film 109 having a film thickness of, for example, about 5 nm is formed as a barrier metal by a CVD method, and an Al film 110 having a film thickness of, for example, about 300 nm is deposited by a sputtering method.

Next, as shown in FIG. 3G, the Al gate 110, the barrier metal TiN film 109, and the Ta ₂ O ₅ film 108 are sequentially subjected to CMP, so that the metal gate electrode 111 is embedded in the gate trench 106. To do.

Next, as shown in FIG. 4H, a resist film 112 having an opening in the element region is formed by lithography or the like, and then the interlayer insulating film 104 and the SiO ₂ film 103 are etched using the resist film 112 as a mask. / Drain trench 113 is formed.

When the interlayer insulating film 104 is etched, the etching is performed under the condition that the silicon nitride film, the Ta ₂ O ₅ film 108 and the metal gate electrode 111 constituting the interlayer insulating film 104 are not etched and the SiO ₂ film is selectively etched. Thus, the source / drain trench 113 sandwiching the metal gate electrode 111 in a self-aligning manner can be formed.

  Next, as shown in FIG. 4I, after removing the resist film 112, an Er film 114 is deposited so that the source / drain trench 113 is filled. Next, as shown in FIG. 4J, the surface of the Er film 114 is planarized by CMP to expose the surface of the interlayer insulating film 104, and the source / drain electrode 114 is formed in the source / drain trench 113. .

Next, as shown in FIG. 5 (k), annealing is performed at a temperature of 450 ° C. or lower to cause the silicon substrate 101 to react with the source and drain electrodes 114, and Schottky junction / source made of silicide such as ErSi _2. / Drain 115 is formed.

After the formation of the source and drain, it is the same as a normal LSI manufacturing process. That is, as shown in FIG. 5L, an interlayer insulating film 116 made of a TEOS-SiO ₂ film is formed by a CVD method, contact holes are formed on the source / drain electrodes 114 and the metal gate electrode 111, and Al A wiring (upper layer metal wiring) 117 is formed by a dual damascene method.

  As described above, since the dummy gate need not be formed and removed, the number of steps can be greatly reduced as compared with the conventional damascene gate process. Further, since it is not necessary to perform a high-temperature heat process (usually about 1000 ° C.) for activating the source and drain, the manufacturing becomes easy.

  Furthermore, since the source and drain are not pn junction but Schottky junction, the short channel effect can be prevented even if a high-k gate insulating film is used. If the short channel effect is suppressed, the channel concentration can be reduced, so that the effect of improving the S-factor and reducing the threshold voltage can be obtained.

  In addition, the following advantages of the damascene gate process continue to exist. That is, [1] Since the gate is processed by CMP instead of RIE, plasma damage is not introduced into the gate insulating film. [2] It is very difficult to RIE a metal gate on a thin gate insulating film, but this is not necessary in the process of the present invention. [3] Since the surface is completely flattened after the gate processing, the subsequent manufacturing process becomes easy. [4] The positions of the source, drain and gate are formed by self-alignment.

(Second Embodiment)
FIG. 6 is a cross-sectional view showing the configuration of the CMOSFET according to the second embodiment of the present invention. FIG. 6 shows a cross section in the gate length direction. The same parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.

In the present embodiment, the material forming the Schottky junction / source / drain is different between NMOS and PMOS. That is, in the NMOSFET formation region, Er is used for the source / drain electrode 114 and ErSi ₂ is used for the Schottky junction / source / drain 115. In the PMOSFET formation region, Pt is used for the source / drain electrode 201 and PtSi is used for the Schottky junction / source / drain 202.

  In the present embodiment, different metal materials are used for the NMOS and PMOS as the source / drain materials, and the following merits arise. That is, in a transistor using a Schottky contact (junction) for the source and drain, a Schottky having a small work function for the N channel and a large work function for the P channel is used in order to avoid a decrease in current driving capability. Contact material is required.

  In this embodiment, erbium silicide (ErSi2) having a small work function can be used for NMOSFET, and PtSi having a large work function can be used for PMOSFET. Therefore, it is possible to increase both NMOSFET and PMOSFET drive currents. become. Further, by selecting the Schottky contact material, the threshold voltages of the NMOSFET and PMOSFET can be controlled separately.

  Next, a method for manufacturing the CMOSFET shown in FIG. 6 will be described. 7 to 9 are process cross-sectional views showing manufacturing steps of the CMOSFET shown in FIG.

  The structure shown in FIG. 7A is formed through the same processes as those described in the first embodiment with reference to FIGS. 2A to 3E, and the description thereof is omitted.

  Next, as shown in FIG. 7B, after a resist film 211 is selectively formed on the surface of the PMOS channel formation region, a transistor threshold voltage adjustment transistor is formed on the surface of the silicon substrate 101 exposed in the NMOS channel formation region. Ions are implanted. Next, as shown in FIG. 7C, after removing the resist film 211 on the surface of the PMOS channel formation region, a resist film 212 is formed on the surface of the NMOS channel formation region, and the silicon substrate exposed to the PMOS channel formation region Ions for adjusting the transistor threshold voltage are implanted into the surface 101.

In the transistor of the present invention, since the source / drain is scheduled to be formed at a low temperature (for example, at 450 ° C. or lower) by a Schottky junction, there is no high-temperature heat treatment step at 450 ° C. or higher after the gate formation. Therefore, a high dielectric constant film or a ferroelectric film (Ta ₂ O ₅ film, TiO ₂ film, Si ₃ N ₄ film, (Ba, Sr) TiO ₃ , HfO ₂ , ZrO ₂ , La ₂ O ₃ , Gd ₂ O _{3, Y 2 O 3, CaF} 2, CaSnF 2, CeO 2, YttriaStabi1ized Zirconia, used for _{Al2O 3, ZrSiO 4, HfSiO 4} , Gd 2 SiO 5, 2La 2 O 3 · 3SiO 2, etc.) of the gate insulating film In addition, a metal material (TiN, WN, Al, W, Ru, etc.) can be used for the gate electrode.

Next, as shown in FIG. 7D, after removing the resist film, a Ta ₂ O ₅ film 108, a barrier metal TiN 109 and an Al film 110 are stacked as a gate insulating film material, as in the first embodiment. The formed metal gate electrode 111 is formed.

  Next, as shown in FIG. 8E, after forming a resist film 213 having an opening in the element region of the NMOS channel formation region, the interlayer insulating film 104 is selectively etched using the resist film 213 as a mask. Side source / drain trenches 214 are formed. Next, as shown in FIG. 7F, an Er film 114 is deposited on the entire surface so as to fill in the NMOS side source / drain trench 214.

  Next, as shown in FIG. 7G, the Er film 114 is subjected to chemical mechanical polishing to expose the surface of the interlayer insulating film 104 to form the source / drain electrodes 114. Then, a silicide reaction is caused at a low temperature of 450 ° C. or lower, for example, to form an NMOS side Schottky junction / source / drain 115 at the interface between the source / drain electrode 114 and the silicon substrate 101.

  Next, as shown in FIG. 9H, after forming a resist film 215 having an opening in the element region of the PMOS channel formation region, the interlayer insulating film 104 is selectively etched using the resist film 215 as a mask. Side source / drain trenches 216 are formed. Next, as shown in FIG. 9I, a Pt film 201 is deposited on the entire surface so as to fill in the PMOS side source / drain trench 216.

  Next, as shown in FIG. 9J, chemical mechanical polishing is performed on the Pt film 201 to expose the surface of the interlayer insulating film, and the source / drain electrode 201 is placed in the PMOS side source / drain trench 216. Form. Then, for example, a silicide reaction is caused at a low temperature of 450 ° C. or lower to form a PMOS-side Schottky junction / source / drain 202 at the interface between the PMOS-side source / drain electrode 201 and the silicon substrate 101.

  After the formation of the Schottky junction / source and drain, it is the same as a normal LSI manufacturing process. That is, an interlayer insulating film TEOS is deposited by CVD, contact holes are formed on the source / drain electrodes 114 and 201 and the metal gate electrode 111, and an upper layer metal wiring (for example, Al wiring) 117 is formed by a dual damascene method. . Since these sectional views are the same as those in the first embodiment, they are omitted.

  As described above, since the dummy gate need not be formed and removed, the number of steps can be greatly reduced as compared with the conventional damascene gate process. Further, since it is not necessary to perform a high-temperature heat process (usually about 1000 ° C.) for activating the source and drain, the manufacturing becomes easy.

  Furthermore, since the source and drain are not pn junctions but Schottky junctions, the short channel effect can be prevented even if a high-k gate insulating film is used. If the short channel effect is suppressed, the channel concentration can be reduced, so that the effect of improving the S-factor and reducing the threshold voltage can be obtained.

  Moreover, in the present embodiment, different metal materials are used for the NMOS and the PMOS as the source / drain materials, and the following merits arise. That is, in a transistor using a Schottky contact (junction) for the source and drain, a Schottky having a small work function for the N channel and a large work function for the P channel is used in order to avoid a decrease in current driving capability. Contact material is required.

In this embodiment, erbium silicide (ErSi ₂ ) having a small work function can be used for NMOSFET, and PtSi having a large work function can be used for PMOSFET. Therefore, the drive current of both NMOSFET and PMOSFET can be increased. It becomes possible. Further, by selecting the Schottky contact material, the threshold voltages of the NMOSFET and PMOSFET can be controlled separately.

  In the present embodiment, the order of manufacturing the NMIS source / drain and the PMIS source / drain may be reversed.

(Third embodiment)
FIG. 10 is a cross-sectional view showing a configuration of an NMOSFET according to the third embodiment of the present invention. FIG. 10 shows a cross section in the gate length direction. 10, parts that are the same as those in FIG. 1 are given the same reference numerals, and explanation thereof is omitted. A feature of this embodiment is that an SOI substrate 300 including a supporting silicon substrate 301, a buried oxide film 302, and a silicon layer 303 is used. Since other configurations are the same as those of the first embodiment, description of the manufacturing method is omitted. According to the present embodiment, the same advantages (merits) as in the first embodiment can be obtained, and the following merits can be obtained in addition to the effects (merits). That is, by applying a Schottky junction to the source / drain of the SOI-MOSFET, it is possible to compensate for the shortcomings of the semiconductor element using the SOI substrate by making use of the characteristics of the contact, and to use the SOI substrate for the Schottky. The faults of contact can be removed.

  More specifically, [1] The substrate floating problem of SOI-MOSFET can be suppressed by the effect of the Schottky barrier in both the source and drain. [2] The leakage current at the drain contact can be suppressed by adopting the SOI structure. The off-state current (power consumption) of the transistor can be reduced.

(Fourth embodiment)
FIG. 11 is a cross-sectional view showing a configuration of an NMOSFET according to the fourth embodiment of the present invention. FIG. 11 shows a cross section in the gate length direction. A feature of the present embodiment is that the Schottky junction / source / drain 115 is formed to extend under the sidewall insulating film 107.

  According to this embodiment, the same effect (merit) as the first embodiment can be obtained. In addition, the following advantages can be obtained. That is, by reducing the distance between the gate electrode and the source / drain, the parasitic resistance of the transistor can be reduced and high driving capability can be realized.

  Next, a manufacturing process of the NMOSFET shown in FIG. 11 will be described. Since the structure shown in FIG. 12A is formed through the steps described with reference to FIGS. 2A to 4H in the first embodiment, the description thereof is omitted. The subsequent steps will be described in order. As shown in FIG. 12B, the silicon substrate exposed at the bottom of the source / drain trench 113 is etched by about 30 nm by CDE to form an undercut 401 under the gate sidewall. To do.

  Next, as shown in FIG. 12C, an Er film is formed so as to fill the source / drain trench 113 in which the undercut 401 is formed. Next, as shown in FIG. 12D, the surface of the Er film 114 is flattened by CMP to expose the surface of the interlayer insulating film 104, and the source / drain electrodes 114 are formed in the source / drain trench 113. . Then, annealing is performed at a temperature of 450 ° C. or lower to cause the silicon substrate 101 to react with the source and drain electrodes 114 to form Schottky junction / source / drain 115 made of ErSi2.

  According to this embodiment, the same effect (merit) as the first embodiment can be obtained. In addition, the following advantages can be obtained. That is, the offset amount (or overlap amount) between the gate and the source / drain can be controlled, the parasitic resistance of the transistor can be reduced, and high driving capability can be realized. If the silicon substrate is eroded during the source / drain silicidation reaction, the source / drain metal material may wrap around the gate sidewall without performing the CDE as described above.

(Embodiment 5)
FIG. 13A to FIG. 14H are process sectional views showing the manufacturing process of the NMOSFET according to the fifth embodiment of the present invention. 13A to 14H show cross sections in the gate length direction. The description will be made in the order of steps. First, as shown in FIG. 13A, a semiconductor silicon substrate 101 is prepared. Next, as shown in FIG. 13B, in order to perform element isolation by STI (Shallow-trench-iso1ation), a groove having a depth of about 200 nm is formed in the element isolation region, and a TEOS-SiO ₂ film is embedded in the groove. Then, an element isolation insulating film 102 is formed. Then, after a SiO2 film 103 of about 5 nm is formed on the surface of the silicon substrate 101 by thermal oxidation, a silicon nitride film 501 of about 10 nm is formed on the entire surface. Next, as shown in FIG. 13C, a TEOS-SiO ₂ film having a thickness of about 150 nm is deposited on the silicon nitride film 501 by using the LPCVD method to form an interlayer insulating film 104.

  Next, as shown in FIG. 13D, a resist film 105 having an opening in the channel formation region is formed by EB direct drawing or lithography, and the interlayer insulating film 104 in the gate formation scheduled region is etched by the RIE method. 106 is formed. At this time, the silicon nitride film 501 serves as an RIE stopper and prevents the silicon substrate 101 from being etched.

  Next, as shown in FIG. 14E, after the resist film 105 is removed, a silicon nitride film is deposited and etched by the RIE method, whereby a sidewall insulating film 107 made of, for example, a silicon nitride film is formed inside the gate groove 106. Form. At the time of RIE for forming the sidewall insulating film 107, the silicon nitride film 501 exposed at the bottom of the trench is also removed at the same time, but if it remains, it is removed by hot phosphoric acid or RIE.

Next, as shown in FIG. 14F, ion implantation for adjusting the threshold voltage of the transistor is performed in the channel region (not shown), and the SiO ₂ film 103 is removed by HF treatment.

The subsequent steps are the same as in the other embodiments. That is, as shown in FIG. 14G, using a damascene process, a Ta ₂ O ₅ film 108 as a gate insulating film material, a metal gate electrode 111 having a laminated structure of a barrier metal TiN film 109 and an Al film 110 is formed. It is embedded in the gate trench 106.

  Then, as shown in FIG. 14H, after forming the source / drain trench, the source / drain electrode 114 made of an Er film is buried in the source / drain trench, and then annealed at a temperature of 450 ° C. or lower. Thus, a Schottky junction / source / drain 115 is formed at the interface between the source / drain electrode 114 and the silicon substrate 101.

According to this embodiment, the same effect (merit) as the first embodiment can be obtained. In addition, the following advantages can be obtained. That is, the gate insulating region 104 is etched by the RIE method using the silicon nitride film 501 of about 10 nm formed between the interlayer insulating film 104 and the SiO ₂ film 103 of about 5 nm, and the gate groove 106 is formed. When formed, the silicon nitride film 501 serves as an RIE stopper, and the silicon substrate 101 can be prevented from being etched or subjected to RIE damage. Therefore, the characteristics of the MOS interface are remarkably improved.

(Sixth embodiment)
15A to 15D are process cross-sectional views illustrating the manufacturing process of the NMOSFET according to the sixth embodiment of the present invention. 15A to 15D show cross sections in the gate length direction. In this embodiment, the metal gate is formed not by the damascene method but by the RIE process. Description will be made in the order of processes. First, as shown in FIG. 15A, an element isolation insulating film 102 using STI technology is formed on a semiconductor silicon substrate 101, and a transistor for adjusting a threshold voltage of a transistor is formed in a channel region. Ion implantation is performed. Then, a Ta ₂ O ₅ film 108 is formed as a gate insulating film material on the silicon substrate surface.

Next, as shown in FIG. 15B, a barrier metal TiN film 109 and an Al film 110 are sequentially deposited as a metal gate material, and then patterned into a gate pattern by EB direct drawing, lithography and RIE, to form a metal gate. An electrode 111 is formed. Next, a sidewall insulating film 107 made of, for example, a silicon nitride film is formed on the side surface of the metal gate electrode 111. Next, as shown in FIG. 15C, a TEOS-SiO ₂ film having a thickness of about 200 nm is deposited and then planarized by CMP to form an interlayer insulating film 104.

  The subsequent steps are the same as in the other embodiments. As shown in FIG. 15D, after the interlayer insulating film 104 in the source / drain region is removed by etching, the source / drain electrode 104 and the Schottky junction / source / drain 115 are formed.

  According to this embodiment, since the formation and removal of the dummy gate are not required, the number of steps can be significantly reduced as compared with the damascene gate process. Further, since it is not necessary to perform a high-temperature heat process (usually about 1000 ° C.) for activating the source and drain, the manufacturing becomes easy. Furthermore, since the source and drain are not pn junctions but Schottky junctions, the short channel effect can be prevented even if a high-k gate insulating film is used. If the short channel effect is suppressed, the channel concentration can be reduced, so that the effect of improving the S-factor and reducing the threshold voltage can be obtained. Of course, the positions of the source and drain and the gate are formed by self-alignment.

(Seventh embodiment)
In the first embodiment, the manufacturing method of the NMOSFET shown in FIG. 1 has been described with reference to FIGS. In the present invention, an NMISFET manufacturing method different from the manufacturing method described with reference to FIGS.

16 and 17 are process cross-sectional views showing the manufacturing process of the NMISFET according to the seventh embodiment of the present invention. First, since the structure shown in FIG. 16A is formed through the steps described with reference to FIGS. 2A to 2C in the first embodiment, description thereof is omitted. Next, as shown in FIG. 16B, after forming a resist film having openings in regions where the source and drain of the MISFET are formed, the interlayer insulating film 104 and the SiO ₂ film 103 are selected using the resist film as a mask. Etching is performed to form source / drain trenches 113.

  Next, as shown in FIG. 16C, a metal material 114 that forms silicide by reacting with silicon in the source / drain trenches is buried in the source / drain trenches using the damascene method. Next, as shown in FIG. 16D, the metal material 114 and the silicon substrate 101 are reacted to form a Schottky junction / source / drain 115 made of silicide.

  In the step shown in FIG. 16B, the silicon substrate exposed at the bottom of the source / drain trench 113 is etched by CDE by about 30 nm, thereby forming an undercut under the gate sidewall and embedding the undercut. In this way, an Er film may be embedded and formed. Then, since the Schottky junction / source / drain 115 is formed to extend below the side wall insulating film 107 to be managed later, the parasitic resistance of the transistor is reduced by shortening the distance between the gate electrode and the source / drain. In addition, high driving ability can be realized.

  Next, as shown in FIG. 17E, a resist film 701 having an opening is formed on the metal material 114 on the Schottky junction / source / drain 115 and the interlayer insulating film 104 between the source / drain 115. Then, the interlayer insulating film 104 is selectively etched using the resist film 701 as a mask to form a gate groove 106 in which the opposite side surfaces of the source / drain electrodes are exposed.

Next, as shown in FIG. 17 (f), after removing the resist film 701, a silicon nitride film is deposited and etched by RIE to form a sidewall insulating film 107 inside the gate groove 106. If necessary, ion implantation for adjusting the threshold voltage of the transistor is performed on the silicon substrate 101 in the channel region via the SiO ₂ film 103 (not shown).

Next, as shown in FIG. 17G, similarly to the first embodiment, a metal gate electrode in which a Ta ₂ O ₅ film 108, a barrier metal TiN film 109 and an Al film 110 are stacked as a gate insulating film material. 111 is formed.

  In this embodiment, unlike the first embodiment, any metal can be used as the metal material embedded in the source / drain trench as long as it forms silicide by reacting with silicon. In the first embodiment, after forming the gate insulating film and the metal gate electrode, a metal for forming silicide at 450 ° C. or less has to be embedded in the source / drain in order to form the source and drain. . In this embodiment, since the gate electrode is formed after the source / drain is formed, a metal material that forms silicide at a high temperature can be used.

  In addition, after forming a groove in which the source / drain electrode 114 is exposed, a gate insulating film is formed on the side wall of the groove to form a gate groove, thereby forming the gate electrode in a self-aligned manner with respect to the source / drain. can do.

(Eighth embodiment)
In the second embodiment, the method for manufacturing the CMOSFET shown in FIG. 6 has been described with reference to FIGS. In the present invention, a CMISFET manufacturing method different from the manufacturing method described with reference to FIGS.

  18 to 20 are process cross-sectional views showing the manufacturing process of the CMOSFET according to the eighth embodiment of the present invention. First, since the cross-sectional view shown in FIG. 18A is formed in the process described with reference to FIGS. 2A to 2B, description thereof is omitted.

  Next, as shown in FIG. 18B, after forming a resist film 801 having an opening in the NMOS source / drain formation region, the interlayer insulating film 104 is selectively etched using the resist film 801 as a mask. Source / drain trenches 802 are formed. Next, as shown in FIG. 18C, an Er film 114 is deposited on the entire surface so as to fill the NMOS side source / drain trench 802.

  Next, as shown in FIG. 18D, the Er film 114 is subjected to chemical mechanical polishing to expose the surface of the interlayer insulating film 104 to form the source / drain electrodes 114. Then, an NMOS side Schottky junction / source / drain 115 is formed at the interface between the source / drain electrode 114 and the silicon substrate 101.

  Next, as shown in FIG. 19E, after forming a resist film 803 having an opening in the PMOS source / drain formation region, the interlayer insulating film 104 is selectively etched using the resist film 803 as a mask. Source / drain trenches 804 are formed. Next, as shown in FIG. 19F, a Pt film 201 is deposited on the entire surface so as to fill the PMOS side source / drain trench 804.

  Next, as shown in FIG. 19G, chemical mechanical polishing is performed on the Pt film 201 to expose the surface of the interlayer insulating film, and the source / drain electrode 201 is placed in the PMOS side source / drain trench 804. Form. Then, for example, a silicide reaction is caused at a low temperature of 450 ° C. or lower to form a PMOS-side Schottky junction / source / drain 202 at the interface between the PMOS-side source / drain electrode 201 and the silicon substrate 101.

  Next, as shown in FIG. 19H, a resist film 805 having an opening is formed on part of the source / drain electrodes 114 and 201 and the interlayer insulating film 104 between the source / drains 115 and 202. Then, using the resist film 805 as a mask, gate grooves 806a and 806b are formed in which the opposite side surfaces of the source / drain electrodes 114 and 201 on the PMOS side and NMOS side are exposed. Next, as shown in FIG. 20I, a sidewall insulating film 807 is formed inside the gate trench 106 by depositing a silicon nitride film and performing etching by the RIE method.

  Next, as shown in FIG. 20J, after a resist film 808 is selectively formed on the surface of the PMOS channel formation region, a transistor is formed on the surface of the silicon substrate 101 exposed on the bottom surface of the gate groove 806a in the NMOS channel formation region. Ions for threshold voltage adjustment are implanted. Next, as shown in FIG. 20 (k), after removing the resist film 808 on the surface of the PMOS channel formation region, a resist film 800 is formed on the surface of the NMOS channel formation region, and the bottom surface of the gate groove 806b in the PMOS channel formation region. Ions for adjusting the transistor threshold voltage are implanted into the exposed silicon substrate 101 surface.

  Next, as shown in FIG. 20L, as in the first embodiment, a metal gate electrode 111 in which a Ta2O5 film 108, a barrier metal TiN film 109 and an Al film 110 are stacked as a gate insulating film material is formed. To do.

(Ninth embodiment)
FIG. 21 is a cross-sectional view showing the configuration of an NMISFET according to the ninth embodiment of the present invention. In FIG. 21, the same parts as those in FIG. FIG. 21 shows a cross section in the gate length direction. In this NMISFET, an N-type extension region 2112 is formed between a Schottky junction / source / drain 115 and a p-type channel region 2111 as shown in FIG. Note that an SOI substrate in which a Si support substrate 2101, a BOX oxide film 2102, and a Si semiconductor layer (channel region 2111, extension region 2112) are stacked is used as the semiconductor substrate.

By forming the extension layer 2112 between the Schottky junction / source / drain 115 and the p-type channel region 2111, the height of the Schottky barrier is reduced and the current driving capability of the transistor is improved. be able to. However, the impurity concentration of the extension layer has an upper limit and is usually about 3 × 10 ¹⁹ cm ⁻³ . This concentration is a limit point at which ballistic conduction occurs at the Schottky junction when ErSi or PtSi is used for the source and drain. Also, in this structure, the impurity concentration of the opposite conductivity type to the extension region in the channel region is about the same as or higher than the impurity concentration of the extension region, so if the impurity concentration of the extension region is too high, the threshold voltage This is because Vth becomes too high. Therefore, depending on the desired threshold voltage Vth, it may be necessary to suppress the concentration to a concentration lower than the above concentration. Further, if the concentration of the extension region and the channel region is too high, there is a problem that the pn junction breakdown voltage of the both decreases, and this problem may determine the upper limit of the extension region.

  Next, the manufacturing process of the NMISFET shown in FIG. 21 will be described with reference to FIGS. Description will be made in the order of steps. First, as shown in FIG. 22A, a semiconductor SOI substrate in which a Si support substrate 2101, a BOX oxide film 2102, and a Si semiconductor layer 2103 are stacked is prepared.

Next, as shown in FIG. 22B, in order to perform element isolation using an STI (Shallow-trench-isolation) technique, the Si semiconductor layer 2103 in the element isolation region is removed to form a trench having a depth of about 100 nm. Then, a TEOS film is embedded in the trench to form an element isolation insulating film 102. Next, a SiO ₂ film 103 is formed on the surface of the Si semiconductor layer 2103 by thermal oxidation of about 5 nm. Then, ion implantation for forming extension regions to be a source and a drain later is performed on the Si semiconductor layer 2103 to form an N-type extension region 2112. For example, As is ion-implanted so as to have a concentration of about 1 × 10 ¹⁹ cm ⁻³ .

  Next, as shown in FIG. 22C, a TEOS film having a thickness of about 150 nm is deposited thereon by LPCVD to form an interlayer insulating film 104. This interlayer insulating film 104 is later used as a CMP stopper.

  Next, as shown in FIG. 22D, a resist film 105 is formed by direct drawing of an electron beam or lithography, and the interlayer insulating film 104 in a gate formation scheduled region is formed by RIE (Reactive-ion-etching) using the resist film 105 as a mask. The gate trench 106 is formed by etching using the above method.

Next, as shown in FIG. 23E, after removing the resist film 105, a sidewall insulating film 107 made of, for example, a silicon nitride film is formed inside the gate groove 106. Next, as shown in FIG. 23 (f), reverse conductivity type ions (boron or the like) are ion-implanted so as to cancel the n-type extension region 2112 previously implanted into the entire surface, and a p-type ion implantation region 2201 is obtained. Form. For example, ion implantation at a higher concentration (> 1 × 10 ¹⁹ cm ⁻³ ) than the extension region is performed so that the channel region becomes a p-type semiconductor. This ion implantation also adjusts the threshold voltage of the transistor. Then, as shown in FIG. 23G, the p-type ion implantation region 2201 is activated to form a P-type channel region 2111.

In the transistor of this embodiment, the formation of the silicide electrode for Schottky junction of the source / drain electrode with the extension region is planned to be formed at a low temperature (for example, 450 ° C. or less) (a deep junction using a high concentration impurity is not formed). There is no high temperature heat treatment step at 450 ° C. or higher after the formation. Therefore, a high dielectric constant film or a ferroelectric film (Ta ₂ O ₅ film, TiO ₂ film, Si ₃ N ₄ film, (Ba, Sr) TiO ₃ , HfO ₂ , ZrO ₂ , La ₂ O ₃ , Gd ₂ O ₃ , Y ₂ O ₃ , CaF ₂ , CaSn ₂ , CeO ₂ , Yttria Stabilized Zirconia, Al ₂ O ₃ , ZrSiO ₄ , HfSiO ₄ , Gd ₂ SiO ₅ , 2La ₂ O ₃ .3SiO ₂ , etc.) Further, a metal material (TiN, WN, Al, W, Ru, Mo, etc.) can be used for the gate electrode.

  If a high-temperature process of about 800 to 1000 ° C. exists after the gate is formed, the metal gate atoms diffuse into the gate insulating film to deteriorate the gate breakdown voltage, or the dielectric constant is low at the interface between the high-k film and silicon. A thin film layer is formed, an effective gate insulating film thickness is remarkably increased, and device performance is deteriorated.

In the present embodiment, a case where a Ta ₂ O ₅ film is used as a gate insulating film material and a laminated structure of barrier metals TiN and W is used as a metal gate material will be described. The manufacturing method will be described in detail. As shown in FIG. 24H, for example, the SiO ₂ film 103 at the bottom of the gate groove 106 is removed to expose the channel region 2111. Then, a silicon nitride film (NO nitride oxynitride film) having a thickness of 1 nm or less and a Ta ₂ O ₅ film 108 of about 4 nm are formed on the bottom of the gate trench 106 by CVD. At this time, the equivalent oxide thickness of the gate insulating film is 1.5 nm or less. Thereafter, a TiN film 109 having a thickness of, for example, about 5 nm is formed by CVD as a barrier metal, and a W film 110 having a thickness of, for example, about 300 nm is formed.

  Next, as shown in FIG. 24I, the laminated structure of the TiN film 109 and the W film 110 is polished by CMP, and the TiN film 109 and the W film 110 on the TEOS film 104 are patterned by the damascene method. Then, the metal gate electrode 111 is formed.

  Thereafter, as shown in FIG. 24J, after forming a resist film 2202 having an opening in the element region by lithography or the like, the interlayer insulating film 104 in the source / drain region is selectively etched away using the resist film 2202 as a mask. Then, the source / drain trench 2203 is formed.

Next, as shown in FIG. 25 (k), a source / drain electrode 114 made of, for example, Er is deposited so that the inside of the source / drain trench 2203 is filled. Next, as shown in FIG. 25L, the source / drain electrode 114 on the interlayer insulating film 104 is polished by CMP to bury and form the source / drain electrode 114 in the source / drain trench 2203. Further, as shown in FIG. 25 (m), a silicide reaction is caused at a low temperature (for example, at 450 ° C. or lower) to form silicide metal (ErSi ₂ ), and Schottky junction source / drain 115 is formed.

  After the formation of the source and drain, it is the same as a normal LSI manufacturing process. That is, an interlayer insulating film TEOS is deposited by a CVD method, contact holes are formed on the source / drain and gate electrodes, and an upper metal wiring (for example, Cu wiring) is formed by a dual damascene method.

  As described above, since the “dummy gate formation and removal” required in the conventional damascene gate becomes unnecessary, the number of processes can be greatly reduced. Further, since it is not necessary to perform a high temperature heat process (usually about 1000 ° C.) for activating the deep diffusion layers of the source and drain, the manufacture becomes easy.

  In addition, the following advantages of the damascene gate process will continue. That is, [1] Since the gate is processed by CMP instead of RIE, plasma damage is not introduced into the gate insulating film. [2] It is very difficult to RIE a metal gate on a thin gate insulating film, but this is not necessary in the process of the present invention. [3] Since the surface is completely flattened after the gate processing, the subsequent manufacturing process becomes easy. [4] The positions of the source, drain and gate are formed by self-alignment.

  Furthermore, by applying a Schottky junction to the source / drain of the SOI-MOSFET, it is possible to make use of the characteristics of the contact to make up for the defects of the SOI element, and by using the SOI, the defects of the Schottky contact. Can be removed. More specifically, [1] The substrate floating problem of SOI-MOSFET can be suppressed by the effect of the Schottky barrier in both the source and drain. [2] The leakage current at the drain contact can be suppressed by adopting the SOI structure. The off-state current (power consumption) of the transistor can be reduced.

(Tenth embodiment)
In the present embodiment, a description will be given of a method of manufacturing a CMOSFET in which the forming materials constituting the Schottky junction / source / drain are different between the NMOSFET and the PMOSFET.

  Next, a method for manufacturing the CMOSFET will be described. 26 to 28 are process cross-sectional views illustrating the manufacturing process of the CMOSFET according to the tenth embodiment of the present invention.

  Since FIGS. 23A to 23E are the same as those in the ninth embodiment, the description thereof is omitted. However, n-type and p-type extension regions 2112a and 2112b are formed in the nMOS and pMOS regions, respectively. The subsequent steps will be described in order. As shown in FIG. 26A, gate trenches 2601a and 2601b are formed in the interlayer insulating film 104 in the gate formation scheduled region, and a sidewall insulating film 107 made of, for example, a silicon nitride film is formed inside thereof. Form.

Next, as shown in FIG. 26B, a resist film 2602 covering the surface of the PMOSFET formation region and having an opening in the NMOSFET formation region is formed, and then the impurity introduced into the extension region 2112a is reversed. Conductive ion implantation is performed to form a p-type ion implantation region 2201a in the extension region 2112a exposed at the bottom of the gate groove 2601a. For example, channel ion implantation is performed at a higher concentration (> 1 × 10 ¹⁹ cm ⁻³ ) than the n-type extension region 2112a so that the channel region becomes a p-type semiconductor. This ion implantation also adjusts the threshold voltage of the transistor.

Next, as shown in FIG. 26C, after the resist film 2602 is removed, a resist film 2603 is formed which covers the surface of the NMOSFET formation region and has an opening in the PMOSFET formation region, and is then introduced into the extension region 2112b. In order to cancel the impurities, reverse conductivity type ion implantation is performed, and an n-type ion implantation region 2201b is formed in the extension region 2112b exposed at the bottom of the gate groove 2601b. For example, channel ion implantation is performed at a higher concentration (> 1 × 10 ¹⁹ cm ⁻³ ) than the p-type extension region 2112b so that the channel region becomes an n-type semiconductor. This ion implantation also adjusts the threshold voltage of the transistor.

  Next, as shown in FIG. 26D, after removing the resist film 2603, heat treatment is performed to activate the ions implanted into the ion implantation regions 2201a and 2201b, so that the P-type channel region 2111a and the N-type channel region are obtained. 2111b is formed.

In the transistor of the present invention, the source / drain electrodes are to be formed at a low temperature (for example, at 450 ° C. or less) by silicide (Schottky) junctions with the extension regions 2112a and 2112b (no deep junction using a high concentration impurity is formed). Therefore, there is no high-temperature heat treatment process at 450 ° C. or higher after gate formation. Therefore, a high dielectric constant film or a ferroelectric film (Ta ₂ O ₅ film, TiO ₂ film, Si ₃ N ₄ film, (Ba, Sr) TiO ₃ , HfO ₂ , ZrO ₂ , La ₂ O ₃ , Gd ₂ O ₃ , Y ₂ O ₃ , CaF ₂ , CaSnF ₂ , CeO ₂ , YttriaStabilizedZirconia, Al ₂ O ₃ , ZrSiO ₄ , HfSiO ₄ , Gd ₂ SiO ₅ , 2La ₂ O ₃ / 3SiO ₂ , etc.) are used for the gate insulating film A metal material (TiN, WN, Al, W, Ru, Mo, etc.) can be used for the gate electrode.

Here, similarly to the ninth embodiment, a Ta2O5 film is used as a gate insulating film material, and a laminated structure of barrier metals TiN and W is used as a metal gate material. As shown in FIG. 27E, a Ta ₂ O ₅ film 108 and a metal gate electrode 111 in which a TiN film and a W film are stacked are formed inside the gate groove.

Thereafter, as shown in FIG. 27F, after forming a resist film 2604 having an opening in the element region on the NMOS side by lithography or the like, the interlayer insulating film 104 in the NMOS source / drain region is formed using the resist film 2202 as a mask. An NMOS side source / drain trench 2605a is formed by selective etching. Next, as shown in FIG. 27G, a metal material, for example, an Er film 114 is deposited in the NMOS side source and drain trenches 2605a. Next, as shown in FIG. 27H, after removing the Er film 114 on the interlayer insulating film 104, a silicide reaction between the Er film 114 and the extension region 2112a is caused at a low temperature (for example, at 450 ° C. or lower). Silicide metal (ErSi ₂ ) is formed, and Schottky junction source / drain 115 is formed.

  Thereafter, as shown in FIG. 28 (i), a resist film 2606 having an opening in the element region on the PMOS side is formed by lithography or the like by lithography or the like, and then the layer between the PMOS source / drain regions is masked using the resist film 2202 as a mask. The insulating film 104 is selectively removed by etching to form a PMOS side source / drain trench 2605b. Next, as shown in FIG. 28J, a metal material, for example, a Pt film 201 is deposited in the PMOS-side source and drain trench 2605b. Next, as shown in FIG. 28 (k), after removing the Pt film on the interlayer insulating film 104, a silicide reaction is caused at a low temperature (for example, at 450 ° C. or lower) to form silicide metal (PtSi), and shot A key junction source / drain 202b is formed.

  After the formation of the source and drain, it is the same as a normal LSI manufacturing process. That is, an interlayer insulating film TEOS is deposited by CVD, contact holes are formed on the source / drain and gate electrodes, and an upper metal wiring (for example, Cu wiring) is formed by a dual damascene method. Since these sectional views are the same as those in the eighth embodiment, they are omitted.

  As described above, since the “dummy gate formation and removal” required in the conventional damascene gate becomes unnecessary, the number of processes can be greatly reduced. Further, since it is not necessary to perform a high temperature heat process (usually about 1000 ° C.) for activating the deep diffusion layers of the source and drain, the manufacture becomes easy.

  Further, in this embodiment, different metal materials are used for the NMOS and PMOS as the source / drain materials, and the following merits arise. That is, in a transistor using a Schottky contact (junction) for the source and drain, a Schottky having a small work function for the N channel and a large work function for the P channel is used in order to avoid a decrease in current driving capability. Contact material is required. In this embodiment, erbium silicide (ErSi2) having a small work function can be used for NMOS, and PtSi having a large work function can be used for PMOS. Therefore, it is possible to increase both NMOS and PMOS drive currents. become. Further, by selecting a Schottky contact material, the threshold voltages of NMOS and PMOS can be controlled separately.

(Eleventh embodiment)
FIG. 29 is a process sectional view showing a manufacturing process of the NMOSFET according to the eleventh embodiment of the present invention. Note that FIG. 29 shows a cross section in the gate length direction for explanation. A feature of this embodiment is that a bulk silicon substrate is used instead of SOI. The rest is the same as in the ninth embodiment, and a detailed description of the manufacturing method is omitted.

  According to this example, the same effect (merit) as in the ninth embodiment can be obtained except for the merit caused by SOI.

  FIG. 29D shows a structure in which the bottom surface of the metal silicide is included in the extension layer 2101. In this way, junction leakage can be reduced.

(Twelfth embodiment)
30 to 32 are process sectional views showing the manufacturing process of the NMOSFET according to the twelfth embodiment of the present invention. 30 to 32 show a cross section in the gate length direction for explanation. In this embodiment, a laminated film of a silicon nitride film of about 10 nm and a SiO ₂ film of about 5 nm is formed under the interlayer film TEOS. In the description in the order of steps, first, as shown in FIG. 30A, a semiconductor SOI substrate in which a Si support substrate 2101, a BOX oxide film 2102, and a Si semiconductor layer 2103 are stacked is prepared.

Next, as shown in FIG. 30B, in order to perform element isolation using STI (Shallow-trench-isolation) technology, the Si semiconductor layer 2103 in the element isolation region is removed to form a trench having a depth of about 100 nm. Then, a TEOS film is embedded in the trench to form an element isolation insulating film 102. Next, a SiO ₂ film 103 is formed on the surface of the Si semiconductor layer 2103 by thermal oxidation of about 5 nm. Then, ion implantation for forming extension regions to be a source and a drain later is performed on the Si semiconductor layer 2103 to form an N-type extension region 2112. For example, As is ion-implanted so as to have a concentration of about 1 × 10 ¹⁹ cm ⁻³ .

  Next, as shown in FIG. 30C, a silicon nitride film 3001 of about 10 nm is deposited on the oxide film, and then a TEOS film 104 of about 150 nm is deposited by LPCVD.

  Next, as shown in FIG. 30D, a resist film 105 is formed by direct drawing of an electron beam or lithography, and the interlayer insulating film 104 in a gate formation scheduled region is formed by RIE (Reactive-ion-etching) using the resist film 105 as a mask. The gate trench 106 is formed by etching using the above method. At this time, the silicon nitride film 3001 serves as an etching stopper and prevents the extension region 2112 from being etched.

Next, as shown in FIG. 31 (e), after removing the resist film 105, a sidewall insulating film 107 made of, for example, a silicon nitride film is formed inside the gate groove 106. Then, reverse conductivity type ions (such as boron) are ion-implanted so as to cancel the n-type extension region 2112 implanted on the entire surface, and then the p-type ion implantation region is activated to form a P-type channel region 2111. Form. This ion implantation also adjusts the threshold voltage of the transistor at the same time. Next, as shown in FIGS. 31F and 31G, the SiO ₂ film 103 on the channel region 2111 is removed with HF or the like, and then the damascene method is used. Is used to form a Ta ₂ O ₅ film 108, a TiN film 109, and a W film 110 (metal gate electrode 111) in the gate trench 106.

Next, as shown in FIG. 32H, a source / drain trench 113 is formed using the resist film 112 as a mask. Then, as shown in FIG. 32 (i), after removing the resist film 112, an Er film 114 is formed in the source / drain trench 113 by using a damascene method. Then, silicide reaction between the Er film 114 and the extension region 2112a is caused at a low temperature (for example, at 450 ° C. or lower) to form silicide metal (ErSi ₂ ), and Schottky junction source / drain 115 is formed.

According to the present embodiment, the same effect (merit) as in the ninth embodiment can be obtained. In addition, the following advantages can be obtained. That is, since a laminated film of a silicon nitride film of about 10 nm and a SiO ₂ film of about 5 nm is formed under the interlayer film TEOS, the TEOS in the gate formation scheduled region is etched by RIE (Reactive-ion-etching) method. When forming the gate trench, the silicon nitride film serves as an RIE stopper, and the silicon substrate can be prevented from being etched or subjected to RIE damage. Therefore, the characteristics of the MOS interface are remarkably improved.

  In addition, this invention is not limited to the said embodiment. For example, in the above embodiment, the material of the gate insulating film is a high dielectric film and the material of the gate electrode is a metal. However, the material of the gate insulating film is a high dielectric film, and the material of the gate electrode is a metal. It is not necessary. Further, the material of the gate electrode may be a metal, and the material of the gate insulating film may not be a high dielectric film.

  In addition, the present invention can be variously modified and implemented without departing from the scope of the invention.

FIG. 3 is a cross-sectional view showing a configuration of an NMOSFET according to the first embodiment. Process sectional drawing which shows the manufacturing process of NMOSFET shown in FIG. Process sectional drawing which shows the manufacturing process of NMOSFET shown in FIG. Process sectional drawing which shows the manufacturing process of NMOSFET shown in FIG. Process sectional drawing which shows the manufacturing process of NMOSFET shown in FIG. Sectional drawing which shows the structure of CMOSFET concerning 2nd Embodiment. Process sectional drawing which shows the manufacturing process of CMOSFET shown in FIG. Process sectional drawing which shows the manufacturing process of CMOSFET shown in FIG. Process sectional drawing which shows the manufacturing process of CMOSFET shown in FIG. Sectional drawing which shows the structure of NMOSFET concerning 3rd Embodiment. Sectional drawing which shows the structure of NMOSFET concerning 4th Embodiment. FIG. 12 is a process cross-sectional view illustrating a manufacturing process of the NMOSFET illustrated in FIG. 11. Process sectional drawing which shows the manufacturing process of NMOSFET concerning 5th Embodiment. Process sectional drawing which shows the manufacturing process of NMOSFET concerning 5th Embodiment. Process sectional drawing which shows the manufacturing process of NMOSFET concerning 6th Embodiment. Process sectional drawing which shows the manufacturing process of NMOSFET concerning 7th Embodiment. Process sectional drawing which shows the manufacturing process of NMOSFET concerning 7th Embodiment. Process sectional drawing which shows the manufacturing process of CMOSFET concerning 8th Embodiment. Process sectional drawing which shows the manufacturing process of CMOSFET concerning 8th Embodiment. Process sectional drawing which shows the manufacturing process of CMOSFET concerning 8th Embodiment. Sectional drawing which shows the structure of NMISFET concerning 9th Embodiment. FIG. 22 is a process cross-sectional view illustrating a manufacturing process of the NMISFET illustrated in FIG. 21. FIG. 22 is a process cross-sectional view illustrating a manufacturing process of the NMISFET illustrated in FIG. 21. FIG. 22 is a process cross-sectional view illustrating a manufacturing process of the NMISFET illustrated in FIG. 21. FIG. 22 is a process cross-sectional view illustrating a manufacturing process of the NMISFET illustrated in FIG. 21. Process sectional drawing which shows the manufacturing process of CMOSFET concerning 10th Embodiment. Process sectional drawing which shows the manufacturing process of CMOSFET concerning 10th Embodiment. Process sectional drawing which shows the manufacturing process of CMOSFET concerning 10th Embodiment. Process sectional drawing which shows the manufacturing process of NMOSFET concerning 11th Embodiment. Process sectional drawing which shows the manufacturing process of NMOSFET concerning 12th Embodiment. Process sectional drawing which shows the manufacturing process of NMOSFET concerning 12th Embodiment. Process sectional drawing which shows the manufacturing process of NMOSFET concerning 12th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Silicon substrate 102 ... Element isolation insulating film 103 ... SiO2 film 104 ... Interlayer insulating film 105 ... Resist film 106 ... Gate groove 107 ... Side wall insulating film 108 ... Ta2O5 film 109 ... Barrier metal TiN film 110 ... Al film 111 ... Metal gate Electrode 112 ... resist film 113 ... source / drain trench 114 ... source / drain electrode 115 ... Schottky junction / source / drain 116 ... interlayer insulating film 117 ... Al wiring

Claims (2)

Forming an interlayer insulating film on the silicon substrate;
A step of selectively removing the interlayer insulating film between the source and drain formation planned regions of the PMISFET and NMISSET to form a gate trench;
Forming a sidewall insulating film on the sidewall of the gate trench;
Exposing the silicon substrate to the bottom surface of the gate groove and forming a gate insulating film on the exposed surface of the silicon substrate;
Embedding and forming a gate electrode in the gate trench;
Removing the interlayer insulating film in the source and drain formation scheduled regions of the PMISFET, and forming a PMIS side source / drain trench in which the surface of the silicon substrate is exposed at the bottom;
Embedding and forming a first metal film in the PMIS side source / drain trench, and forming a source electrode and a drain electrode of the PMISFET;
Reacting the silicon substrate with the source and drain electrodes of the PMISFET to form a silicide film that forms a Schottky junction with the substrate to form the source and drain of the PMISFET;
Removing the interlayer insulating film in regions where NMISFET sources and drains are to be formed, and forming NMIS side source / drain trenches exposing the surface of the silicon substrate at the bottom;
Embedding and forming a second metal film made of a material different from the first metal film in the NMIS side source / drain trench, and forming a source electrode and a drain electrode of the NMISFET;
A step of reacting the silicon substrate with a source electrode and a drain electrode of an NMISFET to form a silicide film that forms a Schottky junction with the substrate to form a source and a drain of the NMISFET. Manufacturing method. The gate electrode and the gate insulating film is formed of a metal material and the high dielectric, reaction between the silicon substrate and the metal film according to claim 1, characterized in that it is carried out at 450 ° C. below the temperature A method for manufacturing a semiconductor device.

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