[go: up one dir, main page]

JP4591051B2 - Three-dimensional multifaceted composite semiconductor chip and arithmetic processing unit - Google Patents

Three-dimensional multifaceted composite semiconductor chip and arithmetic processing unit Download PDF

Info

Publication number
JP4591051B2
JP4591051B2 JP2004333855A JP2004333855A JP4591051B2 JP 4591051 B2 JP4591051 B2 JP 4591051B2 JP 2004333855 A JP2004333855 A JP 2004333855A JP 2004333855 A JP2004333855 A JP 2004333855A JP 4591051 B2 JP4591051 B2 JP 4591051B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
composite semiconductor
dimensional
dimensional multi
transmission pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004333855A
Other languages
Japanese (ja)
Other versions
JP2006147735A (en
Inventor
庸美 徳原
Original Assignee
庸美 徳原
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 庸美 徳原 filed Critical 庸美 徳原
Priority to JP2004333855A priority Critical patent/JP4591051B2/en
Publication of JP2006147735A publication Critical patent/JP2006147735A/en
Application granted granted Critical
Publication of JP4591051B2 publication Critical patent/JP4591051B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)

Description

本発明は、ＬＳＩなどの半導体チップを構成要素とする３次元多面構造複合半導体チップ及び該３次元多面構造複合半導体チップをクラスタ結合して構成した演算処理装置に関する。   The present invention relates to a three-dimensional multifaceted structure composite semiconductor chip having a semiconductor chip such as an LSI as a constituent element, and an arithmetic processing apparatus configured by clustering the three-dimensional multifaceted structure composite semiconductor chip.

薄膜状のＬＳＩチップを３次元的に貼り合わせて集積した３次元半導体チップが従来知られている（例えば特許文献１参照）。また、メモリ密度を効率的に向上させるキュービックメモリ・アレイが従来知られている（例えば特許文献２参照）。
特開２００２−３３４９６７ 特開２００４−５６１４０ Conventionally known is a three-dimensional semiconductor chip in which thin-film LSI chips are three-dimensionally bonded and integrated (see, for example, Patent Document 1). Further, a cubic memory array that efficiently improves the memory density is conventionally known (see, for example, Patent Document 2).
JP 2002-334967 A JP 2004-56140 A

従来のＬＳＩ演算チップは、いずれも演算速度をより高くし、処理速度を速めるために、ＬＳＩを基板上に積層したり、あるいはＬＳＩをより集積化するために回路を基板の平面上に拡大している。しかしながら、ＬＳＩチップの集積度の増大を基板の積層方向又は平面方向に拡大しようとすると、ＬＳＩチップの構造の複雑化や基板の大型化あるいは製造コストの増大化を招いてしまうという問題点がある。
本発明は、上記問題点を解決することを目的とするものである。 All of the conventional LSI computing chips have the LSIs stacked on the substrate in order to increase the calculation speed and the processing speed, or the circuit is expanded on the plane of the substrate to further integrate the LSIs. ing. However, if an increase in the degree of integration of LSI chips is to be expanded in the direction in which the substrates are stacked or planar, there is a problem that the structure of the LSI chips is complicated, the size of the substrate is increased, or the manufacturing cost is increased. .
The present invention aims to solve the above problems.

上記目的を達成するため本発明は、基板に回路部が形成された四角形のエレメント半導体チップを複数貼り合わせ、互いの回路部を接続して内側に共有閉鎖空間を有する多面体形状とし、前記各エレメント半導体チップの表面に電磁／電界結合用の面接触伝送パターンを形成し、該面接触伝送パターンを前記回路部に接続したものである。
また本発明は、前記エレメント半導体チップの背面に背面にアンテナを形成し、該アンテナを前記回路部に接続したものである。
また本発明は、前記各エレメント半導体チップの貼り合わせ面に配線用コンタクトを形成し、互いに向き合った配線用コンタクトどうしの接触により、互いに貼り合わせた一対のエレメント半導体チップの回路部を電子的に接続したものである。
また本発明は、前記回路部は演算回路ブロックと、該演算回路ブロックを制御する制御回路ブロックと、該制御回路ブロックと前記演算回路ブロックに接続するマルチプレクサとより構成され、該マルチプレクサが前記面接触伝送パターンとアンテナに接続しているものである。
また本発明は、基板に回路部が形成された四角形のエレメント半導体チップを複数貼り合わせ、互いの回路部を接続して内側に共有閉鎖空間を有する多面体形状とし、前記各エレメント半導体チップの表面に電磁／電界結合用の面接触伝送パターンを形成し、背面にアンテナを形成し、該面接触伝送パターンと前記アンテナを前記回路部に接続した３次元多面構造複合半導体チップを多数用意し、これら多数の３次元多面構造複合半導体チップを面接触させ、前記面接触伝送パターンを介して任意の方向に結合したものである。
また本発明は、前記３次元多面構造複合半導体チップが立方体であることを特徴とするものである。
また本発明は、前記多数の３次元多面構造複合半導体チップは、回路部が演算回路ブロックを含む演算用３次元多面構造複合半導体チップと、前記共有閉鎖空間に冷却媒体が充填された熱伝導のための３次元多面構造複合半導体チップと、回路部が電力伝送回路ブロックを含む電力伝送のための３次元多面構造複合半導体チップとからなるものである。 In order to achieve the above object, the present invention provides a polyhedral shape in which a plurality of rectangular element semiconductor chips each having a circuit portion formed on a substrate are bonded together, the circuit portions are connected to each other, and a shared closed space is formed inside. A surface contact transmission pattern for electromagnetic / electric field coupling is formed on the surface of the semiconductor chip, and the surface contact transmission pattern is connected to the circuit portion.
In the present invention, an antenna is formed on the back surface of the element semiconductor chip, and the antenna is connected to the circuit portion.
Further, according to the present invention, a wiring contact is formed on a bonding surface of each element semiconductor chip, and a circuit portion of a pair of element semiconductor chips bonded to each other is electronically connected by contact between the wiring contacts facing each other. It is what.
According to the present invention, the circuit unit includes an arithmetic circuit block, a control circuit block for controlling the arithmetic circuit block, and a multiplexer connected to the control circuit block and the arithmetic circuit block. It is connected to the transmission pattern and the antenna.
Further, the present invention provides a polyhedral shape having a plurality of rectangular element semiconductor chips each having a circuit portion formed on a substrate, connected to each other and having a shared closed space inside, and is formed on the surface of each element semiconductor chip. A surface contact transmission pattern for electromagnetic / electric field coupling is formed, an antenna is formed on the back surface, and a large number of three-dimensional multifaceted composite semiconductor chips are prepared in which the surface contact transmission pattern and the antenna are connected to the circuit unit. These three-dimensional multi-face structure composite semiconductor chips are brought into surface contact and coupled in an arbitrary direction via the surface contact transmission pattern.
The present invention is also characterized in that the three-dimensional multi-faceted composite semiconductor chip is a cube.
According to the present invention, the plurality of three-dimensional multi-faceted composite semiconductor chips include an arithmetic three-dimensional multi-faceted composite semiconductor chip having a circuit portion including an arithmetic circuit block, and a heat conducting material in which the shared closed space is filled with a cooling medium. A three-dimensional multi-face structure composite semiconductor chip for power transmission and a three-dimensional multi-face structure composite semiconductor chip for power transmission whose circuit section includes a power transfer circuit block.

本発明は、半導体チップを大型化することなく、小さな占有面積でチップの集積度を高めることができる。しかも、半導体チップどうしの結合のための配線を無くすことができるとともに、多数の半導体チップを結合することにより高速処理が可能となる。   The present invention can increase the degree of integration of a chip with a small occupation area without increasing the size of the semiconductor chip. In addition, wiring for connecting semiconductor chips can be eliminated, and high-speed processing can be performed by connecting a large number of semiconductor chips.

以下に本発明の実施の形態を添付した図面を参照して詳細に説明する。
図１に示す３次元多面構造複合半導体チップ２は、六面体の各面が、四角形のＬＳＩチップからなるエレメント半導体チップ４により構成されている。前記３次元多面構造複合半導体チップ２は、その構成要素である前記エレメント半導体チップ４の回路特性により、演算処理用の３次元多面構造複合半導体チップ２Ａと、熱伝導用の３次元多面構造複合半導体チップ２Ｂと、電力伝送用の３次元多面構造複合半導体チップ２Ｃとが用意されている。 Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
A three-dimensional multi-faceted composite semiconductor chip 2 shown in FIG. 1 is composed of element semiconductor chips 4 each having a hexahedron formed of a square LSI chip. According to the circuit characteristics of the element semiconductor chip 4 which is a component of the three-dimensional multi-face structure composite semiconductor chip 2, the 3-dimensional multi-face structure composite semiconductor chip 2A for arithmetic processing and the three-dimensional multi-face structure composite semiconductor for heat conduction are used. A chip 2B and a three-dimensional multi-face structure composite semiconductor chip 2C for power transmission are prepared.

前記演算用の３次元多面構造複合半導体チップ２Ａを構成するエレメント半導体チップ４のシリコン基板には、各種の演算処理用の回路部６が形成され、演算チップを構成している。前記演算チップを構成するエレメント半導体チップ４には、その表面に、絶縁体を介して面接触伝送パターン８が形成されている。またその背面には、共有閉鎖空間５を通して、他のエレメント半導体チップ４と電磁波的伝送を行うためのアンテナ１０が形成されている。前記面接触伝送パターン８は、他の３次元多面構造複合半導体チップ２の面接触伝送パターンと面接触したとき、これら隣接する３次元多面構造複合半導体チップ２，２が、面接触伝送パターン８，８を介して、互いに電磁／電界結合し、隣接する２つの３次元多面構造複合半導体チップ２，２の間で信号の送受を行うことができるようにするためのものである。 Various arithmetic processing circuit sections 6 are formed on the silicon substrate of the element semiconductor chip 4 constituting the arithmetic three-dimensional multi-plane structure composite semiconductor chip 2A to constitute an arithmetic chip. A surface contact transmission pattern 8 is formed on the surface of the element semiconductor chip 4 constituting the arithmetic chip via an insulator. In addition, an antenna 10 for electromagnetic wave transmission with other element semiconductor chips 4 is formed on the rear surface through the shared closed space 5. When the surface contact transmission pattern 8 is in surface contact with the surface contact transmission pattern of another three-dimensional multi-surface structure composite semiconductor chip 2, these adjacent three-dimensional multi-surface structure composite semiconductor chips 2 and 2 are connected to the surface contact transmission pattern 8, 8 is configured to be electromagnetically / electrically coupled to each other and to transmit and receive signals between two adjacent three-dimensional multi-faceted composite semiconductor chips 2 and 2.

前記演算用３次元多面構造複合半導体チップ２Ａ用の各エレメント半導体チップ４の貼り合わせ面には、配線用コンタクト１２が形成されている。６枚の各エレメント半導体チップ４は、立方体などの多面体を構成するように、縁部の貼り合わせ面が接着され、この配線用コンタクト１２を介して、各エレメント半導体チップ４の回路部６が相互に接続されている。各エレメント半導体チップ４の回路部６は、基板に埋め込まれた多層構造の配線パターン１４を介して、前記配線用コンタクト１２に接続している。 A wiring contact 12 is formed on the bonding surface of each element semiconductor chip 4 for the arithmetic three-dimensional multi-face structure composite semiconductor chip 2A. The six element semiconductor chips 4 are bonded to each other at their edges so as to form a polyhedron such as a cube. The circuit parts 6 of the element semiconductor chips 4 are connected to each other via the wiring contacts 12. It is connected to the. The circuit portion 6 of each element semiconductor chip 4 is connected to the wiring contact 12 via a multilayer wiring pattern 14 embedded in the substrate.

前記演算処理用の回路部６は、図２に示すように、演算回路ブロック２０，制御回路ブロック２４及びマルチプレクサ２２から構成されている。演算回路ブロック２０は、固定小数点乗算器、除算器、加減算器、バレルシフタを備えている。これら演算回路ブロック２０、制御回路ブロック２４は、マルチプレクサ２２に接続し、マルチプレクサ２２は、基板に形成された電気的ドライバ・レシーバ１６，電磁／電界結合器１８及び無線変調／復調器２０に接続している。 The arithmetic processing circuit section 6 includes an arithmetic circuit block 20, a control circuit block 24, and a multiplexer 22, as shown in FIG. The arithmetic circuit block 20 includes a fixed point multiplier, a divider, an adder / subtracter, and a barrel shifter. The arithmetic circuit block 20 and the control circuit block 24 are connected to a multiplexer 22, and the multiplexer 22 is connected to an electric driver / receiver 16, an electromagnetic / electric field coupler 18 and a radio modulator / demodulator 20 formed on a substrate. ing.

熱伝導用の３次元多面構造複合半導体チップ２Ｂは、隣接する３次元多面構造複合半導体チップの発熱を抑制するためのものであり、六面体構造の内側の共有閉鎖空間が適宜な冷却媒体により充填されている。この冷却媒体は、コスト的に可能であれば、ダイヤモンドが望ましいが、特にダイヤモンドでなくても、隣接する３次元多面構造複合半導体チップの発熱を効率的に抑制する物質であれば冷却液その他どのようなものでも良い。 The three-dimensional multi-faced composite semiconductor chip 2B for heat conduction is for suppressing heat generation of the adjacent three-dimensional multi-face structure composite semiconductor chip, and the shared closed space inside the hexahedral structure is filled with an appropriate cooling medium. ing. The cooling medium is preferably diamond if possible in terms of cost. However, even if it is not diamond, any cooling liquid or any other material can be used as long as it is a substance that efficiently suppresses heat generation of the adjacent three-dimensional multi-faceted composite semiconductor chip. Something like that.

熱伝導用の３次元多面構造複合半導体チップ２Ｂの他の構成は、演算用の３次元多面構造複合半導体チップ２Ａと同一である。電力伝送用の３次元多面構造複合半導体チップ２Ｃは、これを構成する各エレメント半導体チップの表面に回路部６Ａが形成され、該回路部６Ａは、マルチプレクサ２２と、電力伝送回路ブロック２０Ａと、制御回路ブロック２４とから構成されている。また、この電力伝送用の３次元多面構造複合半導体チップ２Ｃの各エレメント半導体チップ１２は、表面に面接触伝送パターン８が形成され、背面にはアンテナ１０が形成されている。 Other configurations of the three-dimensional multi-face structure composite semiconductor chip 2B for heat conduction are the same as the 3-dimensional multi-face structure composite semiconductor chip 2A for calculation. The power transmission three-dimensional multi-face structure composite semiconductor chip 2C has a circuit portion 6A formed on the surface of each element semiconductor chip constituting the power transmission circuit. The circuit portion 6A includes a multiplexer 22, a power transmission circuit block 20A, and a control circuit. The circuit block 24 is constituted. Each element semiconductor chip 12 of the three-dimensional multi-face structure composite semiconductor chip 2C for power transmission has a surface contact transmission pattern 8 formed on the front surface and an antenna 10 formed on the back surface.

更に電力伝送用の３次元多面構造複合半導体チップ２Ｃは、他の３次元多面構造複合半導体チップと同様に、基板に、配線パターン１４、配線用コンタクト１２、電気的ドライバ・レシーバ１６、面接触伝送パターン８に接続する電磁／電界結合器１８、アンテナ１０に接続する無線変調／復調器２０が形成されている。電気的ドライバ・レシーバ１６は、配線パターン１４と回路部６，６Ａ側のインピーダンスをマッチングさせ、配線用コンタクト１２と演算回路ブロック２０、電力伝送回路ブロック２０Ａとの間で、マルチプレクサ２２を介して、信号を送受する機能を有している。 Further, the 3D multi-sided composite semiconductor chip 2C for power transmission is similar to the other 3D multi-sided composite semiconductor chip in that the wiring pattern 14, the wiring contact 12, the electrical driver / receiver 16, and the surface contact transmission are formed on the substrate. An electromagnetic / electric field coupler 18 connected to the pattern 8 and a radio modulator / demodulator 20 connected to the antenna 10 are formed. The electrical driver / receiver 16 matches the impedance of the wiring pattern 14 and the circuit units 6 and 6A, and between the wiring contact 12, the arithmetic circuit block 20, and the power transmission circuit block 20A via the multiplexer 22, It has a function to send and receive signals.

次に本実施形態の動作について説明する。
３次元多面構造複合半導体チップ２を構成する６枚のエレメント半導体チップ４は、所定の位置に設定された貼り合わせ部が接着され、６面にＬＳＩチップが形成され内側に共有閉鎖空間５が形成された立方体などの多面体を構成する。３次元多面構造複合半導体チップ２は、図１（Ｄ）のように、演算回路のクラスタ接続の原理に基づいて、複数、立体状に当接配置することにより、互いの接触面の面接触伝送パターン１８を通じて、各３次元多面構造複合半導体チップ２が電磁的、あるいは、電界的に結合する。 Next, the operation of this embodiment will be described.
The six element semiconductor chips 4 constituting the three-dimensional multi-faceted composite semiconductor chip 2 are bonded to each other at a predetermined position, an LSI chip is formed on the six faces, and a shared closed space 5 is formed inside. A polyhedron such as a cube is formed. As shown in FIG. 1 (D), the three-dimensional multifaceted structure composite semiconductor chip 2 is arranged in contact with each other in a three-dimensional manner based on the principle of cluster connection of arithmetic circuits, so that surface contact transmission between the contact surfaces of each other is achieved. Through the pattern 18, each three-dimensional multi-faceted composite semiconductor chip 2 is electromagnetically or electrically coupled.

演算用の３次元多面構造複合半導体チップ２Ａと熱伝導用の３次元多面構造複合半導体チップ２Ｂと電力伝送用の３次元多面構造複合半導体チップ２Ｃを目的に応じて、クラスタ接続の原理に基づき、選択し、且つ、水平方向及び垂直方向に接触結合させることにより、所望の機能を有する、演算処理装置が構成される。このような、３次元多面構造複合半導体チップ２のクラスタ結合集合体の中の各演算チップは、電力伝送用の３次元多面構造複合半導体チップ２Ｃの電力伝送チップから電力が供給され、熱伝導チップにより発熱が抑制される。 Based on the principle of cluster connection, depending on the purpose, the three-dimensional multi-face structure composite semiconductor chip 2A for computation, the three-dimensional multi-face structure composite semiconductor chip 2B for heat conduction, and the three-dimensional multi-face structure composite semiconductor chip 2C for power transmission, An arithmetic processing unit having a desired function is configured by selecting and making contact coupling in the horizontal direction and the vertical direction. Power is supplied from the power transmission chip of the three-dimensional multi-face structure composite semiconductor chip 2C for power transmission to each arithmetic chip in the cluster coupled assembly of the three-dimensional multi-face structure composite semiconductor chip 2 as described above. This suppresses heat generation.

図４は、水平に３個並んだ３次元多面構造複合半導体チップ２からなる集合体の演算処理の一例を示している。図中、＋は積和演算器、ｋ，ｍ，ｎは３次元多面構造複合半導体チップ２，２，２の各加算ＬＳＩチップに設定された係数、ａ０，ａ１，ａ２，ｂ０，ｂ１，ｂ２，ｃ０，ｃ１，ｃ２は、各３次元多面構造複合半導体チップ２，２，２の加算ＬＳＩチップに、時間ｔに対して入力される入力データ、ｘ１，ｙ１，ｚ１は、回路をリセットするときの値で、図に示す例では、０である。各３次元多面構造複合半導体チップ２，２，２の演算チップに順次入力される入力データの演算結果は、 FIG. 4 shows an example of the arithmetic processing of an assembly composed of three three-dimensional multi-faceted composite semiconductor chips 2 arranged horizontally. In the figure, + is a product-sum operation unit, k, m, and n are coefficients set in the respective addition LSI chips of the three-dimensional multifaceted composite semiconductor chips 2, 2, 2, and a0, a1, a2, b0, b1, b2. , C0, c1, and c2 are input data input to the addition LSI chip of each of the three-dimensional multifaceted composite semiconductor chips 2, 2, and 2 with respect to time t, and x1, y1, and z1 are when the circuit is reset This value is 0 in the example shown in the figure. The calculation result of the input data sequentially input to the calculation chip of each three-dimensional multi-face structure composite semiconductor chip 2, 2, 2 is

ｔ０時間において、ｋａ０，ｍｂ０，ｎｃ０
ｔ１時間において、ｋａ１，ｋａ０＋ｍｂ１，ｍｂ０＋ｎｃ１
ｔ２時間において、ｋａ２，ｋａ１＋ｍｂ２，ｋａ０＋ｍｂ１＋ｎｃ２ｍ
となる。 At time t0, ka0, mb0, nc0
At time t1, ka1, ka0 + mb1, mb0 + nc1
At time t2, ka2, ka1 + mb2, ka0 + mb1 + nc2m
It becomes.

次に、図５乃至７を参照して、３次元多面構造複合半導体チップのクラスタ結合の他の実施形態について説明する。
符号２５は、８面体からなる３次元多面構造複合半導体チップであり、これに６面体の３次元多面構造複合半導体チップ２Ａが図示の如くクラスタ接合している。８面体の３次元多面構造複合半導体チップ２５の各面に結合する複数の３次元多面構造複合半導体チップ２Ａは図示の如く、α，β，γの各列を構成する。 Next, with reference to FIGS. 5 to 7, another embodiment of cluster coupling of a three-dimensional multi-faceted composite semiconductor chip will be described.
Reference numeral 25 denotes an octahedral three-dimensional polyhedral structure composite semiconductor chip, to which a hexahedral three-dimensional polyhedral structure composite semiconductor chip 2A is cluster-bonded as shown. A plurality of three-dimensional multi-faceted composite semiconductor chips 2A coupled to each face of the octahedral three-dimensional multi-faceted composite semiconductor chip 25 constitute each row of α, β, and γ, as shown.

隣接する３次元多面構造複合半導体チップ２Ａ，２Ａは、送信側電磁／電界結合器ＴＸと、受信側電磁／電界結合器Ｒｖにより、電子的に接続する。図６に示すように、３次元多面構造複合半導体チップ２Ａのエレメント半導体チップ４は、それぞれ、入力チップ２６，乗算チップ２８，加算チップ３０，出力チップ３２として機能するように構成されている。３次元多面構造複合半導体チップ２５のエレメント半導体チップは、送信チップ３４として機能するように構成されている。 Adjacent three-dimensional multi-faceted composite semiconductor chips 2A, 2A are electronically connected by a transmission-side electromagnetic / electric field coupler TX and a reception-side electromagnetic / electric field coupler Rv. As shown in FIG. 6, the element semiconductor chip 4 of the three-dimensional multifaceted composite semiconductor chip 2 </ b> A is configured to function as an input chip 26, a multiplication chip 28, an addition chip 30, and an output chip 32, respectively. The element semiconductor chip of the three-dimensional multifaceted structure composite semiconductor chip 25 is configured to function as the transmission chip 34.

送信チップ３４のアンテナ１０から共有閉鎖空間３６に向けて送信されたデータα，β，γは、３次元多面構造複合半導体チップ２５の共有閉鎖空間３６を経て、３次元多面構造複合半導体チップ２５の受信チップ３８に受信され、ここで受信データα，β，γが加算され、加算結果Ｒが、受信チップ３８に結合する３次元多面構造複合半導体チップ２Ａのインターフェースチップ４０に送られる。
上記した構成において、Ｒは系全体の結果、αはα列の結果、βはβ列の結果、γはγ列の結果とすると、αは時間ｔ毎に共通クロックで次の式で示されるように、アンテナから出力される。 Data α, β, γ transmitted from the antenna 10 of the transmission chip 34 toward the shared closed space 36 passes through the shared closed space 36 of the three-dimensional multi-faced structure composite semiconductor chip 25, and the data of the three-dimensional multi-face structure composite semiconductor chip 25. The received data is received by the receiving chip 38, where the received data α, β, γ are added, and the addition result R is sent to the interface chip 40 of the three-dimensional multi-faceted composite semiconductor chip 2A coupled to the receiving chip 38.
In the above configuration, when R is the result of the entire system, α is the result of the α column, β is the result of the β column, and γ is the result of the γ column, α is a common clock at each time t and is expressed by the following equation. Is output from the antenna.

(数１)
α１＝ｎｃ０
α２＝ｍｂ０＋ｎｃ１
α３＝ｋａ０＋ｍｂ１＋ｎｃ２
α４＝ｋａ１＋ｍｂ２＋ｎｃ３
αｔ＝ｋａｔ−３＋ｍｂｔ−２＋ｎｃｔ−２
同様にβとγは次式で示されるようにアンテナから出力される。 (Equation 1)
α1 = nc0
α2 = mb0 + nc1
α3 = ka0 + mb1 + nc2
α4 = ka1 + mb2 + nc3
αt = kat-3 + mbt-2 + nct-2
Similarly, β and γ are output from the antenna as shown in the following equation.

(数２)
βｔ＝ｏｄｔ−３＋ｐｅｔ−２＋ｑｆｔ−１
γｔ＝ｕｇｔ−３＋ｖｈｔ−２＋ｗｊｔ−１
ここで、ａ，ｂ，ｃはα列の３次元多面構造複合半導体チップへの入力、ｋ，ｌ，ｍは、α列のそれぞれの３次元多面構造複合半導体チップの演算チップに設定された係数、ｄ，ｅ，ｆはβ列の３次元多面構造複合半導体チップへの入力、ｏ，ｐ，ｑはβ列のそれぞれの３次元多面構造複合半導体チップの演算チップの係数、ｕ，ｖ，ｗは、γ列の３次元多面構造複合半導体チップへの入力、ｇ，ｈ，ｊはγ列のそれぞれの３次元多面構造複合半導体チップの演算チップの係数である。 (Equation 2)
βt = odt-3 + pet-2 + qft-1
γt = ugt-3 + vht-2 + wjt-1
Here, a, b, and c are inputs to the α-column three-dimensional multi-plane structure composite semiconductor chip, and k, l, and m are coefficients set in the arithmetic chips of the respective α-column three-dimensional multi-plane structure composite semiconductor chips. , D, e, and f are inputs to the β-column three-dimensional multi-plane structure composite semiconductor chip, o, p, and q are coefficients of the arithmetic chip of each β-column three-dimensional multi-plane structure composite semiconductor chip, u, v, and w Is an input to the γ-column three-dimensional multi-plane structure composite semiconductor chip, and g, h, j are coefficients of the arithmetic chip of each three-dimensional multi-plane structure composite semiconductor chip in the γ-row.

本発明の説明図である。It is explanatory drawing of this invention. 本発明に使用されるエレメント半導体チップのブロック回路図である。It is a block circuit diagram of the element semiconductor chip used for this invention. 本発明に使用されるエレメント半導体チップのブロック回路図である。It is a block circuit diagram of the element semiconductor chip used for this invention. 本発明の説明図である。It is explanatory drawing of this invention. 本発明の説明図である。It is explanatory drawing of this invention. 本発明の説明図である。It is explanatory drawing of this invention. 本発明の説明図である。It is explanatory drawing of this invention.

符号の説明Explanation of symbols

２ ３次元多面構造複合半導体チップ
４ エレメント半導体チップ
５ 共有閉鎖空間
６ 回路部
８ 面接触伝送パターン
１０ アンテナ
１２ 配線用コンタクト
１４ 配線パターン
１６ 電気的ドライバ・レシーバ
１８ 電磁／電界結合器
２０ 演算回路ブロック
２０Ａ 電力伝送回路ブロック
２２ マルチプレクサ
２４ 制御回路ブロック
２５ ３次元多面構造複合半導体チップ
２６ 入力チップ
２８ 乗算チップ
３０ 加算チップ
３２ 出力チップ
３４ 送信チップ
３６ 閉鎖空間
３８ 受信チップ
４０ インターフェースチップ 2 3D multi-sided composite semiconductor chip
4 Element semiconductor chip 5 Shared closed space
6 Circuit part 8 Surface contact transmission pattern 10 Antenna 12 Wiring contact 14 Wiring pattern 16 Electrical driver / receiver 18 Electromagnetic / electric field coupler 20 Arithmetic circuit block 20A Power transmission circuit block 22 Multiplexer 24 Control circuit block 25 Three-dimensional polyhedral structure composite Semiconductor chip 26 Input chip 28 Multiplication chip 30 Addition chip 32 Output chip 34 Transmission chip 36 Closed space 38 Reception chip 40 Interface chip

Claims (8)

基板に回路部が形成された四角形のエレメント半導体チップを複数貼り合わせ、互いの回路部を接続して内側に共有閉鎖空間を有する多面体形状とし、前記各エレメント半導体チップの表面に電磁／電界結合用の面接触伝送パターンを形成し、該面接触伝送パターンを前記回路部に接続したことを特徴とする３次元多面構造複合半導体チップ。 A plurality of rectangular element semiconductor chips each having a circuit portion formed on a substrate are bonded together, connected to each other to form a polyhedron having a shared closed space inside, and each element semiconductor chip has a surface for electromagnetic / electric field coupling. A three-dimensional multi-face structure composite semiconductor chip, characterized in that a surface contact transmission pattern is formed and the surface contact transmission pattern is connected to the circuit portion. 前記エレメント半導体チップの背面にアンテナを形成し、該アンテナを前記回路部に接続したことを特徴とする請求項１に記載の３次元多面構造複合半導体チップ。 2. The three-dimensional multi-sided composite semiconductor chip according to claim 1, wherein an antenna is formed on a back surface of the element semiconductor chip, and the antenna is connected to the circuit unit. 前記各エレメント半導体チップの貼り合わせ面に配線用コンタクトを形成し、互いに向き合った配線用コンタクトどうしの接触により、互いに貼り合わせた一対のエレメント半導体チップの回路部を電子的に接続したことを特徴とする請求項１に記載の３次元多面構造複合半導体チップ。 A wiring contact is formed on a bonding surface of each element semiconductor chip, and a circuit portion of a pair of element semiconductor chips bonded to each other is electronically connected by contact between wiring contacts facing each other. The three-dimensional multifaceted composite semiconductor chip according to claim 1. 前記回路部は演算回路ブロックと、該演算回路ブロックを制御する制御回路ブロックと、該制御回路ブロックと前記演算回路ブロックに接続するマルチプレクサとより構成され、該マルチプレクサが前記面接触伝送パターンとアンテナに接続していることを特徴とする請求項２に記載の３次元多面構造複合半導体チップ。 The circuit unit includes an arithmetic circuit block, a control circuit block for controlling the arithmetic circuit block, and a multiplexer connected to the control circuit block and the arithmetic circuit block. The multiplexer is connected to the surface contact transmission pattern and the antenna. The three-dimensional multi-faced composite semiconductor chip according to claim 2, wherein the chips are connected. 基板に回路部が形成された四角形のエレメント半導体チップを複数貼り合わせ、互いの回路部を接続して内側に共有閉鎖空間を有する多面体形状とし、前記各エレメント半導体チップの表面に電磁／電界結合用の面接触伝送パターンを形成し、該面接触伝送パターンを前記回路部に接続した３次元多面構造複合半導体チップを多数用意し、これら多数の３次元多面構造複合半導体チップを面接触させ、前記面接触伝送パターンを介して任意の方向に結合したことを特徴とする演算処理装置。 A plurality of rectangular element semiconductor chips each having a circuit portion formed on a substrate are bonded together, connected to each other to form a polyhedron having a shared closed space inside, and each element semiconductor chip has a surface for electromagnetic / electric field coupling. A large number of three-dimensional multi-surface structure composite semiconductor chips formed by connecting the surface-contact transmission pattern to the circuit portion, contacting the multiple three-dimensional multi-surface structure composite semiconductor chips, An arithmetic processing apparatus characterized by being coupled in an arbitrary direction through a contact transmission pattern. 基板に回路部が形成された四角形のエレメント半導体チップを複数貼り合わせ、互いの回路部を接続して内側に共有閉鎖空間を有する多面体形状とし、前記各エレメント半導体チップの表面に電磁／電界結合用の面接触伝送パターンを形成し、背面にアンテナを形成し、該面接触伝送パターンと前記アンテナを前記回路部に接続した３次元多面構造複合半導体チップを多数用意し、これら多数の３次元多面構造複合半導体チップを面接触させ、前記面接触伝送パターンを介して任意の方向に結合したことを特徴とする演算処理装置。 A plurality of rectangular element semiconductor chips each having a circuit portion formed on a substrate are bonded together, connected to each other to form a polyhedron having a shared closed space inside, and each element semiconductor chip has a surface for electromagnetic / electric field coupling. A large number of three-dimensional multi-sided structure semiconductor chips having a surface contact transmission pattern formed thereon, an antenna formed on the back side, and the surface-contact transmission pattern and the antenna connected to the circuit unit. An arithmetic processing unit, wherein a composite semiconductor chip is brought into surface contact and coupled in an arbitrary direction via the surface contact transmission pattern. 前記３次元多面構造複合半導体チップが立方体であることを特徴とする請求項５又は請求項６に記載の演算処理装置。 The arithmetic processing apparatus according to claim 5, wherein the three-dimensional multifaceted structure composite semiconductor chip is a cube. 前記多数の３次元多面構造複合半導体チップは、回路部が演算回路ブロックを含む演算用３次元多面構造複合半導体チップと、前記共有閉鎖空間に冷却媒体が充填された熱伝導のための３次元多面構造複合半導体チップと、回路部が電力伝送回路ブロックを含む電力伝送のための３次元多面構造複合半導体チップとからなることを特徴とする請求項５又は請求項６に記載の演算処理装置。 The plurality of three-dimensional multifaceted composite semiconductor chips include a three-dimensional multifaceted composite semiconductor chip for operation whose circuit section includes an arithmetic circuit block, and a three-dimensional multifaceted surface for heat conduction in which the shared closed space is filled with a cooling medium. The arithmetic processing apparatus according to claim 5 or 6, comprising a structural composite semiconductor chip and a three-dimensional multi-faceted composite semiconductor chip for power transmission, the circuit portion including a power transmission circuit block.
JP2004333855A 2004-11-18 2004-11-18 Three-dimensional multifaceted composite semiconductor chip and arithmetic processing unit Expired - Fee Related JP4591051B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004333855A JP4591051B2 (en) 2004-11-18 2004-11-18 Three-dimensional multifaceted composite semiconductor chip and arithmetic processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004333855A JP4591051B2 (en) 2004-11-18 2004-11-18 Three-dimensional multifaceted composite semiconductor chip and arithmetic processing unit

Publications (2)

Publication Number Publication Date
JP2006147735A JP2006147735A (en) 2006-06-08
JP4591051B2 true JP4591051B2 (en) 2010-12-01

Family

ID=36627086

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004333855A Expired - Fee Related JP4591051B2 (en) 2004-11-18 2004-11-18 Three-dimensional multifaceted composite semiconductor chip and arithmetic processing unit

Country Status (1)

Country Link
JP (1) JP4591051B2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6199361A (en) * 1984-10-22 1986-05-17 Fujitsu Ltd semiconductor equipment
JPS63143855A (en) * 1986-12-01 1988-06-16 モトローラ・インコーポレーテッド Modular integrated circuit and manufacture of the same
JPH10335570A (en) * 1997-05-29 1998-12-18 Kobe Nippon Denki Software Kk Polyhedron ic package
JPH11168172A (en) * 1997-12-04 1999-06-22 Toshiba Tec Corp Method for manufacturing semiconductor chip, three-dimensional structure using the semiconductor chip, method for manufacturing the same, and method for electrically connecting the same
JP2004296925A (en) * 2003-03-27 2004-10-21 Kyocera Corp Electronic component storage package

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6199361A (en) * 1984-10-22 1986-05-17 Fujitsu Ltd semiconductor equipment
JPS63143855A (en) * 1986-12-01 1988-06-16 モトローラ・インコーポレーテッド Modular integrated circuit and manufacture of the same
JPH10335570A (en) * 1997-05-29 1998-12-18 Kobe Nippon Denki Software Kk Polyhedron ic package
JPH11168172A (en) * 1997-12-04 1999-06-22 Toshiba Tec Corp Method for manufacturing semiconductor chip, three-dimensional structure using the semiconductor chip, method for manufacturing the same, and method for electrically connecting the same
JP2004296925A (en) * 2003-03-27 2004-10-21 Kyocera Corp Electronic component storage package

Also Published As

Publication number Publication date
JP2006147735A (en) 2006-06-08

Similar Documents

Publication Publication Date Title
US20220147793A1 (en) Neural network accelerator tile architecture with three-dimensional stacking
TWI442537B (en) Multichip module for communications
US20150199266A1 (en) 3dic memory chips including computational logic-in-memory for performing accelerated data processing
CN103887186A (en) Package structure including discrete antenna assembled on device
US20180217949A1 (en) Microelectronic package communication using radio interfaces connected through waveguides
KR20150066483A (en) Three dimensional dual-port bit cell and method of assembling same
JP2000031614A (en) Memory module, laminate of memory modules, and memory card and computer including memory module
WO2015076153A1 (en) Integrated circuit and layered circuit provided therewith
CN102915996A (en) Electrical interconnection mechanism for 3D integrated circuit
CN115954351A (en) Processing device based on wafer, task processing method and preparation method
JP4591051B2 (en) Three-dimensional multifaceted composite semiconductor chip and arithmetic processing unit
CN107112040A (en) Novel high speed signal route topological for more preferable signal quality
US8742839B2 (en) Double through silicon via structure
CN108027870A (en) Semiconductor device
JPH07335769A (en) Semiconductor integrated circuit
WO2020147107A1 (en) Integrated circuit comprising multiple interconnected interposers
US11308388B2 (en) Electronic circuit, particularly for the implementation of neural networks with multiple levels of precision
US9728497B2 (en) Semiconductor device and method of manufacturing the same
US10715142B2 (en) Low-voltage differential signal driver and receiver module with radiation hardness to 300 kilorad
JP6874355B2 (en) Electronic circuit equipment
KR20180088438A (en) Die and package
CN114565088A (en) Data processing device and method, neural network processor, chip and electronic equipment
CN210926324U (en) Shared antenna assembly and shared antenna structure
KR102295106B1 (en) Printed circuit board
CN102916001B (en) Layer structure with electromagnetic interference shielding function

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20071105

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100820

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20100826

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100830

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20100827

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130924

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees