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JP4572736B2 - Semiconductor device - Google Patents

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Publication number
JP4572736B2
JP4572736B2 JP2005135820A JP2005135820A JP4572736B2 JP 4572736 B2 JP4572736 B2 JP 4572736B2 JP 2005135820 A JP2005135820 A JP 2005135820A JP 2005135820 A JP2005135820 A JP 2005135820A JP 4572736 B2 JP4572736 B2 JP 4572736B2
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semiconductor elements
semiconductor device
bonding wire
conductive member
semiconductor
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JP2006313821A (en
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俊昭 長瀬
宏幸 大西
純 石川
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Toyota Industries Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires

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Description

この発明は、半導体装置に係り、特に複数の半導体素子を備えたパワーモジュール等の半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device such as a power module including a plurality of semiconductor elements.

例えば、特許文献１に開示されている半導体装置では、それぞれその表面に２つの制御電極部を有する複数の半導体素子が基板上に配置されると共に、複数の半導体素子に共通の２つの制御端子が外方へ引き出されている。また、２つの制御端子はそれぞれ基板上に配置される長板状の内部電極部を有しており、各半導体素子の２つの制御電極部がそれぞれ対応する制御端子の内部電極部にボンディングワイヤを介して接続されている。   For example, in the semiconductor device disclosed in Patent Document 1, a plurality of semiconductor elements each having two control electrode portions on the surface thereof are arranged on a substrate, and two control terminals common to the plurality of semiconductor elements are provided. Has been pulled out. Each of the two control terminals has a long plate-like internal electrode portion arranged on the substrate, and two control electrode portions of each semiconductor element have bonding wires attached to the internal electrode portions of the corresponding control terminals. Connected through.

特開平１１−１７７０２１号公報Japanese Patent Laid-Open No. 11-177021

しかしながら、上述のように、複数の半導体素子の２つの制御電極部をそれぞれボンディングワイヤを介して制御端子の内部電極部に接続するには、長大な内部電極部を用いる必要があり、このような内部電極部を基板上に配置すると、半導体装置が大型化してしまうという問題があった。
この発明はこのような問題点を解消するためになされたもので、小型の半導体装置を提供することを目的とする。 However, as described above, in order to connect the two control electrode portions of the plurality of semiconductor elements to the internal electrode portion of the control terminal via the bonding wires, it is necessary to use a long internal electrode portion. When the internal electrode portion is disposed on the substrate, there is a problem that the semiconductor device is increased in size.
The present invention has been made to solve such problems, and an object thereof is to provide a small-sized semiconductor device.

この発明に係る半導体装置は、それぞれの表面に複数の電極部が形成された複数の半導体素子を備える半導体装置において、一方向に整列して配置された複数の半導体素子と、複数の半導体素子の対応する電極部同士にそれぞれ直接に接続される複数の共通配線部材であって、それぞれが複数の半導体素子の整列方向に沿って延伸している複数の共通配線部材と、複数の共通配線部材にそれぞれ対応すると共に互いに隣接して配置され且つ一部が外方に引き出される複数の外部端子と、各半導体素子から複数の共通配線部材の延伸方向に対してほぼ垂直な方向に引き出される主電流配線とを備え、複数の共通配線部材は、互いに近接して平行に配置されると共にそれぞれ対応する外部端子に接続されており、各共通配線部材は、外部端子からの制御信号を各半導体素子の対応する電極部に伝達する制御配線として用いられるものである。
According to another aspect of the present invention, there is provided a semiconductor device including a plurality of semiconductor elements each having a plurality of electrode portions formed on each surface, the plurality of semiconductor elements arranged in one direction, and the plurality of semiconductor elements. A plurality of common wiring members that are directly connected to corresponding electrode portions, respectively, and a plurality of common wiring members that extend along the alignment direction of the plurality of semiconductor elements, and a plurality of common wiring members A plurality of external terminals corresponding to each other and arranged adjacent to each other, and a part of the terminals being drawn outward, and a main current wiring drawn from each semiconductor element in a direction substantially perpendicular to the extending direction of the plurality of common wiring members with bets, plurality of common wiring members are connected to the corresponding external terminals while being arranged parallel to and close to each other, each common wiring members, from the external terminal And it is used to control signal as a control line for transmitting the corresponding electrode portions of the semiconductor elements.

また、複数の半導体素子の整列方向の一方の端部または中央部に複数の外部端子を配置することができる。
 In addition , a plurality of external terminals can be arranged at one end or center of the alignment direction of the plurality of semiconductor elements.

複数の共通配線部材は、ボンディングワイヤ、または板状の導電部材から形成することができる。
また、複数の共通配線部材が板状の導電部材からなる場合に、複数の共通配線部材が絶縁部材を介して互いに固定されていることが好ましい。 The plurality of common wiring members can be formed from bonding wires or plate-like conductive members.
Moreover, when a some common wiring member consists of a plate-shaped electrically-conductive member, it is preferable that the some common wiring member is mutually fixed via the insulating member.

この発明によれば、小型の半導体装置を実現することができる。   According to the present invention, a small semiconductor device can be realized.

以下、この発明の実施の形態を添付図面に基づいて説明する。
実施の形態１．
図１に、この発明の実施の形態１に係る半導体装置の構造を示す。この半導体装置は、パワーモジュール等として用いられるものであり、基板１上に複数の半導体素子２が配置されて筐体状のケース３内に収容されている。これら複数の半導体素子２は一方向に整列して配置されており、その整列方向の一方の端部には第１制御端子４の内部電極部５及び第２制御端子６の内部電極部７が互いに隣接して配置されている。また、第１制御端子４及び第２制御端子６はそれぞれの内部電極部５及び７からケース３の外部にまで引き出されることにより外部端子として図示しない外部機器に接続されている。 Embodiments of the present invention will be described below with reference to the accompanying drawings.
Embodiment 1 FIG.
FIG. 1 shows the structure of a semiconductor device according to Embodiment 1 of the present invention. This semiconductor device is used as a power module or the like, and a plurality of semiconductor elements 2 are arranged on a substrate 1 and accommodated in a casing-like case 3. The plurality of semiconductor elements 2 are arranged in one direction, and an internal electrode portion 5 of the first control terminal 4 and an internal electrode portion 7 of the second control terminal 6 are arranged at one end in the alignment direction. It is arranged adjacent to each other. Further, the first control terminal 4 and the second control terminal 6 are connected to an external device (not shown) as external terminals by being drawn out from the internal electrode portions 5 and 7 to the outside of the case 3.

また、複数の半導体素子２はそれぞれその表面に第１電極部８及び第２電極部９を有している。ここで、個々の半導体素子２の第１電極部８に制御配線としての共通の第１ボンディングワイヤ１０が直接に接続されることにより、複数の半導体素子２のすべての第１電極部８が第１ボンディングワイヤ１０を介して互いに接続されている。第１ボンディングワイヤ１０は複数の半導体素子２の整列方向に沿って延伸しており、この第１ボンディングワイヤ１０の一方の端部が第１制御端子４の内部電極部５に電気的に接続されている。
同様に、個々の半導体素子２の第２電極部９に制御配線としての共通の第２ボンディングワイヤ１１が直接に接続されることにより、複数の半導体素子２のすべての第２電極部９が第２ボンディングワイヤ１１を介して互いに接続されている。第２ボンディングワイヤ１１も複数の半導体素子２の整列方向に沿って延伸しており、この第２ボンディングワイヤ１１の一方の端部が第２制御端子６の内部電極部７に接続されている。なお、第１ボンディングワイヤ１０及び第２ボンディングワイヤ１１は互いに近接して平行に延伸している。 Each of the plurality of semiconductor elements 2 has a first electrode portion 8 and a second electrode portion 9 on the surface thereof. Here, a common first bonding wire 10 as a control wiring is directly connected to the first electrode portion 8 of each semiconductor element 2, whereby all the first electrode portions 8 of the plurality of semiconductor elements 2 are connected to the first electrode portion 8. They are connected to each other via one bonding wire 10. The first bonding wire 10 extends along the alignment direction of the plurality of semiconductor elements 2, and one end of the first bonding wire 10 is electrically connected to the internal electrode portion 5 of the first control terminal 4. ing.
Similarly, a common second bonding wire 11 as a control wiring is directly connected to the second electrode portion 9 of each semiconductor element 2, whereby all the second electrode portions 9 of the plurality of semiconductor elements 2 are connected to the second electrode portion 9. The two bonding wires 11 are connected to each other. The second bonding wire 11 also extends along the alignment direction of the plurality of semiconductor elements 2, and one end portion of the second bonding wire 11 is connected to the internal electrode portion 7 of the second control terminal 6. In addition, the 1st bonding wire 10 and the 2nd bonding wire 11 are extended | stretched in parallel with adjoining each other.

また、主電流端子がケース３内にインサート成形されてケース３の内部から外部に引き出され、ケース３内に位置する主電流端子の内部電極部１２に複数の半導体素子２の第２電極部９がそれぞれ主電流配線としての複数の第３ボンディングワイヤ１３を介して接続されている。また、それぞれの第３ボンディングワイヤ１３は半導体素子２の第２電極部９から第１ボンディングワイヤ１０及び第２ボンディングワイヤ１１の延伸方向に対してほぼ垂直な方向に引き出されている。   The main current terminal is insert-molded in the case 3 and drawn out from the inside of the case 3, and the second electrode portion 9 of the plurality of semiconductor elements 2 is connected to the internal electrode portion 12 of the main current terminal located in the case 3. Are connected via a plurality of third bonding wires 13 as main current wirings. Each third bonding wire 13 is drawn from the second electrode portion 9 of the semiconductor element 2 in a direction substantially perpendicular to the extending direction of the first bonding wire 10 and the second bonding wire 11.

例えば、図１の左方から右方に向かって第１ボンディングワイヤ１０を複数の半導体素子２表面の第１電極部８に順次ワイヤボンディングすると共に第１ボンディングワイヤ１０の右側の端部を第１制御端子４の内部電極部５にワイヤボンディングすることにより、複数の半導体素子２の第１電極部８と第１制御端子４の内部電極部５とを第１ボンディングワイヤ１０を介して互いに電気的に接続することができる。同様に、図１の左方から右方に向かって第２ボンディングワイヤ１１を複数の半導体素子２表面の第２電極部９に順次ワイヤボンディングすると共に第２ボンディングワイヤ１１の右側の端部を第２制御端子６の内部電極部７にワイヤボンディングすることにより、複数の半導体素子２の第２電極部９と第２制御端子６の内部電極部７とを第２ボンディングワイヤ１１を介して互いに電気的に接続することができる。   For example, the first bonding wires 10 are sequentially wire-bonded to the first electrode portions 8 on the surfaces of the semiconductor elements 2 from the left to the right in FIG. By wire bonding to the internal electrode portion 5 of the control terminal 4, the first electrode portion 8 of the plurality of semiconductor elements 2 and the internal electrode portion 5 of the first control terminal 4 are electrically connected to each other via the first bonding wire 10. Can be connected to. Similarly, the second bonding wire 11 is sequentially wire-bonded to the second electrode portions 9 on the surfaces of the plurality of semiconductor elements 2 from the left to the right in FIG. 2 By wire bonding to the internal electrode portion 7 of the control terminal 6, the second electrode portion 9 of the plurality of semiconductor elements 2 and the internal electrode portion 7 of the second control terminal 6 are electrically connected to each other via the second bonding wire 11. Can be connected.

また、第１制御端子４の内部電極部５及び第２制御端子６の内部電極部７からの制御信号がそれぞれ第１ボンディングワイヤ１０及び第２ボンディングワイヤ１１を介して各半導体素子２の第１電極部８及び第２電極部９に伝達されることにより、それぞれの半導体素子２の動作を制御することができる。
例えば、各半導体素子２の第１電極部８をゲート電極部、第２電極部９をソース（またはエミッタ）電極部とし、第１ボンディングワイヤ１０を制御用ゲート配線、第２ボンディングワイヤ１１を制御用ソース（またはエミッタ）配線としてそれぞれ用いることができる。 Also, control signals from the internal electrode portion 5 of the first control terminal 4 and the internal electrode portion 7 of the second control terminal 6 are sent to the first of each semiconductor element 2 via the first bonding wire 10 and the second bonding wire 11, respectively. By being transmitted to the electrode part 8 and the second electrode part 9, the operation of each semiconductor element 2 can be controlled.
For example, the first electrode portion 8 of each semiconductor element 2 is a gate electrode portion, the second electrode portion 9 is a source (or emitter) electrode portion, the first bonding wire 10 is a control gate wiring, and the second bonding wire 11 is controlled. It can be used as a source (or emitter) wiring.

次に、この実施の形態１に係る半導体装置の作用について説明する。複数の半導体素子２の第１電極部８同士及び第２電極部９同士にそれぞれ第１ボンディングワイヤ１０及び第２ボンディングワイヤ１１が直接に接続され、第１ボンディングワイヤ１０の一端部及び第２ボンディングワイヤ１１の一端部のみがそれぞれ第１制御端子４の内部電極部５及び第２制御端子６の内部電極部７に接続されるので、小さい面積の内部電極部５及び７を用いることができ、これにより半導体装置の小型化を達成することができる。
また、個々の半導体素子２の第１電極部８及び第２電極部９からそれぞれ別個にボンディングワイヤを引き出して第１制御端子４及び第２制御端子６に接続する場合に比べて、ワイヤボンディングを行う回数が低減され、したがって配線作業を容易に行うことができる。 Next, the operation of the semiconductor device according to the first embodiment will be described. The first bonding wire 10 and the second bonding wire 11 are directly connected to the first electrode portions 8 and the second electrode portions 9 of the plurality of semiconductor elements 2 respectively, and one end portion of the first bonding wire 10 and the second bonding wire are connected. Since only one end portion of the wire 11 is connected to the internal electrode portion 5 of the first control terminal 4 and the internal electrode portion 7 of the second control terminal 6, respectively, the small-area internal electrode portions 5 and 7 can be used. Thereby, miniaturization of the semiconductor device can be achieved.
Compared with the case where the bonding wires are separately drawn out from the first electrode portion 8 and the second electrode portion 9 of each semiconductor element 2 and connected to the first control terminal 4 and the second control terminal 6, wire bonding is performed. The number of times of performing is reduced, and therefore wiring work can be easily performed.

また、制御配線としての第１ボンディングワイヤ１０及び第２ボンディングワイヤ１１の延伸方向と、主電流配線としての複数の第３ボンディングワイヤ１３の延伸方向とが互いにほぼ垂直であるため、第１ボンディングワイヤ１０及び第２ボンディングワイヤ１１は、第３ボンディングワイヤ１３に大電流が流れた際などに発生するノイズの影響を受けにくい。また、第１ボンディングワイヤ１０及び第２ボンディングワイヤ１１は互いに近接して平行に配置されているため、さらにノイズの影響を受けにくくなる。したがって、信頼性の高い半導体装置を実現することができる。
また、このように互いに近接して平行に配置されている第１ボンディングワイヤ１０及び第２ボンディングワイヤ１１に互いに逆方向の電流が流れるように構成すれば、相互インダクタンスの効果によりこれら第１ボンディングワイヤ１０及び第２ボンディングワイヤ１１のインダクタンスを低減することができる。 In addition, since the extending direction of the first bonding wire 10 and the second bonding wire 11 as the control wiring and the extending direction of the plurality of third bonding wires 13 as the main current wiring are substantially perpendicular to each other, the first bonding wire 10 and the second bonding wire 11 are not easily affected by noise generated when a large current flows through the third bonding wire 13. In addition, since the first bonding wire 10 and the second bonding wire 11 are arranged close to each other in parallel, they are less susceptible to noise. Therefore, a highly reliable semiconductor device can be realized.
Further, if the first bonding wire 10 and the second bonding wire 11 that are arranged in parallel and close to each other in this manner are configured such that currents in opposite directions flow through each other, the first bonding wires are caused by the mutual inductance effect. 10 and the second bonding wire 11 can be reduced in inductance.

実施の形態２．
次に図２を参照して、この発明の実施の形態２に係る半導体装置を説明する。この実施の形態２は、上述の実施の形態１において、複数の半導体素子２の整列方向の一方の端部に第１制御端子４の内部電極部５及び第２制御端子６の内部電極部７を配置する代わりに、複数の半導体素子２の整列方向の中央部に第１制御端子４の内部電極部５及び第２制御端子６の内部電極部７をそれぞれ配置したものである。すなわち、複数の半導体素子２の整列方向の中央部において互いに隣接する半導体素子２の間に、第１制御端子４の内部電極部５及び第２制御端子６の内部電極部７が互いに隣接して配置され、第１ボンディングワイヤ１０の中間部及び第２ボンディングワイヤ１１の中間部がそれぞれ第１制御端子４の内部電極部５及び第２制御端子６の内部電極部７に接続されている。 Embodiment 2. FIG.
Next, a semiconductor device according to the second embodiment of the present invention will be described with reference to FIG. In the second embodiment, in the first embodiment, the internal electrode portion 5 of the first control terminal 4 and the internal electrode portion 7 of the second control terminal 6 are arranged at one end in the alignment direction of the plurality of semiconductor elements 2. Instead of the arrangement, the internal electrode part 5 of the first control terminal 4 and the internal electrode part 7 of the second control terminal 6 are respectively arranged in the center part in the alignment direction of the plurality of semiconductor elements 2. That is, the internal electrode portion 5 of the first control terminal 4 and the internal electrode portion 7 of the second control terminal 6 are adjacent to each other between the semiconductor elements 2 adjacent to each other in the central portion in the alignment direction of the plurality of semiconductor elements 2. The intermediate portion of the first bonding wire 10 and the intermediate portion of the second bonding wire 11 are connected to the internal electrode portion 5 of the first control terminal 4 and the internal electrode portion 7 of the second control terminal 6, respectively.

このような構成にしても、第１ボンディングワイヤ１０の中間部及び第２ボンディングワイヤ１１の中間部のみがそれぞれ第１制御端子４の内部電極部５及び第２制御端子６の内部電極部７に接続されるので、小さい面積の内部電極部５及び７を用いることができる。これにより、上述の実施の形態１と同様に、半導体装置の小型化が達成される。   Even in this configuration, only the intermediate portion of the first bonding wire 10 and the intermediate portion of the second bonding wire 11 are respectively connected to the internal electrode portion 5 of the first control terminal 4 and the internal electrode portion 7 of the second control terminal 6. Since they are connected, the internal electrode portions 5 and 7 having a small area can be used. As a result, the semiconductor device can be reduced in size as in the first embodiment.

なお、１本の第１ボンディングワイヤ１０により複数の半導体素子２の第１電極部８及び第１制御端子４の内部電極部５をすべて接続する代わりに、２本の第１ボンディングワイヤを用意し、第１制御端子４の一方の側に位置する複数の半導体素子２の第１電極部８に１本目の第１ボンディングワイヤを直接に接続すると共に他方の側に位置する複数の半導体素子２の第１電極部８に２本目の第１ボンディングワイヤを直接に接続し、第１制御端子４の内部電極部５にこれら２本の第１ボンディングワイヤの対応する端部を接続することもできる。同様に、一本の第２ボンディングワイヤ１１の代わりに、第２制御端子部６の一方の側に位置する複数の半導体素子２と他方の側に位置する複数の半導体素子２とに対してそれぞれ別個の第２ボンディングワイヤを用いて配線を行うこともできる。   Instead of connecting all of the first electrode portions 8 of the plurality of semiconductor elements 2 and the internal electrode portions 5 of the first control terminals 4 with one first bonding wire 10, two first bonding wires are prepared. The first first bonding wire is directly connected to the first electrode portion 8 of the plurality of semiconductor elements 2 located on one side of the first control terminal 4 and the plurality of semiconductor elements 2 located on the other side are connected. It is also possible to connect the second first bonding wire directly to the first electrode portion 8 and connect the corresponding ends of the two first bonding wires to the internal electrode portion 5 of the first control terminal 4. Similarly, instead of one second bonding wire 11, each of the plurality of semiconductor elements 2 located on one side of the second control terminal portion 6 and the plurality of semiconductor elements 2 located on the other side, respectively. Wiring can also be performed using a separate second bonding wire.

実施の形態３．
次に図３を参照して、この発明の実施の形態３に係る半導体装置を説明する。この実施の形態３は、上述の実施の形態１において、第１ボンディングワイヤ１０及び第２ボンディングワイヤ１１の代わりに、ＣｕまたはＡｌ等からなる板状の第１導電部材２１及び第２導電部材２２をそれぞれ制御配線として用いるものである。 Embodiment 3 FIG.
Next, a semiconductor device according to the third embodiment of the present invention will be described with reference to FIG. In the third embodiment, in place of the first bonding wire 10 and the second bonding wire 11 in the first embodiment, the plate-like first conductive member 21 and second conductive member 22 made of Cu or Al are used. Are used as control wirings.

ここで、第１導電部材２１は、直線部とその下方に垂下する複数の脚部を有し、複数の脚部のうち一方の端部に位置する１つの脚部が第１制御端子４の内部電極部５に接続されると共に、それ以外の脚部がそれぞれ複数の半導体素子２の第１電極部８に接続されている。同様に、第２導電部材２２も、直線部とその下方に垂下する複数の脚部を有しており、複数の脚部のうち一方の端部に位置する１つの脚部が第２制御端子６の内部電極部７に接続されると共に、それ以外の脚部がそれぞれ複数の半導体素子２の第２電極部９に接続されている。また、第１導電部材２１の直線部と第２導電部材２２の直線部とは互いに近接して平行に配置されている。
なお、第１導電部材２１の複数の脚部及び第２導電部材２２の複数の脚部と対応する電極部との接続は、例えばはんだ付けによりなされている。 Here, the first conductive member 21 has a straight portion and a plurality of legs hanging downward below, and one leg located at one end of the plurality of legs is the first control terminal 4. In addition to being connected to the internal electrode portion 5, the other leg portions are respectively connected to the first electrode portions 8 of the plurality of semiconductor elements 2. Similarly, the second conductive member 22 also has a straight portion and a plurality of legs depending below, and one leg located at one end of the plurality of legs is the second control terminal. 6, and other leg portions are connected to the second electrode portions 9 of the plurality of semiconductor elements 2, respectively. Further, the straight portion of the first conductive member 21 and the straight portion of the second conductive member 22 are arranged close to each other and in parallel.
The plurality of legs of the first conductive member 21 and the plurality of legs of the second conductive member 22 are connected to the corresponding electrode portions by, for example, soldering.

このような構成にしても、複数の半導体素子２の第１電極部８同士及び第２電極部９同士にそれぞれ第１導電部材２１及び第２導電部材２２が直接に接続され、第１導電部材２１の１つの脚部及び第２導電部材２２の１つの脚部のみがそれぞれ第１制御端子４の内部電極部５及び第２制御端子６の内部電極部７に接続されるので、小さい面積の内部電極部５及び７を用いることができる。これにより、上述の実施の形態１と同様に、半導体装置の小型化が達成される。
加えて、この実施の形態３では、板状の第１導電部材２１及び第２導電部材２２を用いるため、断面積を大きくして電流を流れやすくすることができる。
また、第１導電部材２１及び第２導電部材２２は、予め所定の形に形成されると共に剛性を有するため、第１導電部材２１の複数の脚部及び第２導電部材２２の複数の脚部と対応する電極部との間にそれぞれはんだを配置して加熱すれば、一度にはんだ付けすることができ、したがって組み立て工数の低減及び製造コストの低減を実現することができる。 Even in such a configuration, the first conductive member 21 and the second conductive member 22 are directly connected to the first electrode portions 8 and the second electrode portions 9 of the plurality of semiconductor elements 2, respectively. Since only one leg portion 21 and one leg portion of the second conductive member 22 are connected to the internal electrode portion 5 of the first control terminal 4 and the internal electrode portion 7 of the second control terminal 6, respectively, Internal electrode portions 5 and 7 can be used. As a result, the semiconductor device can be reduced in size as in the first embodiment.
In addition, in the third embodiment, since the plate-like first conductive member 21 and second conductive member 22 are used, the cross-sectional area can be increased to facilitate the flow of current.
In addition, since the first conductive member 21 and the second conductive member 22 are formed in a predetermined shape and have rigidity, the plurality of leg portions of the first conductive member 21 and the plurality of leg portions of the second conductive member 22 are formed. If the solder is disposed between each of the electrode portions and the corresponding electrode portions and heated, the soldering can be performed at a time, so that the number of assembling steps and the manufacturing cost can be reduced.

なお、この実施の形態３でも、上述の実施の形態２のように、複数の半導体素子２の整列方向の中央部に第１制御端子４の内部電極部５及び第２制御端子６の内部電極部７を互いに隣接して配置し、第１導電部材２１の中間部に位置する１つの脚部及び第２導電部材２２の中間部に位置する１つの脚部をそれぞれ第１制御端子４の内部電極部５及び第２制御端子６の内部電極部７に接続することもできる。
また、この場合、１つの第１導電部材２１の代わりに、２つの第１導電部材を用意し、第１制御端子４の一方の側に位置する複数の半導体素子２に１つ目の導電部材を用い、第１制御端子４の他方の側に位置する複数の半導体素子２に２つ目の導電部材を用いて配線することもできる。同様に、１つの第２導電部材２２の代わりに、第２制御端子６の一方の側に位置する複数の半導体素子２と第２制御端子６の他方の側に位置する複数の半導体素子２とに対してそれぞれ別個の第２導電部材を用いて配線を行うこともできる。 In the third embodiment, as in the above-described second embodiment, the internal electrodes 5 of the first control terminal 4 and the internal electrodes of the second control terminal 6 are arranged at the center in the alignment direction of the plurality of semiconductor elements 2. The portions 7 are arranged adjacent to each other, and one leg portion located in the middle portion of the first conductive member 21 and one leg portion located in the middle portion of the second conductive member 22 are respectively arranged inside the first control terminal 4. It can also be connected to the electrode part 5 and the internal electrode part 7 of the second control terminal 6.
In this case, two first conductive members are prepared instead of one first conductive member 21, and the first conductive member is provided in the plurality of semiconductor elements 2 located on one side of the first control terminal 4. The second conductive member can be used for wiring to the plurality of semiconductor elements 2 located on the other side of the first control terminal 4. Similarly, instead of one second conductive member 22, a plurality of semiconductor elements 2 located on one side of the second control terminal 6 and a plurality of semiconductor elements 2 located on the other side of the second control terminal 6, However, it is also possible to perform wiring using separate second conductive members.

実施の形態４．
次に図４を参照して、この発明の実施の形態４に係る半導体装置を説明する。この実施の形態４は、上述の実施の形態３において、第１導電部材２１の直線部と第２導電部材２２の直線部とを樹脂等からなるフィルム状の絶縁部材２３を介して互いに貼り合わせたものである。このように、板状の第１導電部材２１及び第２導電部材２２の直線部が絶縁部材２３を介して互いに固定されているため、確実に第１導電部材２１と第２導電部材２２とを互いに近接して平行に配置することができる。
また、第１導電部材２１及び第２導電部材２２が一体に形成されているため、第１導電部材２１及び第２導電部材２２のそれぞれの脚部と対応する電極部との位置決め等が容易になり、したがって組み立てを容易に行うことができる。 Embodiment 4 FIG.
Next, a semiconductor device according to the fourth embodiment of the present invention will be described with reference to FIG. In the fourth embodiment, the straight portion of the first conductive member 21 and the straight portion of the second conductive member 22 are bonded to each other via the film-like insulating member 23 made of resin or the like in the third embodiment. It is a thing. As described above, since the straight portions of the plate-like first conductive member 21 and the second conductive member 22 are fixed to each other via the insulating member 23, the first conductive member 21 and the second conductive member 22 are securely connected. They can be placed close to and parallel to each other.
Further, since the first conductive member 21 and the second conductive member 22 are integrally formed, positioning of the leg portions of the first conductive member 21 and the second conductive member 22 with the corresponding electrode portions is easy. Therefore, assembly can be performed easily.

なお、第１導電部材２１と第２導電部材２２をフィルム状の絶縁部材２３を介して貼り合わせる代わりに、第１導電部材２１の直線部及び第２導電部材２２の直線部が樹脂を介して互いに近接するように予めインサート成型したものを用いることもできる。   In addition, instead of bonding the first conductive member 21 and the second conductive member 22 through the film-like insulating member 23, the straight portion of the first conductive member 21 and the straight portion of the second conductive member 22 are routed through resin. Those that are insert-molded in advance so as to be close to each other can also be used.

また、上述の実施の形態１〜４では、複数の半導体素子２が１列に整列していたが、これに限定されるものではなく、この発明は、複数の半導体素子２が２列以上に整列して配置されている半導体装置についても適用することができる。   In the first to fourth embodiments described above, the plurality of semiconductor elements 2 are aligned in one row. However, the present invention is not limited to this, and the present invention includes a plurality of semiconductor elements 2 in two or more rows. The present invention can also be applied to semiconductor devices arranged in alignment.

なお、各半導体素子２の表面に２つの電極部８及び９が形成されている場合について説明したが、各半導体素子２の表面に３つ以上の電極部が形成されている場合についても、複数の半導体素子の対応する電極部にボンディングワイヤまたは板状の導電部材等からなる共通配線部材をそれぞれ直接に接続すると共に複数の共通配線部材をそれぞれ対応する外部端子の内部電極部に接続することにより、上述の実施の形態１〜４と同様に、小型の半導体装置を得ることができる。   Although the case where the two electrode portions 8 and 9 are formed on the surface of each semiconductor element 2 has been described, a plurality of cases where three or more electrode portions are formed on the surface of each semiconductor element 2 are also provided. By directly connecting a common wiring member made of a bonding wire or a plate-like conductive member to the corresponding electrode portion of each semiconductor element, and connecting a plurality of common wiring members to the internal electrode portions of the corresponding external terminals, respectively As in the first to fourth embodiments, a small semiconductor device can be obtained.

この発明の実施の形態１に係る半導体装置を示す平面図である。1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. この発明の実施の形態２に係る半導体装置を示す平面図である。It is a top view which shows the semiconductor device which concerns on Embodiment 2 of this invention. この発明の実施の形態３に係る半導体装置における第１導電部材及び第２導電部材近傍の構造を示す斜視図である。It is a perspective view which shows the structure of the 1st conductive member and the 2nd conductive member vicinity in the semiconductor device concerning Embodiment 3 of this invention. この発明の実施の形態４に係る半導体装置における第１導電部材及び第２導電部材近傍の構造を示す側面図である。It is a side view which shows the structure of the 1st conductive member and the 2nd conductive member vicinity in the semiconductor device concerning Embodiment 4 of this invention.

符号の説明Explanation of symbols

１ 基板、２ 半導体素子、３ ケース、４ 第１制御端子、５，７，１２ 内部電極部、６ 第２制御端子、８ 第１電極部、９ 第２電極部、１０ 第１ボンディングワイヤ、１１ 第２ボンディングワイヤ、１３ 第３ボンディングワイヤ、２１ 第１導電部材、２２ 第２導電部材、２３ 絶縁部材。   DESCRIPTION OF SYMBOLS 1 Board | substrate, 2 Semiconductor element, 3 Case, 4 1st control terminal, 5, 7, 12 Internal electrode part, 6 2nd control terminal, 8 1st electrode part, 9 2nd electrode part, 10 1st bonding wire, 11 Second bonding wire, 13 Third bonding wire, 21 First conductive member, 22 Second conductive member, 23 Insulating member.

Claims (6)

それぞれの表面に複数の電極部が形成された複数の半導体素子を備える半導体装置において、
一方向に整列して配置された複数の半導体素子と、
複数の半導体素子の対応する電極部同士にそれぞれ直接に接続される複数の共通配線部材であって、それぞれが複数の半導体素子の整列方向に沿って延伸している複数の共通配線部材と、
前記複数の共通配線部材にそれぞれ対応すると共に互いに隣接して配置され且つ一部が外方に引き出される複数の外部端子と、
各半導体素子から前記複数の共通配線部材の延伸方向に対してほぼ垂直な方向に引き出される主電流配線と
を備え、
前記複数の共通配線部材は、互いに近接して平行に配置されると共にそれぞれ対応する外部端子に接続されており、
各共通配線部材は、前記外部端子からの制御信号を各半導体素子の対応する電極部に伝達する制御配線として用いられることを特徴とする半導体装置。 In a semiconductor device including a plurality of semiconductor elements in which a plurality of electrode portions are formed on each surface,
A plurality of semiconductor elements arranged in one direction, and
A plurality of common wiring members that are directly connected to corresponding electrode portions of the plurality of semiconductor elements, respectively, each extending along the alignment direction of the plurality of semiconductor elements ;
A plurality of external terminals respectively corresponding to the plurality of common wiring members and arranged adjacent to each other and partially drawn out;
A main current wiring drawn from each semiconductor element in a direction substantially perpendicular to the extending direction of the plurality of common wiring members ,
The plurality of common wiring members are arranged close to each other in parallel and connected to corresponding external terminals ,
Each common wiring member is used as a control wiring that transmits a control signal from the external terminal to a corresponding electrode portion of each semiconductor element . 複数の半導体素子の整列方向の一方の端部に前記複数の外部端子が配置されている請求項１に記載の半導体装置。 The semiconductor device of claim 1, wherein the plurality of external terminals to one end of the alignment direction of the plurality of semiconductor elements are arranged. 複数の半導体素子の整列方向の中央部に前記複数の外部端子が配置されている請求項１に記載の半導体装置。 The semiconductor device of claim 1, wherein the plurality of external terminals to the central portion of the alignment direction of the plurality of semiconductor elements are arranged. 前記複数の共通配線部材は、ボンディングワイヤからなる請求項１〜３のいずれか一項に記載の半導体装置。 Wherein the plurality of common wiring members The semiconductor device according to any one of claims 1 to 3 comprising a bonding wire. 前記複数の共通配線部材は、板状の導電部材からなる請求項１〜３のいずれか一項に記載の半導体装置。 Wherein the plurality of common wiring members The semiconductor device according to any one of claims 1 to 3 comprising a plate-shaped conductive member. 前記複数の共通配線部材は、絶縁部材を介して互いに固定されている請求項５に記載の半導体装置。 The semiconductor device according to claim 5 , wherein the plurality of common wiring members are fixed to each other via an insulating member.
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