JP4567949B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a field effect transistor having a metal / insulator / semiconductor junction, a fin-type field effect transistor having a gate electrode formed on a side surface and an upper surface of a semiconductor region formed on the insulating film via a gate insulating film, and It relates to the manufacturing method.
[0002]
[Prior art]
In recent years, the role of large-scale integrated circuits (LSIs) is becoming more and more important due to the high performance of various mobile devices such as computers and communication devices. In order to improve the performance of an LSI, it is necessary to improve the performance of a field effect transistor (MISFET) having a metal / insulator / semiconductor junction that constitutes the LSI.
[0003]
The high performance of MISFET refers to an increase in drive current, control of threshold voltage, reduction of parasitic resistance / parasitic capacitance, improvement of cut-off characteristics, and the like. Higher performance has been achieved by miniaturizing elements. In recent years, the gate length (also referred to as channel dimension or gate dimension) of a MISFET has approached a length of several tens of nanometers. However, when the channel length is shortened in this way, the problem that the leakage current increases due to the short channel effect and the characteristics of the MISFET deteriorates becomes obvious.
[0004]
Here, in the planar MISFET, the gate length is equal to the length of the short side of the gate electrode having a strip shape. Source / drain regions of the MISFET are formed in the short side direction of the gate, that is, in the gate length direction. The long side of the strip-shaped gate electrode (actually, the portion of the long side on the semiconductor substrate) is called the gate width, and the end of the gate electrode in the gate width direction is generally formed in the element isolation region. That is, the strip-shaped gate width direction and the gate length direction are substantially perpendicular to each other.
[0005]
MOSFETs use an oxide film as an insulator for MISFETs. Preventing punch-through between source and drain regions by thinning the gate oxide film to suppress the short channel effect or increasing the impurity concentration of the channel part to about 10 ¹⁸ / cm ³ Has been done.
[0006]
However, the gate oxide film cannot be made thinner than necessary due to the limitation of the maximum allowable electric field that can guarantee reliability. Further, excessively high channel impurity concentration brings about saturation of drive current due to high concentration impurity scattering in the channel region, and the problem that the drive current does not increase even if the channel length is shortened has become prominent. . In addition, the gate electrode has a high resistance due to miniaturization and an increase in parasitic resistance between the source and drain is also a problem.
[0007]
Under such circumstances, a Fin-type MOSFET structure has been proposed (see Non-Patent Documents 1 and 2). The Fin-type MOSFET has a structure in which a substantially rectangular semiconductor layer is formed on a buried oxide film formed on a semiconductor substrate, and at least both side surfaces of the central portion of the semiconductor layer are used as a channel region. A pair of source / drain regions are formed on both sides in the longitudinal direction of the semiconductor layer, and the central portion of the semiconductor layer sandwiched between them is used as a channel region.
[0008]
The channel is formed on both side surfaces (sometimes the upper surface) of the central portion of the semiconductor layer. A gate electrode is formed through the gate oxide film. Therefore, in a rectangular parallelepiped semiconductor layer, the gate length direction can be said to be substantially equal to the longitudinal direction of the semiconductor layer. Non-Patent Document 1 discloses a Fin-type MOSFET in which a channel is formed only on both side surfaces of a central portion of a semiconductor layer. Non-Patent Document 2 discloses a Fin-type MOSFET in which channels are formed on both side surfaces and an upper surface of a central portion.
[0009]
Since the Fin-type MOSFET uses channel regions formed on both side surfaces, it can be mentioned that more drive current can be obtained than a planar MOSFET having the same element size. Here, the planar MOSFET is a MOSFET in which a channel region and source / drain regions are formed side by side on the substrate surface. The second advantage of the Fin-type MOSFET is that the controllability of the gate voltage for the channel region is improved.
[0010]
In this way, the Fin-type MOSFET can obtain characteristics superior to those of the planar type. However, when the gate length (distance between the source and drain regions) is shortened, the generation of leakage current becomes a problem.
[0011]
[Non-Patent Document 1]
B.Yu etc. (Advanced Micro Devices), "FinFET Scaling to 10nm Gate Length", IEDM2002, pp251-254.
[0012]
[Non-Patent Document 2]
J. Kdzierski etc., "Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation", IEDM2002, pp247-250.
[0013]
[Problems to be solved by the invention]
As described above, miniaturization of MOSFETs is indispensable to advance LSI performance. However, it is becoming increasingly difficult to achieve both an increase in drive current and an improvement in cut-off characteristics.
[0014]
In view of such a background, the present invention provides a semiconductor device and a method for manufacturing the same that can simultaneously increase the drive current and improve the cutoff characteristics by independently controlling the drive current and the leakage current of the MISFET. One of the issues is to do.
[0015]
[Means for Solving the Problems]
In order to solve the above problems, the first aspect of the present invention is an insulating film, a pair of conductive source / drain regions formed on the insulating film, and the pair of source / drain regions. When the direction of current flowing in the channel region formed on both sides of the semiconductor region is the gate length direction, and the direction perpendicular to the gate length direction and the height direction of the semiconductor region is the gate width direction, A leg part on the insulating film side and a wide part wider in the gate width direction than the leg part formed on the leg part, and the width of the leg part / the width of the wide part is ½ or more 9 / The semiconductor region being 10 or less ;
A gate insulating film covering a side surface of the leg portion, a lower surface excluding a contact surface of the wide portion with the leg portion, a side surface of the wide portion, and an upper surface of the wide portion;
Gate poly covering the side surface of the leg portion, the lower surface excluding the contact surface with the leg portion of the wide portion, the side surface of the wide portion , and the upper surface of the wide portion through the gate insulating film,
A gate electrode formed on the gate poly;
To the length Leff between the source and drain regions, the maximum width W of the gate width direction of the wide portion is a semiconductor device which is characterized in that a relation of Leff ≧ W.
[0016]
The second aspect of the present invention is an insulating film, a pair of conductive source / drain regions formed on the insulating film, and a semiconductor region formed between the pair of source / drain regions, Parallel to the gate width direction when the direction of current flowing in the channel regions formed on both side surfaces is the gate length direction and the direction perpendicular to the gate length direction and the height direction of the semiconductor region is the gate width direction. A semiconductor region having a trapezoidal cross section, the width continuously decreasing from the upper surface to the lower surface, and (lower surface width / upper surface width) being ½ or more and 9/10 or less ,
A gate insulating film formed on a side surface and an upper surface of the semiconductor region;
Gate poly covering the side surface and the upper surface of the central region through the gate insulating film,
A gate electrode formed on the gate poly,
The semiconductor device is characterized in that the maximum width W in the gate width direction of the wide portion is in a relationship of Leff ≧ W with respect to the length Leff between the source / drain regions .
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol shall be attached | subjected to a common structure through embodiment and an Example, and the overlapping description is abbreviate | omitted.
[0019]
Each figure is a schematic diagram for promoting explanation and understanding of the invention, and its shape, dimensions, ratio, and the like are different from those of an actual device. However, these are in consideration of the following explanation and known techniques. The design can be changed as appropriate. Hereinafter, the n-type MOSFET will be described, but the same can be applied to the p-type MOSFET and the same functions and effects can be obtained.
[0020]
(First embodiment)
FIGS. 1A and 1B are cross-sectional views for explaining a Fin-type MOSFET according to the first embodiment of the present invention. FIG. 1 (a) shows a cross section in the gate length direction of a Fin-type MOSFET. FIG. 1 (b) shows the AA ′ cross section of FIG. 1 (a).
[0021]
The Fin-type MOSFET according to the first embodiment includes a substrate 1, an insulating film 2 provided on the substrate 1, and a rectangular parallelepiped semiconductor layer formed on the insulating film 2. The semiconductor layer includes a central region 3 and a pair of source / drain regions 6 and 7 sandwiching the central region 3 from the channel length direction.
[0022]
The central region 3 is a semiconductor region where a channel is formed. The central region 3 includes a leg portion 3a on the buried oxide film 2 and a wide portion 3b formed on the leg portion 3a. A gate poly 5 is formed on both side surfaces and the upper surface of the semiconductor region 3 via a gate insulating film 4.
[0023]
The planar shape of the semiconductor layer is not necessarily a rectangular parallelepiped and can be changed as appropriate. For example, the source / drain regions 6 and 7 may be wider than the width of the central region 3 (the width of the wide portion 3b). On the source / drain regions 6, 7, source / drain electrodes 9, 10 are formed. The source / drain electrodes 9 and 10 are contact electrodes, and are connected to other elements via wiring. Therefore, when the width of the source / drain regions 6 and 7 is increased, it is possible to devise such as increasing the contact area with the electrode.
[0024]
A metal gate electrode 8 is formed on the gate poly 5, and the gate poly 5 is connected to the gate control line via the gate electrode 8. Such a gate contact may be performed on the semiconductor layer, but it is preferable to perform the gate contact on the buried oxide film 2 by extending the gate poly on the buried oxide film 2.
[0025]
A channel is formed between the source / drain regions 6 and 7 under the control of the gate poly 5. The channel is formed on the upper surface and side surfaces of the central region 3, that is, on both side surfaces of the leg portion 3a and on both side surfaces of the wide portion 3b and the lower surface excluding the overlapping portion with the upper surface leg portion 3a. Note that the position of the channel can be changed by shifting the positional relationship between the leg portion 3a and the wide portion 3b from the state shown in FIG. For example, the position of the leg 3a in the cross section of FIG. 1 (b) may be moved to the left or right.
[0026]
Further, as described in Non-Patent Document 1, a channel may not be formed on the upper surface of the central region 3 (in the example of FIG. 1B, the upper surface of the wide portion 3b). In this case, the channel can be prevented from being formed by increasing the thickness of the insulating film covering the upper surface of the central region 3 or controlling the impurity concentration of the upper surface.
[0027]
As the substrate, an SOI substrate in which a semiconductor layer is formed on the semiconductor substrate through the buried oxide film 2 can be used. In this embodiment, the semiconductor layer on the buried oxide film 2 is processed into a rectangular parallelepiped shape to form an island-shaped convex semiconductor layer, and the central region 3 and the source / drain regions 6 and 7 are formed thereon. . The semiconductor layer (Fin) may be a plate standing perpendicular to the surface of the insulating film 2, or the thickness (width) thereof may be increased.
[0028]
As shown in the schematic cross-sectional view of FIG. 1 (c) (corresponding to the AA ′ cross-section of FIG. 1 (a)), the central region 3 of the semiconductor layer has a wider upper surface than the lower surface, and extends from the upper surface to the lower surface. It can also be a trapezoid with a gradually narrowing width. In this shape, both side surfaces of the semiconductor layer in the gate width direction are tapered with respect to the surface of the insulating film 2.
[0029]
Figure 2 shows the simulation results for the gate voltage and drain current characteristics of a conventional Fin-type MOSFET with a rectangular central area (no leg and wide part) and the Fin-type MOSFET according to this embodiment. Show.
[0030]
FIG. 2 (a) is a linear representation of the drain current, and FIG. 2 (b) is a logarithmic representation of the drain current. FIG. 2 (a) is a diagram specifically showing drive current characteristics, and FIG. 2 (b) shows cut-off characteristics. The cut-off characteristics are better as the slope of the slope region (from -1.5V to -0.5V) and the slope of the gate voltage / drain current curve (this part is a substantially straight line) in Fig. 2 (b) are larger.
[0031]
Here, the structure of the conventional Fin-type MOSFET has a gate length L = 20 nm, an effective gate length L _eff = 16 nm, a gate poly impurity concentration N _g = 1 × 10 ²⁰ cm ⁻³ , and a central region impurity concentration N _sub = 1 × 10 ¹⁷ cm ^-3 , source / drain region impurity concentration N _ex = 7 × 10 ¹⁹ cm ^-3 , gate insulating film thickness t _ox = 1.5 nm, Fin height h = 20 nm, buried insulating film 2 thickness h _b = 200 nm. The drain voltage V _d = 1V and the gate width W = 10 nm (indicated by ◯ in FIGS. 2A and 2B) or 20 nm (indicated by □ in FIGS. 2A and 2B).
[0032]
Further, the structure according to the present embodiment is L = 20 nm, L _eff = 16 nm, N _g = 1 × 10 ²⁰ cm ⁻³ , N _sub = 1 × 10 ¹⁷ cm ⁻³ , N _ex = 7 × 10 ¹⁹ cm ⁻³ , t _ox = 1.5 nm, the height h of the central region 3 is 20 nm, the width W of the wide portion 3b is 20 nm, and h _{b is} 200 nm. Further, the drain voltage V _d = 1V, the height h ₀ = 10 nm of the leg 3a, and the width W ₀ = 10 nm of the leg 3b. That is, the central region 3 of the present embodiment has a structure in which a conventional structure with W = 10 nm and a conventional structure with W = 20 nm are combined.
[0033]
As can be seen from FIGS. 2A and 2B, when the width of the central region 3 is simply reduced, the cut-off characteristics are improved, but there is a disadvantage that the drive current is greatly reduced because the gate width is shortened. However, according to the present embodiment, it is possible to obtain a cut-off characteristic substantially equivalent to that of the conventional structure with W = 10 nm, and at the same time, it is possible to obtain a drive current substantially equivalent to that of the conventional structure with W = 20 nm. Thus, according to the present embodiment, both the cutoff characteristic and the drive current can be achieved.
[0034]
The Fin-type MISFET has gate electrodes (gate poly) on the top and side surfaces, and controls the potential of the central region from three directions. When the gate width of the Fin-type MISFET is widened, there is a merit that more current can be taken. On the other hand, the controllability to the inside of the central region 3 of the gate electrode becomes worse when the width is widened. Therefore, the width W is desirable to obtain excellent control properties to the effective gate length L _eff ≧ W.
[0035]
FIG. 3 shows the results obtained by simulation of the gate voltage / drain current characteristics when W ₀ is changed to 18 nm, 14 nm, and 10 nm in this embodiment. FIG. 3 (a) is a linear representation of the drain current, and FIG. 3 (b) is a logarithmic representation of the drain current. FIG. 3 (a) is a diagram for showing drive current characteristics, and FIG. 3 (b) shows a cut-off characteristic.
[0036]
It can be seen that the drive current is maintained at a constant value even though the cut-off characteristic is changed by the introduction of the leg portion. That is, according to the present embodiment, it can be said that independent control of the drive current and the cut-off characteristic and compatibility of both can be achieved, which was impossible with the conventional technique.
[0037]
In the present embodiment, the gate poly 5 is formed on the side of the leg 3a, thereby improving the controllability of the leg 3a where punch-through is likely to occur. That is, the controllability of the gate voltage with respect to the inside of the central region 3 is improved, and a structure in which punch-through is less likely to occur can be realized.
[0038]
Here, in a conventional Fin-type MISFET, a structure in which the lower center of the semiconductor layer between the source and drain regions is replaced with an insulator seems to be useful for reducing punch-through. That is, if the side of the lower central insulating film is a semiconductor, the channel region does not decrease and the drive current does not decrease. However, in this structure, the controllability from the gate electrode around the replaced insulator remains weak. For this reason, punch-through around the replaced insulator occurs as in the conventional Fin-type MISFET.
[0039]
Next, a method for manufacturing the Fin-type MOSFET obtained by the present invention will be described with reference to the cross-sectional views of FIGS.
[0040]
First, as shown in FIG. 4, oxygen ions are implanted into a plane-oriented (100) P-type Si substrate 1 having an impurity concentration of about 5 × 10 ¹⁵ cm ⁻³ . By heat-treating the Si substrate 1, a buried oxide film (insulating film) 2 and a P-type silicon layer 11 having a thickness of about 200 nm are formed as shown in FIG. A Si ₃ N ₄ layer 12 having a planar shape of the semiconductor layer 3 (for example, a rectangular planar shape) is formed on the surface of the P-type silicon layer 11. This rectangular Si ₃ N ₄ layer 12 has a long side in the direction perpendicular to the paper surface of FIG. 5 and a short side in the left-right direction of the paper surface.
[0041]
Next, RIE (Reactive Ion Etching) is performed on the P-type silicon layer 11 on the buried oxide film 2 using the Si ₃ N ₄ layer 12 as a mask, for example, about 20 nm in height, about 260 nm in length, and about 20 nm in width. An approximately rectangular parallelepiped silicon layer 13 and a Si ₃ N ₄ layer 12 having a length of about 20 nm and a width of about 20 nm are formed. The width of the silicon layer 13 and the width of the Si ₃ N ₄ layer 12 are the widths in the left-right direction in FIG. 6, and the length is the length in the direction perpendicular to the page in FIG. It is also possible to use the resist pattern used as a mask for RIE of the semiconductor layer 11 to shaping the Si ₃ N ₄ layer 12.
[0042]
Next, two methods for forming the leg portion 3a having a narrower width than the upper wide portion 3b in the central region 3 of the silicon layer 13 will be described.
[0043]
First, the first method will be described with reference to FIGS. 7 to 11 are cross-sectional views of the central region 3 in the channel width direction.
[0044]
First, as shown in FIG. 7, BPSG (Boro-Phospho Silicated Glass) 15 which is an insulating film is deposited on the silicon layer 13 and the buried insulating film 2. Thereafter, the BPSG layer 15 is planarized by CMP (Chemical Mechanical Polishing) using the Si ₃ N ₄ layer 12 as a stopper.
[0045]
Next, the BPSG layer 15 as shown in FIG. 8 is formed into a layer 16 having a thickness of about 5 to 10 nm by RIE etch back. Thereafter, as shown in FIG. 9, SiO ₂ films 17 are formed on both side surfaces of the silicon layer 13 by thermal oxidation.
[0046]
Although both the SiO ₂ film 17 and the BPSG layer 16 are insulating films, only the BPSG layer 16 can be removed because the etching rates thereof are different. FIG. 9 is a cross-sectional view of the central region 3 from which only the BPSG layer 16 is removed.
[0047]
Then, isotropic chemical etching such as CDE is performed. Then, while the upper part of the silicon layer 13 is protected by the Si ₃ N ₄ film 12 and the SiO ₂ film 17, the lower part (leg part) is not protected by the insulating film, so as shown in FIG. The cross-sectional shape of the semiconductor layer 3 is T-shaped. Here, the partial region of the semiconductor layer 3 on the buried insulating film 2 side is a T-shaped leg portion 3a, and the partial region of the semiconductor layer 3 serving as a T-shaped cap portion is a wide portion 3b extending in the channel width direction. .
[0048]
Next, after removing the Si ₃ N ₄ layer 12 and the SiO ₂ film 17, the gate insulating film 4 is formed again on the surface of the semiconductor layer 3 by thermal oxidation, whereby the cross-sectional structure shown in FIG. 11 is obtained.
[0049]
Next, the second method will be described with reference to FIG. 12 and FIG. 12 and 13 show a cross section of the central region 3 in the channel width direction.
[0050]
First, RTA (Rapid Thermal Anneal) is performed on the structure of FIG. 6 at a temperature of about 1050 degrees and a time of about 30 seconds. Then, in addition to the side surface of the silicon layer 13, the oxide film 18 is formed at the corner of the interface between the Si ₃ N ₄ layer 14 and the silicon layer 13 and the interface between the silicon layer 13 and the buried oxide film 2 in contact with the oxidizing atmosphere due to bird's beak. It is formed. As a result, as shown in FIG. 13, the width of the lower surface and the upper surface of the silicon layer 13 can be reduced.
[0051]
Thereafter, if the Si ₃ N ₄ layer 14 and the SiO ₂ film 18 are removed and the gate insulating film 4 is formed on the surface of the silicon layer 13 by thermal oxidation again, a cross-sectional structure as shown in FIG. 13 is obtained. In FIG. 13, the lower side of the semiconductor layer 3 in which the thickness of the gate insulating film 4 is increased corresponds to the leg portion, and the boundary between the leg portion and the wide portion is indicated by a dotted line. Here, the conventional method in which the thermal oxidation is performed for a long time is not preferable because a thick gate insulating film is formed and the effect of bird's beak becomes difficult to see.
[0052]
As described above, the leg portion 3a and the wide portion 3b of the semiconductor layer 3 can be formed by using either the first method or the second method. Hereinafter, the subsequent manufacturing process will be described with reference to FIG.
[0053]
As shown in FIG. 14, a polycrystalline silicon film 19 is deposited on the buried oxide film 2 in which the legs 3a and the wide portions 3b of the semiconductor layer 3 are formed. Impurities such as phosphorus are ion-implanted into the polycrystalline silicon film 19 to form an n ⁺ type polycrystalline silicon film 19 having an impurity concentration of about 7 × 10 ¹⁹ cm ⁻³ .
[0054]
Next, a resist film is provided on the gate formation portion using a mask, and the polycrystalline silicon film 19 on the source / drain regions is removed by RIE. Thereafter, the resist film is peeled off. Then, the gate electrode 5 made of a polycrystalline silicon film is formed through the gate oxide film 4 so as to cover the upper surface and both side surfaces of the central region 3 of the semiconductor layer and the lower surface of the wide portion except for the surface overlapping the leg portion. Can do.
[0055]
FIGS. 15 (a), (b) and (c) show the structures obtained as a result of the above manufacturing process. FIG. 15A is a cross-sectional view in the channel length direction. 15 (b) shows the AA 'cross section (planned source / drain region) of FIG. 15 (a), and FIG. 15 (c) shows the BB' cross section (planned channel / gate region of FIG. 15 (a). ).
[0056]
Here, as shown in FIG. 15B, the gate electrode 5 is left on the side of the leg portion 13a of the planned source / drain region of the silicon layer 13.
[0057]
Next, as shown in FIGS. 16A and 16B, impurities such as phosphorus are ion-implanted into the planned source / drain regions and the gate poly 5. Here, FIG. 16A shows a cross section in the gate length direction of the silicon layer 13, and FIG. 16B shows an AA ′ cross section of FIG. 16A.
[0058]
Then, a heat treatment for activating the implanted impurities is performed, and as shown in FIGS. 17A and 17B, n ⁺ -type source / drain regions 6 having an impurity concentration of about 1 × 10 ¹⁹ cm ⁻³ are obtained. , 7. Here, FIG. 17B shows an AA ′ cross section of FIG.
[0059]
The source / drain regions 6 and 7 in FIG. 17A do not reach the buried insulating film 2, but if the implantation energy of impurity ion implantation is adjusted, the source reaching the upper surface of the buried insulating film 2 as shown in FIG. -Drain regions 6 and 7 can be formed.
[0060]
Further, as shown in 17 (b), the bottom of the eaves of the source and drain regions 6 and 7 wide part, since the remaining polycrystalline silicon film 5 is removed polycrystalline silicon film 5 remaining by CDE be able to.
[0061]
Then, as shown in FIGS. 18A and 18B, an insulating film 20 for element isolation covering the polycrystalline silicon film 5, the buried oxide film 2, the silicon layer 13, and the gate electrode 5 is formed. Here, FIG. 18B is an AA ′ cross section of FIG. Further, contact holes for electrodes connected to the source / drain regions 6, 7 are formed in the insulating film 20, and metal wiring 21 is buried in the contact holes to establish connection with the source / drain regions 6, 7. Similarly, for the gate electrode 5, a contact hole is formed to form a metal wiring (not shown).
[0062]
As described above, the Fin-type MOSFET of the first embodiment is completed. Thereafter, the semiconductor integrated circuit device is completed by connecting to another element via the metal wiring.
[0063]
Next, a method for forming the cross-sectional shape of FIG.
[0064]
After the manufacturing process described with reference to FIGS. 4 and 5, anisotropic etching is performed twice using the Si ₃ N ₄ layer 12 as a mask. That is, etching in which the anisotropic direction of the etching particles incident on the silicon layer 11 is inclined to the right from the normal line of the surface of the insulating film 2 in FIG. 5 and etching is inclined to the left is performed. Then, the planned channel region of the silicon layer 11 can be the central region 3 having the cross-sectional shape shown in FIG. After forming such a cross-sectional shape, a gate insulating film, a gate electrode, and the like are sequentially formed.
[0065]
The present invention can be variously modified in the implementation stage without departing from the scope of the invention. For example, although the MOSFET has been described above, the present invention can also be applied to a Fin-type MISFET using an insulator other than an oxide film.
[0066]
Further, although the leg 3a and the wide part 3b are formed in the central region 3 forming the channel, the leg and the wide part may not be provided in the source / drain region.
[0067]
In addition to silicon, the silicon layer 13 and its central region 3 can use other semiconductor materials or compound semiconductor materials. Further, a high dielectric insulating film or a metal silicide layer can be used for the gate insulating film, and a salicide layer used in a planar MOSFET can be formed in the source / drain regions 6 and 7.
[0068]
Furthermore, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine the component covering different embodiment suitably.
[0069]
【The invention's effect】
According to the semiconductor device of the present invention, excellent drive current and cut-off characteristics can be obtained. In addition, independent control of drive current and cut-off characteristics, which was impossible with the conventional structure, is possible.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view for explaining a semiconductor device according to a first embodiment of the invention.
FIG. 2 compares the gate voltage / drain current characteristics according to the first embodiment with a Fin-type MOSFET having a conventional structure, and FIG. 2 (a) is a diagram showing the drain current linearly; FIG. b) is a logarithmic representation of the drain current.
FIG. 3 compares the gate voltage / drain current characteristics when the width of the leg 3a is changed in the first embodiment, and FIG. 3 (a) is a diagram showing the drain current linearly; FIG. 3 (b) is a diagram showing the drain current in logarithm.
4 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment; FIG.
FIG. 5 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment following FIG. 4;
6 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment following FIG. 5. FIG.
7 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment following FIG. 6;
8 is a cross-sectional view for explaining the manufacturing method of the semiconductor device according to the first embodiment following FIG. 7;
FIG. 9 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment following FIG. 8;
FIG. 10 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment following FIG. 9;
11 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment following FIG. 10; FIG.
FIG. 12 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment following FIG. 6;
13 is a cross-sectional view for explaining the method of manufacturing the semiconductor device according to the first embodiment following FIG. 12. FIG.
FIG. 14 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment following FIG.
15 is a cross-sectional view for explaining the method of manufacturing the semiconductor device according to the first embodiment following FIG. 12;
FIG. 16 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment following FIG. 15;
FIG. 17 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment following FIG. 16;
FIG. 18 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment following FIG. 17;
[Explanation of symbols]
1 ... Silicon substrate
2 ... Insulating film
3 ... Central area
3a ... Leg
3b Wide part
4 ... Gate oxide film
5 ... Gate Poly
6,7 ... Source / drain region
8 ... Gate electrode
9,10 ・ ・ ・ Source / drain electrode
11 ... Silicone layer
12 ... Si ₃ N ₄ film
13 ... Silicon layer
15,16 ... BPSG film
17, 18 ... SiO ₂ film
19 ・ ・ ・ Polycrystalline silicon film
20 ... Insulating film
21 ... Metal wiring

Claims (2)

An insulating film, a pair of conductive source / drain regions formed on the insulating film, and a semiconductor region formed between the pair of source / drain regions, and channel regions formed on both side surfaces When the direction of the flowing current is the gate length direction and the gate length direction is the direction perpendicular to the height direction of the semiconductor region, the gate width direction is formed on the legs and the legs on the insulating film side. A wide portion that is wider in the gate width direction than the leg portion, and (the width of the leg portion / the width of the wide portion) is ½ or more and 9/10 or less ,
A gate insulating film covering a side surface of the leg portion, a lower surface excluding a contact surface of the wide portion with the leg portion, a side surface of the wide portion, and an upper surface of the wide portion;
Gate poly covering the side surface of the leg portion, the lower surface excluding the contact surface with the leg portion of the wide portion, the side surface of the wide portion , and the upper surface of the wide portion through the gate insulating film,
A gate electrode formed on the gate poly;
A semiconductor device , wherein the maximum width W in the gate width direction of the wide portion is in a relationship of Leff ≧ W with respect to the length Leff between the source / drain regions .   The semiconductor device according to claim 1, further comprising a source electrode and a drain electrode on an upper surface of the pair of source / drain regions.

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