JP4564945B2 - Data rate conversion integrated circuit and image forming apparatus - Google Patents

Description

  The present invention relates to a data rate conversion integrated circuit and an image forming apparatus, and more particularly to a data rate conversion integrated circuit and an image forming apparatus, which have two or more types of input interfaces and convert and output the speed of data input via any one of the input interfaces. The present invention relates to a data rate conversion integrated circuit and an image forming apparatus including the data rate conversion integrated circuit.

  Recently, in order to improve development efficiency due to the increase in the number of copier models, units such as the scanner unit, image processing unit, and printer unit have been developed for each unit. Often used for multiple models of copiers.

  However, for example, when a scanner unit developed for a low-speed digital copying machine is connected to an image processing unit developed for a medium-speed digital copying machine, there is a problem that the interface speed does not match.

  Therefore, it is possible to change the circuit to match the speed of one of the units with the speed of the other unit. However, since the circuit configuration is specialized for the unit, it is not versatile and has a burden on design and development. Become heavier. Therefore, integrated circuits that can convert the data rate between units have been developed.

  As a technology for converting the data rate between units, the phase status is the same as the address value is matched from the steady phase state where the write / read operation is normal (phase timing where the address value of both the write address and the read address is matched). Or the unstable phase state where the phase fluctuation margin is biased (the state when the phase fluctuation margin is biased to the front side or the rear side). An integrated circuit is disclosed that outputs a reset signal for detecting that one of the above is detected so that the phase relationship between the write address and the read address becomes the optimum phase relationship (Patent Document 1).

JP 2002-281005 A

  By the way, the memory capacity of the FIFO required for a black and white digital copying machine may be any as long as it can store data for one line. The digital copying machine most commonly has a reading pixel density of 600 dpi, a maximum reading width of A3 (29.7 cm), and the effective number of pixels required for the CCD is 7300-7500 pixels. . Therefore, when an EVEN / ODD 2-channel output CCD is used, 2 channels are output from the scanner unit and converted into 8-bit data, it is desirable that image data of 8000 pixels × 2 ch × 8 bits can be stored at most. However, since general-purpose FIFOs do not have such capacities, large capacity memory memories are often used as FIFOs, which is costly.

  The present invention has been made in view of the above, and an object thereof is to provide an inexpensive and versatile data rate conversion integrated circuit and an image forming apparatus including the data rate conversion integrated circuit.

In order to solve the above-described problems and achieve the object, a data rate conversion integrated circuit according to the present invention is for inputting data in a data rate conversion integrated circuit that converts a transmission rate of input data and outputs the converted data. A data input unit having at least two types of input interfaces, an interface selection unit that selects any one of the two or more types of input interfaces, and the input interface selected by the interface selection unit. A data rate conversion unit that converts a transmission rate of the data input via the clock and outputs the converted data ; and a clock signal selection unit that selects any one of the clock signals from a plurality of clock signals. The data rate conversion means is selected by the clock signal selection means On the basis of the clock signal, and converting the transmission rate of the data.

  In the data rate conversion integrated circuit according to the present invention, the data rate conversion means includes a memory that stores the data and a synchronization signal that is input via the input interface. Control signal generation for controlling writing and generating a memory control signal for controlling reading of the data written in the memory based on the clock signal selected by the clock signal selection means And means.

  Further, in the data rate conversion integrated circuit according to the present invention, the control signal generation means writes in the memory based on a synchronization signal whose period is converted based on the clock signal selected by the clock signal selection means. A memory control signal for further controlling the read position of the data is generated.

  In addition, the data rate conversion integrated circuit according to the present invention further includes a clock signal multiplying unit that multiplies an input clock signal input via the input interface selected by the interface selecting unit, and the clock signal selecting unit includes: One of the clock signals multiplied by the clock signal multiplication means, the input clock signal, and the external clock signal is selected.

  In addition, the data rate conversion integrated circuit according to the present invention includes a selection of the input interface by the interface selection unit and / or the clock based on a signal input from an external terminal and / or a value set in a register. The multiplication number of the input clock signal multiplied by the signal multiplication means is selected and / or the clock signal is selected by the clock signal selection means.

  The data rate conversion integrated circuit according to the present invention is characterized in that the data input means includes at least an LVDS interface and an LVDS receiver.

  An image forming apparatus according to the present invention includes a data rate conversion integrated circuit according to any one of claims 1 to 6, a scanner unit for optically reading image data of a document, and processing of image data. And an image processing unit for performing the above.

  According to the present invention, data input means having at least two or more input interfaces for inputting data, interface selection means for selecting any one of the two or more input interfaces, and interface selection means And a data rate conversion means for converting the transmission rate of data input via the input interface selected by and outputting the converted data, so that an inexpensive and versatile integrated circuit is used. As a result, the speed of input data can be converted.

  Exemplary embodiments of a data rate conversion integrated circuit according to the present invention will be explained below in detail with reference to the accompanying drawings. In addition, this invention is not limited by this embodiment. In this embodiment, an image forming apparatus using a data rate conversion integrated circuit will be described.

  An overall configuration of an image forming apparatus 100 according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a diagram illustrating an example of the overall configuration of an image forming apparatus 100 according to the present embodiment. As shown in the figure, an image forming apparatus 100 according to the present embodiment includes a scanner unit 200 that optically reads image data of a document, and a speed conversion that converts the speed of image data read by the scanner unit 200 to a different speed. The integrated circuit 300, the image processing unit 400 that performs image processing on the image data converted to a different speed by the speed conversion integrated circuit 300, and the image data that has been subjected to the image processing by the image processing unit 400 are output to a print medium. Printer unit 500.

  The scanner unit 200 will be described with reference to FIG. FIG. 2 is a diagram illustrating an example of the configuration of the scanner unit 200. As shown in the figure, the scanner unit 200 includes a CCD 210 for optically reading analog image data, an analog processing circuit 220 for processing image data read by the CCD 210, and processing performed by the analog processing circuit 220. A / D converter 230 that converts the image data subjected to the above to a digital image, a timing generation circuit 240 that generates a synchronization signal and a clock signal, and an LVDS transmitter 250 that transmits LVDS.

  The CCD 210 is an image sensor, and outputs optically read analog image data by a two-phase output method in which the output is divided into two systems of odd phase (ODD) and even phase (EVEN).

  The analog processing circuit 220 samples the signal portion of the analog waveform output from the CCD 210 and adjusts the gain with a built-in amplifier.

  The A / D converter 230 is for converting analog image data into digital image data. The timing signal generator 240 is for generating a synchronization signal and a clock signal.

  The LVDS transmitter 250 converts image data, a synchronization signal, and a clock signal into LVDS (Low Voltage Differential Signaling) and transmits the LVDS to the speed conversion integrated circuit 300. As shown in FIG. 3, the scanner unit 200 according to the present embodiment includes a TTL buffer 260 instead of the LVDS transmitter 250. The TTL buffer 260 includes image data (SDE [7: 0], SDO [7: 0]), the synchronization signal (XSLSYNC), and the input clock signal (XSDCLK) may be transmitted to the speed conversion integrated circuit 300.

  FIG. 4 is a diagram illustrating an example of the configuration of the speed conversion integrated circuit 300 according to the present embodiment. As shown in the figure, the speed conversion integrated circuit 300 according to the present embodiment converts LVDS I / F 310 and TTL I / F 330 which are input interfaces and LVDS input via the LVDS I / F 310 into TTL data. LVDS receiver 320 for switching, a switching circuit 340 for switching an input interface, a clock selection circuit 350 for selecting any one of a plurality of clock signals, and a speed conversion circuit for converting an output speed of image data 360.

  The LVDS I / F 310 receives LVDS + and LVDS− transmitted from the scanner unit 200 via the LVDS transmitter 250, respectively.

  The LVDS receiver 320 converts the LVDS + and LVDS- from the LVDS I / F 310 into TTL data, converts the image data (SDE [7: 0], SDO [7: 0]), the synchronization signal (XSLSYNC), and the input clock signal ( XSDCLK) to the switching circuit 340.

  The TTL I / F 330 receives image data (SDE [7: 0], SDO [7: 0]), a synchronization signal (XSLSYNC), and an input clock signal (XSDCLK) transmitted from the scanner unit 200 via the TTL buffer 260. Receive each one.

  The switching circuit 340 selects one of the LVDS I / F and the TTL I / F based on the logic of the input selection signal input to the switching circuit 340. The input selection signal is input from an external terminal (not shown) of the speed conversion integrated circuit 300.

  The clock selection circuit 350 selects one of a plurality of clock signals. FIG. 5 is a diagram illustrating an example of the configuration of the clock selection circuit 350 of the present embodiment. The clock selection circuit 350 according to the present embodiment includes a PLL (Phased Locked Loop) 352, a frequency dividing circuit 354, and a selection circuit 356, as shown in FIG.

  A PLL (Phase Locked Loop) 352 multiplies an input clock signal (XSDCLK) that is a clock signal transmitted from the scanner unit 200. The frequency dividing circuit 354 divides the clock signal multiplied by the PLL 352 into 1 / N and sends the multiplied clock signal (CLK1) to the selection circuit 356. For example, if the number of multiplications of the input clock signal is set to two types of multiplication of 8 and 6 and N is set to 4 by the frequency dividing circuit 354, the number of divisions is set to 2 (8/4 = 2). A multiplied clock signal (CLK1) whose speed has been converted to 5 times (6/4 = 1.5) can be generated. Note that the multiplication number and the frequency division number can be set based on a signal input from an external terminal (not shown) of the speed conversion integrated circuit 300.

  The selection circuit 356 receives the multiplied clock signal (CLK1) from the frequency divider circuit 354, the input clock signal (XSDCLK) transmitted from the scanner unit 200, and the external clock (CLK2), respectively, and sets the logic of the output selection signal. Based on this, one of the clock signals is selected and output as a selected clock signal (SCN_CLK). The output selection signal is input from an external terminal (not shown) of the speed conversion integrated circuit 300.

  The speed conversion circuit 360 converts the speed of the image data (SDE [7: 0], SDO [7: 0]) and outputs it. FIG. 6 is a diagram illustrating an example of the configuration of the speed conversion circuit 360 of the present embodiment. As shown in the figure, the speed conversion circuit 360 according to the present embodiment further includes a memory 362 and a memory control circuit 364.

  The memory 362 is for storing image data, specifically, for writing image data and reading image data. Writing and reading of image data to and from the memory 362 is performed based on a control signal output from the memory control circuit 364.

  The memory control circuit 364 is for controlling writing and reading of image data to and from the memory 362. Based on the synchronization signal (XSLSYNC) output from the scanner unit 200, the memory control circuit 364 generates a write control signal indicating a write start position in the memory. Based on this write control signal, image data (SDE [7: 0], SDO [7: 0]) is written to the memory 362. The write control signal includes a write clock, a write enable signal, and a reset signal that resets the read counter.

  The memory control circuit 364 generates a read control signal based on the selected clock signal (SCN_CLK) output from the clock selection circuit 350 and based on the synchronization signal (XSLSYNC) from the scanner unit 200. Specifically, a read control signal for controlling the output speed of the image data and the reading position of the image data is generated. The read position of the image data is based on the converted synchronization signal after converting the synchronization signal (XSLSYNC) from the scanner unit 200 into a cycle based on the selected clock signal (SCN_CLK). Based on this read control signal, image data (SDE [7: 0], SDO [7: 0]) is read from the memory 362. The read control signal includes a memory clock, a memory enable signal, and a reset signal that resets the read counter.

  FIG. 7 is a diagram illustrating an example of the configuration of the image processing unit 400 and the printer unit 500 of the present embodiment. As shown in the figure, the image processing unit 400 of the present embodiment includes an I / F unit 402, a level conversion unit 404, a shading correction unit 406, an image area separation unit 408, a scanner γ unit 410, The filter unit 412, the scaling unit 414, the printer γ unit 416, and the gradation processing unit 418 are included.

  The I / F unit 402 is for receiving image data (DE [7: 0], DO [7: 0]), a synchronization signal (LSYNC_N), and a selection clock signal (SCN_CLK) from the speed conversion integrated circuit 300. .

  The level conversion unit 404 converts the level at the time of reading the white reference plate and that at the time of reading the document, and adjusts the level correction coefficient so as to become a target value.

  The shading correction unit 406 corrects the density unevenness of the optical system and the sensitivity variation of the CCD sensor 210 for each signal (DE [7: 0], DO [7: 0], LSYNC_N, SCN_CLK).

  The image area separation unit 408 determines whether or not each pixel of the image data is a character area or a picture area in order to perform an optimum process according to the characteristics of the image in the subsequent image processing. The signal indicating the character area and the picture area is output to the filter unit 412, the scaling unit 414, the printer γ unit 416, and the gradation processing unit 418.

  The scanner γ section 410 converts the image data into characteristics that improve the correction accuracy of the subsequent correction and outputs the image data to the filter section because the image data has linear characteristics with respect to the reflectance.

  The filter unit 412 performs a filtering process on the image data (DE [7: 0], DO [7: 0]) based on a signal (a signal indicating a character area or a picture area) from the image area separation unit 408. And output the filtered image data to the scaling unit. Specifically, the edge is emphasized to sharpen the character area, and the smoothing process is performed to smooth the pattern area.

  A scaling unit 414 performs scaling processing in the main scanning direction and outputs the result to the printer γ unit. The sub-scanning direction is performed by controlling the scanning speed in the sub-scanning direction.

  The printer γ unit 416 performs γ conversion for matching the original and the copy density based on a signal from the image area separation unit 408 (a signal indicating a character area and a picture area), and outputs the result to the gradation processing unit 418. Specifically, in order to finally match the original and the copy density, processing is performed so that the difference in spectral characteristics, gray balance, and top density of the original and toner are appropriate.

  The gradation processing unit 418 binarizes or multi-values 8-bit density information based on a signal (a signal indicating a character area or a picture area) from the image area separation unit 408 and outputs the binarized information to the printer unit 500. Specifically, with respect to 8-bit density information, binarization or multi-level quantization is performed for the character area, and dither processing or error diffusion processing is performed for the pattern area.

  The printer unit 500 further includes an LD writing unit 502, and prints image data on a print medium via the LD writing unit 502.

  In this embodiment, the input selection signal, the signal for setting the number of multiplications by PLL 352 and the number of divisions by frequency divider circuit 354, and the output selection signal are input from the external terminals of speed conversion integrated circuit 300. However, a serial I / F may be provided and set in a register.

  With the above configuration, a data speed conversion process performed by the speed conversion integrated circuit 300 according to the present embodiment will be described with reference to FIG. FIG. 8 is a flowchart showing the procedure of the data speed conversion process performed by the speed conversion integrated circuit 300 of this embodiment.

  First, an input selection signal is input to the switching circuit 340 (step SA-1), and based on the logic of the input selection signal input at step SA-1, the LVDS I / F 310 and the TTL I / F 330 are used as input interfaces. , One of the interfaces is selected (step SA-2).

  When the input interface selected in step SA-2 is the LVDS I / F 310 (step SA-3: Yes), LVDS + and LVDS- are input via the LVDS I / F 310 (step SA-4). Next, the LVDS + and LVDS− input at step SA-4 are converted into TTL data by the LVDS receiver 320 (step SA-5).

  On the other hand, when the input interface selected in step SA-2 is TTL I / F 330 (step SA-3: No), TTL data is input via TTL I / F (step SA-6).

  Next, the clock selection circuit 350 performs clock signal selection processing for selecting one of the plurality of clock signals (step SA-7), and the speed conversion circuit 360 performs image data writing and reading processing. Perform (step SA-8).

  Next, a clock signal selection process performed by the clock selection circuit 350 will be described with reference to FIG. FIG. 9 is a flowchart showing the procedure of the clock signal selection process performed by the clock selection circuit 350 of the present embodiment.

  When the output selection signal is input to the selection circuit 356 (step SB-1), and the output selection signal input at step SB-1 indicates selection of the multiplied clock signal (CLK1) (step SB-2: Yes) ), The PLL 352, which is a multiplication circuit, multiplies the input clock signal (XSDCLK) (step SB-3). For example, the input clock signal (XSDCLK) is multiplied by setting the multiplication number of the input clock signal (XSDCLK) to 8 or 6 or the like. Next, the clock signal multiplied in step SB-3 is set to 1 / N by the frequency dividing circuit 354 (step B-4). For example, when the set multiplication number is 8 or 6 and N = 4, a multiplied clock signal (CLK1) is generated by converting the input clock signal (XSDCLK) to 2 or 1.5 times. be able to.

  Next, the multiplied clock signal (CLK1) is output to the speed conversion circuit 360 and the image processing unit 400 as the selected clock signal (SCN_CLK) (step SB-5).

  On the other hand, when the output selection signal input in step SB-1 does not indicate selection of the multiplied clock signal (CLK1) (step SB-2: No) but indicates selection of the external clock signal (CLK2). (Step SB-6: Yes), the external clock signal (CLK2) is output to the speed conversion circuit 360 and the image processing unit 400 as a selected clock signal (SCN_CLK) (Step SB-7).

  If the output selection signal input at the input SB-1 does not indicate the selection of the multiplied clock signal (CLK1) or the selection of the external clock signal (CLK2) (step SB-6: No), the input clock signal (XSDCLK ) Is output to the speed conversion circuit 360 and the image processing unit 400 as a selected clock signal (step SB-8).

  Next, writing and reading processing of image data performed by the speed conversion circuit 360 of the present embodiment will be described with reference to FIG. FIG. 10 is a flowchart showing a procedure of image data writing and reading processing performed by the speed conversion circuit 360 of the present embodiment.

  When the synchronization signal (XSLSYNC) and the clock signal (XSDCLK) from the scanner unit 200 are input to the memory control circuit 364 (step SC-1), the memory control circuit 364 receives the synchronization signal (step SC-1) Based on (XSLSYNC), a write control signal indicating a write start position to the memory 362 is generated (step SC-2).

  Next, the image data (SPE [7: 0], SDO [7: 0]) from the scanner unit 200 is written in the memory 362 based on the write control signal generated in step SC-2 (step SC-3). ).

  Next, when the selection clock signal (SCN_CLK) from the clock selection circuit 350 is input to the memory control circuit 364 (step SC-4), the memory control circuit 364 selects the selection clock signal (SCN_CLK) input at step SC-4. ) To generate a read control signal (step SC-5).

  Next, image data (SPE [7: 0], SDO [7: 0]) is read based on the read control signal generated at step SC-5 (step SC-6), and read at step SC-6. The processed image data (DE [7: 0], DO [7: 0]) is output to the image processing unit 400 (step SC-7).

  For example, the selected clock signal (SCN_CLK) input to the memory control circuit 364 in step SC-4 is multiplied by 1.5 as compared with the input clock signal (XSDCLK) shown in FIG. , The output speed of the image data (DE [7: 0], DO [7: 0]) is 1.5 times as shown in FIG. Similarly, the selected clock signal (SCN_CLK) input to the memory control circuit 364 at step SC-4 is multiplied by two as compared with the input clock signal (XSDCLK) shown in FIG. ), The output speed of the image data (DE [7: 0], DO [7: 0]) is doubled as shown in FIG.

  As described above, the speed conversion integrated circuit 200 according to the present embodiment selects one of the LVDS I / F and the TTL I / F based on the input selection signal to the switching circuit 340, and Output selection to the clock selection circuit 350 among the input clock signal (XSDCLK) input through the selected input interface, the multiplied clock signal (CLK1) obtained by multiplying the input clock signal, and the external clock signal (CLK2) One clock signal (selected clock signal) is selected based on the signal, the output speed is converted based on the selected clock signal (SCN_CLK), and the image data (DE [7: 0], DO [7: 0] ) To the image processing unit 400.

  Therefore, according to the speed conversion integrated circuit 300 of the present embodiment, it has an LVDS I / F and a TTL I / F (a plurality of input interfaces), and is based on an input selection signal input to the switching circuit 340. Since the output speed of the image data input through the selected input interface is converted and output, the conversion process of the data output speed can be realized by one integrated circuit, and the cost is reduced. Can be suppressed.

  In addition, according to the speed conversion integrated circuit 300 of the present embodiment, since the LVDS I / F and the TTL I / F are provided as input interfaces, the input data speed conversion is performed using a general-purpose integrated circuit. It can be carried out.

  Based on the output selection signal, select one of the input clock signal (XSDCLK), multiplied clock signal (CLK1), and external clock signal (CLK2) as the selected clock signal (SCN_CLK), and select Since the output speed of the image data is converted based on the clock signal (SCN_CLK), the image data can be output at the output speed based on various clock signals.

  The memory control circuit 364 generates a write control signal and a read control signal that are memory control signals, writes image data into the memory 362 based on the generated write control signal, and a selected clock selected by the clock selection circuit 350. Since the image data written in the memory 362 is read and output based on the signal (SCN_CLK), the read start position of the image data written in the memory 362 can be automatically adjusted.

  Further, according to the speed conversion integrated circuit 300 of the present embodiment, the input selection signal is input to the switching circuit 340 from the external terminal, and the input interface is selected based on the input selection signal. A desired input interface can be selected.

  Further, according to the speed conversion integrated circuit 300 of the present embodiment, an output selection signal is input to the clock selection circuit 350 from an external terminal, and any one of a plurality of clock signals is selected based on the input output selection signal. Since the clock signal is selected, the user can select a desired output speed of the image data.

  Further, according to the speed conversion integrated circuit 300 of the present embodiment, the multiplication number and the division number of the input clock signal (XSDCLK) are set from the external terminal, and the multiplication is performed based on the set multiplication number and the division number. Since the clock signal (CLK1) is generated, the user can generate a desired clock signal.

  Further, according to the speed conversion integrated circuit 300 of the present embodiment, the selection of the input interface, the setting of the multiplication number and the frequency division number of the input clock signal (XSDCLK), and the selection of the clock signal can also be set by a register. Therefore, the user can select a desired interface, generate a multiplied clock signal with the input clock signal having a desired multiplication number, and select a desired clock signal.

1 is a diagram illustrating an example of the overall configuration of an image forming apparatus 100. FIG. 2 is a diagram illustrating an example of a configuration of a scanner unit 200. FIG. 2 is a diagram illustrating an example of a configuration of a scanner unit 200. FIG. 3 is a diagram illustrating an example of a configuration of a speed conversion integrated circuit 300. FIG. 3 is a diagram illustrating an example of a configuration of a clock selection circuit 350. FIG. 3 is a diagram illustrating an example of a configuration of a speed conversion circuit 360. FIG. 2 is a diagram illustrating an example of a configuration of an image processing unit 400 and a printer unit 500. FIG. 5 is a flowchart showing a procedure of data speed conversion processing performed by the speed conversion integrated circuit 300. 4 is a flowchart showing a procedure of clock signal selection processing performed by a clock selection circuit 350. 6 is a flowchart showing a procedure of image data writing processing and reading processing performed by a speed conversion circuit 360. It is a figure which shows the output of the image data based on an input clock signal (XSDCLK). It is a figure which shows the output of the image data based on the multiplication clock signal (CLK1) which multiplied the input clock signal (XSDCLK) 1.5. It is a figure which shows the output of the image data based on the multiplication clock signal (CLK1) which multiplied the input clock signal (XSDCLK) 2 times.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Image forming apparatus 200 Scanner part 300 Speed conversion integrated circuit 310 LVDS I / F
320 LVDS receiver 330 TTL I / F
340 switching circuit 350 clock selection circuit 352 PLL
354 Frequency dividing circuit 356 Selection circuit 360 Speed conversion circuit 362 Memory 364 Memory control circuit 400 Image processing unit 500 Printer unit

Claims (7)

In a data rate conversion integrated circuit that converts and outputs the transmission rate of input data,
Data input means having at least two or more input interfaces for inputting data;
Interface selection means for selecting any one of the two or more input interfaces;
Data rate conversion means for converting the transmission rate of the data input via the input interface selected by the interface selection means, and outputting the converted data;
Clock signal selection means for selecting any one of the clock signals among a plurality of clock signals ,
The data rate conversion integrated circuit, wherein the data rate conversion unit converts a transmission rate of the data based on the clock signal selected by the clock signal selection unit . The data rate conversion means includes
A memory for storing the data;
Based on the synchronization signal input through the input interface, the writing of the data to the memory is controlled, and the writing to the memory is performed based on the clock signal selected by the clock signal selection means. Control signal generating means for generating a memory control signal for controlling the reading of the stored data;
The data rate conversion integrated circuit according to claim 1, further comprising: The control signal generating means further controls the reading position of the data written in the memory based on a synchronization signal whose period is converted based on the clock signal selected by the clock signal selecting means. 3. The data rate conversion integrated circuit according to claim 2 , wherein the memory control signal is generated. A clock signal multiplier for multiplying an input clock signal input via the input interface selected by the interface selector;
The clock signal selection means includes
Multiplied clock signal is multiplied by the clock signal multiplying means, said input clock signal, and an external clock input signal, according to any one of claims 1 to 3, characterized in that selects either the clock signal Data rate conversion integrated circuit. Selection of the input interface by the interface selection means and / or multiplication of the input clock signal multiplied by the clock signal multiplication means based on a signal input from an external terminal and / or a value set in a resist 5. The data rate conversion integrated circuit according to claim 4 , wherein selection of the number and / or selection of the clock signal by the clock signal selection means is performed. The data rate conversion integrated circuit according to any one of claims 1 to 5 , wherein the data input means includes at least an LVDS interface and an LVDS receiver. A data rate conversion integrated circuit according to any one of the claims 1 to 6, a scanner section for reading an image data of a document optically, an image processing unit for processing the image data An image forming apparatus comprising the image forming apparatus.

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