JP4559958B2 - Multi-core control method in multi-core processor - Google Patents

Description

  The present invention relates to a control method for a multi-core processor, and more particularly to a multi-core control method in a multi-core processor having an exclusive control function between the multi-core processors.

  In a general microprocessor, that is, a single core processor, a set of processor cores that operate as one component in which an instruction issuer, an arithmetic unit, and the like are combined is included in a package. On the other hand, a multi-core processor has a plurality of processor cores and a state in which a plurality of microprocessors are mounted.

  Conventionally, in a single core processor, a multitasking operation is realized by installing a multitasking OS, and a processing capability is increased by increasing an operating frequency, thereby improving real-time performance.

As described above, the method of increasing the operating frequency by increasing the operating frequency is approaching the limit in terms of heat and power consumption.
On the other hand, the configuration of the multi-core processor can improve the processing capability without increasing the operating frequency, and is more advantageous than the single-core processor in terms of heat and power consumption (see, for example, Patent Document 1).
JP-A-5-342026

  By using a multi-core processor instead of a single-core processor as described above, the processing capability can be improved without increasing the operating frequency, which is advantageous in terms of heat and power consumption. There is a demerit that the exclusion of data and maintaining the identity of data become complicated.

  For this reason, there is a demand for a technique for operating a multi-core processor in an optimal state to perform a multitask operation so as to meet a real-time request of a signal processing system or the like.

  The present invention has been made to solve the above-described problems, and can perform an efficient multitask operation using a multicore processor, and can be applied to a signal processing system having a strict time response performance. An object of the present invention is to provide a multi-core control method in a multi-core processor.

The present invention provides a multi-core processor composed of a plurality of core processors, wherein a plurality of memories are spatially multiplexed by an internal bus to the plurality of core processors so that an arbitrary memory can be accessed. core processor is provided a semaphore management table showing the use state of what is used to control the exclusive control object, and exclusive control in each core processor, and exclusive control among a plurality of core processors, all core processor A semaphore ID is assigned to each exclusive control, and each core processor switches to the exclusive control identified by the semaphore ID, monitors the semaphore management table, and excludes an access interrupt to the exclusive control target. And

  According to the present invention, a semaphore ID is assigned to exclusive control within each core processor, between each core processor, and between all core processors, and the exclusive control identified by this semaphore ID is switched to interrupt access to the exclusive control target. By exclusion, multitask processing can be performed efficiently, and it can be applied to a signal processing system with strict time response performance.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of a multi-core processor according to an embodiment of the present invention. In FIG. 1, 11 is a first core processor (core 0), 12 is a second core processor (core 1), 13 is a third core processor (core 2), and L1 memories 21 to 23 are attached. ing. A cache memory is arranged in a part of the L1 memories 21 to 23. The core processors 11 to 13 operate on a single stack OS, and the priority is set to, for example, “core 0 <core 1 <core 2”.

The core processors 11 to 13 are connected to the internal bus 14 and the external bus 15.
A plurality of, for example, four L2 memories (0) 31, an L2 memory (1) 32, an L2 memory (2) 33, and an L2 memory (3) 34 are connected to the internal bus. The L2 memories 31 to 34 are provided with semaphore management tables. In this case, the semaphore management table may be arranged in any of the L2 memories 31 to 34.

  The core processors 11 to 13 and the L2 memories 31 to 34 spatially multiplexly connect the internal bus 14. For example, while the core processor 11 is accessing the L2 memory 31, the core processor 12 is connected to the L2 memory 32. The processor (core 2) 13 is connected to the L2 memory (3) 34 so as to be simultaneously accessible. For example, 32 data buses are connected to each of the L2 memories 31 to 34, and the upper bits of the address bus are assigned to the chip select signal to select an access target. Therefore, the core processors 11 to 13 can access any of the L2 memories 31 to 34.

The external bus 15 is connected to a host (HOST) processor 41, an SDRAM (Synchronous DRAM) 42, and a communication device 43.
FIG. 2 shows an example of a multitask configuration in the embodiment. Each of the core processors 11 to 13 includes one task (Task 0, Task 1, Task 2), a plurality of software interrupts (SWI 0, SWI 1), and a plurality of hardware interrupts (HWI). A common unit 50 includes a library 51, an IPL (Initial Program Loader) 52, an OS (Operating System) 53, and a driver 54. In general, when multitasking is executed by one core processor, it is necessary to switch task contexts (registers and stacks) when switching tasks. In this embodiment, as described above, by assigning one task (Task 0, Task 1, Task 2) to each of the core processors 11 to 13, it is not necessary to switch task contexts within the same core processor. .

  The common unit 50 is stored in the L2 memories 31 to 34 and is accessed from the core processors 11 to 13 via a cache memory arranged in a part of the L1 memories 21 to 23. By arranging the common unit 50 in the L2 memories 31 to 34, the L1 memories 21 to 23 having a small capacity are supplemented.

  The core processors 11 to 13 assign a semaphore ID to exclusive control within the core, between the cores, and between all the cores, identify the semaphore ID, and switch the exclusive control processing.

Hereinafter, exclusive control processing within the core, between the cores, and between all the cores in the core processors 11 to 13 will be described.
[In-core exclusive control processing]
For example, when an ID specifying a semaphore in each of the core processors 11 to 13 is given as an argument of the function, access to the exclusive control target 61 is sandwiched between interrupt prohibition processing and interrupt prohibition cancellation processing as shown in FIG. As a result, access to the exclusive control target 61 is exclusive. FIG. 3 shows exclusive control processing in the core processor 11, and the software interrupt SWI 0 manages prohibition / release of activation of the software interrupt SWI 1.

  In FIG. 3, for example, when the task Task 0 accesses the exclusive control target 61, the task Task 0 first instructs the software interrupt SWI 0 to disable interrupts (step A1), and waits for a response to the exclusive control target. 61 is accessed (step A2). If an SWI 1 interrupt request is generated from the hardware interrupt HWI to the software interrupt SWI 0 during this access, the interrupt request by the hardware interrupt HWI is not accepted because the software interrupt SWI 0 is in the interrupt disabled state at this time.

  Thereafter, when the task Task 0 finishes accessing the exclusive control target 61, the task Task 0 sends a notification of interrupt prohibition cancellation to the software interrupt SWI 0 (step A3), and the interrupt prohibition of the software interrupt SWI 0 is cancelled. . As a result, the software interrupt SWI 0 receives the SWI 1 interrupt request from the hardware interrupt HWI and outputs a start command to the software interrupt SWI 1 (step A4).

The software interrupt SWI 1 is activated by the activation command, instructs the exclusive control target 61 to prohibit interruption (step A5), and waits for a response to access the exclusive control target 61 (step A6). When the access to the exclusive control target 61 is completed, the software interrupt SWI 1 notifies the exclusive control target 61 of the interrupt prohibition release (step A7), and waits for a response to notify the exclusive control target 61 of the end of processing. (Step A8). The exclusive control target 61 notifies the task Task 0 that the access by the software interrupt SWI 1 has been completed (step A9).
As described above, the exclusive control processing for access to the exclusive control target 61 is performed in each of the core processors 11 to 13.

[Inter-core exclusive control processing]
In addition, when an ID for designating a semaphore between two cores is designated in the core processors 11 to 13, the semaphore management tables 62 arranged in the L2 memories 31 to 34 as shown in FIG. The exclusive control is realized by monitoring at 13. FIG. 4 shows a case where exclusive control is performed on the exclusive control target 61 between the core processors 11 and 12, and the semaphore management table 62 is provided with a core 0 state area 62a and a core 1 state area 62b.

  In the core 0 state area 62a of the semaphore management table 62, it is written whether the core processor (core 0) 11 is “in use” or “empty”, and the core processor (core 1) is written in the core 1 state area 62b. ) Write and manage whether 12 is “in use” or “empty”.

[Operation procedure of core processor 11]
First, the operation procedure of the core processor 11 will be described with reference to the flowchart of FIG.
The core processor 11 reads the use state of the core processor 12 from the core 1 state area 62b of the semaphore management table 62 (step B1), and determines whether it is “free” or in use (step B2). When the core processor 12 is free, “in use” is written in the core 0 state area 62a (step B3), and the exclusive control target 61 is accessed (step B4). In step B5, it is determined whether or not the processing for the exclusive control target 61 has been completed. When access to the exclusive control target 61 is completed, “empty” is written in the core 0 state area 62a (step B6), and the processing is terminated. To do.

  If it is determined in step B2 that the core processor 12 is in use, the core processor 12, that is, the "core 1 state", waits for a spin lock until the "core 1 state" becomes "free" (step B7). . When the core processor 12 becomes “empty”, the exclusive control target 61 is accessed (step B8). In step B9, it is determined whether or not the processing for the exclusive control target 61 has been completed. When access to the exclusive control target 61 is completed, “empty” is written in the core 0 state area 62a (step B10), and the processing is terminated. To do.

[Operation procedure of core processor 12]
Next, the operation procedure of the core processor 12 will be described with reference to the flowchart of FIG.
The core processor 12 reads the use state of the core processor 11, that is, the “core 0 state” from the core 0 state area 62a of the semaphore management table 62 (step C1), and determines whether it is “free” or in use. (Step C2). If the core processor 11 is free, “in use” is written in the core 1 state area 62b (step C3), and the exclusive control target 61 is accessed (step C4). In step C5, it is determined whether or not the processing for the exclusive control target 61 has been completed. When access to the exclusive control target 61 is completed, “empty” is written in the core 1 state area 62b (step C6), and the processing is terminated. To do.

  If it is determined in step C2 that the core processor 11 is in use, the core processor 11, that is, the "core 0 state", is waited in a spin lock until "free" (step C7). . When the core processor 11 becomes “empty”, the exclusive control target 61 is accessed (step C8). In step C9, it is determined whether or not the processing for the exclusive control target 61 has been completed. When access to the exclusive control target 61 is completed, “empty” is written in the core 1 state area 62b (step C10), and the processing ends. To do.

[Exclusive control between all cores]
Next, exclusive control processing between all cores will be described.
When the core processor 11 to 13 specifies an ID for specifying a semaphore between all cores, the core processors 11 to 13 monitor the semaphore management table 63 shown in FIG. 7 arranged in the L2 memories 31 to 34. Exclusive control is realized by. Here, as described above, each of the core processors 11 to 13 has a core 0 <core 1 <core 2
By giving this priority, the processing of the core with the higher priority is preferentially performed with a short overhead.

  As shown in FIG. 7, the semaphore management table 63 includes an exclusive control target state area 63a, a core 0 state area 63b, a core 1 state area 63c, and a core 2 state area 63d. In the exclusive control target state area 63a, the state of “core 0 / core 1 / core 2 / free” is selectively written. In the core 0 state area 63b, the state of “in use / free / waiting” regarding the core 0 (core processor 11) is selectively written. In the core 1 state area 63c, a state of “in use / free / waiting” regarding the core 1 (core processor 12) is selectively written. In the core 2 state area 63d, the state of “in use / free / waiting” regarding the core 2 (core processor 13) is selectively written.

[Operation Procedure of Core Processor 11 (Priority “Low”)]
First, the operation procedure of the core processor (core 0) 11 will be described with reference to the flowchart of FIG.
The core processor 11 writes “wait” in the core 0 state area 63b of the semaphore management table 63 (step D1), and then reads the states of the core 1 and the core 2 from the core 1 state area 63c and the core 2 state area 63d. It is determined whether or not both are “vacant” (steps D2 and D3). If the states of the core 1 and the core 2 are both “empty”, the process waits with a spin lock until the exclusive control target state in the exclusive control target state area 63a becomes “free” (step D4).

  When the exclusive control target state becomes “vacant”, “core 0” is written in the exclusive control target state area 63a (step D5), and “in use” is written in the core 0 state area 63b (step D6). Thereafter, the core processor 11 uses the exclusive control target (step D7). Next, it is determined whether or not the use of the exclusive control target is finished (step D8). When the use of the exclusive control target is finished, “empty” is written in the core 0 state area 63b and the exclusive control target state area 63a is written. “Free” is written (steps D9 and D10), and the processing of the core processor 11 is terminated.

  If it is determined in step D3 that either one of the cores 1 and 2 is in a state other than “free”, the exclusive control target state in the exclusive control target state area 63a is set to “free”. Until it becomes, it waits with a spin lock (step D11). Then, when the exclusive control target state becomes “empty”, the process returns to step D2, and the above-described processing is repeated.

[Operation Procedure of Core Processor 12 (Priority “Medium”)]
Next, the operation procedure of the core processor (core 1) 12 will be described with reference to the flowchart of FIG.
The core processor 12 writes “wait” in the core 1 state area 63c of the semaphore management table 63 (step E1), and then reads the state of the core 2 from the core 2 state area 63d to determine whether it is “free”. Judgment is made (steps E2, E3). If the state of the core 2 is “empty”, it waits with a spin lock until the exclusive control target state in the exclusive control target state area 63a becomes “free” (step E4).

  When the exclusive control target state becomes “vacant”, the core processor 12 writes “core 1” in the exclusive control target state area 63a and “in use” in the core 1 state area 63c (steps E5 and E6). The exclusive control target is used (step E7).

  Next, it is determined whether or not the use of the exclusive control target is finished (step E8). When the use of the exclusive control target is finished, “empty” is written in the core 1 state area 63c and the exclusive control target state area 63a is written. “Free” is written (steps E9 and E10), and the processing of the core processor 12 is terminated.

  If it is determined in step E3 that the core 2 is in a state other than “free”, the process waits with a spin lock until the exclusive control target state in the exclusive control target state area 63a becomes “free”. (Step E11). Then, when the exclusive control target state becomes “empty”, the process returns to step E2, and the above-described processing is repeatedly executed.

[Operation Procedure of Core Processor 13 (Priority “High”)]
Next, the operation procedure of the core processor (core 2) 13 will be described with reference to the flowchart of FIG.
The core processor 13 writes “wait” in the core 2 state area 63d of the semaphore management table 63 (step F1), and then spin-locks until the exclusive control target state in the exclusive control target state area 63a becomes “free”. Wait (step F2).

  When the exclusive control target state becomes “free”, the core processor 13 writes “core 1” in the exclusive control target state area 63a and “in use” in the core 2 state area 63d (steps F3 and F4). Thereafter, the exclusive control target is used (step F5).

  Next, it is determined whether or not the use of the exclusive control target is finished (step F6). When the use of the exclusive control target is finished, “empty” is written in the core 2 state area 63d and the exclusive control target state area 63a is written. “Free” is written (steps F7 and F8), and the processing of the core processor 13 is terminated.

  As described above, the priority of “core 0 <core 1 <core 2” is given to each of the core processors 11 to 13, and the semaphore management table 63 shown in FIG. In addition, it is possible to realize exclusive control between the high-priority cores, and it is possible to preferentially perform core processing with a short overhead.

  In the above embodiment, the ring buffer type shared memory 64 as shown in FIG. 11 is arranged in the L2 memories 31 to 34 or the SDRAM 42 connected to the external bus 15, thereby allowing data communication between the core processors 11 to 13. It is also possible to perform. In this case, access from the core processors 11 to 13 to the L2 memories 31 to 34 or the SDRAM 42 is guaranteed by atomic hardware in order to reduce the load of software processing. That is, only one of the core processors 11 to 13 can access the L2 memories 31 to 34 or the SDRAM 42 at a certain time.

  FIG. 11 shows an example in which data is written and read between the core processor 11 and the core processor 12, and the shared memory 64 includes, for example, a core 0 write pointer 64a, a core 1 read pointer 64b, and a ring buffer. Are provided with 0 to N fixed length data areas 65a to 65n.

  Next, operation procedures of the write-side core processor (core 0) 11 and the read-side core processor (core 1) 12 will be described with reference to the flowcharts of FIGS.

[Operation Procedure of Core Processor (Core 0) 11 on Writing Side]
As shown in the flowchart of FIG. 12, the core processor 11 reads the core 0 write pointer 64a and the core 1 read pointer 64b (step G1), and has the core 0 write pointer 64a make one round to catch up with the core 1 read pointer 64b? Judgment is made (step G2). If the core 0 write pointer 64a does not catch up with the core 1 read pointer 64b, the data is written to the next area of the fixed length data pointed to by the core 0 write pointer 64a (step G3), and the core 0 write pointer 64a is moved to the next area. The data is updated to point (step G4), and the data writing process is terminated.

  If it is determined in step G2 that the core 0 write pointer 64a has caught up with the core 1 read pointer 64b, the write data is discarded (step G5) and the process ends with an error.

[Operation Procedure of Core Processor (Core 1) 12 on Reading Side]
As shown in the flowchart of FIG. 13, the core processor 12 reads the core 0 write pointer 64a and the core 1 read pointer 64b (step H1), and has the core 1 read pointer 64b go around once and catch up with the core 0 write pointer 64a? Judgment is made (step H2). If the core 1 read pointer 64b does not catch up with the core 0 write pointer 64a, the fixed length data area pointed to by the core 1 read pointer 64b is read (step H3), and the core 1 read pointer 64b is updated to adopt the next area ( Step H4) After that, the process returns to Step H1 to repeat the above-described processing.

  If it is determined in step H2 that the core 1 read pointer 64b has caught up with the core 0 write pointer 64a, the process proceeds to step H5 and ends without reading data.

  According to the above embodiment, when multitasking is executed by a multicore processor, only one task is assigned to one core processor, thereby executing multitask processing without switching task context (registers and stacks). Can do.

  The core processors 11 to 13 and the L2 memories 31 to 34 are configured so that the internal bus 14 can be spatially multiplexed to access each of the L2 memories 31 to 34 at the same time, and the L2 memories 31 to 34 are managed as semaphores. By arranging the table, it is possible to alleviate busy lock caused by increased bus access during spin lock.

  In addition, each semaphore ID is assigned to the exclusive control within each core processor 11-13, between each core processor 11-13, and between all core processors 11-13, and the exclusive control process identified by this semaphore ID is switched and exclusive. By excluding access interrupts to controlled objects, multitask processing can be performed efficiently.

  In the exclusive control among all the core processors 11 to 13, by giving priority to the core processors 11 to 13, high priority processing can be preferentially performed with short overhead.

  In addition, by arranging the ring buffer type shared memory 64 in an atomic area, for example, the L2 memories 31 to 34 or the SDRAM 42 connected to the external bus 15, data communication between the core processors 11 to 13 can be performed. Become. In this case, the load of software processing can be reduced by arranging the shared memory 64 in an atomic area.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying constituent elements without departing from the scope of the invention in the implementation stage.

It is a block diagram which shows the structure of the multi-core processor which concerns on one Embodiment of this invention. It is a block diagram which shows the structural example of the multitask in the same embodiment. It is operation | movement explanatory drawing of the exclusive control in a core in the same embodiment. It is a figure which shows the structural example of the exclusive control object and semaphore management table in inter-core exclusive control. It is a flowchart which shows the operation | movement procedure of the core processor (core 0) in the inter-core exclusive control. It is a flowchart which shows the operation | movement procedure of the core processor (core 1) in inter-core exclusive control. It is a figure which shows the structural example of the semaphore management table in all the cores exclusive control. It is a flowchart which shows the operation | movement procedure of the core processor (core 0, priority: low) in all the inter-core exclusive control. It is a flowchart which shows the operation | movement procedure of the core processor (core 1, priority: medium) in all core exclusive control. It is a flowchart which shows the operation | movement procedure of the core processor (core 2, priority: high) in all the inter-core exclusive control. It is a figure which shows the structural example of the shared memory used when exchanging data between each core processor. It is a flowchart which shows the operation | movement procedure of the core processor (core 0) by the side of data writing in the case of exchanging data between each core processor. It is a flowchart which shows the operation | movement procedure of the core processor (core 1) by the side of data reading in the case of exchanging data between each core processor.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11-13 ... Core processor, 14 ... Internal bus, 15 ... External bus, 21-23 ... L1 memory, 31-34 ... L2 memory, 41 ... Host processor, 42 ... SDRAM, 43 ... Communication device, 50 ... Common part, 51 ... Library, 52 ... IPL, 53 ... OS, 54 ... Driver, 61 ... Exclusive control target, 62 ... Semaphore management table, 62a ... Core 0 state area, 62b ... Core 1 state area, 63 ... Semaphore management table, 63a ... exclusive control target status area, 63b ... core 0 status area, 63c ... core 1 status area, 63d ... core 2 status area, 64 ... shared memory, 64a ... write pointer, 64b ... read pointer, 65a- 65n: Fixed length data area.

Claims (1)

In a multi-core processor composed of a plurality of core processors, a plurality of memories are spatially connected to the plurality of core processors by an internal bus so that an arbitrary memory can be accessed, and the plurality of core processors are connected to the memory. It provided the semaphore management table showing the use state of what is used to control the exclusive control object, and exclusive control in each core processor, and exclusive control among a plurality of core processors, exclusive control between the total core processor A multi-core processor, wherein each core processor switches to exclusive control identified by the semaphore ID, monitors the semaphore management table, and excludes an access interrupt to the exclusive control target. Multi-core control method.

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